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Tan et al., 2017 - Google Patents

Highly uniform zinc blende GaAs nanowires on Si (111) using a controlled chemical oxide template

Tan et al., 2017

Document ID
12862468213269590838
Author
Tan S
Genuist Y
Den Hertog M
Bellet-Amalric E
Mariette H
Pelekanos N
Publication year
Publication venue
Nanotechnology

External Links

Snippet

GaAs-based nanowires (NWs) can be grown without extrinsic catalyst using the Ga-assisted vapor–liquid–solid method in an epitaxy reactor, on Si (111) substrates covered with native oxide. Despite its wide use, the conventional method fails to provide a good control over …
Continue reading at iopscience.iop.org (other versions)

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02521—Materials
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    • H01L21/02546—Arsenides
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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