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Stitt et al., 2011 - Google Patents

Thread warping: Dynamic and transparent synthesis of thread accelerators

Stitt et al., 2011

Document ID
12787625156125794880
Author
Stitt G
Vahid F
Publication year
Publication venue
ACM Transactions on Design Automation of Electronic Systems (TODAES)

External Links

Snippet

We introduce thread warping, a dynamic optimization technique that customizes multicore architectures to a given application by dynamically synthesizing threads into custom accelerator circuits on FPGAs (Field-Programmable Gate Arrays). Thread warping builds …
Continue reading at dl.acm.org (other versions)

Classifications

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    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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