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Bajwa et al., 1997 - Google Patents

Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP

Bajwa et al., 1997

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Document ID
12116769113624645915
Author
Bajwa R
Schumann N
Kojima H
Publication year
Publication venue
Proceedings of the 1997 international symposium on Low power electronics and design

External Links

Snippet

While power consumption has become an important design constraint very few reports of power analysis of processors are available in the literature. The processor considered is an experimental integration of a 16-bit DSP and a 32-bit RISC microcontroller, ERDI. Simulation …
Continue reading at dl.acm.org (PDF) (other versions)

Classifications

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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
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    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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    • G06F2207/3804—Details

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