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Chen et al., 1995 - Google Patents

Effective hardware-based data prefetching for high-performance processors

Chen et al., 1995

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Document ID
11529225808840839167
Author
Chen T
Baer J
Publication year
Publication venue
IEEE transactions on computers

External Links

Snippet

Memory latency and bandwidth are progressing at a much slower pace than processor performance. In this paper, we describe and evaluate the performance of three variations of a hardware function unit whose goal is to assist a data cache in prefetching data accesses …
Continue reading at people.cs.pitt.edu (PDF) (other versions)

Classifications

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    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
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    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
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    • G06F9/3455—Addressing or accessing the instruction operand or the result; Formation of operand address; Addressing modes of multiple operands or results using stride
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    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
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    • G06F8/44—Encoding
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