[go: up one dir, main page]

Li et al., 2023 - Google Patents

Model Checking TileLink Cache Coherence Protocols By Murphi

Li et al., 2023

Document ID
11488612940388195231
Author
Li Z
Li Y
Wang K
Ma K
Yu S
Publication year
Publication venue
2023 IEEE 41st International Conference on Computer Design (ICCD)

External Links

Snippet

TileLink is a standard interface used for on-chip communication within the RISC-V open- source processor ecosystem. It offers a scalable, low-latency, and coherent method of exchanging data between various components of a System-on-Chip (SoC) design, such as …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Programme synchronisation; Mutual exclusion, e.g. by means of semaphores; Contention for resources among tasks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F19/00—Digital computing or data processing equipment or methods, specially adapted for specific applications

Similar Documents

Publication Publication Date Title
Seo et al. Distributed socialite: A datalog-based language for large-scale graph analysis
Sinclair et al. Chasing away rats: Semantics and evaluation for relaxed atomics on heterogeneous systems
WO2014110922A1 (en) Extended cache coherence protocol-based multi-level coherence domain simulation verification and test method
Conchon et al. Invariants for finite instances and beyond
Zhang et al. Fractal coherence: Scalably verifiable cache coherence
Sinclair et al. HeteroSync: A benchmark suite for fine-grained synchronization on tightly coupled GPUs
Martínez-Angeles et al. A datalog engine for gpus
Oswald et al. Heterogen: Automatic synthesis of heterogeneous cache coherence protocols
Oswald et al. HieraGen: Automated generation of concurrent, hierarchical cache coherence protocols
DeOrio et al. Post-silicon verification for cache coherence
Li et al. Model Checking TileLink Cache Coherence Protocols By Murphi
Li et al. Fastblock: Accelerating blockchains via hardware transactional memory
Chen et al. Efficient methods for formally verifying safety properties of hierarchical cache coherence protocols
Elver et al. VerC3: A library for explicit state synthesis of concurrent systems
Sinclair Efficient coherence and consistency for specialized memory hierarchies
Michael et al. Scalability of Atomic Primitives on Distributed Shared Memory Multiprocessors.
Ramdas et al. ECI: a Customizable Cache Coherency Stack for Hybrid FPGA-CPU Architectures
Ghosh et al. Exploring network on chip architectures using GEM5
CN119396539B (en) A protocol processing method, device, electronic device and readable storage medium
Olausson Towards the automatic synthesis of cache coherence protocols
Fernández-Pascual et al. Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study
Sung DeNovo: rethinking the memory hierarchy for disciplined parallelism
Ha et al. D2. 4 report on the final prototype of programming abstractions for energy-efficient inter-process communication
Aisopos et al. Extending open core protocol to support system-level cache coherence
Graf Shared memory verification for multicore chip designs