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Shiono et al., 1979 - Google Patents

Surface State Formation during Long-Term Bias-Temperature Stress Aging of Thin SiO2–Si Interfaces

Shiono et al., 1979

Document ID
10069617176711124031
Author
Shiono N
Yashiro T
Publication year
Publication venue
Japanese Journal of Applied Physics

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Snippet

Surface state formation during bias-temperature (BT) stress aging is investigated in polycrystalline silicon (phosphorous doped)–thin SiO 2–silicon capacitor fabricated by the standard silicon gate process. The applied stress field was 2.3–4.5 MV/cm. The stress …
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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