WO2025254157A1

WO2025254157A1 - Substrate with built-in capacitor and multi-terminal capacitor

Info

Publication number: WO2025254157A1
Application number: PCT/JP2025/020260
Authority: WO
Inventors: 亮葛西; 青路日▲高▼; 幸宏藤田
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2024-06-07
Filing date: 2025-06-04
Publication date: 2025-12-11
Anticipated expiration: 2026-12-07

Abstract

Provided is a substrate with a built-in capacitor having an improved noise reduction effect. A substrate 100A with a built-in capacitor has an IC mounted thereon, and comprises a multi-terminal capacitor 1A that has a first internal electrode layer 21 and a second internal electrode layer that are embedded in the substrate and face each other, and has at least five terminals 41, 42, wherein the multi-terminal capacitor 1A is connected to the IC so that at least a portion of a DC electric current of an electric power supply of the IC flows through the first internal electrode layer 21 of the multi-terminal capacitor 1A.

Description

Capacitor-embedded board and multi-terminal capacitor

　本発明は、コンデンサ内蔵基板および多端子コンデンサに関する。 The present invention relates to a substrate with a built-in capacitor and a multi-terminal capacitor.

　特許文献１には、ビアアレイ型コンデンサ、および、ビアアレイ型コンデンサを内蔵した配線基板が開示されている。このビアアレイ型コンデンサは、
・複数の誘電体層が積層された積層体と、
・積層体の内部に配置され、誘電体層を挟んで対向する第１内部電極層および第２内部電極層と、
・積層体の内部に配置され、積層方向に延在し、第１内部電極層に電気的に接続された複数の第１導体ビアと、
・積層体の内部に配置され、積層方向に延在し、第２内部電極層に電気的に接続された複数の第２導体ビアと、
・積層体の第１主面および第２主面に配置され、複数の第１導体ビアにそれぞれ接続された複数の第１外部電極と、
・積層体の第１主面および第２主面に配置され、複数の第２導体ビアにそれぞれ接続された複数の第２外部電極と、
を備える。 Patent Document 1 discloses a via array capacitor and a wiring board incorporating the via array capacitor.
a laminate in which a plurality of dielectric layers are stacked;
a first internal electrode layer and a second internal electrode layer that are disposed inside the laminate and face each other with a dielectric layer interposed therebetween;
a plurality of first conductor vias disposed inside the laminate, extending in the lamination direction, and electrically connected to the first internal electrode layers;
a plurality of second conductor vias disposed inside the laminate, extending in the lamination direction, and electrically connected to the second internal electrode layers;
a plurality of first external electrodes arranged on the first main surface and the second main surface of the laminate and connected to the plurality of first conductive vias, respectively;
a plurality of second external electrodes arranged on the first main surface and the second main surface of the laminate and connected to the plurality of second conductive vias, respectively;
Equipped with.

　このビアアレイ型コンデンサを内蔵した配線基板では、ビアアレイ型コンデンサを、配線基板の第１主面側に搭載されるＩＣの電源のデカップリング用コンデンサとして用い、第２主面の第１外部電極および第２外部電極にマザーボード側の電源配線を接続し、第１主面の第１外部電極および第２外部電極にＩＣ側の電源配線を接続する。 In a wiring board incorporating this via array capacitor, the via array capacitor is used as a decoupling capacitor for the power supply of an IC mounted on the first main surface of the wiring board, with the power supply wiring on the motherboard connected to the first and second external electrodes on the second main surface, and the power supply wiring on the IC connected to the first and second external electrodes on the first main surface.

　また、特許文献２には、シリコンコンデンサを含むブリッジダイ、および、シリコンコンデンサを含むブリッジダイを内蔵した基板が開示されている。このコンデンサ内蔵基板では、シリコンコンデンサを、ブリッジダイが跨る２つのＩＣの電源のデカップリング用コンデンサとして用いる。 Patent document 2 also discloses a bridge die including a silicon capacitor, and a substrate incorporating a bridge die including a silicon capacitor. In this capacitor-embedded substrate, the silicon capacitor is used as a decoupling capacitor for the power supplies of the two ICs that the bridge die spans.

特許第５１３９１７１号公報Patent No. 5139171 米国特許第１０８８６２２８号明細書U.S. Pat. No. 10,886,228

　特許文献１に開示のビアアレイ型コンデンサでは、ＩＣの電源のＤＣ電流は導体ビアを流れるため、ノイズ低減効果が低い。例えば、ＩＣで発生するノイズがマザーボードに伝わりＩＣパッケージの外部に放射される。また、例えば、マザーボードからのノイズがＩＣに伝わりＩＣが誤動作することがある。 In the via array type capacitor disclosed in Patent Document 1, the DC current of the IC's power supply flows through conductive vias, resulting in a low noise reduction effect. For example, noise generated in the IC is transmitted to the motherboard and radiated outside the IC package. Furthermore, noise from the motherboard may be transmitted to the IC, causing it to malfunction.

　また、特許文献２に開示のコンデンサ内蔵基板では、一方のＩＣで発生するノイズが電源配線を伝搬して他方のＩＣに伝わり、他方のＩＣが誤動作することがある。 Furthermore, with the capacitor-embedded board disclosed in Patent Document 2, noise generated in one IC can propagate through the power supply wiring and be transmitted to the other IC, causing the other IC to malfunction.

　本発明は、ノイズ低減効果を高めたコンデンサ内蔵基板および多端子コンデンサを提供することを目的とする。 The present invention aims to provide a capacitor-embedded substrate and a multi-terminal capacitor with enhanced noise reduction effects.

　本願発明者らは、鋭意検討の結果、ノイズを低減ための、電源配線に対する多端子コンデンサの接続方法を新たに見出した。具体的には、本願発明者らは、電源配線の間に直列に多端子コンデンサの内部電極層を介在させ、電源のＤＣ電流が多端子コンデンサの内部電極層を流れるようにすることにより、ノイズを低減することができることを見出した。
　そこで、このような多端子コンデンサの接続を実現するための多端子コンデンサの新たな構成、および、その多端子コンデンサを内蔵する基板を、以下に考案する。なお、以下の多端子コンデンサ内蔵基板の考案は、特許文献１に記載のような従来の多端子コンデンサの新たな接続構造の考案をも含むものである。 As a result of extensive research, the present inventors have discovered a new method for connecting a multi-terminal capacitor to a power supply wiring to reduce noise. Specifically, the present inventors have discovered that noise can be reduced by connecting the internal electrode layers of the multi-terminal capacitor in series between the power supply wirings and allowing the DC current of the power supply to flow through the internal electrode layers of the multi-terminal capacitor.
Therefore, a new configuration for a multi-terminal capacitor that realizes such a connection of the multi-terminal capacitor and a substrate that incorporates the multi-terminal capacitor are proposed below. Note that the invention of the following multi-terminal capacitor-embedded substrate also includes the invention of a new connection structure for the conventional multi-terminal capacitor as described in Patent Document 1.

　本発明に係るコンデンサ内蔵基板は、ＩＣが搭載される基板であって、内部に埋め込まれており、互いに対向する第１内部電極層および第２内部電極層を有し、少なくとも５つの端子を有する多端子コンデンサを備え、前記ＩＣの電源のＤＣ電流の少なくとも一部が、前記多端子コンデンサの前記第１内部電極層を流れるように、前記ＩＣに対して前記多端子コンデンサが接続される。 The capacitor-embedded substrate of the present invention is a substrate on which an IC is mounted, and is equipped with a multi-terminal capacitor embedded therein, having first and second internal electrode layers facing each other, and having at least five terminals, and the multi-terminal capacitor is connected to the IC so that at least a portion of the DC current of the power supply for the IC flows through the first internal electrode layer of the multi-terminal capacitor.

　本発明に係る多端子コンデンサは、
　複数の誘電体層が積層され、積層方向に対向する第１主面および第２主面を有する積層体と、
　前記積層体の内部に配置され、前記複数の誘電体層のうちの少なくとも１つの誘電体層を挟んで前記積層方向に対向する第１内部電極層および第２内部電極層と、
　前記積層体の内部に配置され、前記積層方向に延在し、前記第１内部電極層に電気的に接続され、前記第２内部電極層に対して電気的に絶縁された複数の第１導体ビアと、
　前記積層体の内部に配置され、前記積層方向に延在し、前記第１内部電極層に対して電気的に絶縁され、前記第２内部電極層に電気的に接続された複数の第２導体ビアと、
　前記第１主面および前記第２主面の少なくとも一方に配置され、前記複数の第１導体ビアにそれぞれ接続された複数の第１外部電極と、
　前記第１主面および前記第２主面の少なくとも一方に配置され、前記複数の第２導体ビアにそれぞれ接続された複数の第２外部電極と、
を備え、
　前記複数の第１導体ビアは、
　　前記第１主面まで延在せず、前記第１主面において前記複数の第１外部電極のうちの１つに接続されておらず、前記第２主面まで延在し、前記第２主面において前記複数の第１外部電極のうちの１つに接続されている第１主面非接続導体ビアと、
　　前記第１主面まで延在し、前記第１主面において前記複数の第１外部電極のうちの１つに接続されており、前記第２主面まで延在せず、前記第２主面において前記複数の第１外部電極のうちの１つに接続されていない第２主面非接続導体ビアと、
を含み、
　前記複数の第２導体ビアの各々は、前記第１主面から前記第２主面まで延在し、前記第１主面および前記第２主面において前記複数の第２外部電極のうちの１つにそれぞれ接続されている。 The multi-terminal capacitor according to the present invention comprises:
a laminate in which a plurality of dielectric layers are stacked, the laminate having a first main surface and a second main surface opposing each other in a stacking direction;
a first internal electrode layer and a second internal electrode layer that are disposed inside the laminate and that face each other in the lamination direction with at least one dielectric layer of the plurality of dielectric layers interposed therebetween;
a plurality of first conductor vias disposed inside the laminate, extending in the lamination direction, electrically connected to the first internal electrode layers, and electrically insulated from the second internal electrode layers;
a plurality of second conductor vias disposed inside the laminate, extending in the stacking direction, electrically insulated from the first internal electrode layers, and electrically connected to the second internal electrode layers;
a plurality of first external electrodes disposed on at least one of the first main surface and the second main surface and connected to the plurality of first conductive vias, respectively;
a plurality of second external electrodes disposed on at least one of the first main surface and the second main surface and connected to the plurality of second conductive vias, respectively;
Equipped with
The plurality of first conductive vias are
a first-main-surface unconnected conductor via that does not extend to the first main surface and is not connected to one of the plurality of first external electrodes on the first main surface, and that extends to the second main surface and is connected to one of the plurality of first external electrodes on the second main surface;
a second-main-surface unconnected conductor via that extends to the first main surface and is connected to one of the plurality of first external electrodes on the first main surface, but does not extend to the second main surface and is not connected to one of the plurality of first external electrodes on the second main surface;
Including,
Each of the plurality of second conductive vias extends from the first principal surface to the second principal surface, and is connected to one of the plurality of second external electrodes on the first principal surface and the second principal surface.

　本発明に係る他の多端子コンデンサは、
　複数の誘電体層が積層され、積層方向に対向する第１主面および第２主面を有する積層体と、
　前記積層体の内部に配置され、前記複数の誘電体層のうちの少なくとも１つの誘電体層を挟んで前記積層方向に対向する第１内部電極層および第２内部電極層と、
　前記積層体の内部に配置され、前記積層方向に延在し、前記第１内部電極層に電気的に接続され、前記第２内部電極層に対して電気的に絶縁された複数の第１導体ビアと、
　前記積層体の内部に配置され、前記積層方向に延在し、前記第１内部電極層に対して電気的に絶縁され、前記第２内部電極層に電気的に接続された複数の第２導体ビアと、
　前記第１主面および前記第２主面の少なくとも一方に配置され、前記複数の第１導体ビアにそれぞれ接続された複数の第１外部電極と、
　前記第１主面および前記第２主面の少なくとも一方に配置され、前記複数の第２導体ビアにそれぞれ接続された複数の第２外部電極と、
を備え、
　前記複数の第１導体ビアは、
　　前記第１主面から前記第２主面に延在し、前記第１主面および前記第２主面において前記複数の第１外部電極のうちの１つにそれぞれ接続されている導体ビアと、
　　前記第１主面まで延在し、前記第１主面において前記複数の第１外部電極のうちの１つに接続されており、前記第２主面まで延在せず、前記第２主面において前記複数の第１外部電極のうちの１つに接続されていない第２主面非接続導体ビアと、
を含み、
　前記複数の第２導体ビアの各々は、前記第１主面から前記第２主面に延在し、前記第１主面および前記第２主面において前記複数の第２外部電極のうちの１つにそれぞれ接続されている。 Another multi-terminal capacitor according to the present invention comprises:
a laminate in which a plurality of dielectric layers are stacked, the laminate having a first main surface and a second main surface opposing each other in a stacking direction;
a first internal electrode layer and a second internal electrode layer that are disposed inside the laminate and that face each other in the lamination direction with at least one dielectric layer of the plurality of dielectric layers interposed therebetween;
a plurality of first conductor vias disposed inside the laminate, extending in the lamination direction, electrically connected to the first internal electrode layers, and electrically insulated from the second internal electrode layers;
a plurality of second conductor vias disposed inside the laminate, extending in the stacking direction, electrically insulated from the first internal electrode layers, and electrically connected to the second internal electrode layers;
a plurality of first external electrodes disposed on at least one of the first main surface and the second main surface and connected to the plurality of first conductive vias, respectively;
a plurality of second external electrodes disposed on at least one of the first main surface and the second main surface and connected to the plurality of second conductive vias, respectively;
Equipped with
The plurality of first conductive vias are
conductor vias extending from the first main surface to the second main surface and connected to one of the plurality of first external electrodes on the first main surface and the second main surface, respectively;
a second-main-surface unconnected conductor via that extends to the first main surface and is connected to one of the plurality of first external electrodes on the first main surface, but does not extend to the second main surface and is not connected to one of the plurality of first external electrodes on the second main surface;
Including,
Each of the plurality of second conductor vias extends from the first main surface to the second main surface and is connected to one of the plurality of second external electrodes on the first main surface and the second main surface.

　また、本願発明者らは、鋭意検討の結果、ノイズを低減ための、電源配線に対する多端子コンデンサの接続方法を新たに見出した。具体的には、本願発明者らは、電源配線の間に直列に多端子コンデンサの内部電極層を介在させ、電源のＡＣ電流が多端子コンデンサの内部電極層を流れるようにすることにより、ノイズを低減することができることを見出した。
　そこで、このような多端子コンデンサの接続を実現するための多端子コンデンサを内蔵する基板を、以下に考案する。 Furthermore, as a result of extensive research, the inventors have discovered a new method for connecting a multi-terminal capacitor to a power supply wiring to reduce noise. Specifically, the inventors have discovered that noise can be reduced by connecting the internal electrode layers of the multi-terminal capacitor in series between the power supply wirings and allowing the AC current of the power supply to flow through the internal electrode layers of the multi-terminal capacitor.
Therefore, a substrate incorporating a multi-terminal capacitor to realize such a multi-terminal capacitor connection is devised below.

　本発明に係るコンデンサ内蔵基板は、２つのＩＣが搭載される基板であって、内部に埋め込まれており、互いに対向する第１内部電極層および第２内部電極層を有し、少なくとも５つの端子を有する多端子コンデンサを備え、前記２つのＩＣ間を伝搬する電源のＡＣ電流の少なくとも一部が、前記多端子コンデンサの前記第１内部電極層を流れるように、前記２つのＩＣに対して前記多端子コンデンサが接続される。 The capacitor-embedded substrate of the present invention is a substrate on which two ICs are mounted, and is equipped with a multi-terminal capacitor having at least five terminals, embedded internally and having first and second internal electrode layers that face each other, and is connected to the two ICs so that at least a portion of the AC current of the power supply propagating between the two ICs flows through the first internal electrode layer of the multi-terminal capacitor.

　本発明に係る他のコンデンサ内蔵基板は、２つのＩＣ間に跨って配置されるブリッジ型の基板であって、互いに対向する第１内部電極層および第２内部電極層を有し、少なくとも５つの端子を有する多端子コンデンサを備え、前記２つのＩＣ間を伝搬する電源のＡＣ電流の少なくとも一部が、前記多端子コンデンサの前記第１内部電極層を流れるように、前記２つのＩＣに対して前記多端子コンデンサが接続される。 Another capacitor-embedded substrate according to the present invention is a bridge-type substrate placed across two ICs, having first and second internal electrode layers facing each other, and including a multi-terminal capacitor with at least five terminals, the multi-terminal capacitor being connected to the two ICs so that at least a portion of the AC current of the power supply propagating between the two ICs flows through the first internal electrode layer of the multi-terminal capacitor.

　本発明によれば、ＩＣパッケージ技術において、ノイズ低減効果を高めることができる。 This invention can improve noise reduction effects in IC packaging technology.

第１実施形態に係る多端子コンデンサの断面模式図である。1 is a schematic cross-sectional view of a multi-terminal capacitor according to a first embodiment. 第２実施形態に係る多端子コンデンサの断面模式図である。FIG. 10 is a schematic cross-sectional view of a multi-terminal capacitor according to a second embodiment. 従来の多端子コンデンサの断面模式図である。FIG. 1 is a cross-sectional view of a conventional multi-terminal capacitor. 図１Ａに示す多端子コンデンサにおける第１内部電極層の平面図である。FIG. 1B is a plan view of a first internal electrode layer in the multi-terminal capacitor shown in FIG. 1A. 図１Ａに示す多端子コンデンサにおける第２内部電極層の平面図である。FIG. 1B is a plan view of a second internal electrode layer in the multi-terminal capacitor shown in FIG. 1A. 本発明のコンデンサ内蔵基板における図１Ａの本発明の多端子コンデンサの接続構造の一例を示す断面模式図である。1B is a cross-sectional view schematically illustrating an example of a connection structure of the multi-terminal capacitor of the present invention shown in FIG. 1A in a capacitor-embedded substrate of the present invention. FIG. 本発明のコンデンサ内蔵基板における図１Ｂの本発明の多端子コンデンサの接続構造の一例を示す断面模式図である。2 is a cross-sectional view showing an example of a connection structure of the multi-terminal capacitor of the present invention shown in FIG. 1B in a capacitor-embedded substrate of the present invention. FIG. 本発明のコンデンサ内蔵基板における多端子コンデンサの接続構造の一例を示す断面模式図である。1 is a cross-sectional view schematically illustrating an example of a connection structure of a multi-terminal capacitor in a capacitor-embedded substrate according to the present invention. 本発明のコンデンサ内蔵基板における図１Ｂの本発明の多端子コンデンサの接続構造の一例を示す断面模式図である。2 is a cross-sectional view showing an example of a connection structure of the multi-terminal capacitor of the present invention shown in FIG. 1B in a capacitor-embedded substrate of the present invention. FIG. 本発明のコンデンサ内蔵基板における多端子コンデンサの接続構造の一例を示す断面模式図である。1 is a cross-sectional view schematically illustrating an example of a connection structure of a multi-terminal capacitor in a capacitor-embedded substrate according to the present invention. 本発明のコンデンサ内蔵基板における多端子コンデンサの接続構造の一例を示す断面模式図である。1 is a cross-sectional view schematically illustrating an example of a connection structure of a multi-terminal capacitor in a capacitor-embedded substrate according to the present invention. 従来のコンデンサ内蔵基板における図１Ｃの従来の多端子コンデンサの接続構造の一例を示す断面模式図である。1D is a cross-sectional view showing an example of a connection structure of the conventional multi-terminal capacitor of FIG. 1C in a conventional capacitor-embedded substrate. FIG. 図４Ａに示す接続構造の図１Ａの本発明の多端子コンデンサの各部電流を示す模式図である。4B is a schematic diagram showing currents at each part of the multi-terminal capacitor of the present invention shown in FIG. 1A in the connection structure shown in FIG. 4A. 図４Ｂに示す接続構造の図１Ｂの本発明の多端子コンデンサの各部電流を示す模式図である。4B is a schematic diagram showing the current flow at each part of the multi-terminal capacitor of the present invention shown in FIG. 1B in the connection structure shown in FIG. 4B. 図４Ｄに示す接続構造の図１Ｂの本発明の多端子コンデンサの各部電流を示す模式図である。4D is a schematic diagram showing the current flow at each part of the multi-terminal capacitor of the present invention shown in FIG. 1B in the connection structure shown in FIG. 図４Ｇに示す接続構造の図１Ｃの従来の多端子コンデンサの各部電流を示す模式図である。4G is a schematic diagram showing currents at each part of the conventional multi-terminal capacitor of FIG. 1C having the connection structure shown in FIG. 4G. 第１実施形態、後述する第２実施形態および従来の多端子コンデンサの電力通過特性Ｓ２１のシミュレーション結果である。10 shows simulation results of power passing characteristics S21 of the first embodiment, the second embodiment described later, and a conventional multi-terminal capacitor. 第１実施形態、後述する第２実施形態および従来の多端子コンデンサのＩＣ側からみたインピーダンス特性Ｚ１１のシミュレーション結果である。10 shows simulation results of impedance characteristics Z11 as viewed from the IC side of the first embodiment, the second embodiment described later, and a conventional multi-terminal capacitor. 第１実施形態に係るコンデンサ内蔵基板の断面模式図である。1 is a schematic cross-sectional view of a capacitor-embedded substrate according to a first embodiment. 第２実施形態に係るコンデンサ内蔵基板の断面模式図である。FIG. 10 is a schematic cross-sectional view of a capacitor-embedded substrate according to a second embodiment. 変形例に係る多端子コンデンサの断面模式図である。FIG. 10 is a schematic cross-sectional view of a multi-terminal capacitor according to a modified example. 変形例に係るコンデンサ内蔵基板の断面模式図である。FIG. 10 is a schematic cross-sectional view of a capacitor-embedded substrate according to a modified example. 変形例に係るコンデンサ内蔵基板の断面模式図である。FIG. 10 is a schematic cross-sectional view of a capacitor-embedded substrate according to a modified example.

　以下、添付の図面を参照して本発明の実施形態の一例について説明する。なお、各図面において同一または相当の部分に対しては同一の符号を附すこととする。 An example of an embodiment of the present invention will now be described with reference to the accompanying drawings. Note that the same or equivalent parts in each drawing will be designated by the same reference numerals.

［多端子コンデンサ］
（第１実施形態）
　図１Ａは、第１実施形態に係る多端子コンデンサの断面模式図である。図２は、図１Ａに示す多端子コンデンサにおける第１内部電極層の平面図であり、図３は、図１Ａに示す多端子コンデンサにおける第２内部電極層の平面図である。なお、図１Ａの断面模式図は、図２および図３に示すIA-IA線断面模式図であり、第１導体ビアおよび第２導体ビアの数が省略されている。また、図２および図３でも、第１導体ビアおよび第２導体ビアの数はこれに限定されない。図１Ａに示すように、第１実施形態の多端子コンデンサ１Ａは、積層体１０と、複数の第１内部電極層２１および複数の第２内部電極層２２と、複数の第１導体ビア３１および複数の第２導体ビア３２と、複数の第１外部電極（端子）４１および複数の第２外部電極（端子）４２とを備える。多端子コンデンサ１Ａは、少なくとも５つの端子を有する。 [Multi-terminal capacitor]
(First embodiment)
FIG. 1A is a cross-sectional schematic diagram of a multi-terminal capacitor according to a first embodiment. FIG. 2 is a plan view of a first internal electrode layer in the multi-terminal capacitor shown in FIG. 1A, and FIG. 3 is a plan view of a second internal electrode layer in the multi-terminal capacitor shown in FIG. 1A. Note that the cross-sectional schematic diagram of FIG. 1A is a cross-sectional schematic diagram along line IA-IA shown in FIGS. 2 and 3, and the number of first conductive vias and second conductive vias is omitted. Furthermore, the number of first conductive vias and second conductive vias is not limited to this in FIGS. 2 and 3. As shown in FIG. 1A, the multi-terminal capacitor 1A according to the first embodiment includes a laminate 10, a plurality of first internal electrode layers 21 and a plurality of second internal electrode layers 22, a plurality of first conductive vias 31 and a plurality of second conductive vias 32, a plurality of first external electrodes (terminals) 41 and a plurality of second external electrodes (terminals) 42. The multi-terminal capacitor 1A has at least five terminals.

　積層体１０は、略直方体形状であり、積層方向Ｔに対向する第１主面Ｓ１および第２主面Ｓ２を有する。積層体１０は、積層方向Ｔに積層された複数の誘電体層１２を有する。 The laminate 10 has a substantially rectangular parallelepiped shape and has a first main surface S1 and a second main surface S2 that face each other in the stacking direction T. The laminate 10 has multiple dielectric layers 12 stacked in the stacking direction T.

　誘電体層１２の材料としては、特に限定されないが、例えば、ＢａＴｉＯ_３、ＣａＴｉＯ_３、ＳｒＴｉＯ_３、またはＣａＺｒＯ_３等を主成分として含む誘電体セラミックを用いることができる。また、誘電体層１２の材料としては、Ｍｎ化合物、Ｆｅ化合物、Ｃｒ化合物、Ｃｏ化合物、またはＮｉ化合物等を副成分として添加されてもよい。 The material of the dielectric layer 12 is not particularly limited, but may be, for example, a dielectric ceramic containing BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ , or the like as a main component. The material of the dielectric layer 12 may also contain a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like as a secondary component.

　第１内部電極層２１および第２内部電極層２２は、積層体１０の内部に配置されている。第１内部電極層２１と第２内部電極層２２とは、積層体１０の積層方向Ｔにおいて、交互に配置されており、少なくとも１つの誘電体層１２を挟んで互いに対向している。第１内部電極層２１および第２内部電極層２２の形状は、特に限定されないが、例えば略矩形状である。第１内部電極層２１と第２内部電極層２２とは、静電容量を発生させ実質的にコンデンサとして機能する。 The first internal electrode layers 21 and the second internal electrode layers 22 are arranged inside the laminate 10. The first internal electrode layers 21 and the second internal electrode layers 22 are arranged alternately in the stacking direction T of the laminate 10, and face each other with at least one dielectric layer 12 sandwiched between them. The shapes of the first internal electrode layers 21 and the second internal electrode layers 22 are not particularly limited, but may be, for example, approximately rectangular. The first internal electrode layers 21 and the second internal electrode layers 22 generate electrostatic capacitance and essentially function as a capacitor.

　図２に示すように、第１内部電極層２１は複数の貫通孔２１Ａを有する。また、図３に示すように、第２内部電極層２２は複数の貫通孔２２Ａを有する。第１主面Ｓ１および第２主面Ｓ２に沿う平面視において、貫通孔２１Ａおよび貫通孔２２Ａの各々は略等間隔に並んでおり、貫通孔２１Ａと貫通孔２２Ａとは重ならない。 As shown in FIG. 2, the first internal electrode layer 21 has a plurality of through holes 21A. Furthermore, as shown in FIG. 3, the second internal electrode layer 22 has a plurality of through holes 22A. In a plan view along the first principal surface S1 and the second principal surface S2, the through holes 21A and the through holes 22A are arranged at approximately equal intervals, and the through holes 21A and the through holes 22A do not overlap.

　第１内部電極層２１および第２内部電極層２２は、特に限定されないが、例えば、金属Ｎｉを主成分として含む。また、第１内部電極層２１および第２内部電極層２２は、例えば、Ｃｕ、Ａｇ、Ｐｄ、またはＡｕ等の金属、またはＡｇ－Ｐｄ合金等の、それらの金属の少なくとも一種を含む合金、から選ばれる少なくとも１つを主成分として含んでもよいし、主成分以外の成分として含んでもよい。なお、本明細書において、主成分の金属とは、最も重量％が高い金属成分であると定める。 The first internal electrode layer 21 and the second internal electrode layer 22 are not particularly limited, but may contain, for example, metallic Ni as a main component. Furthermore, the first internal electrode layer 21 and the second internal electrode layer 22 may contain, as a main component, at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as Ag-Pd alloys, or may contain this as a component other than the main component. Note that, in this specification, the main metal component is defined as the metal component with the highest weight percentage.

　第１導体ビア３１および第２導体ビア３２は、積層体１０の内部に配置されており、積層体１０の積層方向Ｔに延在している。第１導体ビア３１は、第１内部電極層２１に電気的に接続されており、第２内部電極層２２に対して貫通孔２２Ａにおいて電気的に絶縁されている。第２導体ビア３２は、第１内部電極層２１に対して貫通孔２１Ａにおいて電気的に絶縁され、第２内部電極層２２に電気的に接続されている。 The first conductor via 31 and the second conductor via 32 are arranged inside the laminate 10 and extend in the stacking direction T of the laminate 10. The first conductor via 31 is electrically connected to the first internal electrode layer 21 and is electrically insulated from the second internal electrode layer 22 at the through hole 22A. The second conductor via 32 is electrically insulated from the first internal electrode layer 21 at the through hole 21A and is electrically connected to the second internal electrode layer 22.

　第１導体ビア３１は、第１主面非接続導体ビア３１Ａと第２主面非接続導体ビア３１Ｂとを含む。第１主面非接続導体ビア３１Ａは、第２主面Ｓ２まで延在し、第２主面Ｓ２に露出し、第２主面Ｓ２において第１外部電極４１に接続されている。一方、第１主面非接続導体ビア３１Ａは、第１主面Ｓ１まで延在せず、第１主面Ｓ１に露出せず、第１主面Ｓ１において第１外部電極４１に接続されていない。 The first conductive vias 31 include a first principal surface unconnected conductive via 31A and a second principal surface unconnected conductive via 31B. The first principal surface unconnected conductive via 31A extends to the second principal surface S2, is exposed on the second principal surface S2, and is connected to the first external electrode 41 on the second principal surface S2. On the other hand, the first principal surface unconnected conductive via 31A does not extend to the first principal surface S1, is not exposed on the first principal surface S1, and is not connected to the first external electrode 41 on the first principal surface S1.

　第２主面非接続導体ビア３１Ｂは、第１主面Ｓ１まで延在し、第１主面Ｓ１に露出し、第１主面Ｓ１において第１外部電極４１に接続されている。一方、第２主面非接続導体ビア３１Ｂは、第２主面Ｓ２まで延在せず、第２主面Ｓ２に露出せず、第２主面Ｓ２において第１外部電極４１に接続されていない。 The second principal surface unconnected conductive via 31B extends to the first principal surface S1, is exposed on the first principal surface S1, and is connected to the first external electrode 41 on the first principal surface S1. On the other hand, the second principal surface unconnected conductive via 31B does not extend to the second principal surface S2, is not exposed on the second principal surface S2, and is not connected to the first external electrode 41 on the second principal surface S2.

　一方、第２導体ビア３２は、第１主面Ｓ１から第２主面Ｓ２まで延在し、第１主面Ｓ１および第２主面Ｓ２に露出し、第１主面Ｓ１および第２主面Ｓ２において第２外部電極４２に接続されている。これにより、ＧＮＤ電位を安定化させることができる。 On the other hand, the second conductor via 32 extends from the first principal surface S1 to the second principal surface S2, is exposed on the first principal surface S1 and the second principal surface S2, and is connected to the second external electrode 42 on the first principal surface S1 and the second principal surface S2. This stabilizes the GND potential.

　第１導体ビア３１と第２導体ビア３２とが交互に隣接して配置され、第１導体ビア３１を流れる電流の方向と、隣接する第２導体ビア３２を流れる電流の方向とが逆であるため、第１導体ビア３１を流れる電流が発生させる磁界と、隣接する第２導体ビア３２を流れる電流が発生させる磁界とが相殺され、等価直列インダクタンスＥＳＬが低減される。 The first conductor vias 31 and the second conductor vias 32 are arranged alternately adjacent to each other, and the direction of the current flowing through the first conductor via 31 is opposite to the direction of the current flowing through the adjacent second conductor via 32. This causes the magnetic field generated by the current flowing through the first conductor via 31 to cancel out, reducing the equivalent series inductance ESL.

　第１導体ビア３１および第２導体ビア３２は、特に限定されないが、例えば、第１内部電極層２１および第２内部電極層２２と同様に、金属Ｎｉを主成分として含む。また、第１導体ビア３１および第２導体ビア３２は、例えば、Ｃｕ、Ａｇ、Ｐｄ、またはＡｕ等の金属、またはＡｇ－Ｐｄ合金等の、それらの金属の少なくとも一種を含む合金、から選ばれる少なくとも１つを主成分として含んでもよいし、主成分以外の成分として含んでもよい。 The first conductor via 31 and the second conductor via 32 are not particularly limited, but may contain, for example, metal Ni as a main component, similar to the first internal electrode layer 21 and the second internal electrode layer 22. Furthermore, the first conductor via 31 and the second conductor via 32 may contain, as a main component, or as a component other than the main component, at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

　なお、図１Ａ、図２および図３、および後述する図面は模式図であり、第１導体ビア３１および第２導体ビア３２の数はこれに限定されない。 Note that Figures 1A, 2, and 3, as well as the drawings described below, are schematic diagrams, and the number of first conductor vias 31 and second conductor vias 32 is not limited to these.

　第１外部電極（端子）４１は、第２主面Ｓ２における第１主面非接続導体ビア３１Ａの位置に配置され、第１導体ビア３１の第１主面非接続導体ビア３１Ａに接続されている。また、第１外部電極４１は、第１主面Ｓ１における第２主面非接続導体ビア３１Ｂの位置に配置され、第１導体ビア３１の第２主面非接続導体ビア３１Ｂに接続されている。第２外部電極（端子）４２は、第１主面Ｓおよび第２主面Ｓ２における第２導体ビア３２の位置に配置され、第２導体ビア３２に接続されている。 The first external electrode (terminal) 41 is arranged at the position of the first-main-surface unconnected conductor via 31A on the second main surface S2 and is connected to the first-main-surface unconnected conductor via 31A of the first conductor via 31. The first external electrode 41 is arranged at the position of the second-main-surface unconnected conductor via 31B on the first main surface S1 and is connected to the second-main-surface unconnected conductor via 31B of the first conductor via 31. The second external electrode (terminal) 42 is arranged at the position of the second conductor via 32 on the first main surface S and the second main surface S2 and is connected to the second conductor via 32.

　第１主面Ｓ１における第１外部電極４１の数と、第２主面Ｓ２における第１外部電極４１の数とは、異なっていてもよい。また、第１外部電極４１は、第１主面Ｓ１および第２主面Ｓ２に埋め込まれていてもよいし、第２外部電極４２は、第１主面Ｓ１および第２主面Ｓ２に埋め込まれていてもよい。 The number of first external electrodes 41 on the first principal surface S1 may be different from the number of first external electrodes 41 on the second principal surface S2. Furthermore, the first external electrodes 41 may be embedded in the first principal surface S1 and the second principal surface S2, and the second external electrodes 42 may be embedded in the first principal surface S1 and the second principal surface S2.

　第１外部電極４１および第２外部電極４２は、特に限定されないが、例えば、金属Ｃｕを主成分として含む。また、第１外部電極４１および第２外部電極４２は、例えば、Ｎｉ、Ａｇ、Ｐｄ、またはＡｕ等の金属、またはＡｇ－Ｐｄ合金等の合金、から選ばれる少なくとも１つを主成分として含んでもよいし、主成分以外の成分として含んでもよい。第１外部電極４１および第２外部電極４２は、焼成膜、蒸着膜、またはめっき膜で形成された導体パッドである。なお、第１外部電極４１および第２外部電極４２は、導体パッド上に形成された導体バンプを含んでいてもよい。 The first external electrode 41 and the second external electrode 42 are not particularly limited, but may contain, for example, metal Cu as a main component. Furthermore, the first external electrode 41 and the second external electrode 42 may contain, as a main component, at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, or may contain this as a component other than the main component. The first external electrode 41 and the second external electrode 42 are conductor pads formed from a fired film, a vapor-deposited film, or a plated film. The first external electrode 41 and the second external electrode 42 may also include conductor bumps formed on the conductor pads.

　ここで、特許文献１に開示のように、従来の多端子コンデンサについて説明する。図１Ｃは、従来の多端子コンデンサの断面模式図である。図１Ｃに示す従来の多端子コンデンサ１Ｘは、図１Ａに示す第１実施形態の多端子コンデンサ１Ａにおいて、第１導体ビア３１、すなわち第１主面非接続導体ビア３１Ａおよび第２主面非接続導体ビア３１Ｂに代えて、第１導体ビア３１Ｘを備える点で異なる。第１導体ビア３１Ｘは、第１主面Ｓ１から第２主面Ｓ２まで延在し、第１主面Ｓ１および第２主面Ｓ２に露出し、第１主面Ｓ１および第２主面Ｓ２において第１外部電極４１に接続されている。 Here, a conventional multi-terminal capacitor as disclosed in Patent Document 1 will be described. Figure 1C is a schematic cross-sectional view of a conventional multi-terminal capacitor. The conventional multi-terminal capacitor 1X shown in Figure 1C differs from the multi-terminal capacitor 1A of the first embodiment shown in Figure 1A in that it includes first conductor vias 31X instead of the first conductor vias 31, i.e., the first main surface unconnected conductor vias 31A and the second main surface unconnected conductor vias 31B. The first conductor vias 31X extend from the first main surface S1 to the second main surface S2, are exposed on the first main surface S1 and the second main surface S2, and are connected to the first external electrodes 41 on the first main surface S1 and the second main surface S2.

　図４Ｇは、従来のコンデンサ内蔵基板における図１Ｃの従来の多端子コンデンサの接続構造の一例を示す断面模式図である。図４Ｇに示すように、多端子コンデンサ１Ｘの第２主面Ｓ２の第１導体ビア３１Ｘおよび第２導体ビア３２がマザーボード側の電源配線ＶＤＤおよびＶＳＳに接続され、多端子コンデンサ１Ｘの第１主面Ｓ１の第１導体ビア３１Ｘおよび第２導体ビア３２がＩＣ側の電源配線ＶＤＤおよびＶＳＳに接続される。このとき、多端子コンデンサ１Ｘには、矢印で示すように電流が流れる。 Figure 4G is a schematic cross-sectional view showing an example of the connection structure of the conventional multi-terminal capacitor of Figure 1C in a conventional capacitor-embedded substrate. As shown in Figure 4G, the first conductive via 31X and second conductive via 32 on the second main surface S2 of the multi-terminal capacitor 1X are connected to the power supply wiring VDD and VSS on the motherboard side, and the first conductive via 31X and second conductive via 32 on the first main surface S1 of the multi-terminal capacitor 1X are connected to the power supply wiring VDD and VSS on the IC side. At this time, current flows through the multi-terminal capacitor 1X as shown by the arrows.

　図５Ｄは、図４Ｇに示す接続構造の図１Ｃの従来の多端子コンデンサの各部（１）～（３）における電流を示す模式図である。なお、図５Ｄは模式図であり、第１導体ビア３１および第２導体ビア３２の数が省略されている。各部（１）～（３）は、図４Ｄに示すように、（１）多端子コンデンサ１Ｘの第１導体ビア３１の第２主面Ｓ２近傍、（２）多端子コンデンサ１Ｘの第１内部電極層２１、（３）多端子コンデンサ１Ｘの第１導体ビア３１の第１主面Ｓ１近傍である。図５Ｄには、（１）多端子コンデンサ１Ｘの第１導体ビア３１の第２主面Ｓ２近傍に流れるＤＣ電流と、（２）多端子コンデンサ１Ｘの第１内部電極層２１に流れるＤＣ電流と、（２）多端子コンデンサ１Ｘの第１内部電極層２１に流れるＩＣ側からのＡＣ電流と、（３）多端子コンデンサ１Ｘの第１導体ビア３１の第１主面Ｓ１近傍に流れるＤＣ電流とが示されている。 Figure 5D is a schematic diagram showing the currents in each portion (1) to (3) of the conventional multi-terminal capacitor of Figure 1C having the connection structure shown in Figure 4G. Note that Figure 5D is a schematic diagram, and the number of first conductor vias 31 and second conductor vias 32 has been omitted. As shown in Figure 4D, each portion (1) to (3) is (1) the vicinity of the second main surface S2 of the first conductor via 31 of the multi-terminal capacitor 1X, (2) the first internal electrode layer 21 of the multi-terminal capacitor 1X, and (3) the vicinity of the first main surface S1 of the first conductor via 31 of the multi-terminal capacitor 1X. FIG. 5D shows (1) DC current flowing near the second main surface S2 of the first conductive via 31 of the multi-terminal capacitor 1X, (2) DC current flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1X, (3) AC current from the IC side flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1X, and (3) DC current flowing near the first main surface S1 of the first conductive via 31 of the multi-terminal capacitor 1X.

　図５Ｄの（１）に示すように、多端子コンデンサ１Ｘでは、全ての第１導体ビア３１に電流が入力され、図５Ｄの（３）に示すように、多端子コンデンサ１Ｘでは、全ての第１導体ビア３１から電流が出力される。 As shown in (1) of Figure 5D, in the multi-terminal capacitor 1X, current is input to all of the first conductor vias 31, and as shown in (3) of Figure 5D, in the multi-terminal capacitor 1X, current is output from all of the first conductor vias 31.

　図５Ｄの（２）ＩＣ側からのＡＣ電流に示すように、多端子コンデンサ１Ｘでは、ＩＣ側からのＡＣ電流は、第１導体ビア３１から隣接する第２導体ビア３２に向けて第１内部電極層２１を流れる。これにより、ノイズ低減効果が得られる。一方、図５Ｄの（２）ＤＣ電流に示すように、多端子コンデンサ１Ｘでは、ＤＣ電流は、第１導体ビア３１のみを通過し、第１内部電極層２１には流れない。 As shown in Figure 5D (2) AC current from the IC side, in the multi-terminal capacitor 1X, the AC current from the IC side flows through the first internal electrode layer 21 from the first conductor via 31 toward the adjacent second conductor via 32. This achieves a noise reduction effect. On the other hand, as shown in Figure 5D (2) DC current, in the multi-terminal capacitor 1X, the DC current passes only through the first conductor via 31 and does not flow through the first internal electrode layer 21.

　この従来の多端子コンデンサ１Ｘでは、ＤＣ電流は、第１導体ビア３１Ｘのみを流れるため、ノイズ低減効果が低い。例えば、ＩＣで発生するノイズがマザーボードに伝わりＩＣパッケージの外部に放射される。また、例えば、マザーボードからのノイズがＩＣに伝わりＩＣが誤動作することがある。 In this conventional multi-terminal capacitor 1X, DC current flows only through the first conductive via 31X, resulting in a low noise reduction effect. For example, noise generated in the IC is transmitted to the motherboard and radiated outside the IC package. Furthermore, noise from the motherboard may be transmitted to the IC, causing the IC to malfunction.

　図４Ａは、本発明のコンデンサ内蔵基板における図１Ａの本発明の多端子コンデンサの接続構造の一例を示す断面模式図である。図４Ａに示すように、多端子コンデンサ１Ａの第２主面Ｓ２の第１導体ビア３１の第１主面非接続導体ビア３１Ａおよび第２導体ビア３２がマザーボードの電源配線ＶＤＤおよびＶＳＳに接続され、多端子コンデンサ１Ａの第１主面Ｓ１の第１導体ビア３１の第２主面非接続導体ビア３１Ｂおよび第２導体ビア３２がＩＣの電源配線ＶＤＤおよびＶＳＳに接続される。このとき、多端子コンデンサ１Ａには、矢印で示すように電流が流れる。 FIG. 4A is a cross-sectional schematic diagram showing an example of the connection structure of the multi-terminal capacitor of FIG. 1A in a capacitor-embedded substrate of the present invention. As shown in FIG. 4A, first-main-surface unconnected conductor vias 31A and second conductor vias 32 of the first conductor vias 31 on the second main surface S2 of multi-terminal capacitor 1A are connected to the power supply wiring VDD and VSS of the motherboard, and second-main-surface unconnected conductor vias 31B and second conductor vias 32 of the first conductor vias 31 on the first main surface S1 of multi-terminal capacitor 1A are connected to the power supply wiring VDD and VSS of the IC. At this time, current flows through multi-terminal capacitor 1A as shown by the arrows.

　図５Ａは、図４Ａに示す接続構造の第１実施形態の多端子コンデンサの各部（１）～（３）における電流を示す模式図である。なお、図５Ａは模式図であり、第１導体ビア３１および第２導体ビア３２の数が省略されている。各部（１）～（３）は、図４Ａに示すように、（１）多端子コンデンサ１Ａの第１導体ビア３１の第１主面非接続導体ビア３１Ａの第２主面Ｓ２近傍、（２）多端子コンデンサ１Ａの第１内部電極層２１、（３）多端子コンデンサ１Ａの第１導体ビア３１の第２主面非接続導体ビア３１Ｂの第１主面Ｓ１近傍である。図５Ａには、（１）多端子コンデンサ１Ａの第１導体ビア３１の第１主面非接続導体ビア３１Ａの第２主面Ｓ２近傍に流れるＤＣ電流と、（２）多端子コンデンサ１Ａの第１内部電極層２１に流れるＤＣ電流と、（２）多端子コンデンサ１Ａの第１内部電極層２１に流れるＩＣ側からのＡＣ電流と、（３）多端子コンデンサ１Ａの第１導体ビア３１の第２主面非接続導体ビア３１Ｂの第１主面Ｓ１近傍に流れるＤＣ電流とが示されている。 Figure 5A is a schematic diagram showing the current in each portion (1) to (3) of the multi-terminal capacitor of the first embodiment of the connection structure shown in Figure 4A. Note that Figure 5A is a schematic diagram, and the number of first conductor vias 31 and second conductor vias 32 has been omitted. As shown in Figure 4A, each portion (1) to (3) is: (1) the vicinity of the second main surface S2 of the first main surface unconnected conductor via 31A of the first conductor via 31 of the multi-terminal capacitor 1A; (2) the first internal electrode layer 21 of the multi-terminal capacitor 1A; and (3) the vicinity of the first main surface S1 of the second main surface unconnected conductor via 31B of the first conductor via 31 of the multi-terminal capacitor 1A. FIG. 5A shows (1) a DC current flowing near the second main surface S2 of the first main surface unconnected conductor via 31A of the first conductive via 31 of the multi-terminal capacitor 1A, (2) a DC current flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1A, (3) an AC current from the IC side flowing in the first internal electrode layer 21 of the multi-terminal capacitor 1A, and (3) a DC current flowing near the first main surface S1 of the second main surface unconnected conductor via 31B of the first conductive via 31 of the multi-terminal capacitor 1A.

　図５Ａの（１）に示すように、多端子コンデンサ１Ａでは、第１導体ビア３１における第１主面非接続導体ビア３１Ａに電流が入力され、図５Ａの（３）に示すように、多端子コンデンサ１Ａでは、第１導体ビア３１における第２主面非接続導体ビア３１Ｂから電流が出力される。なお、第１実施形態の多端子コンデンサ１Ａでは、従来の多端子コンデンサ１Ｘと比較して、第２主面Ｓ２側の入力の第１導体ビア３１の数が減少し、第１主面Ｓ１側の出力の第１導体ビア３１の数が減少する。 As shown in (1) of Figure 5A, in the multi-terminal capacitor 1A, current is input to the first main surface unconnected conductive vias 31A of the first conductive vias 31, and as shown in (3) of Figure 5A, in the multi-terminal capacitor 1A, current is output from the second main surface unconnected conductive vias 31B of the first conductive vias 31. Note that in the multi-terminal capacitor 1A of the first embodiment, the number of first conductive vias 31 at the input on the second main surface S2 side is reduced, and the number of first conductive vias 31 at the output on the first main surface S1 side is reduced, compared to the conventional multi-terminal capacitor 1X.

　図５Ａの（２）ＩＣ側からのＡＣ電流に示すように、多端子コンデンサ１Ａでは、ＩＣ側からのＡＣ電流は、第１導体ビア３１から隣接する第２導体ビア３２に向けて第１内部電極層２１を流れる。これにより、ノイズ低減効果が得られる。例えば、ＩＣで発生するノイズ、マザーボードからのノイズが低減される。なお、第１実施形態の多端子コンデンサ１Ａでは、従来の多端子コンデンサ１Ｘと比較して、ＡＣ電流経路が減少する。 As shown in (2) AC current from the IC side in Figure 5A, in the multi-terminal capacitor 1A, the AC current from the IC side flows through the first internal electrode layer 21 from the first conductive via 31 toward the adjacent second conductive via 32. This provides a noise reduction effect. For example, noise generated by the IC and noise from the motherboard are reduced. Note that in the multi-terminal capacitor 1A of the first embodiment, the AC current path is reduced compared to the conventional multi-terminal capacitor 1X.

　一方、図５Ａの（２）ＤＣ電流に示すように、多端子コンデンサ１Ａでは、ＤＣ電流は、第１導体ビア３１の第１主面非接続導体ビア３１Ａから第２主面非接続導体ビア３１Ｂに向けて第１内部電極層２１を流れる。これにより、ノイズ低減効果を高めることができる。例えば、ＩＣで発生するノイズ、マザーボードからのノイズが低減される。 On the other hand, as shown in (2) DC current in Figure 5A, in the multi-terminal capacitor 1A, DC current flows through the first internal electrode layer 21 from the first main surface unconnected conductive via 31A of the first conductive via 31 to the second main surface unconnected conductive via 31B. This enhances the noise reduction effect. For example, noise generated in the IC and noise from the motherboard are reduced.

　このように、第１実施形態の多端子コンデンサ１Ａによれば、電源配線の間に直列に第１内部電極層２１を介在させ、電源のＤＣ電流が第１内部電極層２１を流れるようにする。これにより、ノイズ低減効果を高めることができる。例えば、ＩＣで発生するノイズがマザーボードに伝わりＩＣパッケージの外部に放射されることを抑制することができる。また、例えば、マザーボードからのノイズがＩＣに伝わりＩＣが誤動作することを抑制することができる。 In this way, with the multi-terminal capacitor 1A of the first embodiment, the first internal electrode layer 21 is interposed in series between the power supply wiring, allowing the DC current of the power supply to flow through the first internal electrode layer 21. This enhances the noise reduction effect. For example, it is possible to prevent noise generated in the IC from being transmitted to the motherboard and radiated outside the IC package. It is also possible to prevent noise from the motherboard from being transmitted to the IC and causing the IC to malfunction.

　以下では、上述した効果についてシミュレーションにて考察する。図６Ａは、第１実施形態、後述する第２実施形態および従来の多端子コンデンサの電力通過特性Ｓ２１のシミュレーション結果であり、図６Ｂは、第１実施形態、後述する第２実施形態および従来の多端子コンデンサのＩＣ側からみたインピーダンス特性Ｚ１１のシミュレーション結果である。 Below, the above-mentioned effects are considered through simulation. Figure 6A shows the simulation results of the power passing characteristics S21 of the first embodiment, the second embodiment described below, and a conventional multi-terminal capacitor, and Figure 6B shows the simulation results of the impedance characteristics Z11 as viewed from the IC side of the first embodiment, the second embodiment described below, and a conventional multi-terminal capacitor.

　シミュレーションでは、３次元電磁界解析ツールＡｎｓｙｓＨＦＳＳを用い、電力通過特性Ｓ２１およびＩＣ側からみたインピーダンス特性Ｚ１１を得た。シミュレーヨンにおける各部の材料の設定は以下の通りである。
誘電体層：ＢａＴｉＯ_３
第１内部電極層および第２内部電極層：Ｎｉ
第１導体ビアおよび第２導体ビア：Ｎｉ
第１外部電極および第２外部電極：Ｎｉ In the simulation, a three-dimensional electromagnetic field analysis tool Ansys HFSS was used to obtain the power passing characteristic S21 and the impedance characteristic Z11 seen from the IC side. The materials used in the simulation were as follows:
Dielectric layer: _BaTiO3
First internal electrode layer and second internal electrode layer: Ni
First conductor via and second conductor via: Ni
First external electrode and second external electrode: Ni

　図６Ａに示すように、従来の多端子コンデンサ１Ｘと比較して、第１実施形態の多端子コンデンサ１Ａの電力通過特性Ｓ２１が、高周波数側において低い。これによれば、従来の多端子コンデンサ１Ｘと比較して、第１実施形態の多端子コンデンサ１Ａのノイズ低減効果が高いことがわかる（ノイズフィルタ効果）。 As shown in Figure 6A, the power passing characteristics S21 of the multi-terminal capacitor 1A of the first embodiment are lower on the high frequency side compared to the conventional multi-terminal capacitor 1X. This shows that the multi-terminal capacitor 1A of the first embodiment has a higher noise reduction effect (noise filtering effect) compared to the conventional multi-terminal capacitor 1X.

　一方、図６Ｂに示すように、従来の多端子コンデンサ１Ｘと比較して、第１実施形態の多端子コンデンサ１ＡのＩＣ側からみたインピーダンス特性Ｚ１１および等価直列レジスタンスＥＳＲが、高周波数側において高い。これによれば、従来の多端子コンデンサ１Ｘと比較して、第１実施形態の多端子コンデンサ１Ａの電源のデカップリング効果（インピーダンス低減、電源安定化）が低いことがわかる。すなわち、第１実施形態の多端子コンデンサ１Ａでは、ノイズフィルタ効果の向上と引き換えに、電源のデカップリング効果が低い。 On the other hand, as shown in Figure 6B, the impedance characteristic Z11 and equivalent series resistance ESR seen from the IC side of the multi-terminal capacitor 1A of the first embodiment are higher on the high frequency side compared to the conventional multi-terminal capacitor 1X. This shows that the power supply decoupling effect (impedance reduction, power supply stabilization) of the multi-terminal capacitor 1A of the first embodiment is lower compared to the conventional multi-terminal capacitor 1X. In other words, the multi-terminal capacitor 1A of the first embodiment has a lower power supply decoupling effect in exchange for an improved noise filtering effect.

（第２実施形態）
　図１Ｂは、第２実施形態に係る多端子コンデンサの断面模式図である。図１Ｂに示す第２実施形態の多端子コンデンサ１Ｂは、図１Ａに示す第１実施形態の多端子コンデンサ１Ａにおいて、第１導体ビア３１の第１主面非接続導体ビア３１Ａに代えて、導体ビア３１Ｃを備える点で異なる。導体ビア３１Ｃは、第１主面Ｓ１から第２主面Ｓ２まで延在し、第１主面Ｓ１および第２主面Ｓ２に露出し、第１主面Ｓ１および第２主面Ｓ２において第１外部電極４１に接続されている。 Second Embodiment
Fig. 1B is a cross-sectional schematic diagram of a multi-terminal capacitor according to a second embodiment. The multi-terminal capacitor 1B of the second embodiment shown in Fig. 1B differs from the multi-terminal capacitor 1A of the first embodiment shown in Fig. 1A in that it includes a conductor via 31C instead of the first-main-surface unconnected conductor via 31A of the first conductor via 31. The conductor via 31C extends from the first main surface S1 to the second main surface S2, is exposed on the first main surface S1 and the second main surface S2, and is connected to the first external electrode 41 on the first main surface S1 and the second main surface S2.

　このように、第１導体ビア３１として、第１実施形態の多端子コンデンサ１Ａの第１導体ビア３１の第２主面非接続導体ビア３１Ｂと、従来の多端子コンデンサ１Ｘの第１導体ビア３１Ｘに相当する導体ビア３１Ｃとを組み合わせてもよい。 In this way, the first conductive via 31 may be a combination of the second main surface unconnected conductive via 31B of the first conductive via 31 of the multi-terminal capacitor 1A of the first embodiment and the conductive via 31C corresponding to the first conductive via 31X of the conventional multi-terminal capacitor 1X.

　図４Ｂは、本発明のコンデンサ内蔵基板における図１Ｂの本発明の多端子コンデンサの接続構造の一例を示す断面模式図である。図４Ｂに示すように、多端子コンデンサ１Ｂの第２主面Ｓ２の第１導体ビア３１の導体ビア３１Ｃおよび第２導体ビア３２がマザーボードの電源配線ＶＤＤおよびＶＳＳに接続され、多端子コンデンサ１Ｂの第１主面Ｓ１の第１導体ビア３１の第２主面非接続導体ビア３１Ｂおよび導体ビア３１Ｃ、並びに第２導体ビア３２がＩＣの電源配線ＶＤＤおよびＶＳＳに接続される。このとき、多端子コンデンサ１Ｂには、矢印で示すように電流が流れる。 FIG. 4B is a cross-sectional schematic diagram showing an example of the connection structure of the multi-terminal capacitor of FIG. 1B in a capacitor-embedded substrate of the present invention. As shown in FIG. 4B, conductor via 31C of first conductor via 31 on second main surface S2 of multi-terminal capacitor 1B and second conductor via 32 are connected to the power supply wiring VDD and VSS of the motherboard, and second-main-surface unconnected conductor via 31B and conductor via 31C of first conductor via 31 on first main surface S1 of multi-terminal capacitor 1B, as well as second conductor via 32, are connected to the power supply wiring VDD and VSS of the IC. At this time, current flows through multi-terminal capacitor 1B as shown by the arrows.

　図５Ｂは、図４Ｂに示す接続構造の第２実施形態の多端子コンデンサの各部（１）～（３）における電流を示す模式図である。なお、図５Ｂは模式図であり、第１導体ビア３１および第２導体ビア３２の数が省略されている。各部（１）～（３）は、図４Ｂに示すように、（１）多端子コンデンサ１Ｂの第１導体ビア３１の導体ビア３１Ｃの第２主面Ｓ２近傍、（２）多端子コンデンサ１Ｂの第１内部電極層２１、（３）多端子コンデンサ１Ｂの第１導体ビア３１の第２主面非接続導体ビア３１Ｂおよび導体ビア３１Ｃの第１主面Ｓ１近傍である。図５Ｂには、（１）多端子コンデンサ１Ｂの第１導体ビア３１の導体ビア３１Ｃの第２主面Ｓ２近傍に流れるＤＣ電流と、（２）多端子コンデンサ１Ｂの第１内部電極層２１に流れるＤＣ電流と、（２）多端子コンデンサ１Ｂの第１内部電極層２１に流れるＩＣ側からのＡＣ電流と、（３）多端子コンデンサ１Ｂの第１導体ビア３１の第２主面非接続導体ビア３１Ｂおよび導体ビア３１Ｃの第１主面Ｓ１近傍に流れるＤＣ電流とが示されている。 Figure 5B is a schematic diagram showing the currents in each portion (1) to (3) of a multi-terminal capacitor of a second embodiment of the connection structure shown in Figure 4B. Note that Figure 5B is a schematic diagram, and the number of first conductor vias 31 and second conductor vias 32 has been omitted. As shown in Figure 4B, each portion (1) to (3) is (1) the vicinity of the second main surface S2 of conductor via 31C of first conductor via 31 of multi-terminal capacitor 1B, (2) the first internal electrode layer 21 of multi-terminal capacitor 1B, and (3) the vicinity of the first main surface S1 of second main surface unconnected conductor via 31B and conductor via 31C of first conductor via 31 of multi-terminal capacitor 1B. FIG. 5B shows (1) DC current flowing near the second main surface S2 of conductor via 31C of first conductor via 31 of multi-terminal capacitor 1B, (2) DC current flowing in the first internal electrode layer 21 of multi-terminal capacitor 1B, (3) AC current from the IC side flowing in the first internal electrode layer 21 of multi-terminal capacitor 1B, and (3) DC current flowing near the first main surface S1 of second main surface unconnected conductor via 31B and conductor via 31C of first conductor via 31 of multi-terminal capacitor 1B.

　図５Ｂの（１）によれば、多端子コンデンサ１Ｂでは、第１導体ビア３１における導体ビア３１Ｃに電流が入力され、図５Ｂの（３）に示すように、多端子コンデンサ１Ｂでは、第１導体ビア３１における第２主面非接続導体ビア３１Ｂおよび導体ビア３１Ｃから電流が出力される。なお、第１実施形態の多端子コンデンサ１Ｂでは、第１実施形態の多端子コンデンサ１Ａと比較して、第２主面Ｓ２側の入力の第１導体ビア３１の数は同等であり、第１主面Ｓ１側の出力の第１導体ビア３１の数は増加する。 According to (1) in Figure 5B, in multi-terminal capacitor 1B, current is input to conductor via 31C in first conductor via 31, and as shown in (3) in Figure 5B, in multi-terminal capacitor 1B, current is output from second main surface unconnected conductor via 31B and conductor via 31C in first conductor via 31. Note that in multi-terminal capacitor 1B of the first embodiment, the number of first conductor vias 31 on the input side of second main surface S2 is the same as in multi-terminal capacitor 1A of the first embodiment, but the number of first conductor vias 31 on the output side of first main surface S1 is increased.

　図５Ｂの（２）ＩＣ側からのＡＣ電流に示すように、多端子コンデンサ１Ｂでは、ＩＣ側からのＡＣ電流は、第１導体ビア３１から隣接する第２導体ビア３２に向けて第１内部電極層２１を流れる。これにより、ノイズ低減効果が得られる。例えば、ＩＣで発生するノイズ、マザーボードからのノイズが低減される。なお、第２実施形態の多端子コンデンサ１Ｂでは、第１実施形態の多端子コンデンサ１Ａと比較して、ＡＣ電流経路が増加する。 As shown in (2) AC current from the IC side in Figure 5B, in the multi-terminal capacitor 1B, the AC current from the IC side flows through the first internal electrode layer 21 from the first conductive via 31 toward the adjacent second conductive via 32. This provides a noise reduction effect. For example, noise generated by the IC and noise from the motherboard are reduced. Note that in the multi-terminal capacitor 1B of the second embodiment, the number of AC current paths is increased compared to the multi-terminal capacitor 1A of the first embodiment.

　一方、図５Ｂの（２）ＤＣ電流に示すように、多端子コンデンサ１Ｂでは、ＤＣ電流は、第１導体ビア３１の導体ビア３１Ｃを通過するとともに、第１導体ビア３１の導体ビア３１Ｃから第２主面非接続導体ビア３１Ｂに向けて第１内部電極層２１を流れる。これにより、ノイズ低減効果を高めることができる。例えば、ＩＣで発生するノイズ、マザーボードからのノイズが低減される。なお、第２実施形態の多端子コンデンサ１Ｂでは、第１実施形態の多端子コンデンサ１Ａと比較して、ＤＣ電流経路が減少する。 On the other hand, as shown in (2) DC current in Figure 5B, in the multi-terminal capacitor 1B, the DC current passes through the conductor via 31C of the first conductor via 31, and also flows through the first internal electrode layer 21 from the conductor via 31C of the first conductor via 31 toward the second main surface unconnected conductor via 31B. This enhances the noise reduction effect. For example, noise generated in the IC and noise from the motherboard are reduced. Note that in the multi-terminal capacitor 1B of the second embodiment, the DC current path is reduced compared to the multi-terminal capacitor 1A of the first embodiment.

　この第２実施形態の多端子コンデンサ１Ｂでも、電源配線の間に直列に第１内部電極層２１を介在させ、電源のＤＣ電流が第１内部電極層２１を流れるようにする。これにより、ノイズ低減効果を高めることができる。例えば、ＩＣで発生するノイズがマザーボードに伝わりＩＣパッケージの外部に放射されることを抑制することができる。また、例えば、マザーボードからのノイズがＩＣに伝わりＩＣが誤動作することを抑制することができる。 In the multi-terminal capacitor 1B of this second embodiment, the first internal electrode layer 21 is also interposed in series between the power supply wiring, allowing the DC current of the power supply to flow through the first internal electrode layer 21. This enhances the noise reduction effect. For example, it is possible to prevent noise generated in the IC from being transmitted to the motherboard and radiated outside the IC package. It is also possible to prevent noise from the motherboard from being transmitted to the IC and causing the IC to malfunction.

　以下では、上述した効果についてシミュレーションにて考察する。図６Ａに示すように、従来の多端子コンデンサ１Ｘと比較して、第２実施形態の多端子コンデンサ１Ｂの電力通過特性Ｓ２１が、高周波数側において低い。これによれば、従来の多端子コンデンサ１Ｘと比較して、第２実施形態の多端子コンデンサ１Ｂのノイズ低減効果が高いことがわかる（ノイズフィルタ効果）。 Below, the above-mentioned effects are considered through simulation. As shown in Figure 6A, the power passing characteristics S21 of the multi-terminal capacitor 1B of the second embodiment are lower on the high frequency side compared to the conventional multi-terminal capacitor 1X. This shows that the multi-terminal capacitor 1B of the second embodiment has a higher noise reduction effect (noise filter effect) compared to the conventional multi-terminal capacitor 1X.

　一方、図６Ｂに示すように、従来の多端子コンデンサ１Ｘと比較して、第２実施形態の多端子コンデンサ１ＢのＩＣ側からみたインピーダンス特性Ｚ１１および等価直列レジスタンスＥＳＲが、高周波数側において同等である。これによれば、従来の多端子コンデンサ１Ｘと比較して、第２実施形態の多端子コンデンサ１Ｂの電源のデカップリング効果（インピーダンス低減、電源安定化）が同等であることがわかる。 On the other hand, as shown in Figure 6B, the impedance characteristic Z11 and equivalent series resistance ESR seen from the IC side of the multi-terminal capacitor 1B of the second embodiment are equivalent to those of the conventional multi-terminal capacitor 1X on the high frequency side. This shows that the power supply decoupling effect (impedance reduction, power supply stabilization) of the multi-terminal capacitor 1B of the second embodiment is equivalent to that of the conventional multi-terminal capacitor 1X.

　また、第１実施形態の多端子コンデンサ１Ａと比較して、第２実施形態の多端子コンデンサ１ＢのＩＣ側からみたインピーダンス特性Ｚ１１および等価直列レジスタンスＥＳＲが、高周波数側において低い。これによれば、第１実施形態の多端子コンデンサ１Ａと比較して、第２実施形態の多端子コンデンサ１Ｂの電源のデカップリング効果（インピーダンス低減、電源安定化）が高いことがわかる。すなわち、第２実施形態の多端子コンデンサ１Ｂでは、第１導体ビア３１として、第１実施形態の多端子コンデンサ１Ａの第１導体ビア３１の第２主面非接続導体ビア３１Ｂと、従来の多端子コンデンサ１Ｘの第１導体ビア３１Ｘに相当する導体ビア３１Ｃとを組み合わせることにより、ＩＣ側からみたインピーダンス特性Ｚ１１および等価直列レジスタンスＥＳＲを低下させることなく、ノイズフィルタ効果を向上することができた。 Furthermore, compared to the multi-terminal capacitor 1A of the first embodiment, the impedance characteristic Z11 and equivalent series resistance ESR of the multi-terminal capacitor 1B of the second embodiment as viewed from the IC side are lower on the high-frequency side. This shows that the power supply decoupling effect (impedance reduction, power supply stabilization) of the multi-terminal capacitor 1B of the second embodiment is higher than that of the multi-terminal capacitor 1A of the first embodiment. That is, in the multi-terminal capacitor 1B of the second embodiment, by combining, as the first conductive via 31, the second-main-surface unconnected conductive via 31B of the first conductive via 31 of the multi-terminal capacitor 1A of the first embodiment and the conductive via 31C equivalent to the first conductive via 31X of the conventional multi-terminal capacitor 1X, it is possible to improve the noise filtering effect without reducing the impedance characteristic Z11 and equivalent series resistance ESR as viewed from the IC side.

（第２実施形態の変形例）
　図４Ｄは、本発明のコンデンサ内蔵基板における図１Ｂの本発明の多端子コンデンサの接続構造の一例を示す断面模式図である。図４Ｄに示すように、多端子コンデンサ１Ｂの第１主面Ｓ１の第１導体ビア３１の第２主面非接続導体ビア３１Ｂおよび導体ビア３１Ｃの一部が一方の電源配線ＶＤＤに接続され、多端子コンデンサ１Ｂの第１主面Ｓ１の第１導体ビア３１の導体ビア３１Ｃであって、一方の電源配線ＶＤＤに接続されていない導体ビア３１Ｃが他方の電源配線ＶＤＤに接続されてもよい。このとき、多端子コンデンサ１Ｂには、矢印で示すように電流が流れる。 (Modification of the second embodiment)
4D is a cross-sectional schematic diagram showing an example of a connection structure of the multi-terminal capacitor of FIG. 1B in a capacitor-embedded substrate of the present invention. As shown in FIG. 4D, second-main-surface unconnected conductor vias 31B and a portion of conductor vias 31C of first conductor vias 31 on first main surface S1 of multi-terminal capacitor 1B may be connected to one power supply wiring VDD, and conductor vias 31C of first conductor vias 31 on first main surface S1 of multi-terminal capacitor 1B that are not connected to one power supply wiring VDD may be connected to the other power supply wiring VDD. In this case, a current flows through multi-terminal capacitor 1B as shown by the arrows.

　図５Ｃは、図４Ｄに示す接続構造の第２実施形態の多端子コンデンサの各部（１）～（３）における電流を示す模式図である。なお、図５Ｃは模式図であり、第１導体ビア３１および第２導体ビア３２の数が省略されている。各部（１）～（３）は、図４Ｄに示すように、（１）多端子コンデンサ１Ｂの第１導体ビア３１の導体ビア３１Ｃの第２主面Ｓ２近傍、（２）多端子コンデンサ１Ｂの第１内部電極層２１、（３）多端子コンデンサ１Ｂの第１導体ビア３１の第２主面非接続導体ビア３１Ｂおよび導体ビア３１Ｃの第１主面Ｓ１近傍である。図５Ｃには、（１）多端子コンデンサ１Ｂの第１導体ビア３１の導体ビア３１Ｃの第２主面Ｓ２近傍に流れるＤＣ電流と、（２）多端子コンデンサ１Ｂの第１内部電極層２１に流れるＤＣ電流と、（２）多端子コンデンサ１Ｂの第１内部電極層２１に流れるＩＣ側からのＡＣ電流と、（３）多端子コンデンサ１Ｂの第１導体ビア３１の第２主面非接続導体ビア３１Ｂおよび導体ビア３１Ｃの第１主面Ｓ１近傍に流れるＤＣ電流とが示されている。 Figure 5C is a schematic diagram showing the currents in the respective parts (1) to (3) of the multi-terminal capacitor of the second embodiment of the connection structure shown in Figure 4D. Note that Figure 5C is a schematic diagram, and the number of first conductor vias 31 and second conductor vias 32 has been omitted. The respective parts (1) to (3) are, as shown in Figure 4D, (1) the vicinity of the second main surface S2 of the conductor via 31C of the first conductor via 31 of the multi-terminal capacitor 1B, (2) the first internal electrode layer 21 of the multi-terminal capacitor 1B, and (3) the vicinity of the first main surface S1 of the second main surface non-connected conductor via 31B and conductor via 31C of the first conductor via 31 of the multi-terminal capacitor 1B. FIG. 5C shows (1) DC current flowing near the second main surface S2 of conductor via 31C of first conductor via 31 of multi-terminal capacitor 1B, (2) DC current flowing in the first internal electrode layer 21 of multi-terminal capacitor 1B, (3) AC current from the IC side flowing in the first internal electrode layer 21 of multi-terminal capacitor 1B, and (3) DC current flowing near the first main surface S1 of second main surface unconnected conductor via 31B and conductor via 31C of first conductor via 31 of multi-terminal capacitor 1B.

　図５Ｃの（３）によれば、多端子コンデンサ１Ｂでは、第１主面Ｓ１における第１導体ビア３１の一部に電流が入力され、第１主面Ｓ１における第１導体ビア３１の他の一部から電流が出力される。 According to (3) in Figure 5C, in the multi-terminal capacitor 1B, current is input to a portion of the first conductive via 31 on the first main surface S1, and current is output from another portion of the first conductive via 31 on the first main surface S1.

　図５Ｃの（２）ＩＣ側からのＡＣ電流に示すように、多端子コンデンサ１Ｂでは、ＩＣ側からのＡＣ電流は、第１導体ビア３１から隣接する第２導体ビア３２に向けて第１内部電極層２１を流れる。これにより、ノイズ低減効果が得られる。例えば、ＩＣで発生するノイズ、マザーボードからのノイズが低減される。 As shown in (2) AC current from the IC side in Figure 5C, in the multi-terminal capacitor 1B, AC current from the IC side flows through the first internal electrode layer 21 from the first conductive via 31 to the adjacent second conductive via 32. This provides a noise reduction effect. For example, noise generated by the IC and noise from the motherboard are reduced.

　一方、図５Ｃの（２）ＤＣ電流に示すように、多端子コンデンサ１Ｂでは、ＤＣ電流は、第１導体ビア３１の一部から他の一部に向けて第１内部電極層２１を流れる。これにより、ノイズ低減効果を高めることができる。例えば、ＩＣで発生するノイズ、マザーボードからのノイズが低減される。 On the other hand, as shown in (2) DC current in Figure 5C, in the multi-terminal capacitor 1B, DC current flows through the first internal electrode layer 21 from one part of the first conductive via 31 to another part. This enhances the noise reduction effect. For example, noise generated by the IC and noise from the motherboard are reduced.

　この第２実施形態の変形例の接続構造の多端子コンデンサ１Ｂでも、電源配線の間に直列に第１内部電極層２１を介在させ、電源のＤＣ電流が第１内部電極層２１を流れるようにする。これにより、ノイズ低減効果を高めることができる。例えば、ＩＣで発生するノイズがマザーボードに伝わりＩＣパッケージの外部に放射されることを抑制することができる。また、例えば、マザーボードからのノイズがＩＣに伝わりＩＣが誤動作することを抑制することができる。 In the multi-terminal capacitor 1B having the connection structure of this modified example of the second embodiment, the first internal electrode layer 21 is also interposed in series between the power supply wiring, allowing the DC current of the power supply to flow through the first internal electrode layer 21. This enhances the noise reduction effect. For example, it is possible to prevent noise generated in the IC from being transmitted to the motherboard and radiated outside the IC package. It is also possible to prevent noise from the motherboard from being transmitted to the IC and causing the IC to malfunction.

［コンデンサ内蔵基板］
　ＩＣパッケージ技術において、チップレット技術が注目されている。チップレット技術とは、大規模な集積回路（ＩＣ）を１つのチップに集積するのではなく、大規模な集積回路（ＩＣ）を複数の小さなチップ（チップレット）に個片化し、これらのチップを基板（パッケージ基板、インターポーザ、等）に搭載して組み合わせ、１つのＩＣパッケージに収める技術である。 [Capacitor built-in board]
Chiplet technology is attracting attention as an IC packaging technology. Chiplet technology is a technology in which, instead of integrating a large-scale integrated circuit (IC) onto a single chip, the large-scale integrated circuit (IC) is separated into multiple small chips (chiplets), which are then mounted and combined on a substrate (package substrate, interposer, etc.) to form a single IC package.

　チップレット技術では、複数のプロセッサ（ＩＣ）ごとに電源電圧が異なるため、基板上の電源配線が複雑化する。この点に関し、基板上のプロセッサ（ＩＣ）近傍に電圧レギュレータ（ＩＣ）を設け、電圧レギュレータに供給する電源電圧を統一することが考えられる。この場合、電圧レギュレータおよびプロセッサの近傍にデカップリング用およびスイッチングノイズフィルタ用のコンデンサが必要になる。そこで、内部にコンデンサが埋め込まれたコンデンサ内蔵基板を考案する。 In chiplet technology, the power supply voltage differs for each of the multiple processors (ICs), which makes the power supply wiring on the board complex. To address this issue, it is possible to install voltage regulators (ICs) near the processors (ICs) on the board and unify the power supply voltage supplied to the voltage regulators. In this case, capacitors for decoupling and switching noise filtering are required near the voltage regulators and processors. Therefore, we devised a capacitor-embedded board with capacitors embedded inside.

（第１実施形態）
　図７Ａ、図４Ａ～図４Ｆを参照して、第１実施形態に係るコンデンサ内蔵基板について説明する。図７Ａは、第１実施形態に係るコンデンサ内蔵基板の模式図である。 (First embodiment)
The capacitor-embedded substrate according to the first embodiment will be described with reference to Fig. 7A and Fig. 4A to Fig. 4F. Fig. 7A is a schematic diagram of the capacitor-embedded substrate according to the first embodiment.

　図７Ａに示すコンデンサ内蔵基板１００Ａは、ＩＣパッケージに用いられるパッケージ基板である。コンデンサ内蔵基板１００Ａには、電圧レギュレータＶＲおよびプロセッサ等のＩＣが導体バンプを介して搭載される。なお、ＩＣパッケージはマザーボードに搭載され、これにより、コンデンサ内蔵基板１００ＡのＩＣ搭載面と反対側にはマザーボードが配置される（図示省略）。 The capacitor-embedded substrate 100A shown in Figure 7A is a package substrate used in an IC package. A voltage regulator VR and an IC such as a processor are mounted on the capacitor-embedded substrate 100A via conductive bumps. The IC package is mounted on a motherboard, and thus the motherboard is placed on the side of the capacitor-embedded substrate 100A opposite the IC-mounted surface (not shown).

　コンデンサ内蔵基板１００Ａの内部には、電圧レギュレータＶＲを構成するインダクタＬ、多端子コンデンサ１，２が埋め込まれている。多端子コンデンサ１には、上述した本発明の多端子コンデンサ１Ａ，１Ｂが適用される。また、多端子コンデンサ１には、上述した従来の多端子コンデンサ１Ｘが適用されてもよい。一方、多端子コンデンサ２には、上述した本発明の多端子コンデンサ１Ｂが適用される。また、多端子コンデンサ２には、上述した従来の多端子コンデンサ１Ｘ、多端子コンデンサ１Ｙが適用されてもよい。多端子コンデンサ１，２は、少なくとも５つの端子を有する。 Inductor L and multi-terminal capacitors 1 and 2 that constitute the voltage regulator VR are embedded inside capacitor-embedded substrate 100A. Multi-terminal capacitor 1 is the multi-terminal capacitors 1A and 1B of the present invention described above. Multi-terminal capacitor 1 may also be the conventional multi-terminal capacitor 1X described above. On the other hand, multi-terminal capacitor 2 is the multi-terminal capacitor 1B of the present invention described above. Multi-terminal capacitor 2 may also be the conventional multi-terminal capacitor 1X or multi-terminal capacitor 1Y described above. Multi-terminal capacitors 1 and 2 have at least five terminals.

　多端子コンデンサ１は、コンデンサ内蔵基板１００Ａの主面に沿う平面視において、電圧レギュレータＶＲと重なる位置、すなわち電圧レギュレータＶＲの直下、に配置されている。多端子コンデンサ１の第２主面の外部電極は、マザーボードの電源配線に接続されており、多端子コンデンサ１の第１主面の外部電極は、電圧レギュレータＶＲの入力の電源配線に接続されている。これにより、ノイズ低減効果を高めることができる。例えば、電圧レギュレータＶＲで発生するスイッチングノイズがノイズ源近傍で抑制され、スイッチングノイズがマザーボードに伝わりＩＣパッケージの外部に放射されることを抑制することができる。 The multi-terminal capacitor 1 is positioned so as to overlap the voltage regulator VR, i.e., directly below the voltage regulator VR, in a plan view along the main surface of the capacitor-embedded substrate 100A. The external electrode on the second main surface of the multi-terminal capacitor 1 is connected to the power supply wiring of the motherboard, and the external electrode on the first main surface of the multi-terminal capacitor 1 is connected to the power supply wiring for the input of the voltage regulator VR. This enhances the noise reduction effect. For example, switching noise generated by the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

　一方、多端子コンデンサ２は、コンデンサ内蔵基板１００Ａの主面に沿う平面視において、プロセッサと重なる位置、すなわちプロセッサの直下、に配置されている。多端子コンデンサ２の第１主面の外部電極は、電圧レギュレータＶＲの出力の電源配線に接続されており、多端子コンデンサ２の第１主面の外部電極は、プロセッサの電源の電源配線に接続されている。これにより、ノイズ低減効果を高めることができる。例えば、電圧レギュレータＶＲで発生するスイッチングノイズが抑制され、スイッチングノイズがプロセッサに伝わりプロセッサが誤動作することを抑制することができる。 Meanwhile, the multi-terminal capacitor 2 is positioned so as to overlap the processor, i.e., directly below the processor, in a plan view along the main surface of the capacitor-embedded substrate 100A. The external electrode on the first main surface of the multi-terminal capacitor 2 is connected to the power supply wiring for the output of the voltage regulator VR, and the external electrode on the first main surface of the multi-terminal capacitor 2 is connected to the power supply wiring for the processor's power supply. This enhances the noise reduction effect. For example, switching noise generated by the voltage regulator VR is suppressed, preventing the switching noise from being transmitted to the processor and causing it to malfunction.

　図４Ａに示すように、コンデンサ内蔵基板１００Ａは、コア基材１０１と配線層１０２とを有する。コンデンサ内蔵基板１００Ａの多端子コンデンサ１近傍では、マザーボード側の配線層１０２には、電源配線ＶＤＤ，ＶＳＳ（ＧＮＤ）が配置されており、電圧レギュレータＶＲ（ＩＣ）側の配線層１０２には、電源配線ＶＤＤ，ＶＳＳ（ＧＮＤ）が配置されている。 As shown in FIG. 4A, the capacitor-embedded substrate 100A has a core substrate 101 and a wiring layer 102. Near the multi-terminal capacitor 1 of the capacitor-embedded substrate 100A, power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the motherboard side, and power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the voltage regulator VR (IC) side.

　多端子コンデンサ１として上述した本発明の多端子コンデンサ１Ａが適用される場合、マザーボード側の電源配線ＶＤＤは、多端子コンデンサ１の第２主面Ｓ２の第１導体ビア３１の第１主面非接続導体ビア３１Ａに、第１外部電極４１および導体ビアを介して接続される。マザーボード側の電源配線ＶＳＳは、多端子コンデンサ１の第２主面Ｓ２の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 When the multi-terminal capacitor 1A of the present invention described above is used as the multi-terminal capacitor 1, the power supply wiring VDD on the motherboard side is connected to the first main surface unconnected conductor via 31A of the first conductor vias 31 on the second main surface S2 of the multi-terminal capacitor 1 via the first external electrode 41 and the conductor via. The power supply wiring VSS on the motherboard side is connected to the second conductor via 32 on the second main surface S2 of the multi-terminal capacitor 1 via the second external electrode 42 and the conductor via.

　電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＤＤは、多端子コンデンサ１の第１主面Ｓ１の第１導体ビア３１の第２主面非接続導体ビア３１Ｂに、第１外部電極４１および導体ビアを介して接続される。電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＳＳは、多端子コンデンサ１の第１主面Ｓ１の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 The power supply wiring VDD on the voltage regulator VR(IC) side is connected to the second main surface unconnected conductor via 31B of the first conductor via 31 on the first main surface S1 of the multi-terminal capacitor 1 via the first external electrode 41 and a conductor via. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to the second conductor via 32 on the first main surface S1 of the multi-terminal capacitor 1 via the second external electrode 42 and a conductor via.

　これにより、マザーボード側の電源配線ＶＤＤと電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＤＤとの間に直列に、多端子コンデンサ１の第１内部電極層２１の一部が介在する。これにより、矢印で示されるように、電圧レギュレータＶＲ（ＩＣ）の入力の電源のＤＣ電流の少なくとも一部が、多端子コンデンサ１の第１内部電極層２１を流れる。これにより、ノイズ低減効果を高めることができる。例えば、電圧レギュレータＶＲで発生するスイッチングノイズがノイズ源近傍で抑制され、スイッチングノイズがマザーボードに伝わりＩＣパッケージの外部に放射されることを抑制することができる。 As a result, part of the first internal electrode layer 21 of the multi-terminal capacitor 1 is interposed in series between the power supply wiring VDD on the motherboard side and the power supply wiring VDD on the voltage regulator VR (IC) side. As a result, as shown by the arrow, at least part of the DC current of the power supply input to the voltage regulator VR (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. This enhances the noise reduction effect. For example, switching noise generated by the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

　なお、第１主面Ｓ１および第２主面Ｓ２に沿う平面視において、電源配線ＶＤＤに接続される第１主面Ｓ１の第１外部電極４１の位置と、電源配線ＶＤＤに接続される第２主面Ｓ２の第１外部電極４１の位置とはずれている。また、電源配線ＶＤＤに接続される第１主面Ｓ１の第１外部電極４１の数と、電源配線ＶＤＤに接続される第２主面Ｓ２の第１外部電極４１の数とは異なる。また、第１主面Ｓ１に配置された第１外部電極４１および第２外部電極４２の総数は、第２主面Ｓ２に配置された第１外部電極４１および第２外部電極４２の総数よりも多い。 Note that, in a plan view along the first principal surface S1 and the second principal surface S2, the positions of the first external electrodes 41 on the first principal surface S1 connected to the power supply wiring VDD are offset from the positions of the first external electrodes 41 on the second principal surface S2 connected to the power supply wiring VDD. Furthermore, the number of first external electrodes 41 on the first principal surface S1 connected to the power supply wiring VDD is different from the number of first external electrodes 41 on the second principal surface S2 connected to the power supply wiring VDD. Furthermore, the total number of first external electrodes 41 and second external electrodes 42 arranged on the first principal surface S1 is greater than the total number of first external electrodes 41 and second external electrodes 42 arranged on the second principal surface S2.

　コア基材１０１の材料としては、ガラスエポキシ等の公知の材料が挙げられ、配線層１０２の材料としては、エポキシ樹脂等の公知の材料が挙げられる。電源配線ＶＤＤ，ＶＳＳは、配線層１０２に形成された導体パターンおよび導体ビアで構成される。導体パターンおよび導体ビアの材料としては、Ｃｕ等の公知の金属材料が挙げられる。 The core substrate 101 can be made of a known material such as glass epoxy, and the wiring layer 102 can be made of a known material such as epoxy resin. The power supply wiring VDD and VSS is composed of conductor patterns and conductor vias formed on the wiring layer 102. The conductor patterns and conductor vias can be made of known metal materials such as Cu.

　或いは、図４Ｂに示すように、多端子コンデンサ１として上述した本発明の多端子コンデンサ１Ｂが適用される場合、マザーボード側の電源配線ＶＤＤは、多端子コンデンサ１の第２主面Ｓ２の第１導体ビア３１の導体ビア３１Ｃに、第１外部電極４１および導体ビアを介して接続される。マザーボード側の電源配線ＶＳＳは、多端子コンデンサ１の第２主面Ｓ２の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 Alternatively, as shown in FIG. 4B, when the multi-terminal capacitor 1B of the present invention described above is used as the multi-terminal capacitor 1, the power supply wiring VDD on the motherboard side is connected to the conductor via 31C of the first conductor via 31 on the second main surface S2 of the multi-terminal capacitor 1 via the first external electrode 41 and the conductor via. The power supply wiring VSS on the motherboard side is connected to the second conductor via 32 on the second main surface S2 of the multi-terminal capacitor 1 via the second external electrode 42 and the conductor via.

　これにより、マザーボード側の電源配線ＶＤＤと電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＤＤとの間に直列に、多端子コンデンサ１の第１内部電極層２１の一部が介在する。これにより、矢印で示されるように、電圧レギュレータＶＲ（ＩＣ）の電源のＤＣ電流の少なくとも一部が、多端子コンデンサ１の第１内部電極層２１を流れる。これにより、ノイズ低減効果を高めることができる。例えば、電圧レギュレータＶＲで発生するスイッチングノイズがノイズ源近傍で抑制され、スイッチングノイズがマザーボードに伝わりＩＣパッケージの外部に放射されることを抑制することができる。 As a result, part of the first internal electrode layer 21 of the multi-terminal capacitor 1 is interposed in series between the power supply wiring VDD on the motherboard side and the power supply wiring VDD on the voltage regulator VR (IC) side. As a result, as shown by the arrow, at least part of the DC current of the power supply for the voltage regulator VR (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. This enhances the noise reduction effect. For example, switching noise generated by the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

　或いは、図４Ｃに示すように、多端子コンデンサ１として上述した従来の多端子コンデンサ１Ｘが適用される場合、マザーボード側の電源配線ＶＤＤは、多端子コンデンサ１の第２主面Ｓ２の第１導体ビア３１Ｘの一部に、第１外部電極４１Ｘおよび導体ビアを介して接続される。マザーボード側の電源配線ＶＳＳは、多端子コンデンサ１の第２主面Ｓ２の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 Alternatively, as shown in FIG. 4C , when the above-described conventional multi-terminal capacitor 1X is used as the multi-terminal capacitor 1, the power supply wiring VDD on the motherboard side is connected to a portion of the first conductive via 31X on the second main surface S2 of the multi-terminal capacitor 1 via a first external electrode 41X and a conductive via. The power supply wiring VSS on the motherboard side is connected to the second conductive via 32 on the second main surface S2 of the multi-terminal capacitor 1 via a second external electrode 42 and a conductive via.

　電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＤＤは、多端子コンデンサ１の第１主面Ｓ１の第１導体ビア３１Ｘであって、第２主面Ｓ２においてマザーボード側の電源配線ＶＤＤに接続されていない第１導体ビア３１Ｘに、第１外部電極４１および導体ビアを介して接続される。電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＳＳは、多端子コンデンサ１の第１主面Ｓ１の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 The power supply wiring VDD on the voltage regulator VR(IC) side is connected via a first external electrode 41 and a conductor via to a first conductor via 31X on the first main surface S1 of the multi-terminal capacitor 1 that is not connected to the power supply wiring VDD on the motherboard side on the second main surface S2. The power supply wiring VSS on the voltage regulator VR(IC) side is connected via a second external electrode 42 and a conductor via to a second conductor via 32 on the first main surface S1 of the multi-terminal capacitor 1.

　一方、図４Ｄに示すように、コンデンサ内蔵基板１００Ａの多端子コンデンサ２近傍では、電圧レギュレータＶＲおよびプロセッサ（ＩＣ）側の配線層１０２には、電圧レギュレータＶＲ側の電源配線ＶＤＤ，ＶＳＳ（ＧＮＤ）と、プロセッサ側の電源配線ＶＤＤ，ＶＳＳ（ＧＮＤ）とが配置されており、マザーボード側の配線層１０２には、電源配線ＶＳＳ（ＧＮＤ）のみが配置されている。 On the other hand, as shown in Figure 4D, near the multi-terminal capacitor 2 of the capacitor-embedded substrate 100A, the wiring layer 102 on the voltage regulator VR and processor (IC) side has power supply wiring VDD and VSS (GND) on the voltage regulator VR side and power supply wiring VDD and VSS (GND) on the processor side, while the wiring layer 102 on the motherboard side has only power supply wiring VSS (GND).

　多端子コンデンサ２として上述した本発明の多端子コンデンサ１Ｂが適用される場合、電圧レギュレータＶＲ側の電源配線ＶＤＤは、多端子コンデンサ２の第１主面Ｓ１の第１導体ビア３１の第１主面非接続導体ビア３１Ａ、および、導体ビア３１Ｃの一部に、第１外部電極４１および導体ビアを介して接続される。プロセッサ側の電源配線ＶＤＤは、多端子コンデンサ２の第１主面Ｓ１の第１導体ビア３１の導体ビア３１Ｃであって、電圧レギュレータＶＲ側の電源配線ＶＤＤに接続されていない導体ビア３１Ｃに、第１外部電極４１および導体ビアを介して接続される。電圧レギュレータＶＲおよびプロセッサ側の電源配線ＶＳＳは、多端子コンデンサ２の第１主面Ｓ１の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。また、マザーボード側の電源配線ＶＳＳは、多端子コンデンサ２の第２主面Ｓ２の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 When the multi-terminal capacitor 1B of the present invention described above is used as the multi-terminal capacitor 2, the power supply wiring VDD on the voltage regulator VR side is connected to first-surface unconnected conductor vias 31A and a portion of conductor vias 31C of the first conductor vias 31 on the first main surface S1 of the multi-terminal capacitor 2 via the first external electrode 41 and conductor vias. The power supply wiring VDD on the processor side is connected to conductor vias 31C of the first conductor vias 31 on the first main surface S1 of the multi-terminal capacitor 2 that are not connected to the power supply wiring VDD on the voltage regulator VR side via the first external electrode 41 and conductor vias. The power supply wiring VSS on the voltage regulator VR and processor side is connected to second conductor vias 32 on the first main surface S1 of the multi-terminal capacitor 2 via the second external electrode 42 and conductor vias. The power supply wiring VSS on the motherboard side is connected to second conductor vias 32 on the second main surface S2 of the multi-terminal capacitor 2 via the second external electrode 42 and conductor vias.

　これにより、電圧レギュレータ（ＩＣ）側の電源配線ＶＤＤとプロセッサ（ＩＣ）側の電源配線ＶＤＤとの間に直列に、多端子コンデンサ２の第１内部電極層２１の一部が介在する。これにより、矢印で示されるように、プロセッサ（ＩＣ）の電源のＤＣ電流の少なくとも一部が、多端子コンデンサ２の第１内部電極層２１を流れる。これにより、ノイズ低減効果を高めることができる。例えば、例えば、電圧レギュレータＶＲで発生するスイッチングノイズが抑制され、スイッチングノイズがプロセッサに伝わりプロセッサが誤動作することを抑制することができる。 As a result, a portion of the first internal electrode layer 21 of the multi-terminal capacitor 2 is interposed in series between the power supply wiring VDD on the voltage regulator (IC) side and the power supply wiring VDD on the processor (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the processor (IC) power supply flows through the first internal electrode layer 21 of the multi-terminal capacitor 2. This enhances the noise reduction effect. For example, switching noise generated in the voltage regulator VR is suppressed, preventing the switching noise from being transmitted to the processor and causing it to malfunction.

　或いは、図４Ｅに示すように、多端子コンデンサ２として上述した従来の多端子コンデンサ１Ｘが適用される場合、電圧レギュレータＶＲ側の電源配線ＶＤＤは、多端子コンデンサ２の第１主面Ｓ１の第１導体ビア３１Ｘの一部に、第１外部電極４１および導体ビアを介して接続される。プロセッサ側の電源配線ＶＤＤは、多端子コンデンサ２の第１主面Ｓ１の第１導体ビア３１Ｘであって、電圧レギュレータＶＲ側の電源配線ＶＤＤに接続されていない第１導体ビア３１Ｘに、第１外部電極４１および導体ビアを介して接続される。電圧レギュレータＶＲおよびプロセッサ側の電源配線ＶＳＳは、多端子コンデンサ２の第１主面Ｓ１の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。また、マザーボード側の電源配線ＶＳＳは、多端子コンデンサ２の第２主面Ｓ２の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 Alternatively, as shown in FIG. 4E, when the above-described conventional multi-terminal capacitor 1X is used as the multi-terminal capacitor 2, the power supply wiring VDD on the voltage regulator VR side is connected to a portion of the first conductive vias 31X on the first main surface S1 of the multi-terminal capacitor 2 via the first external electrode 41 and a conductive via. The power supply wiring VDD on the processor side is connected to the first conductive vias 31X on the first main surface S1 of the multi-terminal capacitor 2 that are not connected to the power supply wiring VDD on the voltage regulator VR side via the first external electrode 41 and a conductive via. The power supply wiring VSS on the voltage regulator VR and processor side is connected to the second conductive vias 32 on the first main surface S1 of the multi-terminal capacitor 2 via the second external electrode 42 and a conductive via. Furthermore, the power supply wiring VSS on the motherboard side is connected to the second conductive vias 32 on the second main surface S2 of the multi-terminal capacitor 2 via the second external electrode 42 and a conductive via.

　これにより、電圧レギュレータ（ＩＣ）側の電源配線ＶＤＤとプロセッサ（ＩＣ）側の電源配線ＶＤＤとの間に直列に、多端子コンデンサ２の第１内部電極層２１の一部が介在する。これにより、矢印で示されるように、プロセッサ（ＩＣ）の電源のＤＣ電流の少なくとも一部が、多端子コンデンサ２の第１内部電極層２１を流れる。これにより、ノイズ低減効果を高めることができる。例えば、電圧レギュレータＶＲで発生するスイッチングノイズが抑制され、スイッチングノイズがプロセッサに伝わりプロセッサが誤動作することを抑制することができる。 As a result, part of the first internal electrode layer 21 of the multi-terminal capacitor 2 is interposed in series between the power supply wiring VDD on the voltage regulator (IC) side and the power supply wiring VDD on the processor (IC) side. As a result, as shown by the arrow, at least part of the DC current of the processor (IC) power supply flows through the first internal electrode layer 21 of the multi-terminal capacitor 2. This enhances the noise reduction effect. For example, switching noise generated in the voltage regulator VR is suppressed, preventing the switching noise from being transmitted to the processor and causing it to malfunction.

　ここで、図４Ｆに示すように、図４Ｅにおいて多端子コンデンサ２は、多端子コンデンサ１Ｘに代えて多端子コンデンサ１Ｙが適用されてもよい。多端子コンデンサ１Ｙは、多端子コンデンサ１Ｘにおいて第１導体ビア３１Ｘに代えて第１導体ビア３１Ｙを備える。第１導体ビア３１Ｙは、第１導体ビア３１Ｘと比較して、第２主面Ｓ２まで延在せず、第２主面Ｓ２に露出せず、第２主面Ｓ２において第１外部電極４１に接続されていない点で異なる。 Here, as shown in FIG. 4F, the multi-terminal capacitor 2 in FIG. 4E may be a multi-terminal capacitor 1Y instead of the multi-terminal capacitor 1X. The multi-terminal capacitor 1Y has a first conductor via 31Y instead of the first conductor via 31X in the multi-terminal capacitor 1X. The first conductor via 31Y differs from the first conductor via 31X in that it does not extend to the second main surface S2, is not exposed on the second main surface S2, and is not connected to the first external electrode 41 on the second main surface S2.

　図４Ｆに示すように、多端子コンデンサ２として多端子コンデンサ１Ｙが適用される場合、電圧レギュレータＶＲ側の電源配線ＶＤＤは、多端子コンデンサ２の第１主面Ｓ１の第１導体ビア３１Ｙの一部に、第１外部電極４１および導体ビアを介して接続される。プロセッサ側の電源配線ＶＤＤは、多端子コンデンサ２の第１主面Ｓ１の第１導体ビア３１Ｙであって、電圧レギュレータＶＲ側の電源配線ＶＤＤに接続されていない第１導体ビア３１Ｙに、第１外部電極４１および導体ビアを介して接続される。電圧レギュレータＶＲおよびプロセッサ側の電源配線ＶＳＳは、多端子コンデンサ２の第１主面Ｓ１の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。また、マザーボード側の電源配線ＶＳＳは、多端子コンデンサ２の第２主面Ｓ２の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 As shown in FIG. 4F, when a multi-terminal capacitor 1Y is used as the multi-terminal capacitor 2, the power supply wiring VDD on the voltage regulator VR side is connected to a portion of the first conductive via 31Y on the first main surface S1 of the multi-terminal capacitor 2 via the first external electrode 41 and a conductive via. The power supply wiring VDD on the processor side is connected to a portion of the first conductive via 31Y on the first main surface S1 of the multi-terminal capacitor 2 that is not connected to the power supply wiring VDD on the voltage regulator VR side via the first external electrode 41 and a conductive via. The power supply wiring VSS on the voltage regulator VR and processor side is connected to the second conductive via 32 on the first main surface S1 of the multi-terminal capacitor 2 via the second external electrode 42 and a conductive via. The power supply wiring VSS on the motherboard side is connected to the second conductive via 32 on the second main surface S2 of the multi-terminal capacitor 2 via the second external electrode 42 and a conductive via.

（第２実施形態）
　次に、図７Ｂ、図４Ａ～図４Ｃを参照して、第２実施形態に係るコンデンサ内蔵基板について説明する。図７Ｂは、第２実施形態に係るコンデンサ内蔵基板の模式図である。 Second Embodiment
Next, a capacitor-embedded substrate according to a second embodiment will be described with reference to Fig. 7B and Fig. 4A to Fig. 4C. Fig. 7B is a schematic diagram of the capacitor-embedded substrate according to the second embodiment.

　図７Ｂに示すコンデンサ内蔵基板１００Ｂは、ＩＣパッケージに用いられるインターポーザである。コンデンサ内蔵基板１００Ｂは、パッケージ基板１１０と、電圧レギュレータＶＲおよびプロセッサ等のＩＣとの間に配置される。コンデンサ内蔵基板１００Ｂは、パッケージ基板１１０と導体バンプを介して接続され、電圧レギュレータＶＲおよびプロセッサ等のＩＣと導体バンプを介して接続される。なお、ＩＣパッケージはマザーボードに搭載され、これにより、パッケージ基板１１０のＩＣ搭載面と反対側にはマザーボードが配置される（図示省略）。 The capacitor-embedded substrate 100B shown in Figure 7B is an interposer used in an IC package. The capacitor-embedded substrate 100B is placed between the package substrate 110 and an IC such as a voltage regulator VR and a processor. The capacitor-embedded substrate 100B is connected to the package substrate 110 via conductor bumps, and is connected to the voltage regulator VR and an IC such as a processor via conductor bumps. The IC package is mounted on a motherboard, and thus the motherboard is placed on the side of the package substrate 110 opposite the IC-mounted surface (not shown).

　パッケージ基板１１０の内部には、電圧レギュレータＶＲを構成するインダクタＬが埋め込まれている。コンデンサ内蔵基板１００Ｂの内部には、多端子コンデンサ１，３が埋め込まれている。多端子コンデンサ１，３には、上述した本発明の多端子コンデンサ１Ａ，１Ｂが適用される。また、多端子コンデンサ１，３には、上述した従来の多端子コンデンサ１Ｘが適用されてもよい。多端子コンデンサ１，３は、少なくとも５つの端子を有する。 An inductor L that constitutes the voltage regulator VR is embedded inside the package substrate 110. Multi-terminal capacitors 1 and 3 are embedded inside the capacitor-embedded substrate 100B. The multi-terminal capacitors 1 and 3 are the multi-terminal capacitors 1A and 1B of the present invention described above. The multi-terminal capacitors 1 and 3 may also be the conventional multi-terminal capacitor 1X described above. The multi-terminal capacitors 1 and 3 have at least five terminals.

　多端子コンデンサ１は、コンデンサ内蔵基板１００Ｂの主面に沿う平面視において、電圧レギュレータＶＲと重なる位置、すなわち電圧レギュレータＶＲの直下、に配置されている。多端子コンデンサ１の第２主面の外部電極は、マザーボードの電源配線に接続されており、多端子コンデンサ１の第１主面の外部電極は、電圧レギュレータＶＲの入力の電源配線に接続されている。これにより、ノイズ低減効果を高めることができる。例えば、電圧レギュレータＶＲで発生するスイッチングノイズがノイズ源近傍で抑制され、スイッチングノイズがマザーボードに伝わりＩＣパッケージの外部に放射されることを抑制することができる。 The multi-terminal capacitor 1 is positioned so as to overlap the voltage regulator VR, i.e., directly below the voltage regulator VR, in a plan view along the main surface of the capacitor-embedded substrate 100B. The external electrode on the second main surface of the multi-terminal capacitor 1 is connected to the power supply wiring of the motherboard, and the external electrode on the first main surface of the multi-terminal capacitor 1 is connected to the power supply wiring for the input of the voltage regulator VR. This enhances the noise reduction effect. For example, switching noise generated by the voltage regulator VR is suppressed near the noise source, preventing the switching noise from being transmitted to the motherboard and radiated outside the IC package.

　一方、多端子コンデンサ３は、コンデンサ内蔵基板１００Ｂの主面に沿う平面視において、プロセッサと重なる位置、すなわちプロセッサの直下、に配置されている。また、多端子コンデンサ３は、コンデンサ内蔵基板１００Ｂの主面に沿う平面視において、インダクタＬと重なる位置、すなわちインダクタの直上、に配置されている。多端子コンデンサ３の第２主面の外部電極は、電圧レギュレータＶＲの出力の電源配線に接続されており、多端子コンデンサ３の第１主面の外部電極は、プロセッサの電源の電源配線に接続されている。これにより、ノイズ低減効果を高めることができる。例えば、電圧レギュレータＶＲで発生するスイッチングノイズが抑制され、また、インダクタＬで発生するノイズがノイズ源近傍で抑制され、これらのノイズがプロセッサに伝わりプロセッサが誤動作することを抑制することができる。 Meanwhile, multi-terminal capacitor 3 is positioned so that it overlaps with the processor, i.e., directly below the processor, when viewed in a plan view along the main surface of capacitor-embedded substrate 100B. Furthermore, multi-terminal capacitor 3 is positioned so that it overlaps with inductor L, i.e., directly above the inductor, when viewed in a plan view along the main surface of capacitor-embedded substrate 100B. The external electrode on the second main surface of multi-terminal capacitor 3 is connected to the power supply wiring for the output of voltage regulator VR, and the external electrode on the first main surface of multi-terminal capacitor 3 is connected to the power supply wiring for the processor's power supply. This enhances the noise reduction effect. For example, switching noise generated by voltage regulator VR is suppressed, and noise generated by inductor L is suppressed near the noise source, preventing this noise from being transmitted to the processor and causing it to malfunction.

　図４Ａに示すように、コンデンサ内蔵基板１００Ｂは、コア基材１０１と配線層１０２とを有する。コンデンサ内蔵基板１００Ｂの多端子コンデンサ１近傍では、マザーボード側の配線層１０２には、電源配線ＶＤＤ，ＶＳＳ（ＧＮＤ）が配置されており、電圧レギュレータＶＲ（ＩＣ）側の配線層１０２には、電源配線ＶＤＤ，ＶＳＳ（ＧＮＤ）が配置されている。 As shown in FIG. 4A, the capacitor-embedded substrate 100B has a core substrate 101 and a wiring layer 102. Near the multi-terminal capacitor 1 of the capacitor-embedded substrate 100B, power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the motherboard side, and power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the voltage regulator VR (IC) side.

　コア基材１０１の材料としては、エポキシ樹脂等の公知の材料が挙げられ、配線層１０２の材料としては、エポキシ樹脂等の公知の材料が挙げられる。電源配線ＶＤＤ，ＶＳＳは、配線層１０２に形成された導体パターンおよび導体ビアで構成される。導体パターンおよび導体ビアの材料としては、Ｃｕ等の公知の金属材料が挙げられる。 The core substrate 101 may be made of a known material such as epoxy resin, and the wiring layer 102 may be made of a known material such as epoxy resin. The power supply wiring VDD and VSS is composed of a conductor pattern and conductor vias formed on the wiring layer 102. The conductor pattern and conductor vias may be made of a known metal material such as Cu.

　一方、図４Ａに示すように、コンデンサ内蔵基板１００Ｂの多端子コンデンサ３近傍では、電圧レギュレータＶＲ（ＩＣ）側の配線層１０２には、電源配線ＶＤＤ，ＶＳＳ（ＧＮＤ）が配置されており、プロセッサ（ＩＣ）側の配線層１０２には、電源配線ＶＤＤ，ＶＳＳ（ＧＮＤ）が配置されている。 On the other hand, as shown in Figure 4A, near the multi-terminal capacitor 3 of the capacitor-embedded substrate 100B, power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the voltage regulator VR (IC) side, and power supply wiring VDD and VSS (GND) are arranged on the wiring layer 102 on the processor (IC) side.

　多端子コンデンサ３として上述した本発明の多端子コンデンサ１Ａが適用される場合、電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＤＤは、多端子コンデンサ３の第２主面Ｓ２の第１導体ビア３１の第１主面非接続導体ビア３１Ａに、第１外部電極４１および導体ビアを介して接続される。電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＳＳは、多端子コンデンサ３の第２主面Ｓ２の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 When the multi-terminal capacitor 1A of the present invention described above is used as the multi-terminal capacitor 3, the power supply wiring VDD on the voltage regulator VR(IC) side is connected to the first main surface unconnected conductor via 31A of the first conductor vias 31 on the second main surface S2 of the multi-terminal capacitor 3 via the first external electrode 41 and a conductor via. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to the second conductor via 32 on the second main surface S2 of the multi-terminal capacitor 3 via the second external electrode 42 and a conductor via.

　プロセッサ（ＩＣ）側の電源配線ＶＤＤは、多端子コンデンサ３の第１主面Ｓ１の第１導体ビア３１の第２主面非接続導体ビア３１Ｂに、第１外部電極４１および導体ビアを介して接続される。プロセッサ側の電源配線ＶＳＳは、多端子コンデンサ１の第１主面Ｓ１の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 The power supply wiring VDD on the processor (IC) side is connected to the second main surface unconnected conductor via 31B of the first conductor via 31 on the first main surface S1 of the multi-terminal capacitor 3 via the first external electrode 41 and a conductor via. The power supply wiring VSS on the processor side is connected to the second conductor via 32 on the first main surface S1 of the multi-terminal capacitor 1 via the second external electrode 42 and a conductor via.

　これにより、電圧レギュレータ（ＩＣ）側の電源配線ＶＤＤとプロセッサ（ＩＣ）側の電源配線ＶＤＤとの間に直列に、多端子コンデンサ３の第１内部電極層２１の一部が介在する。これにより、矢印で示されるように、プロセッサ（ＩＣ）の電源のＤＣ電流の少なくとも一部が、多端子コンデンサ３の第１内部電極層２１を流れる。これにより、ノイズ低減効果を高めることができる。例えば、例えば、電圧レギュレータＶＲで発生するスイッチングノイズが抑制され、スイッチングノイズがプロセッサに伝わりプロセッサが誤動作することを抑制することができる。 As a result, a portion of the first internal electrode layer 21 of the multi-terminal capacitor 3 is interposed in series between the power supply wiring VDD on the voltage regulator (IC) side and the power supply wiring VDD on the processor (IC) side. As a result, as shown by the arrow, at least a portion of the DC current of the processor (IC) power supply flows through the first internal electrode layer 21 of the multi-terminal capacitor 3. This enhances the noise reduction effect. For example, switching noise generated in the voltage regulator VR is suppressed, preventing the switching noise from being transmitted to the processor and causing it to malfunction.

　或いは、図４Ｂに示すように、多端子コンデンサ３として上述した本発明の多端子コンデンサ１Ｂが適用される場合、電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＤＤは、多端子コンデンサ３の第２主面Ｓ２の第１導体ビア３１の導体ビア３１Ｃに、第１外部電極４１および導体ビアを介して接続される。電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＳＳは、多端子コンデンサ１の第２主面Ｓ２の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 Alternatively, as shown in FIG. 4B, when the multi-terminal capacitor 1B of the present invention described above is used as the multi-terminal capacitor 3, the power supply wiring VDD on the voltage regulator VR(IC) side is connected to the conductor via 31C of the first conductor via 31 on the second main surface S2 of the multi-terminal capacitor 3 via the first external electrode 41 and the conductor via. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to the second conductor via 32 on the second main surface S2 of the multi-terminal capacitor 1 via the second external electrode 42 and the conductor via.

　或いは、図４Ｃに示すように、多端子コンデンサ３として上述した従来の多端子コンデンサ１Ｘが適用される場合、電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＤＤは、多端子コンデンサ３の第２主面Ｓ２の第１導体ビア３１Ｘの一部に、第１外部電極４１および導体ビアを介して接続される。電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＳＳは、多端子コンデンサ１の第２主面Ｓ２の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 Alternatively, as shown in FIG. 4C , when the above-described conventional multi-terminal capacitor 1X is used as the multi-terminal capacitor 3, the power supply wiring VDD on the voltage regulator VR(IC) side is connected to a portion of the first conductive via 31X on the second main surface S2 of the multi-terminal capacitor 3 via the first external electrode 41 and a conductive via. The power supply wiring VSS on the voltage regulator VR(IC) side is connected to the second conductive via 32 on the second main surface S2 of the multi-terminal capacitor 1 via the second external electrode 42 and a conductive via.

　プロセッサ（ＩＣ）側の電源配線ＶＤＤは、多端子コンデンサ３の第１主面Ｓ１の第１導体ビア３１Ｘであって、第２主面Ｓ２において電圧レギュレータＶＲ（ＩＣ）側の電源配線ＶＤＤに接続されていない第１導体ビア３１Ｘに、第１外部電極４１および導体ビアを介して接続される。プロセッサ（ＩＣ）側の電源配線ＶＳＳは、多端子コンデンサ１の第１主面Ｓ１の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 The power supply wiring VDD on the processor (IC) side is connected via a first external electrode 41 and a conductor via to a first conductor via 31X on the first main surface S1 of the multi-terminal capacitor 3 that is not connected to the power supply wiring VDD on the voltage regulator VR (IC) side on the second main surface S2. The power supply wiring VSS on the processor (IC) side is connected via a second external electrode 42 and a conductor via to a second conductor via 32 on the first main surface S1 of the multi-terminal capacitor 1.

　以上、本発明の実施形態について説明したが、本発明は上述した実施形態に限定されることなく、種々の変更および変形が可能である。例えば、上述した実施形態では、誘電体層と内部電極層とが積層された積層セラミックコンデンサを内蔵した基板における接続構造について例示した。しかし、本発明の特徴はこれに限定されず、例えば、半導体プロセスを応用して３次元化することで電極面を大幅に増やし、基板単位面積当たりの静電容量を大きくしたシリコンコンデンサを内蔵した基板における接続構造にも適用可能であり、また、陰極に導電性ポリマー（導電性高分子）を用いたポリマーコンデンサを内蔵した基板における接続構造にも適用可能である。 The above describes embodiments of the present invention, but the present invention is not limited to the above-described embodiments and various modifications and variations are possible. For example, the above-described embodiments illustrate connection structures in substrates incorporating multilayer ceramic capacitors in which dielectric layers and internal electrode layers are stacked. However, the features of the present invention are not limited to this. For example, the present invention can also be applied to connection structures in substrates incorporating silicon capacitors that have been made three-dimensional using semiconductor processes to significantly increase the electrode surface and increase the capacitance per unit area of the substrate, and can also be applied to connection structures in substrates incorporating polymer capacitors that use conductive polymers (conductive polymers) for the cathode.

［多端子コンデンサの変形例］
　以下では、多端子コンデンサの変形例として、シリコンコンデンサを例示する。図８は、変形例に係る多端子コンデンサの断面模式図である。図８に示すように、変形例の多端子コンデンサ１Ｃは、シリコン基板１０Ａと、第１内部電極層２１および第２内部電極層２２と、複数の第１外部電極（端子）４１および複数の第２外部電極（端子）４２とを備える。多端子コンデンサ１Ｃは、少なくとも５つの端子を有する。 [Modification of multi-terminal capacitor]
Below, a silicon capacitor will be exemplified as a modified example of a multi-terminal capacitor. Fig. 8 is a schematic cross-sectional view of a multi-terminal capacitor according to the modified example. As shown in Fig. 8, the modified multi-terminal capacitor 1C includes a silicon substrate 10A, first internal electrode layers 21 and second internal electrode layers 22, a plurality of first external electrodes (terminals) 41, and a plurality of second external electrodes (terminals) 42. The multi-terminal capacitor 1C has at least five terminals.

　シリコン基板１０Ａは、略直方体形状であり、第１主面Ｓ１および第２主面Ｓ２を有する。 The silicon substrate 10A has a generally rectangular parallelepiped shape and has a first main surface S1 and a second main surface S2.

　第１内部電極層２１および第２内部電極層２２は、シリコン基板１０Ａの第１主面Ｓ１に配置されている。第１内部電極層２１と第２内部電極層２２とは、誘電体層１２を挟んで互いに対向している。第１内部電極層２１および第２内部電極層２２の形状は、特に限定されないが、例えばトレンチ構造であってもよいし、平板構造であってもよい。第１内部電極層２１と第２内部電極層２２とは、静電容量を発生させ実質的にコンデンサとして機能する。 The first internal electrode layer 21 and the second internal electrode layer 22 are disposed on the first main surface S1 of the silicon substrate 10A. The first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric layer 12 sandwiched between them. The shapes of the first internal electrode layer 21 and the second internal electrode layer 22 are not particularly limited, but may be, for example, a trench structure or a flat plate structure. The first internal electrode layer 21 and the second internal electrode layer 22 generate electrostatic capacitance and essentially function as a capacitor.

　第１内部電極層２１および第２内部電極層２２の材料は、特に限定されないが、例えば、ポリシリコン等の半導体であってもよいし、金属等の導電体であってもよい。 The material of the first internal electrode layer 21 and the second internal electrode layer 22 is not particularly limited, but may be, for example, a semiconductor such as polysilicon, or a conductor such as metal.

　多端子コンデンサ１Ｃは、複数の第１導体ビア３１および複数の第２導体ビア３２を備えていてもよい。第１導体ビア３１および第２導体ビア３２は、シリコン基板１０Ａの内部に配置されている。第１導体ビア３１は、第１主面Ｓ１から第２主面Ｓ２まで延在し、第１主面Ｓ１および第２主面Ｓ２に露出し、第１主面Ｓ１および第２主面Ｓ２において第１外部電極４１に接続されている。第２導体ビア３２は、第１主面Ｓ１から第２主面Ｓ２まで延在し、第１主面Ｓ１および第２主面Ｓ２に露出し、第１主面Ｓ１および第２主面Ｓ２において第２外部電極４２に接続されている。 The multi-terminal capacitor 1C may include a plurality of first conductor vias 31 and a plurality of second conductor vias 32. The first conductor vias 31 and second conductor vias 32 are disposed inside the silicon substrate 10A. The first conductor vias 31 extend from the first main surface S1 to the second main surface S2, are exposed on the first main surface S1 and the second main surface S2, and are connected to the first external electrode 41 on the first main surface S1 and the second main surface S2. The second conductor vias 32 extend from the first main surface S1 to the second main surface S2, are exposed on the first main surface S1 and the second main surface S2, and are connected to the second external electrode 42 on the first main surface S1 and the second main surface S2.

　第１外部電極（端子）４１は、第１主面Ｓ１における第１内部電極層２１の複数の位置に配置され、第１内部電極層２１に接続されている。また、第１外部電極４１は、第１主面Ｓおよび第２主面Ｓ２における第１導体ビア３１の位置に配置され、第１導体ビア３１に接続されている。 The first external electrodes (terminals) 41 are arranged at multiple positions on the first internal electrode layer 21 on the first principal surface S1 and are connected to the first internal electrode layer 21. The first external electrodes 41 are also arranged at the positions of the first conductor vias 31 on the first principal surface S and the second principal surface S2 and are connected to the first conductor vias 31.

　第２外部電極（端子）４２は、第１主面Ｓ１における第２内部電極層２２の複数の位置に配置され、例えば導電体ビア（図示省略）を介して第２内部電極層２２に接続されている。また、第２外部電極（端子）４２は、第１主面Ｓおよび第２主面Ｓ２における第２導体ビア３２の位置に配置され、第２導体ビア３２に接続されている。 The second external electrodes (terminals) 42 are arranged at multiple positions on the second internal electrode layer 22 on the first principal surface S1 and are connected to the second internal electrode layer 22, for example, via conductive vias (not shown). The second external electrodes (terminals) 42 are also arranged at the positions of the second conductor vias 32 on the first principal surface S and the second principal surface S2 and are connected to the second conductor vias 32.

［コンデンサ内蔵基板の変形例］
　上述したＩＣパッケージ技術におけるチップレット技術において、例えば、プロセッサ（ＩＣ）とプロセッサ（ＩＣ）、プロセッサ（ＩＣ）とＨＢＭ（High Bandwidth Memory）等のメモリ（ＩＣ）のように、電源電圧が同一のチップを基板（パッケージ基板、インターポーザ、等）に搭載して組み合わせ、１つのＩＣパッケージに収める技術がある。 [Modification of Capacitor-Built-In Substrate]
The chiplet technology in the IC package technology described above includes a technology in which chips with the same power supply voltage, such as two processors (ICs) or one processor (IC) and a memory (IC) such as an HBM (High Bandwidth Memory), are mounted on a substrate (package substrate, interposer, etc.) and combined into a single IC package.

　例えば、プロセッサ（ＩＣ）とプロセッサ（ＩＣ）間、または、プロセッサ（ＩＣ）とメモリ（ＩＣ）間において、高周波信号の送受信のために、シリコン基板上に再配線層（Redistribution Layer：RDL）が配置されたブリッジダイが用いられることが知られている。 For example, it is known that bridge dies with a redistribution layer (RDL) disposed on a silicon substrate are used to transmit and receive high-frequency signals between processors (ICs) or between processors (ICs) and memory (ICs).

　この場合にも、プロセッサおよびメモリの近傍にデカップリング用およびノイズフィルタ用のコンデンサが必要になる。そこで、内部に、シリコンコンデンサおよび再配線層で構成されたブリッジダイが埋め込まれたコンデンサ内蔵基板を考案する。 In this case, too, capacitors for decoupling and noise filtering are required near the processor and memory. Therefore, we devised a capacitor-embedded substrate with an embedded bridge die made up of silicon capacitors and rewiring layers.

　図９Ａは、変形例に係るコンデンサ内蔵基板の断面模式図である。図９Ａに示すコンデンサ内蔵基板１００Ｃは、ＩＣパッケージに用いられるパッケージ基板またはインターポーザである。コンデンサ内蔵基板１００Ｃには、プロセッサおよびメモリ等のＩＣが例えば導体バンプ（図示省略）を介して搭載される。なお、ＩＣパッケージはマザーボードに搭載され、これにより、コンデンサ内蔵基板１００ＣのＩＣ搭載面と反対側にはマザーボードが配置される（図示省略）。 Figure 9A is a schematic cross-sectional view of a capacitor-embedded substrate according to a modified example. The capacitor-embedded substrate 100C shown in Figure 9A is a package substrate or interposer used in an IC package. ICs such as processors and memories are mounted on the capacitor-embedded substrate 100C via, for example, conductor bumps (not shown). The IC package is mounted on a motherboard, and thus a motherboard (not shown) is placed on the side of the capacitor-embedded substrate 100C opposite the IC-mounted surface.

　コンデンサ内蔵基板１００Ｃの内部には、上述したシリコンコンデンサで構成された多端子コンデンサ１Ｃおよび再配線層１０２で構成されたブリッジダイが埋め込まれている。ブリッジダイは、プロセッサとメモリとの間に跨って配置されている。 Embedded inside the capacitor-embedded substrate 100C is a multi-terminal capacitor 1C made of the silicon capacitor described above and a bridge die made of a rewiring layer 102. The bridge die is positioned across the processor and memory.

　再配線層１０２には、プロセッサ（ＩＣ）とメモリ（ＩＣ）とを接続する信号配線および電源配線ＶＤＤ，ＶＳＳ（ＧＮＤ）が配置されている。 The redistribution layer 102 contains signal wiring and power supply wiring VDD and VSS (GND) that connect the processor (IC) and memory (IC).

　マザーボード側の電源配線ＶＤＤは、多端子コンデンサ１Ｃの第２主面Ｓ２の第１導体ビア３１に、第１外部電極４１および導体ビアを介して接続される。マザーボード側の電源配線ＶＳＳは、多端子コンデンサ１Ｃの第２主面Ｓ２の第２導体ビア３２に、第２外部電極４２および導体ビアを介して接続される。 The power supply wiring VDD on the motherboard side is connected to the first conductive via 31 on the second main surface S2 of the multi-terminal capacitor 1C via the first external electrode 41 and a conductive via. The power supply wiring VSS on the motherboard side is connected to the second conductive via 32 on the second main surface S2 of the multi-terminal capacitor 1C via the second external electrode 42 and a conductive via.

　プロセッサ（ＩＣ）の電源配線ＶＤＤは、多端子コンデンサ１Ｃの第１主面Ｓ１の第１導体ビア３１および第１内部電極層２１の一部に、第１外部電極４１および導体ビアを介して接続される。プロセッサ（ＩＣ）の電源配線ＶＳＳは、多端子コンデンサ１Ｃの第１主面Ｓ１の第２導体ビア３２および第２内部電極層２２の一部に、第２外部電極４２および導体ビアを介して接続される。 The power supply wiring VDD of the processor (IC) is connected to the first conductive via 31 and part of the first internal electrode layer 21 on the first main surface S1 of the multi-terminal capacitor 1C via the first external electrode 41 and conductive via. The power supply wiring VSS of the processor (IC) is connected to the second conductive via 32 and part of the second internal electrode layer 22 on the first main surface S1 of the multi-terminal capacitor 1C via the second external electrode 42 and conductive via.

　メモリ（ＩＣ）の電源配線ＶＤＤは、多端子コンデンサ１Ｃの第１主面Ｓ１の第１導体ビア３１および第１内部電極層２１の他の一部に、第１外部電極４１および導体ビアを介して接続される。メモリ（ＩＣ）の電源配線ＶＳＳは、多端子コンデンサ１Ｃの第１主面Ｓ１の第２導体ビア３２および第２内部電極層２２の他の一部に、第２外部電極４２および導体ビアを介して接続される。 The power supply wiring VDD of the memory (IC) is connected to the first conductive via 31 and another portion of the first internal electrode layer 21 on the first main surface S1 of the multi-terminal capacitor 1C via the first external electrode 41 and a conductive via. The power supply wiring VSS of the memory (IC) is connected to the second conductive via 32 and another portion of the second internal electrode layer 22 on the first main surface S1 of the multi-terminal capacitor 1C via the second external electrode 42 and a conductive via.

　プロセッサ（ＩＣ）の電源配線ＶＤＤとメモリ（ＩＣ）の電源配線ＶＤＤとは、多端子コンデンサ１Ｃの第１内部電極層２１上の一部において切断されている。これにより、プロセッサ（ＩＣ）の電源配線ＶＤＤとメモリ（ＩＣ）の電源配線ＶＤＤとの間に直列に、多端子コンデンサ１Ｃの第１内部電極層２１の一部が介在する。 The power supply wiring VDD of the processor (IC) and the power supply wiring VDD of the memory (IC) are disconnected at a portion on the first internal electrode layer 21 of the multi-terminal capacitor 1C. As a result, a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1C is interposed in series between the power supply wiring VDD of the processor (IC) and the power supply wiring VDD of the memory (IC).

　これにより、プロセッサ（ＩＣ）とメモリ（ＩＣ）との間を伝搬する電源のＡＣ電流（ノイズ）の少なくとも一部が、多端子コンデンサ１Ｃの第１内部電極層２１を流れる。例えば、矢印で示されるように、プロセッサ（ＩＣ）で生じてメモリ（ＩＣ）に伝搬するノイズに起因するＡＣ電流は、多端子コンデンサ１Ｃの第１内部電極層２１の一部を流れる。或いは、メモリ（ＩＣ）で生じてプロセッサ（ＩＣ）に伝搬するノイズに起因するＡＣ電流は、多端子コンデンサ１Ｃの第１内部電極層２１の一部を流れる。これにより、プロセッサからメモリに伝わる伝導ノイズ、メモリからプロセッサに伝わる伝導ノイズが低減される。 As a result, at least a portion of the AC current (noise) of the power supply propagating between the processor (IC) and memory (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1C. For example, as shown by the arrows, AC current caused by noise generated in the processor (IC) and propagating to the memory (IC) flows through a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1C. Alternatively, AC current caused by noise generated in the memory (IC) and propagating to the processor (IC) flows through a portion of the first internal electrode layer 21 of the multi-terminal capacitor 1C. This reduces the conducted noise transmitted from the processor to the memory, and the conducted noise transmitted from the memory to the processor.

　ところで、実際には、プロセッサ（ＩＣ）の電源電圧とメモリ（ＩＣ）の電源電圧とには、ある程度の電位差が生じることがある。この場合、プロセッサ（ＩＣ）の入力の電源のＤＣ電流の少なくとも一部が、多端子コンデンサ１の第１内部電極層２１を流れる。或いは、メモリ（ＩＣ）の入力の電源のＤＣ電流の少なくとも一部が、多端子コンデンサ１の第１内部電極層２１を流れる。これにより、プロセッサからメモリに伝わる伝導ノイズ、メモリからプロセッサに伝わる伝導ノイズが低減される。 In reality, there may be a certain degree of potential difference between the power supply voltage of the processor (IC) and the power supply voltage of the memory (IC). In this case, at least a portion of the DC current of the power supply input to the processor (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. Alternatively, at least a portion of the DC current of the power supply input to the memory (IC) flows through the first internal electrode layer 21 of the multi-terminal capacitor 1. This reduces the conducted noise transmitted from the processor to the memory, and the conducted noise transmitted from the memory to the processor.

　上述したコンデンサ内蔵基板１００Ｃは、シリコンコンデンサで構成された多端子コンデンサ１Ｃおよび再配線層１０２で構成されたブリッジダイが基板（パッケージ基板、インターポーザ、等）に埋め込まれた形態である。なお、図９Ｂに示すように、コンデンサ内蔵基板１００Ｃは、ブリッジダイが基板に埋め込まれておらず、シリコンコンデンサで構成された多端子コンデンサ１Ｃおよび再配線層１０２で構成されたブリッジダイ単体であってもよい。 The above-mentioned capacitor-embedded substrate 100C has a configuration in which a bridge die made up of a multi-terminal capacitor 1C made up of a silicon capacitor and a rewiring layer 102 is embedded in a substrate (package substrate, interposer, etc.). As shown in Figure 9B, the capacitor-embedded substrate 100C may not have the bridge die embedded in the substrate, but may instead consist of a single bridge die made up of a multi-terminal capacitor 1C made up of a silicon capacitor and a rewiring layer 102.

　１，１Ａ，１Ｂ，１Ｃ，１Ｘ，１Ｙ，２，３　多端子コンデンサ
　１０　積層体
　１０Ａ　シリコン基板
　１２　誘電体層
　２１　第１内部電極層
　２１Ａ，２２Ａ　貫通孔
　２２　第２内部電極層
　３１，３１Ｘ　第１導体ビア
　３１Ａ　第１主面非接続導体ビア
　３１Ｂ　第２主面非接続導体ビア
　３１Ｃ　導体ビア
　３２　第２導体ビア
　４１　第１外部電極（端子）
　４２　第２外部電極（端子）
　１００Ａ，１００Ｂ，１００Ｃ　コンデンサ内蔵基板
　１０１　コア基材
　１０２　配線層，再配線層
　Ｌ　インダクタ
　Ｓ１　第１主面
　Ｓ２　第２主面
　Ｔ　積層方向
　ＶＤＤ，ＶＳＳ　電源配線 1, 1A, 1B, 1C, 1X, 1Y, 2, 3 Multi-terminal capacitor 10 Laminate 10A Silicon substrate 12 Dielectric layer 21 First internal electrode layer 21A, 22A Through hole 22 Second internal electrode layer 31, 31X First conductive via 31A First principal surface non-connected conductive via 31B Second principal surface non-connected conductive via 31C Conductor via 32 Second conductive via 41 First external electrode (terminal)
42 Second external electrode (terminal)
100A, 100B, 100C: Capacitor-embedded substrate 101: Core substrate 102: Wiring layer, rewiring layer L: Inductor S1: First principal surface S2: Second principal surface T: Stacking direction VDD, VSS: Power supply wiring

Claims

A substrate on which an IC is mounted,
a multi-terminal capacitor having at least five terminals, the multi-terminal capacitor having a first internal electrode layer and a second internal electrode layer that are embedded inside and opposed to each other;
the multi-terminal capacitor is connected to the IC so that at least a part of a DC current of a power supply of the IC flows through the first internal electrode layer of the multi-terminal capacitor;
Board with built-in capacitor.

a power supply wiring for supplying power to the IC;
the multi-terminal capacitor is a capacitor for decoupling a power supply of the IC,
the multi-terminal capacitor is connected to the power supply wiring in series with a part of the first internal electrode layer of the multi-terminal capacitor interposed therebetween;
The capacitor-embedded substrate according to claim 1 .

The multi-terminal capacitor is
a first main surface and a second main surface that face each other in a stacking direction of the first internal electrode layers and the second internal electrode layers;
a plurality of first conductor vias extending in the stacking direction, electrically connected to the first internal electrode layers, and electrically insulated from the second internal electrode layers;
a plurality of second conductor vias extending in the stacking direction, electrically insulated from the first internal electrode layers, and electrically connected to the second internal electrode layers;
a plurality of first external electrodes disposed on at least one of the first main surface and the second main surface and connected to the plurality of first conductive vias, respectively;
a plurality of second external electrodes disposed on at least one of the first main surface and the second main surface and connected to the plurality of second conductive vias, respectively;
The capacitor-embedded substrate according to claim 2 , comprising:

some of the plurality of first external electrodes are disposed on the first main surface;
another part of the plurality of first external electrodes is disposed on the second main surface;
a first external electrode on the first main surface and a first external electrode on the second main surface are connected to the power supply wiring in series with a part of the first internal electrode layer of the multi-terminal capacitor interposed therebetween;
The capacitor-embedded substrate according to claim 3 .

The capacitor-embedded substrate according to claim 3 or 4, wherein, in a plan view along the first principal surface and the second principal surface, the position of the first external electrode on the first principal surface connected to the power supply wiring is offset from the position of the first external electrode on the second principal surface connected to the power supply wiring.

The capacitor-embedded substrate according to claim 3 or 4, wherein the number of first external electrodes on the first principal surface connected to the power supply wiring is different from the number of first external electrodes on the second principal surface connected to the power supply wiring.

The capacitor-embedded substrate according to claim 3 or 4, wherein the total number of first external electrodes and second external electrodes arranged on the first principal surface is greater than the total number of first external electrodes and second external electrodes arranged on the second principal surface.

the IC includes a processor and a voltage regulator;
the multi-terminal capacitor is connected to the power supply wiring to the input of the voltage regulator;
The capacitor-embedded substrate according to any one of claims 2 to 7.

The capacitor-embedded substrate according to claim 8, wherein the multi-terminal capacitor is connected to the power supply wiring from the output of the voltage regulator to the power supply of the processor.

The capacitor-embedded substrate according to any one of claims 1 to 9, which is a package substrate or interposer used in an IC package.

The capacitor-embedded substrate according to any one of claims 1 to 10, wherein the multi-terminal capacitor is a multilayer ceramic capacitor, a silicon capacitor, or a polymer capacitor.

The capacitor-embedded substrate according to claim 8 or 9, wherein the multi-terminal capacitor is arranged in a position overlapping the IC, the voltage regulator, the processor, or an inductor constituting the voltage regulator, in a plan view along the main surface of the capacitor-embedded substrate.

A substrate on which two ICs are mounted,
a multi-terminal capacitor having at least five terminals, the multi-terminal capacitor having a first internal electrode layer and a second internal electrode layer that are embedded inside and opposed to each other;
the multi-terminal capacitor is connected to the two ICs so that at least a part of an AC current of a power supply propagating between the two ICs flows through the first internal electrode layer of the multi-terminal capacitor;
Board with built-in capacitor.

A bridge-type substrate disposed between two ICs,
a multi-terminal capacitor having first and second internal electrode layers opposed to each other and having at least five terminals;
the multi-terminal capacitor is connected to the two ICs so that at least a part of an AC current of a power supply propagating between the two ICs flows through the first internal electrode layer of the multi-terminal capacitor;
Board with built-in capacitor.

a power supply wiring for supplying power to the two ICs, the power supply wiring connecting the two ICs;
the multi-terminal capacitor is a capacitor for decoupling the power supplies of the two ICs,
the multi-terminal capacitor is connected to the power supply wiring in series with a part of the first internal electrode layer of the multi-terminal capacitor interposed therebetween;
The capacitor-embedded substrate according to claim 13 or 14.

The power supply voltages of the two ICs are the same,
the multi-terminal capacitor is a silicon capacitor,
a part of the power supply wiring is cut, so that a part of the first internal electrode layer of the multi-terminal capacitor is interposed in series with the power supply wiring;
The capacitor-embedded substrate according to claim 15.

a laminate in which a plurality of dielectric layers are stacked, the laminate having a first main surface and a second main surface opposing each other in a stacking direction;
a first internal electrode layer and a second internal electrode layer that are disposed inside the laminate and that face each other in the lamination direction with at least one dielectric layer of the plurality of dielectric layers interposed therebetween;
a plurality of first conductor vias disposed inside the laminate, extending in the lamination direction, electrically connected to the first internal electrode layers, and electrically insulated from the second internal electrode layers;
a plurality of second conductor vias disposed inside the laminate, extending in the stacking direction, electrically insulated from the first internal electrode layers, and electrically connected to the second internal electrode layers;
a plurality of first external electrodes disposed on at least one of the first main surface and the second main surface and connected to the plurality of first conductive vias, respectively;
a plurality of second external electrodes disposed on at least one of the first main surface and the second main surface and connected to the plurality of second conductive vias, respectively;
Equipped with
The plurality of first conductive vias are
a first-main-surface unconnected conductor via that does not extend to the first main surface and is not connected to one of the plurality of first external electrodes on the first main surface, and that extends to the second main surface and is connected to one of the plurality of first external electrodes on the second main surface;
a second-main-surface unconnected conductor via that extends to the first main surface and is connected to one of the plurality of first external electrodes on the first main surface, but does not extend to the second main surface and is not connected to one of the plurality of first external electrodes on the second main surface;
Including,
each of the plurality of second conductor vias extends from the first main surface to the second main surface and is connected to one of the plurality of second external electrodes on the first main surface and the second main surface;
Multi-terminal capacitor.

a laminate in which a plurality of dielectric layers are stacked, the laminate having a first main surface and a second main surface opposing each other in a stacking direction;
a first internal electrode layer and a second internal electrode layer that are disposed inside the laminate and that face each other in the lamination direction with at least one dielectric layer of the plurality of dielectric layers interposed therebetween;
a plurality of first conductor vias disposed inside the laminate, extending in the lamination direction, electrically connected to the first internal electrode layers, and electrically insulated from the second internal electrode layers;
a plurality of second conductor vias disposed inside the laminate, extending in the stacking direction, electrically insulated from the first internal electrode layers, and electrically connected to the second internal electrode layers;
a plurality of first external electrodes disposed on at least one of the first main surface and the second main surface and connected to the plurality of first conductive vias, respectively;
a plurality of second external electrodes disposed on at least one of the first main surface and the second main surface and connected to the plurality of second conductive vias, respectively;
Equipped with
The plurality of first conductive vias are
conductor vias extending from the first main surface to the second main surface and connected to one of the plurality of first external electrodes on the first main surface and the second main surface, respectively;
a second-main-surface unconnected conductor via that extends to the first main surface and is connected to one of the plurality of first external electrodes on the first main surface, but does not extend to the second main surface and is not connected to one of the plurality of first external electrodes on the second main surface;
Including,
each of the plurality of second conductor vias extends from the first main surface to the second main surface and is connected to one of the plurality of second external electrodes on the first main surface and the second main surface;
Multi-terminal capacitor.

A multi-terminal capacitor as described in claim 17 or 18, wherein the number of first external electrodes on the first principal surface is different from the number of first external electrodes on the second principal surface.

The multi-terminal capacitor described in claim 17 or 18, wherein each of the first external electrode and the second external electrode is a conductive pad or a conductive bump.