WO2025243586A1 - Doherty amplification circuit - Google Patents

Abstract

A Doherty amplification circuit (10) to which a D-ET mode or an SPT mode is applied comprises: a power amplifier (11) used as a carrier amplifier; a power amplifier (12) used as a peak amplifier; and a synthesizer (22) including an input terminal (221) connected to an output terminal of the power amplifier (11), an input terminal (222) connected to an output terminal of the power amplifier (12), and an output terminal (223). The size of the power amplifier (12) is smaller than the size of the power amplifier (11).

Description

Doherty amplifier circuit

The present invention relates to a Doherty amplifier circuit.

In recent years, wide modulation bandwidths (channel bandwidths) have been used for signals transmitted by wireless communication devices such as smartphones, tablet computers, and IoT (Internet of Things) devices. High-efficiency technologies have been proposed for power amplifier circuits that amplify signals with such wide modulation bandwidths.

For example, Patent Document 1 discloses a digital-envelope tracking (D-ET) mode that selectively supplies multiple discrete voltages to a Doherty amplifier circuit based on an envelope signal.

For example, Patent Document 2 discloses a symbol power tracking (SPT) mode in which the power supply voltage level is modulated in units of one symbol based on the power of the symbol interval.

US Patent Application Publication No. 2020/0350866 U.S. Pat. No. 1,068,6407

However, when D-ET mode or SPT mode is applied to a Doherty amplifier circuit, efficiency may decrease.

The present invention therefore provides a Doherty amplifier circuit that can suppress the decrease in efficiency of the Doherty amplifier circuit due to D-ET mode or SPT mode.

A Doherty amplifier circuit according to one aspect of the present invention is a Doherty amplifier circuit to which a Digital-Envelope Tracking (D-ET) mode or a Symbol Power Tracking (SPT) mode is applied, and includes a first power amplifier used as a carrier amplifier, a second power amplifier used as a peak amplifier, and a combiner including a first input terminal connected to the output end of the first power amplifier, a second input terminal connected to the output end of the second power amplifier, and a first output terminal, wherein the size of the second power amplifier is smaller than the size of the first power amplifier.

According to the present invention, it is possible to suppress the decrease in efficiency of a Doherty amplifier circuit due to D-ET mode or SPT mode.

FIG. 1A is a graph showing an example of the transition of the power supply voltage in the APT mode. FIG. 1B is a graph showing an example of the transition of the power supply voltage in the A-ET mode. FIG. 1C is a graph showing an example of the transition of the power supply voltage in the D-ET mode and the SPT mode. FIG. 2A is a diagram illustrating frames, subframes, slots, and symbols. FIG. 2B is a diagram showing an example of a transition of the power supply voltage in the SPT mode. FIG. 3 is a circuit configuration diagram of a communication device according to an embodiment. FIG. 4 is a graph showing the relationship between output power and efficiency in the Doherty amplifier circuits according to the embodiment and the comparative example. FIG. 5 is a flowchart showing the operation of the Doherty amplifier circuit according to this embodiment. FIG. 6 is a diagram showing the state of the Doherty amplifier circuit in the HP mode and the D-ET mode/SPT mode. FIG. 7 is a graph showing the relationship between output power and efficiency in the HP mode and the D-ET mode/SPT mode. FIG. 8 is a diagram showing the state of the Doherty amplifier circuit in the HP mode and the APT mode. FIG. 9 is a graph showing the relationship between input power and efficiency in the HP mode and the APT mode. FIG. 10 is a diagram showing the state of the Doherty amplifier circuit in the LP mode and the APT mode. FIG. 11 is a graph showing the relationship between input power and efficiency in the LP mode and the APT mode. FIG. 12 is a circuit configuration diagram of a Doherty amplifier circuit according to the first modification. FIG. 13 is a circuit configuration diagram of a Doherty amplifier circuit according to the second modification.

As a technology for highly efficient amplification of high-frequency signals, this section explains tracking mode, which supplies a power amplifier with a power supply voltage that is dynamically adjusted over time based on the high-frequency signal. Tracking mode is a mode that dynamically adjusts the power supply voltage applied to the power amplifier. There are several types of tracking mode, but here we will explain APT (Average Power Tracking) mode, A-ET (Analog Envelope Tracking) mode, D-ET mode, and SPT mode.

First, we will explain the APT mode, A-ET mode, and D-ET mode with reference to Figures 1A, 1B, and 1C. In Figures 1A, 1B, and 1C, the horizontal axis represents time and the vertical axis represents voltage. Furthermore, the thick solid line represents the power supply voltage, and the thin solid line (waveform) represents the modulation signal.

Figure 1A is a graph showing an example of the transition of power supply voltage in APT mode. APT mode is a mode in which the power supply voltage is varied between multiple discrete voltage levels in one-frame units based on the average power.

A frame is a unit that makes up a high-frequency signal (modulated signal). For example, in 5GNR (5th Generation New Radio) and LTE (Long Term Evolution), a frame contains 10 subframes, each subframe contains multiple slots, and each slot contains multiple symbols. The subframe length is 1 millisecond, and the frame length is 10 milliseconds.

Note that the APT mode may include a mode in which the voltage level is varied in units larger than one frame based on the average power, and may also include a mode in which the voltage level is varied in units smaller than one frame (e.g., subframe or slot units) based on the average power.

Figure 1B is a graph showing an example of the progression of the power supply voltage in A-ET mode. A-ET mode is a mode in which the power supply voltage is continuously varied based on an envelope signal. In A-ET mode, the power supply voltage can track the envelope of the modulating signal.

An envelope signal is a signal that indicates the envelope of a modulated signal. The envelope value is expressed, for example, as the square root of (I ² +Q ² ). Here, (I, Q) represent constellation points. A constellation point is a point that represents a digitally modulated signal on a constellation diagram. (I, Q) is determined, for example, by a BBIC (Baseband Integrated Circuit) based on transmission information.

Figure 1C is a graph showing an example of the transition of the power supply voltage in D-ET mode and SPT mode. D-ET mode is a mode in which the power supply voltage is varied to multiple discrete voltage levels within one frame based on an envelope signal. In D-ET mode, the power supply voltage can track the envelope of the modulating signal, and the power supply voltage level varies at shorter time intervals than in APT mode.

SPT mode is a mode in which the power supply voltage level is modulated in units of one symbol based on the power of the symbol interval. In other words, in SPT mode, the power supply voltage level can be changed in units of one symbol.

Here, SPT mode will be explained with reference to Figures 2A and 2B. Figure 2A is a diagram showing frames, subframes, slots, and symbols. Figure 2B is a diagram showing changes in power supply voltage levels in SPT mode. Note that Figures 2A and 2B show the relationship between frames, subframes, slots, and symbols in 5G NR and LTE.

As shown in Figure 2A, a frame is a unit of high-frequency signals with a length of 10 milliseconds and includes 10 subframes. A subframe is a unit of high-frequency signals with a length of 1 millisecond and includes two slots. A slot is a unit of high-frequency signals with a length of 0.5 milliseconds and includes six symbols. A symbol is a unit of high-frequency signals with a length of 71 microseconds and includes a cyclic prefix (CP).

As shown in Figure 2B, in SPT mode, the power supply voltage level is modulated in units of one symbol. At this time, the voltage level is changed in the CP section. For example, in symbol "1", the voltage level is changed to a higher voltage level in the CP, and in symbol "2", the voltage level is changed to a lower voltage level in the CP. Note that the voltage level does not have to be changed, as in symbol "5". The power supply voltage level can be modulated based on the data signal in each symbol section.

(Embodiment)
Hereinafter, embodiments will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present invention.

Note that each figure is a schematic diagram in which emphasis, omission, or adjustment of proportions has been made as appropriate, and is not necessarily an exact illustration, and may differ from the actual shape, positional relationship, and proportions. In each figure, the same reference numerals are used to designate substantially identical components, and redundant explanations may be omitted or simplified.

In the following explanation, "connected" includes not only direct connection via connection terminals and/or wiring conductors, but also electrical connection via other circuit elements. "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B, and that they are arranged in series on the path connecting A and B. "Path connecting A and B" means a path made up of conductors that electrically connect A to B.

"Terminal" means the point where a conductor within an element terminates. Note that if the impedance of the conductor between elements is sufficiently low, terminal is interpreted as any point on the conductor between elements or the entire conductor, not just a single point.

"Filter passband" is the portion of the frequency spectrum transmitted by the filter, and is defined as the frequency band between two frequencies 3 dB above the minimum power insertion loss.

"Transmission band" refers to the frequency band used for transmission in a communication device, and "reception band" refers to the frequency band used for reception in a communication device. For example, in a frequency division duplex (FDD) band, different frequency bands (e.g., uplink and downlink bands) are used as the transmission band and reception band. Also, for example, in a time division duplex (TDD) band, the same frequency band is used as the transmission band and reception band.

"Power amplifier size" refers to the area of the emitter region in a planar view if the amplifying transistor is a bipolar transistor, and to the gate width if the amplifying transistor is a FET.

Terms indicating the relationship between elements, such as "parallel" and "perpendicular," terms indicating the shape of elements, such as "rectangle," and numerical ranges do not only express strict meanings, but also include substantially equivalent ranges, for example, including an error of a few percent.

[1. Circuit configuration of communication device 6]
An exemplary circuit configuration of the communication device 6 according to this embodiment will be described with reference to Fig. 3. Fig. 3 is a circuit configuration diagram of the communication device 6 according to this embodiment.

Note that FIG. 3 is an exemplary circuit diagram, and the communication device 6 may be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the communication device 6 provided below should not be construed as limiting.

The communication device 6 according to this embodiment can be used to provide wireless connectivity. For example, the communication device 6 can be implemented in UEs in a cellular network (also called a mobile network), such as mobile phones, smartphones, tablet computers, and wearable devices. In another example, the communication device 6 can be implemented to provide wireless connectivity to Internet of Things (IoT) sensor devices, medical/healthcare devices, cars, unmanned aerial vehicles (UAVs) (also known as drones), and automated guided vehicles (AGVs). In yet another example, the communication device 6 can be implemented to provide wireless connectivity at a wireless access point or wireless hotspot.

The communication device 6 includes a high-frequency circuit 1, an antenna 2, an RFIC (Radio Frequency Integrated Circuit) 3, a BBIC (Baseband Integrated Circuit) 4, and a tracker circuit 5.

The high-frequency circuit 1 can transmit high-frequency signals between the antenna 2 and the RFIC 3. The circuit configuration of the high-frequency circuit 1 will be described later.

Antenna 2 is connected to antenna connection terminal 100 of high-frequency circuit 1. Antenna 2 can receive high-frequency signals from high-frequency circuit 1 and transmit them to the outside of communication device 6. Antenna 2 may also receive high-frequency signals from the outside of communication device 6 and output them to high-frequency circuit 1. Antenna 2 does not have to be included in communication device 6. Communication device 6 may also include one or more antennas in addition to antenna 2.

The RFIC 3 is an example of a signal processing circuit that processes high-frequency signals. Specifically, the RFIC 3 can process the transmission signal input from the BBIC 4 by up-conversion or the like, and output the high-frequency transmission signal generated by this signal processing to the high-frequency circuit 1. Furthermore, the RFIC 3 can process the high-frequency reception signal input via the reception path of the high-frequency circuit 1 by down-conversion or the like, and output the reception signal generated by this signal processing to the BBIC 4. The RFIC 3 may also have a control unit that controls the switches and power amplifiers of the high-frequency circuit 1. Note that some or all of the control unit functions of the RFIC 3 may be included outside the RFIC 3, and may be included in the BBIC 4 or the high-frequency circuit 1, for example.

The BBIC 4 is a baseband signal processing circuit that processes signals using a frequency band lower than the high-frequency signals transmitted by the high-frequency circuit 1. Signals processed by the BBIC 4 include, for example, image signals for image display and/or audio signals for calls via a speaker. The BBIC 4 does not necessarily have to be included in the communication device 6.

The tracker circuit 5 can supply a power supply voltage for operating the Doherty amplifier circuit 10 in D-ET mode and/or SPT mode. Furthermore, the tracker circuit 5 can also supply a power supply voltage for operating the Doherty amplifier circuit 10 in APT mode.

[2. Circuit configuration of high-frequency circuit 1]
Next, the circuit configuration of the high-frequency circuit 1 according to this embodiment will be described with reference to Fig. 3. Note that Fig. 3 is an exemplary circuit configuration diagram, and the high-frequency circuit 1 can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the high-frequency circuit 1 provided below should not be interpreted as limiting.

The high-frequency circuit 1 includes a Doherty amplifier circuit 10, filters 41, 42, 43, and 44, switch circuits 51 and 52, and an antenna connection terminal 100.

The antenna connection terminal 100 is an external connection terminal of the high-frequency circuit 1, and is connected to the antenna 2 outside the high-frequency circuit 1, and is connected to the switch circuit 51 inside the high-frequency circuit 1.

The Doherty amplifier circuit 10 is an amplifier circuit that achieves high efficiency by using multiple power amplifiers as carrier amplifiers and peak amplifiers. In the Doherty amplifier circuit 10, a carrier amplifier is a power amplifier that operates regardless of whether the power of the input signal (high-frequency signal) is low or high. Basically, a carrier amplifier operates in class A or class AB. In the Doherty amplifier circuit 10, a peak amplifier is a power amplifier that primarily operates when the power of the input signal is high. Basically, a peak amplifier operates in class C.

Filter 41 is a bandpass filter having a passband that includes the transmission band of band A. Filter 41 is connected between switch circuits 51 and 52.

Filter 42 is a bandpass filter having a passband that includes the transmission band of band B. Filter 42 is connected between switch circuits 51 and 52.

Filter 43 is a bandpass filter having a passband that includes the transmission band of band C. Filter 43 is connected between switch circuits 51 and 52.

Filter 44 is a bandpass filter having a passband that includes the transmission band of band D. Filter 44 is connected between switch circuits 51 and 52.

Filters 41 to 44 may be, but are not limited to, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, LC resonant filters, dielectric resonant filters, or any combination thereof.

Bands A to D are frequency bands for communication systems built using Radio Access Technology (RAT), and are pre-defined by standardization organizations (such as 3GPP (registered trademark) (3rd Generation Partnership Project) and IEEE (Institute of Electrical and Electronics Engineers)). Examples of communication systems include 5G NR systems, LTE systems, and WLAN (Wireless Local Area Network) systems.

The switch circuit 51 is connected between the antenna connection terminal 100 and the filters 41 to 44, and includes a common terminal 510 and selection terminals 511, 512, 513, and 514. The common terminal 510 is connected to the antenna connection terminal 100. The selection terminals 511 to 514 are connected to the filters 41 to 44, respectively.

In this connection configuration, the switch circuit 51 can exclusively connect the common terminal 510 to the selection terminals 511 to 514, for example, based on a control signal from the RFIC 3. The switch circuit 51 is configured, for example, as an SP4T (Single-Pole Quadruple-Throw) type switch circuit.

The switch circuit 52 is connected between the Doherty amplifier circuit 10 and the filters 41 to 44, and includes a common terminal 520 and selection terminals 521, 522, 523, and 524. The common terminal 520 is connected to the Doherty amplifier circuit 10. The selection terminals 521 to 524 are connected to the filters 41 to 44, respectively.

In this connection configuration, the switch circuit 52 can exclusively connect the common terminal 520 to the selection terminals 521 to 524, for example, based on a control signal from the RFIC 3. The switch circuit 52 is configured, for example, as an SP4T type switch circuit.

3. Circuit Configuration of Doherty Amplifier Circuit 10
Next, the circuit configuration of the Doherty amplifier circuit 10 according to this embodiment will be described with reference to FIG.

Note that FIG. 3 is an exemplary circuit diagram, and the Doherty amplifier circuit 10 may be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the Doherty amplifier circuit 10 provided below should not be construed as limiting.

The Doherty amplifier circuit 10 includes power amplifiers 11, 12, and 13, a divider 21, a combiner 22, bias circuits 31 and 32, a switch 33, a capacitor 34, a high-frequency input terminal 101, a high-frequency output terminal 102, and a power supply voltage terminal 103.

The radio frequency input terminal 101 is an external connection terminal of the Doherty amplifier circuit 10. The radio frequency input terminal 101 is connected to the RFIC 3 outside the Doherty amplifier circuit 10, and is connected to the distributor 21 inside the Doherty amplifier circuit 10. The Doherty amplifier circuit 10 can receive transmission signals of bands A to D from the RFIC 3 via the radio frequency input terminal 101.

The radio frequency output terminal 102 is an external connection terminal of the Doherty amplifier circuit 10. The radio frequency output terminal 102 is connected to the common terminal 520 of the switch circuit 52 outside the Doherty amplifier circuit 10, and is connected to the combiner 22 inside the Doherty amplifier circuit 10. The Doherty amplifier circuit 10 can supply amplified transmission signals for bands A to D to the switch circuit 52 via the radio frequency output terminal 102.

The power supply voltage terminal 103 is an external connection terminal of the Doherty amplifier circuit 10. The power supply voltage terminal 103 is connected to the tracker circuit 5 outside the Doherty amplifier circuit 10, and is connected to the power amplifiers 11 to 13 inside the Doherty amplifier circuit 10. The Doherty amplifier circuit 10 can receive a power supply voltage from the tracker circuit 5 via the power supply voltage terminal 103.

Power amplifier 11 is an example of a first power amplifier and is used as a carrier amplifier. Power amplifier 11 is the power stage (output stage) of a multi-stage amplifier circuit, and is able to amplify the high-frequency signal amplified by power amplifier 13 using the power supply voltage supplied from tracker circuit 5. The input terminal of power amplifier 11 is connected to distributor 21, and the output terminal of power amplifier 11 is connected to combiner 22.

Power amplifier 12 is an example of a second power amplifier and is used as a peak amplifier. Power amplifier 12 is the power stage (output stage) of a multi-stage amplifier circuit, and can amplify the high-frequency signal amplified by power amplifier 13 using the power supply voltage supplied from tracker circuit 5. The input terminal of power amplifier 12 is connected to distributor 21, and the output terminal of power amplifier 12 is connected to combiner 22.

Note that the size of power amplifier 12 is smaller than the size of power amplifier 11. As a result, in the Doherty amplifier circuit 10 (present embodiment), fluctuations in output power and efficiency due to the operation and non-operation of the peak amplifier are smaller than in a Doherty amplifier circuit (comparison example) in which the size of the peak amplifier is equal to the size of the carrier amplifier, and the difference in output power at which peak efficiency can be obtained (back-off) is smaller.

Figure 4 is a graph showing the relationship between output power and efficiency in the Doherty amplifier circuits according to this embodiment and a comparative example. In Figure 4, the horizontal axis represents output power Pout, and the vertical axis represents the power-added efficiency Eff of the Doherty amplifier circuit. In the Doherty amplifier circuit according to the comparative example, the size of the peak amplifier is equal to the size of the carrier amplifier, and 6 dB back-off is obtained. In the Doherty amplifier circuit 10 according to this embodiment, the size of the peak amplifier is smaller than the size of the carrier amplifier, and 3 dB back-off, which is smaller than 6 dB back-off, is obtained.

Power amplifier 13 is an example of a third power amplifier and is the drive stage (input stage) of a multi-stage amplifier circuit. The input terminal of power amplifier 13 is connected to radio frequency input terminal 101, and the output terminal of power amplifier 13 is connected to distributor 21. Note that power amplifier 13 does not necessarily have to be included in Doherty amplifier circuit 10.

Power amplifiers 11-13 may be configured with heterojunction bipolar transistors (HBTs) and may be manufactured using semiconductor materials. Examples of semiconductor materials that may be used include silicon germanium (SiGe) and gallium arsenide (GaAs). The amplifying transistors of power amplifiers 11-13 are not limited to HBTs. For example, power amplifiers 11-13 may be configured with high electron mobility transistors (HEMTs) or metal-semiconductor field effect transistors (MESFETs). In this case, gallium nitride (GaN) or silicon carbide (SiC) may be used as the semiconductor material. Also, different types of amplifying transistors may be used for power amplifiers 11 and 12 and power amplifier 13. For example, HBTs may be used for power amplifiers 11 and 12, and a complementary metal oxide semiconductor (CMOS) may be used for power amplifier 13.

The divider 21 is connected between the power amplifier 13 and the power amplifiers 11 and 12, and can divide the high-frequency signal amplified by the power amplifier 13 into two high-frequency signals with a phase difference of 90 degrees and supply them to the power amplifiers 11 and 12, respectively. Specifically, the divider 21 includes an input terminal 211 and output terminals 212 and 213. The input terminal 211 is an example of a third input terminal and is connected to the output terminal of the power amplifier 13. The output terminal 212 is an example of a second output terminal and is connected to the input terminal of the power amplifier 11. The output terminal 213 is an example of a third output terminal and is connected to the input terminal of the power amplifier 12. Note that the divider 21 does not have to be included in the Doherty amplifier circuit 10. In this case, the Doherty amplifier circuit 10 may have two high-frequency input terminals for respectively receiving the two already-divided high-frequency signals.

In FIG. 3, a quadrature hybrid coupler (90-degree hybrid coupler) is used as the divider 21. The quadrature hybrid coupler of the divider 21 may be, for example, a parallel plate coupler, a lumped constant coupler, a quarter-wave line coupler, or a branch-line coupler, but is not limited to these. Furthermore, the divider 21 is not limited to a quadrature hybrid coupler. For example, the divider 21 may be a 180-degree hybrid coupler or an in-phase divider (e.g., a Wilkinson divider). In this case, a phase adjustment circuit may be connected to the 180-degree hybrid coupler or the in-phase divider.

The combiner 22 is connected between the power amplifiers 11 and 12 and the high-frequency output terminal 102, and can combine two high-frequency signals amplified by the power amplifiers 11 and 12, each having a phase difference of 90 degrees, and supply the combined signal to the high-frequency output terminal 102. Specifically, the combiner 22 includes input terminals 221 and 222, an output terminal 223, and a quarter-wave line 224. The input terminal 221 is an example of a first input terminal and is connected to the output terminal of the power amplifier 11. The input terminal 222 is an example of a second input terminal and is connected to the output terminal of the power amplifier 12. The output terminal 223 is an example of a first output terminal and is connected to the high-frequency output terminal 102. The quarter-wave line 224 is connected between the input terminal 221 and the output terminal 223, and can shift the phase of the high-frequency signal amplified by the power amplifier 11 by -90 degrees (delay by 90 degrees). The quarter-wave line 224 can also rotate the load impedance by 180 degrees on the Smith chart.

The bias circuit 31 is connected to the power amplifier 11 and can supply a bias current to the power amplifier 11. The bias circuit 31 can supply a bias current according to the power control level.

The bias circuit 32 is connected to the power amplifier 12 and can supply a bias current to the power amplifier 12. The bias circuit 31 can supply a bias current according to the power control level.

The switch 33 and the capacitor 34 are connected in series between the path connecting the output terminal of the power amplifier 11 and the input terminal 221 of the combiner 22 and ground. In FIG. 3, the capacitor 34 is connected between the switch 33 and ground. Specifically, one end of the switch 33 is connected to the path connecting the output terminal of the power amplifier 11 and the input terminal 221 of the combiner 22, and the other end of the switch 33 is connected to the capacitor 34. One of the two electrodes of the capacitor 34 is connected to the switch 33, and the other of the two electrodes of the capacitor 34 is connected to ground. The switch 33 may also be connected between the capacitor 34 and ground. The switch 33 and the capacitor 34 do not have to be included in the Doherty amplifier circuit 10.

In this type of connection configuration, the switch 33 can switch between conductive and non-conductive states based on, for example, a control signal from the RFIC 3. The switch 33 is configured, for example, as an SPST (Single-Pole Single-Throw) type switch circuit.

In the circuit configuration of the Doherty amplifier circuit 10 shown in FIG. 3, other circuit elements and wiring may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawing. For example, in the Doherty amplifier circuit 10, an impedance matching circuit may be inserted between the power amplifier 13 and the divider 21.

4. Operation of Doherty Amplifier Circuit 10
The operation of the Doherty amplifier circuit 10 described above will be described with reference to Fig. 5. Fig. 5 is a flowchart showing the operation of the Doherty amplifier circuit 10 according to this embodiment.

First, as shown in FIG. 5, a determination is made between high power (HP) mode and low power (LP) mode (S100). HP mode is a mode that is applied when the power control level is equal to or greater than a threshold level. On the other hand, LP mode is a mode that is applied when the power control level is less than the threshold level. The threshold level can be determined in advance experimentally and/or empirically.

Here, if the HP mode is determined in step S100 (HPM in S100), the switch 33 is set to the OFF state (S102). That is, the switch 33 is open, and the capacitor 34 is not connected between the path connecting the power amplifier 11 and the combiner 22 and ground. Furthermore, the bias circuit 31 supplies a bias current Ib11 to the power amplifier 11 (carrier amplifier) (S104). As a result, the power amplifier 11 operates in class A or class AB. Furthermore, the bias circuit 32 supplies a bias current Ib21 to the power amplifier 12 (peak amplifier) (S106). The bias current Ib21 is an example of a first bias current, and has a smaller current value than the bias current Ib22 described below. As a result, the power amplifier 12 operates in class C. In this state, the D-ET mode, SPT mode, or APT mode is applied to the Doherty amplifier circuit 10 (S108). For example, if the modulation bandwidth (channel bandwidth) of the high-frequency signal is less than the threshold width, D-ET mode or SPT mode may be applied, and if the modulation bandwidth of the high-frequency signal is equal to or greater than the threshold width, APT mode may be applied.

On the other hand, if the LP mode is determined in step S100 (LPM in S100), the switch 33 is set to the ON state (S112). That is, the switch 33 is closed, and the capacitor 34 is connected between the path connecting the power amplifier 11 and the combiner 22 and ground. Furthermore, the bias circuit 31 does not supply a bias current to the power amplifier 11 (carrier amplifier) (S114). As a result, the power amplifier 11 does not operate. Furthermore, the bias circuit 32 supplies a bias current Ib22 to the power amplifier 12 (peak amplifier) (S116). The bias current Ib22 is an example of a second bias current, and has a current value greater than the bias current Ib21. As a result, the power amplifier 12 operates in class A or class AB. In this state, the APT mode is applied to the Doherty amplifier circuit 10 (S118).

Each of the above modes will be explained in detail with reference to Figures 6 to 11.

Figure 6 shows the state of the Doherty amplifier circuit in HP mode and D-ET mode/SPT mode. Figure 7 is a graph showing the relationship between output power and efficiency in HP mode and D-ET mode/SPT mode. In Figure 7, the horizontal axis represents output power Pout, and the vertical axis represents power-added efficiency Eff of the Doherty amplifier circuit 10.

As shown in Figure 6, in HP mode and D-ET mode/SPT mode, switch 33 is open, and bias circuits 31 and 32 supply bias currents Ib11 and Ib21 to power amplifiers 11 and 12, respectively. This causes power amplifiers 11 and 12 to operate in class AB (or class A) and class C, respectively. Furthermore, power amplifiers 11 to 13 are supplied with a power supply voltage Vcc1 that fluctuates between multiple discrete voltage levels Vcc11 to Vcc13 within one frame based on the envelope or symbol.

As a result, the relationship between output power Pout and power-added efficiency Eff is obtained as shown in Figure 7. At voltage level Vcc13, a 3 dB back-off is achieved by operating and non-operating the peak amplifier and the resulting changes in load impedance. By achieving a 3 dB back-off, which is smaller than the 5 dB back-off that corresponds to the PAPR (Peak-to-Average Power Ratio) of a typical high-frequency signal, it is possible to switch the voltage level of power supply voltage Vcc1 before power amplifiers 11 and 12 saturate, thereby suppressing gain fluctuations. This reduces the difficulty of digital pre-distortion (DPD) and contributes to reducing distortion.

Furthermore, at lower output power Pout, a power supply voltage Vcc1 with a voltage level Vcc12, which is lower than the voltage level Vcc13, is supplied, expanding the high-efficiency region. At even lower output power Pout, a power supply voltage Vcc1 with a voltage level Vcc11, which is lower than the voltage level Vcc12, is supplied, further expanding the high-efficiency region. This makes it possible to achieve high efficiency in the 5 dB back-off region, which corresponds to the PAPR of typical high-frequency signals.

Figure 8 shows the state of the Doherty amplifier circuit in HP mode and APT mode. Figure 9 is a graph showing the relationship between input power and efficiency in HP mode and APT mode. In Figure 9, the horizontal axis represents output power Pout, and the vertical axis represents power-added efficiency Eff of the Doherty amplifier circuit 10.

As shown in Figure 8, in HP mode and APT mode, switch 33 is open, and bias circuits 31 and 32 supply bias currents Ib11 and Ib21 to power amplifiers 11 and 12, respectively. This causes power amplifiers 11 and 12 to operate in class AB (or class A) and class C, respectively. Furthermore, power amplifiers 11 to 13 are supplied with power supply voltage Vcc2, which fluctuates between multiple discrete voltage levels in one-frame units based on the average power.

As a result, the relationship between output power Pout and power-added efficiency Eff is obtained as shown in Figure 9. A 3 dB back-off is achieved by operating and disabling the peak amplifier and by changing the load impedance accordingly. This type of APT mode may be used when it is difficult to apply D-ET mode or SPT mode in HP mode.

Figure 10 shows the state of the Doherty amplifier circuit in LP mode and APT mode. Figure 11 is a graph showing the relationship between input power and efficiency in LP mode and APT mode. In Figure 11, the horizontal axis represents output power Pout, and the vertical axis represents power-added efficiency Eff of the Doherty amplifier circuit 10.

As shown in Figure 10, in LP mode and APT mode, bias circuit 31 does not supply bias current to power amplifier 11, and bias circuit 32 supplies bias current Ib22, which has a current value greater than bias current Ib21, to power amplifier 12. This causes power amplifier 11 to be shut down (SD), and power amplifier 12 operates in class AB (or class A). Furthermore, power amplifiers 11 to 13 are supplied with power supply voltage Vcc2, which fluctuates between multiple discrete voltage levels in one-frame units based on the average power.

At this time, switch 33 is closed. As a result, the output impedance of power amplifier 11 is shorted and rotated 180 degrees on the Smith chart by quarter-wave line 224. Therefore, the impedance seen from output terminal 223 toward power amplifier 11 is open.

As a result, the relationship between output power Pout and power-added efficiency Eff is obtained as shown in Figure 11. Because the smaller-sized power amplifier 12 operates and the larger-sized power amplifier 11 is stopped, power consumption in the Doherty amplifier circuit 10 is reduced. Furthermore, by applying the APT mode, power consumption in the tracker circuit 5 is also reduced.

5. Summary
As described above, the Doherty amplifier circuit 10 according to this embodiment is a Doherty amplifier circuit 10 to which the D-ET mode or the SPT mode is applied, and includes a power amplifier 11 used as a carrier amplifier, a power amplifier 12 used as a peak amplifier, and a combiner 22 including an input terminal 221 connected to the output end of the power amplifier 11 and an input terminal 222 and an output terminal 223 connected to the output end of the power amplifier 12, and the size of the power amplifier 12 is smaller than the size of the power amplifier 11.

As a result, because the peak amplifier is smaller than the carrier amplifier, fluctuations in output power and efficiency due to operation and non-operation of the peak amplifier are smaller, achieving a smaller back-off. The smaller back-off provided by the Doherty amplifier circuit, combined with the synergistic effect of D-ET mode or SPT mode, can further improve efficiency. Furthermore, the voltage level of power supply voltage Vcc1 can be switched before power amplifiers 11 and 12 reach saturation, suppressing gain fluctuations. As a result, the difficulty of digital pre-distortion can be reduced, contributing to reduced distortion.

Furthermore, for example, in the Doherty amplifier circuit 10 according to this embodiment, in the HP mode in which the power control level is equal to or greater than the threshold level, power amplifiers 11 and 12 may operate, and in the LP mode in which the power control level is less than the threshold level, power amplifier 12 may operate and power amplifier 11 may be shut down.

As a result, by operating the two power amplifiers 11 and 12 in HP mode, it is possible to handle high output power. On the other hand, by shutting down the larger power amplifier 11 in LP mode, high efficiency can be achieved.

Furthermore, for example, in the Doherty amplifier circuit 10 according to this embodiment, the combiner 22 may include a quarter-wave line 224 connected between the input terminal 221 and the output terminal 223.

As a result, impedance conversion according to the output of the peak amplifier is performed by the quarter-wave line 224, improving power efficiency.

Furthermore, for example, the Doherty amplifier circuit 10 according to this embodiment may further include a switch 33 and a capacitor 34 connected in series between the path connecting the output end of the power amplifier 11 and the input terminal 221 and ground.

This allows the impedance (phase) of the power amplifier 11 as seen from the output terminal 223 of the combiner 22 to be adjusted by opening and closing the switch 33.

Furthermore, for example, in the Doherty amplifier circuit 10 according to this embodiment, the switch 33 may be open in the HP mode and closed in the LP mode.

As a result, switch 33 is closed in LP mode, so when power amplifier 11 is shut down, the impedance seen from output terminal 223 of combiner 22 toward power amplifier 11 can be brought closer to an open state. This prevents the high-frequency signal amplified by power amplifier 12 from leaking to power amplifier 11, improving power efficiency.

Furthermore, for example, in the Doherty amplifier circuit 10 according to this embodiment, the power amplifier 12 may operate in class C in HP mode, and in LP mode, the power amplifier 12 may operate in class A or class AB.

As a result, by operating the power amplifier 12 in class C in HP mode, it can be operated as a peak amplifier, improving power efficiency. On the other hand, by operating the power amplifier 12 in class A or class AB in LP mode, it becomes possible to shut down the power amplifier 11, improving power efficiency at low output power.

Furthermore, for example, the Doherty amplifier circuit 10 according to this embodiment may further include a bias circuit 32 configured to supply a bias current to the power amplifier 12, and in HP mode, the bias circuit 32 may supply a bias current Ib21 to the power amplifier 12, and in LP mode, the bias circuit 32 may supply a bias current Ib22 having a current value greater than the bias current Ib21 to the power amplifier 12.

As a result, by reducing the bias current value of the power amplifier 12 in HP mode, it is possible to operate it as a peak amplifier, improving power efficiency. On the other hand, by increasing the bias current value of the power amplifier 12 in LP mode, it is possible to shut down the power amplifier 11, improving power efficiency at low output powers.

Furthermore, for example, in the Doherty amplifier circuit 10 according to this embodiment, the D-ET mode, SPT mode, or APT mode may be applied in the HP mode, and the APT mode may be applied in the LP mode.

As a result, D-ET mode, SPT mode, or APT mode can be applied in HP mode, which requires high output power, and by prioritizing improving the power-added efficiency of the Doherty amplifier circuit 10, the power efficiency of the communication device 6 can be improved. On the other hand, APT mode can be applied in LP mode, which does not require high output power, and by prioritizing reducing power consumption in the tracker circuit 5, the power efficiency of the communication device 6 can be improved.

Furthermore, for example, in the Doherty amplifier circuit 10 according to this embodiment, when the modulation bandwidth of the high-frequency signal is less than the threshold width in HP mode, the D-ET mode or SPT mode may be applied, and when the modulation bandwidth of the high-frequency signal is equal to or greater than the threshold width in HP mode, the APT mode may be applied.

As a result, when the modulation bandwidth is wide, causing drastic envelope changes and making tracking more difficult using D-ET mode or SPT mode, power efficiency can be improved by applying APT mode. On the other hand, when the modulation bandwidth is narrow and tracking is easier, power efficiency can be improved by applying D-ET mode or SPT mode.

Furthermore, for example, the Doherty amplifier circuit 10 according to this embodiment may further include a power amplifier 13 and a distributor 21 including an input terminal 211 connected to the output terminal of the power amplifier 13, an output terminal 212 connected to the input terminal of the power amplifier 11, and an output terminal 213 connected to the input terminal of the power amplifier 12.

This allows the high-frequency signal amplified by power amplifier 13 to be supplied to both power amplifiers 11 and 12, reducing the number of power amplifiers compared to connecting power amplifiers 11 and 12 individually.

(Variation 1)
A first modification of the embodiment will be described. This modification differs from the above embodiment mainly in that a quadrature hybrid coupler is used as a combiner. This modification will be described below with reference to FIG. 12, focusing on the differences from the above embodiment.

FIG. 12 is a circuit diagram of a Doherty amplifier circuit 10A according to this modified example. Note that FIG. 12 is an exemplary circuit diagram, and the Doherty amplifier circuit 10A can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the Doherty amplifier circuit 10A provided below should not be interpreted as limiting.

The Doherty amplifier circuit 10A includes power amplifiers 11, 12, and 13, a divider 21, a combiner 22A, bias circuits 31 and 32, a switch 33, a capacitor 34, a high-frequency input terminal 101, a high-frequency output terminal 102, and a power supply voltage terminal 103.

The combiner 22A is a quadrature hybrid coupler that combines two high-frequency signals amplified by the power amplifiers 11 and 12 and having a phase difference of 90 degrees, and supplies the combined signal to the high-frequency output terminal 102. Specifically, the combiner 22A includes input terminals 221 and 222, and an output terminal 223. The input terminal 221 is an example of a first input terminal and is connected to the output terminal of the power amplifier 11. The input terminal 222 is an example of a second input terminal and is connected to the output terminal of the power amplifier 12. The output terminal 223 is an example of a first output terminal and is connected to the high-frequency output terminal 102.

The quadrature hybrid coupler of combiner 22A may be, for example, a parallel plate coupler, a lumped constant coupler, a quarter-wave line coupler, or a branch-line coupler, but is not limited to these.

As described above, in the Doherty amplifier circuit 10A according to this embodiment, the combiner 22A may be a quadrature hybrid coupler.

This makes it possible to omit the quarter-wavelength line in the combiner 22A, thereby enabling the Doherty amplifier circuit 10A to be made smaller.

(Variation 2)
A second modification of the embodiment will now be described. This modification differs from the above embodiment mainly in that two drive stages are connected to two power stages individually. This modification will be described below with reference to FIG. 13, focusing on the differences from the above embodiment.

FIG. 13 is a circuit diagram of a Doherty amplifier circuit 10B according to this modified example. Note that FIG. 13 is an exemplary circuit diagram, and the Doherty amplifier circuit 10B can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the Doherty amplifier circuit 10B provided below should not be interpreted as limiting.

The Doherty amplifier circuit 10B includes power amplifiers 11, 12, 13a, and 13b, a divider 21, a combiner 22, bias circuits 31 and 32, a switch 33, a capacitor 34, a high-frequency input terminal 101, a high-frequency output terminal 102, and a power supply voltage terminal 103.

Power amplifier 13a is an example of a third power amplifier. The input terminal of power amplifier 13a is connected to output terminal 212 of distributor 21, and the output terminal of power amplifier 13a is connected to the input terminal of power amplifier 11. Power amplifiers 13a and 11 respectively constitute the drive stage and power stage of a multi-stage amplifier circuit. Power amplifier 13a may be shut down in the same way as power amplifier 11 in LP mode and APT mode.

Power amplifier 13b is an example of a fourth power amplifier. The input terminal of power amplifier 13b is connected to output terminal 213 of distributor 21, and the output terminal of power amplifier 13b is connected to the input terminal of power amplifier 12. Power amplifiers 13b and 12 respectively constitute the drive stage and power stage of a multi-stage amplifier circuit.

As described above, the Doherty amplifier circuit 10B according to this embodiment may further include a power amplifier 13a connected to the input terminal of power amplifier 11 and a power amplifier 13b connected to the input terminal of power amplifier 12.

In this way, power amplifiers 13a and 13b are connected to power amplifiers 11 and 12 individually, so that power amplifier 13a can also be shut down when power amplifier 11 is shut down, improving power efficiency at low output power.

(Other embodiments)
Although the Doherty amplifier circuit according to the present invention has been described above based on the embodiments, the Doherty amplifier circuit according to the present invention is not limited to the above embodiments. The present invention also includes other embodiments realized by combining any of the components in the above embodiments, modifications obtained by applying various modifications to the above embodiments that would occur to those skilled in the art without departing from the spirit of the present invention, and various devices incorporating the above Doherty amplifier circuit.

For example, in the circuit configuration of the Doherty amplifier circuit according to each of the above embodiments, other circuit elements and wiring may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings. For example, in the Doherty amplifier circuit 10, a phase adjustment circuit may be connected between the distributor 21 and the power amplifier 11.

Below are the features of the Doherty amplifier circuits described based on the above embodiments.

<1>
A Doherty amplifier circuit to which a digital-envelope tracking (D-ET) mode or a symbol power tracking (SPT) mode is applied,
a first power amplifier used as a carrier amplifier;
a second power amplifier used as a peak amplifier;
a combiner including a first input terminal connected to an output terminal of the first power amplifier, a second input terminal connected to an output terminal of the second power amplifier, and a first output terminal;
The size of the second power amplifier is smaller than the size of the first power amplifier.
Doherty amplifier circuit.

<2>
In a high power (HP) mode in which a power control level is equal to or greater than a threshold level, the first power amplifier and the second power amplifier operate;
In a low power (LP) mode where the power control level is less than the threshold level, the second power amplifier operates and the first power amplifier shuts down.
The Doherty amplifier circuit according to <1>.

<3>
the combiner includes a quarter-wave line connected between the first input terminal and the first output terminal;
The Doherty amplifier circuit according to <2>.

＜4＞
the combiner is a quadrature hybrid coupler;
The Doherty amplifier circuit according to <2>.

<5>
the Doherty amplifier circuit further includes a switch and a capacitor connected in series between a path connecting the output end of the first power amplifier and the first input terminal and ground.
<3> or <4>, the Doherty amplifier circuit.

＜6＞
In the HP mode, the switch is open,
In the LP mode, the switch is closed.
<5> The Doherty amplifier circuit according to <5>.

＜７＞
In the HP mode, the second power amplifier operates in class C;
In the LP mode, the second power amplifier operates in class A or class AB.
<6> The Doherty amplifier circuit according to any one of <2> to <6>.

＜8＞
the Doherty amplifier circuit further comprises a bias circuit configured to provide a bias current to the second power amplifier;
In the HP mode, the bias circuit supplies a first bias current to the second power amplifier;
In the LP mode, the bias circuit supplies a second bias current, the second bias current having a current value greater than that of the first bias current, to the second power amplifier.
<7> The Doherty amplifier circuit according to any one of <2> to <7>.

＜９＞
In the HP mode, a D-ET mode, an SPT mode, or an Average Power Tracking (APT) mode is applied;
In the LP mode, the APT mode is applied.
<8> The Doherty amplifier circuit according to any one of <2> to <8>.

<10>
In the HP mode, when the modulation bandwidth of the high frequency signal is less than a threshold width, the D-ET mode or the SPT mode is applied;
In the HP mode, when the modulation bandwidth of the high frequency signal is equal to or greater than the threshold width, an APT mode is applied.
The Doherty amplifier circuit according to <9>.

<11>
The Doherty amplifier circuit further comprises:
a third power amplifier;
a divider including a third input terminal connected to the output terminal of the third power amplifier, a second output terminal connected to the input terminal of the first power amplifier, and a third output terminal connected to the input terminal of the second power amplifier,
<10> The Doherty amplifier circuit according to any one of <1> to <10>.

<12>
The Doherty amplifier circuit further comprises:
a third power amplifier connected to an input terminal of the first power amplifier;
a fourth power amplifier connected to the input end of the second power amplifier,
<10> The Doherty amplifier circuit according to any one of <1> to <10>.

This invention can be widely used as a Doherty amplifier circuit placed in the front end of communication devices such as mobile phones.

1 High frequency circuit 2 Antenna 3 RFIC
4. BBIC
5 Tracker circuit 6 Communication device 10, 10A, 10B Doherty amplifier circuit 11, 12, 13, 13a, 13b Power amplifier 21 Distributor 22, 22A Combiner 31, 32 Bias circuit 33 Switch 34 Capacitor 41, 42, 43, 44 Filter 51, 52 Switch circuit 100 Antenna connection terminal 101 High frequency input terminal 102 High frequency output terminal 103 Power supply voltage terminal 211, 221, 222 Input terminal 212, 213, 223 Output terminal 224 1/4 wavelength line 510, 520 Common terminal 511, 512, 513, 514, 521, 522, 523, 524 Selection terminal

Claims (12)

A Doherty amplifier circuit to which a digital-envelope tracking (D-ET) mode or a symbol power tracking (SPT) mode is applied,
a first power amplifier used as a carrier amplifier;
a second power amplifier used as a peak amplifier;
a combiner including a first input terminal connected to an output terminal of the first power amplifier, a second input terminal connected to an output terminal of the second power amplifier, and a first output terminal;
The size of the second power amplifier is smaller than the size of the first power amplifier.
Doherty amplifier circuit. In a high power (HP) mode in which a power control level is equal to or greater than a threshold level, the first power amplifier and the second power amplifier operate;
In a low power (LP) mode where the power control level is less than the threshold level, the second power amplifier operates and the first power amplifier shuts down.
2. The Doherty amplifier circuit of claim 1. the combiner includes a quarter-wave line connected between the first input terminal and the first output terminal;
3. The Doherty amplifier circuit of claim 2. the combiner is a quadrature hybrid coupler;
3. The Doherty amplifier circuit of claim 2. the Doherty amplifier circuit further includes a switch and a capacitor connected in series between a path connecting the output end of the first power amplifier and the first input terminal and ground.
5. The Doherty amplifier circuit according to claim 3 or 4. In the HP mode, the switch is open,
In the LP mode, the switch is closed.
6. The Doherty amplifier circuit of claim 5. In the HP mode, the second power amplifier operates in class C;
In the LP mode, the second power amplifier operates in class A or class AB.
The Doherty amplifier circuit according to any one of claims 2 to 6. the Doherty amplifier circuit further comprises a bias circuit configured to provide a bias current to the second power amplifier;
In the HP mode, the bias circuit supplies a first bias current to the second power amplifier;
In the LP mode, the bias circuit supplies a second bias current, the second bias current having a current value greater than that of the first bias current, to the second power amplifier.
The Doherty amplifier circuit according to any one of claims 2 to 7. In the HP mode, a D-ET mode, an SPT mode, or an Average Power Tracking (APT) mode is applied;
In the LP mode, the APT mode is applied.
The Doherty amplifier circuit according to any one of claims 2 to 8. In the HP mode, when the modulation bandwidth of the high frequency signal is less than a threshold width, the D-ET mode or the SPT mode is applied;
In the HP mode, when the modulation bandwidth of the high frequency signal is equal to or greater than the threshold width, an APT mode is applied.
10. The Doherty amplifier circuit of claim 9. The Doherty amplifier circuit further comprises:
a third power amplifier;
a divider including a third input terminal connected to the output terminal of the third power amplifier, a second output terminal connected to the input terminal of the first power amplifier, and a third output terminal connected to the input terminal of the second power amplifier,
The Doherty amplifier circuit according to any one of claims 1 to 10. The Doherty amplifier circuit further comprises:
a third power amplifier connected to an input terminal of the first power amplifier;
a fourth power amplifier connected to the input end of the second power amplifier,
The Doherty amplifier circuit according to any one of claims 1 to 10.