WO2025210468A1 - Semiconductor device and production method for same - Google Patents

Abstract

The present invention provides a semiconductor device that uses a high-quality semiconductor film. The present invention provides a high-performance semiconductor device. The semiconductor device comprises first and second transistors, first and second insulation layers, and first and second single crystal substrates. In the first transistor, a channel is formed in a first single crystal semiconductor of the first single crystal substrate. The second transistor is positioned above the first transistor. In the second transistor, a channel is formed in a second single crystal semiconductor that contacts the first single crystal substrate. The second single crystal substrate is positioned above the second transistor. The first insulation layer is positioned between the first transistor and the second transistor. The second insulation layer is positioned between the first insulation layer and the second transistor and has a first joining surface that contacts the first insulation layer. The first single crystal semiconductor contains silicon, and the second single crystal semiconductor contains a metal oxide.

Description

Semiconductor device and manufacturing method thereof

One aspect of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. Examples of technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input/output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

In recent years, semiconductor devices have been developed, and are now primarily used in LSIs, CPUs, and memory. A CPU is a collection of semiconductor elements processed from a semiconductor wafer and containing chipped semiconductor integrated circuits (at least transistors and memory), with electrodes serving as connection terminals.

Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.

In addition, technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

Transistors using oxide semiconductors are known to have extremely low leakage current when they are off. For example, Patent Document 1 discloses a low-power CPU that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Furthermore, Patent Document 2 discloses a memory device that uses an oxide semiconductor and can retain stored data for a long period of time.

Furthermore, Non-Patent Document 1 reports a polycrystalline indium oxide film that exhibits high hole mobility and a transistor using it.

JP 2012-257187 A JP 2011-151383 A

Y. Magari et al. ,”High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3 ▼:H) thin-film transistors”, Nature Communications 13, 1078, (2022).

An object of one embodiment of the present invention is to provide a semiconductor device using a high-quality semiconductor film. Another object is to provide a semiconductor device using a single-crystal oxide semiconductor film. Another object is to provide a high-performance semiconductor device. Another object is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device that can be easily highly integrated. Another object is to provide a semiconductor device with low power consumption.

An object of one aspect of the present invention is to provide a semiconductor device having a novel structure. An object of one aspect of the present invention is to alleviate at least one of the problems of the prior art.

Note that the description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment of the present invention to solve all of these problems. It is possible to extract problems other than these from the description in the specification, drawings, claims, etc.

One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, a second insulating layer, a first single crystal substrate, and a second single crystal substrate. The first transistor has a channel formed in a first single crystal semiconductor included in the first single crystal substrate. The second transistor is located above the first transistor and has a channel formed in a second single crystal semiconductor in contact with the second single crystal substrate. The second single crystal substrate is located above the second transistor. The first insulating layer is located between the first transistor and the second transistor. The second insulating layer is located between the first insulating layer and the second transistor and has a first junction surface in contact with the first insulating layer. The first single crystal semiconductor contains silicon. The second single crystal semiconductor contains metal oxide.

Furthermore, in the above, it is preferable that the second single crystal substrate has a cubic crystal structure, and the second single crystal semiconductor has a cubic crystal structure.

Furthermore, in the above, it is preferable that the second single crystal substrate has an oxide containing yttrium and zirconium, and the second single crystal semiconductor has indium oxide.

Furthermore, in the above, it is preferable that the lattice mismatch of the second single crystal semiconductor with respect to the second single crystal substrate is between -5% and 5%.

Furthermore, in the above, it is preferable that the semiconductor device further comprises a first conductive layer and a second conductive layer. In this case, it is preferable that the first conductive layer is connected to one of the source electrode and drain electrode of the first transistor and is embedded in the first insulating layer. Furthermore, it is preferable that the second conductive layer is connected to one of the source electrode and drain electrode of the second transistor, is embedded in the second insulating layer, and has a second junction surface in contact with the first conductive layer.

Another aspect of the present invention is a method for manufacturing a semiconductor device, which includes a first transistor and a first insulating layer over the first transistor, and includes the steps of: preparing a first single crystal substrate including a first single crystal semiconductor; preparing a second single crystal substrate; forming a semiconductor film including the second single crystal semiconductor over the second single crystal substrate; processing the semiconductor film into an island shape to form a semiconductor layer; forming a gate insulating layer, a gate electrode, a source electrode, and a drain electrode over the semiconductor layer to manufacture a second transistor; forming a second insulating layer over the second transistor; and bonding an upper surface of the first insulating layer to an upper surface of the second insulating layer.

Furthermore, in the above, it is preferable that the first single crystal semiconductor contains silicon and the second single crystal semiconductor contains metal oxide.

Furthermore, in the above, it is preferable that the second single crystal substrate has a cubic crystal structure, and the second single crystal semiconductor has a cubic crystal structure.

Furthermore, in the above, it is preferable that the second single crystal substrate has an oxide containing yttrium and zirconium, and the second single crystal semiconductor has indium oxide.

Furthermore, in the above, it is preferable that the lattice mismatch of the second single crystal semiconductor with respect to the second single crystal substrate is between -5% and 5%.

According to one embodiment of the present invention, a semiconductor device using a high-quality semiconductor film can be provided. Alternatively, a semiconductor device using a single-crystal oxide semiconductor film can be provided. Alternatively, a high-performance semiconductor device can be provided. Alternatively, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device that can be easily highly integrated can be provided. Alternatively, a low-power semiconductor device can be provided.

According to one aspect of the present invention, a semiconductor device having a novel configuration can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be at least alleviated.

Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have to have all of these effects. Note that other effects can be extracted from the description in the specification, drawings, claims, etc.

1A to 1I are diagrams illustrating a method for manufacturing a semiconductor device.
2A to 2D are diagrams illustrating a method for manufacturing a semiconductor device.
3A and 3B are schematic diagrams illustrating the vicinity of the bonding surface.
4A and 4B are schematic diagrams illustrating the vicinity of the bonding surface.
5A to 5E are diagrams illustrating a method for manufacturing a semiconductor device.
6A to 6D show examples of the configuration of a semiconductor device.
FIG. 7 shows an example of the configuration of a semiconductor device.
FIG. 8 shows an example of the configuration of a semiconductor device.
9A to 9D show examples of the configuration of a semiconductor device.
10A to 10D show examples of the configuration of a semiconductor device.
11A1 to 11D2 are diagrams illustrating a method for manufacturing a semiconductor device.
12A1 to 12C2 are diagrams illustrating a method for manufacturing a semiconductor device.
FIG. 13 shows an example of the configuration of a storage device.
14A and 14B show examples of the configuration of a storage device.
15A to 15D show examples of the configuration of a storage device.
FIG. 16 shows an example of the configuration of a storage device.
17A and 17B show examples of the configuration of a display device.
FIG. 18 shows an example of the configuration of a display device.
19A to 19C show examples of the configuration of a display device.
20A and 20B show examples of the configuration of a display device.
21A to 21D show configuration examples of electronic devices.
22A to 22F show configuration examples of electronic devices.
23A to 23G show configuration examples of electronic devices.
24A and 24B show examples of the configuration of electronic components.
25A to 25C show examples of the configuration of a mainframe computer.
26A and 26B are cross-sectional images according to an embodiment.
27A and 27B are cross-sectional images according to an embodiment.

The following describes embodiments with reference to the drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

In the configuration of the invention described below, the same parts or parts with similar functions will be denoted by the same reference numerals in different drawings, and repeated explanations will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

Note that in the figures described in this specification, the size of each component, layer thickness, or area may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale.

In addition, ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components and do not imply any numerical limitation.

A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage, and switching to control conduction or non-conduction. In this specification, the term "transistor" includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).

Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows for the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

In this specification, when two nodes are connected via an insulator, such as the dielectric of a capacitive element, the gate insulating film of a transistor, or an interlayer insulating film, this is not considered to be an "electrical connection."

In this specification, "top surface shapes that roughly match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where only a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer; in these cases, the term "top surface shapes that roughly match" may also be used.

In this specification, the top surface shape of a certain component refers to the contour shape of that component when viewed from a plan view. Furthermore, a plan view refers to a view from the normal direction of the surface on which the component is formed, or the surface of the support (e.g., substrate) on which the component is formed.

In the following, expressions indicating directions such as "up" and "down" will generally be used in accordance with the directions in the drawings. However, for purposes such as ease of explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (formed surface, support surface, adhesive surface, flat surface, etc.) is located above the laminate in the drawings, the formed surface side may be expressed as "down" and the laminate side as "up."

Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

Furthermore, in this specification, unless otherwise specified, off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or cut-off state). Unless otherwise specified, the off state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).

(Embodiment 1)
In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described.

One embodiment of the present invention has a structure in which a first transistor whose channel is formed in part of a first single crystal substrate is stacked above the first transistor whose channel is formed in a single crystal semiconductor film. It is preferable to use a metal oxide for the semiconductor film of the second transistor.

The semiconductor film having a single crystal structure used in the second transistor is preferably obtained by forming it by an epitaxial method using a second single crystal substrate, separate from the first single crystal substrate, as the base material. If the crystal structure of the second single crystal substrate and the crystal structure of the semiconductor film are the same crystal system, the lattice mismatch between them is small, making it possible to obtain a semiconductor film with good crystallinity. Note that even if the crystal structures of the two are different, this does not apply if epitaxial growth is used.

As the metal oxide used for the semiconductor film, it is preferable to use an oxide containing indium, zinc, tin, etc. In particular, it is preferable to use a metal oxide that crystallizes easily. For example, indium oxide is preferable because it easily crystallizes at low temperatures and can produce a single-crystal film with good crystallinity. Single-crystal or polycrystalline indium oxide is also preferable because it exhibits extremely high reliability. In particular, a single-crystal indium oxide film is preferable. For example, in a polycrystalline film, impurities such as hydrogen may be unevenly distributed at the grain boundaries. This hydrogen generates carriers in the semiconductor film, increasing the carrier concentration in the semiconductor film, which may cause fluctuations in the threshold voltage of the transistor. Therefore, using a single-crystal indium oxide film for the semiconductor film makes it possible to achieve a transistor with extremely good electrical characteristics.

For example, when a cubic oxide film such as indium oxide is used as the semiconductor film, it is preferable to use a single crystal substrate of the same cubic crystal system as the second single crystal substrate. For example, it is preferable to use a cubic single crystal substrate such as a YSZ (yttria-stabilized zirconia) substrate, a zirconium oxide substrate, or a silicon substrate. Alternatively, a semiconductor film having a cubic single crystal structure can be formed using a tetragonal single crystal substrate. The material and crystal structure of the second single crystal substrate can be selected appropriately depending on the crystal structure of the desired semiconductor film. For example, single crystal substrates such as silicon carbide, gallium nitride, and gallium oxide can also be used. Even when the crystal structures of the second single crystal substrate and the desired semiconductor film differ, epitaxial growth may be possible by providing a buffer layer to relieve strain between them.

Furthermore, the smaller the lattice mismatch between the second single crystal substrate and the semiconductor film, the more preferable. Here, the lattice mismatch corresponds to the difference between the length of the unit lattice vector of the substrate and the length of the unit lattice vector of the thin film, divided by the length of the unit lattice vector of the substrate, when a thin film is epitaxially grown on the substrate. The lattice constant can also be used instead of the unit lattice vector. For example, when the substrate and the thin film have the same crystal structure, the lattice mismatch can be the difference between the two lattice constants divided by the lattice constant of the substrate. The smaller the lattice mismatch between the second single crystal substrate and the semiconductor film, the more preferable it is, for example, between -5% and 5%, preferably between -4% and 4%, more preferably between -3% and 3%, and even more preferably between -2% and 2%. Here, the lattice mismatch is positive when the unit lattice vector of the thin film is larger than that of the substrate, and negative when it is smaller. When the buffer layer is provided, increasing the thickness of the buffer layer may enable epitaxial growth even with a combination with a large lattice mismatch. In this case, the lattice mismatch can be less than -5% or greater than 5%. For example, the lattice mismatch between the second single crystal substrate and the semiconductor film may be -20% to 20%, -15% to 15%, or -10% to 10%.

A semiconductor substrate can be used for the first single crystal substrate. Typically, a single crystal silicon substrate is preferably used. Alternatively, a semiconductor substrate made of a single element, a compound semiconductor substrate, or an insulating substrate on which a single crystal semiconductor thin film is formed can be used. A first transistor having a channel formed in a part of the first single crystal substrate can be provided on the first single crystal substrate. Furthermore, a first insulating layer having a bonding surface with the second single crystal substrate is provided on the first transistor.

After forming a single-crystal semiconductor film on a second single-crystal substrate, the semiconductor film is processed into an island shape. By forming a gate insulating layer, a gate electrode, and source and drain electrodes on the island-shaped semiconductor film (hereinafter also referred to as a semiconductor layer), a transistor in which a channel is formed in the single-crystal semiconductor can be manufactured on the second single-crystal substrate. Then, a second insulating layer having a bonding surface with the first single-crystal substrate is formed on the transistor.

Next, the first single crystal substrate and the second single crystal substrate are bonded together, so that the surfaces of the first insulating layer and the second insulating layer are in contact. Using the same material for the first insulating layer and the second insulating layer is preferable, as this increases the bonding strength. Furthermore, the flatter the surfaces of the first insulating layer and the second insulating layer, the better, so it is preferable to perform a planarization process beforehand. After bonding, the surface of the first insulating layer facing the second insulating layer and the surface of the second insulating layer facing the first insulating layer form the bonding surfaces, respectively.

The above process allows for the manufacture of a semiconductor device in which a first transistor, whose channel is formed in a portion of a first single-crystal substrate, and a second transistor, whose channel is formed in a single-crystal semiconductor film, are stacked. In this case, the stacked structure including the first transistor and the stacked structure including the second transistor are upside down across the junction plane.

After bonding the first single crystal substrate and the second single crystal substrate, the second single crystal substrate may be removed, or the second single crystal substrate may be ground (also called back-grinding) to reduce its thickness. Furthermore, functional elements such as light-emitting elements, light-receiving elements, sensor elements, and transistors may be fabricated on the back surface of the second single crystal substrate (the surface opposite the second transistor). In this case, the functional elements may be connected to the second transistor via plugs provided in the second single crystal substrate. This makes it possible to fabricate a highly functional semiconductor device. For example, when a display element is used as the functional element, it is possible to stack the circuit and the display element, thereby realizing a display device with a small chip area, extremely high resolution, and high display quality.

More specific examples will be explained below with reference to the drawings.

[Example 1 of manufacturing method of semiconductor device]
1A to 2D are schematic cross-sectional views illustrating steps of a manufacturing method of a semiconductor device according to one embodiment of the present invention.

First, the substrate 11 is prepared (Figure 1A). A single crystal substrate can be used for the substrate 11. For example, a single crystal substrate such as YSZ, zirconium oxide, silicon, silicon carbide, gallium nitride, or gallium oxide can be used. Rare earth oxides and lanthanide oxides such as yttrium oxide, erbium oxide, gadolinium oxide, and ytterbium oxide can also be used. In particular, when indium oxide is used for the semiconductor film 21f, it is preferable to use yttrium oxide or erbium oxide. A material with a small lattice mismatch with the semiconductor film 21f to be formed later can be used for the substrate 11. Furthermore, if the substrate 11 is to be removed later, it is not limited to an insulating substrate; conductive substrates and semiconductor substrates can also be used.

Next, a semiconductor film 21f is formed on the substrate 11 (Figure 1B). A metal oxide can be used for the semiconductor film 21f. In particular, it is preferable to use an oxide film whose main component is indium, tin, or zinc. Among these, single-crystal indium oxide is particularly preferable because it combines high mobility with high reliability.

Semiconductor film 21f can be formed by methods such as atomic layer deposition (ALD), sputtering, chemical vapor deposition (CVD), pulsed laser deposition (PLD), molecular beam epitaxy (MBE), and wet processes.

The semiconductor film 21f is preferably formed while the substrate 11 is heated. This allows for a single-crystal film with fewer defects. Furthermore, the higher the heating temperature of the substrate 11, the cleaner the surface of the substrate 11 can be and the fewer lattice defects there are, which is preferable. On the other hand, if the temperature of the substrate 11 during film formation is too high, oxygen in the film may be desorbed, potentially preventing the formation of a film with the desired composition. Therefore, the temperature of the substrate 11 during film formation can be set to between room temperature and 1200°C, preferably between 100°C and 600°C. It is also possible to first heat the substrate 11 to a high temperature (1000°C or higher) in a film formation apparatus, and then lower the surface temperature of the substrate 11 to 600°C or lower without exposing it to the atmosphere, and then form the semiconductor film 21f.

Indium oxide is particularly preferable for use as the semiconductor film 21f. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor. Furthermore, by using indium oxide with a single crystal structure in the channel formation region of a transistor, a highly reliable transistor can be realized. Furthermore, the band gap of indium oxide is 2.5 eV or more and 3.7 eV or less. By using indium oxide with a wide band gap in the channel formation region of a transistor, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be significantly reduced.

When a film having a cubic crystal structure, such as indium oxide, is used for the semiconductor film 21f, it is preferable to use a substrate having a cubic crystal structure for the substrate 11. This allows the semiconductor film 21f to grow epitaxially, improving the crystallinity of the semiconductor film 21f. For example, zirconium oxide or yttria-stabilized zirconia (YSZ), which are cubic crystal structures, can be used for the substrate 11. Note that when the semiconductor film 21f and the substrate 11 have the same crystal structure, the crystal orientation of the surface of the substrate 11 is not particularly limited. For example, the crystal orientation of the surface of the substrate 11 may be [100], [110], or [111]. Note that when a YSZ substrate is used for the substrate 11 and an indium oxide film is used for the semiconductor film 21f, it is particularly preferable to use a YSZ substrate with a surface crystal orientation of [100] or [111] for the substrate 11, from the perspective of lattice mismatch, as described below. Substrate 11 may also be a substrate whose surface is tilted from a specific crystal plane, i.e., a substrate with an off-angle of 0° or more.

Furthermore, it is preferable that the lattice mismatch between the semiconductor film 21f and the substrate 11 is small. By selecting a material for the substrate 11 that minimizes the lattice mismatch, the crystallinity of the semiconductor film 21f can be improved.

One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa [%] of the crystals of the formed film (e.g., semiconductor film 21f) with respect to the crystals of the film to be formed (e.g., substrate 11) is calculated by Δa = (( _L1 - _L2 ) / L2) × ₁₀₀ , where _L1 is the length or lattice constant of the unit lattice vector of the crystals of the formed film, and _L2 is the length or lattice constant of the unit lattice vector of the crystals of the film to be formed.

The smaller the absolute value of the lattice mismatch Δa between the substrate 11 and the semiconductor film 21f, the better, with 0 being most preferable. For example, Δa is preferably between -5% and 5%, preferably between -4% and 4%, more preferably between -3% and 3%, and even more preferably between -2% and 2%. The smaller the lattice mismatch Δa, the less strain can be in the semiconductor film 21f and the greater the critical film thickness for misfit dislocations, allowing for a film with high crystallinity even when the semiconductor film 21f is thick.

For example, indium oxide with a cubic crystal structure (bixbyite type) has a lattice constant of 1.0117 nm (see ICSD ₍ Inorganic Crystal Structure Database) col.code.14387). On the other hand, YSZ ( _{Zr0.9Y0.1O1.95} ) with a cubic crystal structure (fluorite type) has a lattice constant of 0.51481 nm (see ICSD col.code.248790). Therefore, the lattice mismatch of the crystal grains of _the indium oxide film with respect to the crystal grains of YSZ is -1.74%. Here, since the lattice constant of YSZ changes depending on the yttrium content, the yttrium content of YSZ is set to 2 atomic % or more and 15 atomic % or less, preferably 5 atomic % or more and 10 atomic % or less, thereby making it possible to reduce the lattice mismatch between YSZ and indium oxide and form a single-crystal indium oxide film with few defects.

The crystal orientation of the substrate 11 and the crystal orientation of the semiconductor film 21f may not necessarily be the same. For example, a film having hexagonal or trigonal crystals may be used under indium oxide having cubic crystals. For example, the crystal orientation of the surface of the substrate 11 may be [001], and the crystal orientation of the underside of the semiconductor film 21f may be [111] _, thereby satisfying the requirements for the crystal orientation necessary for epitaxial growth. Examples of hexagonal or _trigonal crystals include a wurtzite structure, a _YbFe2O4 structure, a _Yb2Fe3O7 structure, and _modified structures thereof.

The semiconductor film 21f is not limited to indium oxide, and a metal oxide film containing indium, tin, or zinc as its main component can also be used. Here, "main component" refers to a metal oxide in which the ratio of the target atoms to the total number of atoms of the metal elements that make up the metal oxide is 0.1% or more. Elements with a ratio of less than 0.1% are sometimes called impurities.

Figures 3A and 3B show schematic cross sections near the interface between substrate 11 and semiconductor film 21f. Figure 3A corresponds to the case where the lattice constant of the crystal of semiconductor film 21f is smaller than the lattice constant of the crystal of substrate 11, i.e., Δa<0, and Figure 3B corresponds to the case where Δa>0.

Element 15s is periodically arranged in substrate 11, and element 15f is periodically arranged in semiconductor film 21f formed on substrate 11. Because the lattice constants differ between substrate 11 and semiconductor film 21f, the lattice is distorted in the vicinity of substrate 11 in semiconductor film 21f, maintaining the continuity of the lattice at the interface. The thicker the region where the lattice of semiconductor film 21f is distorted, the easier it is to relax the distortion, making it less likely for dislocations to occur. The thickness of this region can range from a single atomic layer if thin to several μm if thick.

At this time, the lattice of semiconductor film 21f may distort so as to expand or contract in the in-plane direction, but may show almost no distortion in the film thickness direction. For example, in the general relationship between stress and strain, when an external force is applied to an object and it expands in a certain direction, it generally contracts in the direction perpendicular to that (and the opposite is true when it contracts due to an external force), but semiconductor film 21f may show a different tendency.

Figures 4A and 4B show an example in which an intermediate layer 16 exists between the substrate 11 and the semiconductor film 21f. The intermediate layer 16 functions as a buffer layer to relieve stress associated with lattice mismatch between the substrate 11 and the semiconductor film 21f. The presence of the intermediate layer 16 relieves strain in the semiconductor film 21f, making the semiconductor film 21f a film with few defects such as dislocations and good crystallinity. The intermediate layer 16 may be a low-density region due to the presence of sites where no atoms exist. Furthermore, the element 15m located in the intermediate layer 16 may be not only an element that constitutes the semiconductor film 21f, but also a mixture of elements that constitute the substrate 11. In this case, the intermediate layer 16 may also be called a mixed layer.

The intermediate layer 16 can be confirmed, for example, in an image of a cross section near the interface between the substrate 11 and the semiconductor film 21f observed using high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM). The intermediate layer 16 can be observed as a layer with lower contrast than other regions. The thickness of the intermediate layer 16 varies depending on the crystal orientation of the substrate 11, and may be one atomic layer, two atomic layers, or more.

Next, a conductive film 24f is formed on the semiconductor film 21f (Figure 1C). Conductive materials that do not easily diffuse oxygen, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide, can be used for the conductive film 24f. This prevents oxidation by oxygen contained in the semiconductor film 21f, etc., and a decrease in conductivity. The conductive film 24f can be formed by a method such as sputtering, ALD, or CVD.

Next, a resist mask is formed on the conductive film 24f, and unnecessary portions of the conductive film 24f and the semiconductor film 21f are removed by etching, forming island-shaped conductive layer 24 and semiconductor layer 21 (Figure 1D). The resist mask is then removed. Etching can be performed by dry etching or wet etching, but dry etching is preferred as it facilitates fine processing.

Next, insulating layer 32, which functions as a barrier film, and insulating layer 33a, which functions as an interlayer insulating film, are formed in this order to cover conductive layer 24 and semiconductor layer 21 (Figure 1E). Insulating layer 32 and insulating layer 33a can be formed by sputtering, ALD, CVD, or the like.

For the insulating layer 32, it is preferable to use an insulating material such as silicon nitride, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). These materials have barrier properties against oxygen, hydrogen, and water, and can prevent these impurities from diffusing into the semiconductor layer 21.

It is preferable to use an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride oxide for the insulating layer 33a. By using a material with a low dielectric constant for the insulating layer 33a, parasitic capacitance can be reduced.

In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen atoms than nitrogen atoms. A nitride oxide refers to a material whose composition contains more nitrogen atoms than oxygen atoms. For example, silicon oxynitride refers to a material whose composition contains more oxygen atoms than nitrogen atoms, and silicon nitride oxide refers to a material whose composition contains more nitrogen atoms than oxygen atoms.

Next, insulating layer 33a, insulating layer 32, and a portion of conductive layer 24 are removed by etching to form a groove that reaches semiconductor layer 21 and substrate 11 (Figure 1F). At this time, conductive layer 24 is divided into two at the groove. After that, insulating film 22f is formed along the groove (Figure 1G). Next, a conductive film that becomes conductive layer 23 is formed on insulating film 22f so as to fill the groove. Next, planarization is performed by CMP until insulating layer 33a is exposed, thereby forming insulating layer 22 and conductive layer 23 in the groove (Figure 1H). Insulating layer 22 functions as a gate insulating layer, and conductive layer 23 functions as a gate electrode. Furthermore, the pair of conductive layers 24 divided on semiconductor layer 21 function as a source electrode and a drain electrode, respectively. In this manner, transistor 10 can be fabricated.

Insulating layer 22 can be made of insulating materials such as silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and hafnium aluminate, either in a single layer or in a laminated structure. The insulating layer 22 can be formed using film-forming methods such as sputtering, CVD, and ALD. However, ALD, which has excellent step coverage, is preferable from the standpoint of voltage resistance, as it allows the layer to be formed to a uniform thickness even inside the trench.

Conductive layer 23 is preferably made of a low-resistance conductive material such as tungsten, molybdenum, copper, or aluminum. It is also preferable to form conductive layer 23 in a layered structure, with a film of a conductive material that does not easily diffuse oxygen, which can be used for conductive layer 24, provided on the side in contact with insulating layer 22. This prevents conductive layer 23 from being oxidized by oxygen diffusing from insulating layer 22 or the like, resulting in a decrease in conductivity.

Then, insulating layer 33b is formed to cover transistor 10 and insulating layer 33a. Insulating layer 33b functions as an interlayer insulating film and can be formed using the same method as insulating layer 33a. Next, openings reaching conductive layer 24 are formed in insulating layers 33b, 33a, and 32. Next, a conductive film is formed to fill these openings, and then planarization is performed using CMP until insulating layer 33b is exposed, thereby forming plugs 61c that connect to conductive layer 24. The conductive film is preferably formed using CVD.

Next, a conductive film is formed and unnecessary portions are removed by etching to form conductive layer 71c (Figure 1I). Conductive layer 71c is connected to conductive layer 24 via plug 61c.

Next, insulating layer 33c is formed, covering insulating layer 33b and conductive layer 71c. After that, an opening reaching conductive layer 71c is formed in insulating layer 33c, and plug 61d is formed in the opening. Next, conductive layer 71d is formed on insulating layer 33c. After that, an insulating film is formed covering insulating layer 33c and conductive layer 71d, and a planarization process is performed until the top surface of conductive layer 71d is exposed, thereby forming insulating layer 33d (Figure 2A). As a result, conductive layer 71d is embedded in insulating layer 33d, and the top surfaces are planarized and at the same height.

This completes the process on the substrate 10 side.

Next, a substrate 51 on which a transistor 50 is mounted is prepared (Figure 2B).

Substrate 51 is a single-crystal semiconductor substrate, and has transistor 50 formed thereon. Transistor 50 has a semiconductor region 51c formed in part of substrate 51. Substrate 51 can typically be made of single-crystal silicon. Alternatively, semiconductors made of elemental elements such as germanium, or compound semiconductors made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, gallium nitride, etc. can be used. Furthermore, a semiconductor substrate having an insulator region within the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, can also be used. Alternatively, a substrate having a thin-film semiconductor film provided on an insulating substrate such as a glass substrate, quartz substrate, sapphire substrate, YSZ substrate, or resin substrate can also be used.

The transistor 50 is provided on a substrate 51 and has a conductive layer 53 that functions as a gate, an insulating layer 52 that functions as a gate insulating layer, a semiconductor region 51c that is part of the substrate 51, and a pair of low-resistance regions 54 that function as a source region and a drain region. The transistor 50 has a channel formed in the single-crystal semiconductor of the substrate 51. The transistor 50 may be either a p-channel type or an n-channel type. An element isolation layer 81 is provided on the substrate 51 between two adjacent transistors 50.

In the transistor 50, the semiconductor region 51c in which the channel is formed has a convex (fin-shaped) shape. Furthermore, although not shown in FIG. 2B, a conductive layer 53 is provided to cover the side and top surfaces of the semiconductor region 51c in the depth direction, with an insulating layer 52 interposed between them. Such a transistor 50 is also called a FIN-type transistor.

An insulating layer 82 is provided covering a portion of the transistor 50, and insulating layers 83a to 83d are provided in this order on top of the insulating layer 82. The conductive layer 71a is embedded in the insulating layer 83b and is connected to the low-resistance region 54 via a plug 61a that penetrates the insulating layer 83a and the insulating layer 82. The conductive layer 71b is embedded in the insulating layer 83d and is connected to the conductive layer 71a via a plug 61b that penetrates the insulating layer 83c.

Since the upper surface of the insulating layer 83d will be the bonding surface, it is preferably planarized by CMP. This allows the upper surfaces of the insulating layer 83d and the conductive layer 71b to be planarized and to be configured to be the same height.

Substrate 51 and substrate 11 are then bonded together (Figure 2C).

Bonding of substrate 51 and substrate 11 is performed by overlapping the two substrates so that insulating layer 33d and insulating layer 83d face each other. It is also important to adjust the positions so that conductive layer 71d and conductive layer 71b are in contact.

It is preferable that insulating layer 33d and insulating layer 83d are a combination that allows bonding. It is particularly preferable that they are made of the same material. In particular, using silicon oxide for each layer is preferable, as this allows for a strong bond. It is also preferable that conductive layer 71b and conductive layer 71d are made of the same material, as this reduces contact resistance. In particular, using copper for each layer allows for easy bonding and low contact resistance.

When bonding, pressing one point on substrate 51 or substrate 11 can spread van der Waals bonds, hydrogen bonds, etc. from that point across the entire bonding surface. If one or both of the bonding surfaces have a hydrophilic surface, hydroxyl groups, water molecules, etc. act as an adhesive, and subsequent heat treatment causes the water molecules to diffuse, with the remaining components forming silanol groups (Si-OH), which form a bond through hydrogen bonds. Furthermore, as hydrogen is released from this bond, siloxane bonds (O-Si-O) are formed, which becomes a covalent bond, resulting in an even stronger bond.

A semiconductor device can be manufactured using the above process.

The semiconductor device shown in Figure 2D has a stacked structure of a transistor 50 whose channel is formed in part of a single-crystal substrate and a transistor 10 whose channel is formed in a single-crystal oxide semiconductor.

[Example 2 of manufacturing method of semiconductor device]
An example of a method for manufacturing a semiconductor device using a method for forming a semiconductor film different from the above will be described below.

First, the substrate 11a is prepared (Figure 5A). A single-crystal semiconductor substrate is used as the substrate 11a. It is preferable to select a substrate 11a that has a small degree of lattice mismatch with the base film 12 to be formed later. Here, we will explain the case where a silicon substrate is used as the substrate 11a.

Next, a single-crystal base film 12 is formed on the substrate 11a. The base film 12 can be formed using the same film formation method as the semiconductor film 21f described above. A high-quality single-crystal film can be obtained by epitaxially growing the base film 12 on the substrate 11a. The base film 12 is preferably an insulating film. In other words, the base film 12 is preferably a film containing a single-crystal insulator.

The base film 12 can typically be made of oxides such as YSZ and zirconium oxide. It is also possible to use rare earth oxides and lanthanide oxides such as yttrium oxide, erbium oxide, gadolinium oxide, and ytterbium oxide. In particular, when indium oxide is used for the semiconductor film 21f, it is preferable to use yttrium oxide or erbium oxide.

For example, a silicon substrate can be used for the substrate 11a, and a YSZ film can be used for the base film 12. However, this is not a limitation, and the base film 12 can be any insulating film, conductive film, or semiconductor film. It is preferable to select a film that has a small lattice mismatch with both the substrate 11a and the semiconductor film 21f for the base film 12. For example, it is preferable to select the base film 12 so that the lattice mismatch Δa with both the substrate 11a and the semiconductor film 21f is in the range of -20% to 20%, preferably -10% to 10%, more preferably -7% to 7%, even more preferably -5% to 5%, and even more preferably -4% to 4%. A buffer layer for alleviating strain may be provided between the substrate 11a and the base film 12 and between the base film 12 and the semiconductor film 21f, or both.

When a silicon substrate is used as the substrate 11a, a natural oxide film forms on the surface of the substrate 11a. Therefore, a process of removing the natural oxide film may be added before depositing the base film 12. The natural oxide film can be removed by wet etching using an acid such as hydrofluoric acid. Alternatively, it can be removed by dry etching. When using dry etching, it is preferable to deposit the base film 12 immediately after etching without exposing the substrate 11a to the atmosphere. This prevents a natural oxide film from forming again on the substrate 11a.

Alternatively, the base film 12 may be formed without removing the native oxide film of the substrate 11a. Even if a native oxide film is provided, it may be possible to form the base film 12 having a crystalline structure that reflects the crystallinity of the substrate 11a. In this case, a layer 12a that functions as a buffer layer may be formed between the substrate 11a and the base film 12. By providing the layer 12a between the substrate 11a and the base film 12, the lattice distortion of the base film 12 associated with the lattice mismatch between the substrate 11a and the base film 12 can be alleviated, allowing the formation of an base film 12 having a high-quality single-crystal structure.

Next, a semiconductor film 21f having a single crystal structure is formed on the base film 12 (Figure 5B). Because the base film 12 has a single crystal structure, the semiconductor film 21f can be epitaxially grown in the same manner as above, resulting in a film with a high-quality single crystal structure.

Thereafter, semiconductor layer 21, conductive layer 24, insulating layer 32, insulating layer 33a, insulating layer 22, and conductive layer 23 are formed in the same manner as above to fabricate transistor 10. Furthermore, insulating layer 33d and conductive layer 71d are formed in the same manner as above (Figure 5C).

Substrate 51 and substrate 11a are then bonded together so that insulating layer 33d and insulating layer 83d are bonded together (Figure 5D).

A semiconductor device can be manufactured through the above process. Using the method described here broadens the range of materials that can be used for the substrate 11a, eliminating the need to use expensive materials and reducing costs. For example, a single-crystal silicon substrate can be used for the substrate 11a.

Substrate 11a may then be removed, as shown in Figure 5E. Substrate 11a can be removed, for example, by applying upward force to the edge of substrate 11a, so that the area with the poorest adhesion becomes the peeling surface, allowing substrate 11a to be peeled off. In this case, peeling preferably occurs between substrate 11a and base film 12. Furthermore, if layer 12a is present between substrate 11a and base film 12, peeling may occur inside layer 12a, at the interface between layer 12a and substrate 11a, or at the interface between layer 12a and base film 12.

Alternatively, the substrate 11a can be removed by chemical methods such as etching, or physical methods such as grinding, polishing, or sandblasting, or a combination of these. Alternatively, peeling can be caused at the interface between the substrate 11a and the semiconductor film 21f by injecting a liquid such as water or alcohol into the interface. In this case, the substrate 11a may be immersed in the liquid, or the liquid may be brought into contact with the sides of the substrate 11a and the base film 12. Furthermore, using a conductive liquid (such as an ionic liquid or water containing carbon dioxide) is preferable, as this can suppress the generation of static electricity during peeling.

If layer 12a remains on base film 12 after removing substrate 11a, it is preferable to remove it by etching, CMP, or the like. Also, a damaged layer may be formed on the surface of base film 12 or in its vicinity. In such cases, it is preferable to remove the upper part of base film 12 by etching, CMP, or the like. Alternatively, base film 12 may be completely removed to expose semiconductor layer 21 and insulating layer 32, and a new insulating layer may be provided in contact with the surface.

After removing the substrate 11a, functional elements such as light-emitting elements, light-receiving elements, sensor elements, and transistors can also be fabricated above the transistor 10 (above the base film 12 in Figure 5E).

In addition, although the substrate 11a was removed here, the substrate 11a may be thinned by back-grinding or other methods. In this case, it is preferable to thin the substrate 11a to a thickness that allows for the formation of vias for embedding plugs. For example, the thickness of the substrate 11a can be set to 1 μm or more and 100 μm or less, preferably 1 μm or more and 50 μm or less, and more preferably 1 μm or more and 20 μm or less.

The above is an explanation of an example production method.

This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.

(Embodiment 2)
In this embodiment, a structure example and a manufacturing method example of a transistor that can be used in a semiconductor device of one embodiment of the present invention will be described.

[Configuration example of semiconductor device]
6A to 6D are top views and cross-sectional views of the transistor 200. FIG. 6A is a top view of the transistor 200, and FIGS. 6B to 6D are schematic cross-sectional views corresponding to the cutting lines A1-A2, A3-A4, and A5-A6 in FIG. 6A, respectively. FIG. 6B corresponds to a cross section of the transistor 200 in the channel length direction, and FIGS. 6C and 6D correspond to cross sections in the channel width direction, respectively. FIG. 7 is an enlarged view of FIG. 6B. Note that some components shown in FIG. 7 are omitted in FIGS. 6A and the like.

Transistor 200 has a semiconductor layer 230 provided on an insulating layer 201 provided on a substrate (not shown), conductive layers 242a and 242b on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. An insulating layer 275 is provided covering the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b, and an insulating layer 280 is provided on the insulating layer 275. A groove is provided in the insulating layer 280 and the insulating layer 275, reaching the semiconductor layer 230, and the conductive layer 242a and the conductive layer 242b are separated by the groove. The insulating layer 250 is provided inside the groove along the surfaces of the insulating layer 280, the insulating layer 275, the conductive layer 242a, the conductive layer 242b, and the semiconductor layer 230. The conductive layer 260 is provided on the insulating layer 250 so as to fill the groove. In addition, insulating layer 282, insulating layer 283, and insulating layer 285 are provided in this order to cover insulating layer 280, insulating layer 250, and conductive layer 260.

The semiconductor layer 230 functions as a channel formation region of the transistor 200. The conductive layer 260 functions as a gate electrode of the transistor 200. The insulating layer 250 functions as a gate insulator of the transistor 200.

The conductive layer 242a functions as one of the source and drain electrodes of the transistor 200, and the conductive layer 242b functions as the other.

The conductive layers 242a and 242b preferably have a stacked structure. A conductor that is resistant to oxidation, such as a metal nitride, is preferably used on the side in contact with the semiconductor layer 230. This prevents the conductive layers 242a and 242b from being excessively oxidized by oxygen contained in the semiconductor layer 230. Furthermore, a metal or alloy that is more conductive than the layer in contact with the semiconductor layer 230 is preferably used on the side that is not in contact with the semiconductor layer 230. This allows the conductive layers 242a and 242b to function as wiring or electrodes with high conductivity.

In the conductive layers 242a and 242b, it is preferable to use a metal nitride on the side in contact with the semiconductor layer 230. For example, it is preferable to use a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. It is also possible to use, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain their conductivity even when they absorb oxygen.

The insulating layer 201 is a layer in contact with the semiconductor layer 230, and can be made of a material having a single crystal structure. For example, single crystal materials such as YSZ, zirconium oxide, silicon, silicon carbide, gallium nitride, and gallium oxide can be used. In particular, it is preferable to use oxide insulating materials such as zirconium oxide or YSZ. It is also possible to use rare earth oxides and lanthanide oxides such as yttrium oxide, erbium oxide, gadolinium oxide, and ytterbium oxide. In particular, when indium oxide is used for the semiconductor layer 230, it is preferable to use yttrium oxide or erbium oxide.

In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the semiconductor layer 230. Furthermore, in order to reduce the impurity concentration in the semiconductor layer 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in the semiconductor layer 230 refer to, for example, anything other than the main component that constitutes the semiconductor layer 230. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

It is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the semiconductor layer 230.

The band gap of a metal oxide that functions as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. A transistor that has a metal oxide in its channel formation region is called an OS transistor. Because OS transistors have a low off-state current, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because OS transistors have high frequency characteristics, the semiconductor device can operate at high speed.

For the semiconductor layer 230, it is preferable to use indium oxide. In particular, it is preferable to use a single-crystal indium oxide film. Note that it is preferable to use a crystalline film for the semiconductor layer 230, and it is particularly preferable to use indium oxide with a single-crystal structure, but indium oxide with a polycrystalline structure or microcrystalline structure can also be used. By using indium oxide with a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, making it possible to realize a transistor with high field-effect mobility. It also makes it possible to realize a highly reliable transistor.

When using indium oxide having a polycrystalline structure, it is preferable that no grain boundaries are observed at least in the channel formation region (the region overlapping with the conductive layer 260). This allows indium oxide having a polycrystalline structure to achieve the same effects as indium oxide having a single-crystalline structure.

The film thickness of the semiconductor layer 230 is preferably 2 nm or more and 50 nm or less, more preferably 2.5 nm or more and 30 nm or less, more preferably 2.5 nm or more and 20 nm or less, more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 10 nm or less. By setting the film thickness of the semiconductor layer 230 within the above range, the crystallinity of the semiconductor layer 230 can be improved.

Among highly crystalline oxide semiconductors, indium oxide is a film in which hydrogen and/or oxygen move more easily than, for example, an IGZO (In-Ga-Zn-O-based oxide) film. Therefore, indium oxide is a film in which hydrogen and/or oxygen are more easily supplied and discharged than, for example, an IGZO film. This means that excess oxygen or excess hydrogen, which can become carriers or fixed charges, is less likely to accumulate in the semiconductor layer 230, resulting in a transistor with good electrical characteristics and reliability.

It is preferable that the semiconductor layer 230 has a reduced concentration of elements that reduce crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

Furthermore, because gallium has the property of easily bonding with excess oxygen atoms, if the gallium content is high, the threshold voltage may fluctuate greatly in PBTS (Positive Bias Temperature Stress) testing. Therefore, the gallium concentration in the semiconductor layer 230 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

Other metal oxides that can be used for the semiconductor layer 230 include tin oxide, zinc oxide, indium tin oxide, indium titanium oxide, indium gallium oxide, indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, and indium gallium aluminum zinc oxide. Alternatively, silicon-containing indium tin oxide, gallium tin oxide, aluminum tin oxide, and the like can also be used. When using these, it is preferable that the film has at least some crystallinity, and more preferably has a single crystal structure.

The insulating layer 250, which functions as a gate insulating layer, preferably has the function of capturing and fixing hydrogen. This reduces the hydrogen concentration in the channel formation region of the semiconductor layer 230. This allows the channel formation region to be i-type or substantially i-type.

Here, it is preferable that the insulating layer 250 has a laminated structure of a first layer in contact with the semiconductor layer 230, a second layer on the first layer, and a third layer on the second layer. In this case, it is preferable that the first layer has the function of capturing and fixing hydrogen.

An example of an insulator capable of capturing and fixing hydrogen is a metal oxide with an amorphous structure. For the first layer, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides with an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the ability to capture or fix hydrogen. In other words, metal oxides with an amorphous structure have a high ability to capture or fix hydrogen.

It is also preferable to use a high-dielectric constant (high-k) material for the first layer. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the first layer makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

For the first layer, it is preferable to use an oxide containing one or both of aluminum and hafnium, more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably aluminum oxide having an amorphous structure.

Next, the second layer is preferably made of an insulator with a thermally stable structure, such as silicon oxide or silicon oxynitride.

Alternatively, a fourth layer may be provided on the second layer. In this case, the fourth layer may be an insulator that can be used for the first layer. For example, hafnium oxide may be used for the fourth layer. Here, by providing the fourth layer between the third and second layers, hydrogen contained in the second layer, etc., can be more effectively captured and fixed.

The third layer preferably has barrier properties against oxygen. The third layer is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260, and between the insulating layer 280 and the conductive layer 260. This structure prevents oxygen contained in the channel formation region of the semiconductor layer 230 from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. It also prevents oxygen contained in the semiconductor layer 230 and oxygen contained in the insulating layer 280 from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The third layer preferably has a lower oxygen permeability than the insulating layer 280. For example, it is preferable to use a silicon nitride film as the third layer. In this case, the third layer is an insulator containing at least nitrogen and silicon.

Furthermore, it is preferable that the third layer has barrier properties against hydrogen. This prevents impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

The insulating layer 275 preferably has barrier properties against oxygen. The insulating layer 275 is provided between the insulating layer 280 and the conductive layer 242a, and between the insulating layer 280 and the conductive layer 242b. This configuration prevents oxygen contained in the insulating layer 280 from diffusing into the conductive layer 242a and the conductive layer 242b. This prevents the conductive layer 242a and the conductive layer 242b from being oxidized by the oxygen contained in the insulating layer 280, increasing their resistivity and reducing their on-current. The insulating layer 275 is preferably at least less permeable to oxygen than the insulating layer 280. For example, it is preferable to use silicon nitride as the insulating layer 275. In this case, the insulating layer 275 becomes an insulator containing at least nitrogen and silicon.

Furthermore, in this embodiment, in addition to the above structure, the semiconductor device preferably has a structure that prevents hydrogen from being mixed into the transistor 200, etc. For example, it is preferable to provide an insulator that has the function of preventing hydrogen diffusion so as to cover the transistor 200. In the semiconductor device described in this embodiment, the insulator is, for example, insulating layer 282 or insulating layer 283. Furthermore, a similar film may be provided under the transistor 200.

One or more of the insulating layers 282 and 283 preferably function as a barrier insulator that suppresses diffusion of impurities such as water and hydrogen from above the transistor 200 to the transistor 200. Therefore, one or more of the insulating layers 282 and 283 preferably include an insulating material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as _N2O , NO, and _NO2 ), and copper atoms (through which the impurities are less likely to permeate). Alternatively, it is preferable to include an insulating material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (through which the oxygen is less likely to permeate).

The insulating layers 282 and 283 each preferably contain an insulator that suppresses the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulating layer 283 is preferably made of silicon nitride, which has excellent hydrogen barrier properties. The insulating layer 282 also preferably contains aluminum oxide or magnesium oxide, which has excellent hydrogen capture and fixation properties. This can suppress the diffusion of impurities such as water and hydrogen from interlayer insulating films disposed outside the insulating layer 283 to the transistor 200, etc. The diffusion of oxygen contained in the insulating layer 280, etc., through the insulating layer 282, etc., above the transistor 200, etc., can be suppressed. Furthermore, providing a film similar to one or both of the insulating layers 282 and 283 below the transistor 200 can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200, etc.

Insulating layers 271a and 271b are inorganic insulators that function as etching stoppers when conductive layers 242a and 242b are processed, protecting conductive layers 242a and 242b. Furthermore, since insulating layers 271a and 271b are in contact with conductive layers 242a and 242b, respectively, they are preferably inorganic insulators that do not easily oxidize conductive layers 242a and 242b. For example, insulating layers 271a and 271b may have a stacked structure, with silicon nitride used on the side in contact with conductive layers 242a and 242b and silicon oxide used elsewhere.

Openings reaching conductive layer 242a are formed in insulating layer 285, insulating layer 283, insulating layer 282, insulating layer 280, insulating layer 275, and insulating layer 271a, and conductive layer 240a and insulating layer 241a are provided within the openings. Insulating layer 241a is provided in contact with the sidewalls of the openings, and conductive layer 240a is provided inside insulating layer 241a. Furthermore, openings reaching conductive layer 242b are formed in insulating layer 285, insulating layer 283, insulating layer 282, insulating layer 280, insulating layer 275, and insulating layer 271b, and conductive layer 240b and insulating layer 241b are provided within the openings. Insulating layer 241b is provided in contact with the sidewalls of the openings, and conductive layer 240b is provided inside insulating layer 241b. The conductive layers 240a and 240b function as vias that connect wiring or the like provided on the transistor 200 to the source or drain of the transistor 200.

Conductive layer 240a and conductive layer 240b are preferably made of a conductive material whose main component is, for example, tungsten, copper, or aluminum. Conductive layer 240a and conductive layer 240b may also have a layered structure.

For example, as shown in FIG. 7, conductive layer 240a and conductive layer 240b may have a two-layer laminated structure. Conductive layer 240a has conductive layer 240a1 formed along the opening and conductive layer 240a2 formed inside conductive layer 240a1. Conductive layer 240b has conductive layer 240b1 formed along the opening and conductive layer 240b2 formed inside conductive layer 240b1.

Conductive layers 240a1 and 240b1 are preferably made of a conductive material such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide, which has the function of suppressing the permeation of impurities such as water and hydrogen. Furthermore, conductive materials that have the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. Providing conductive layers 240a1 and 240b1 can suppress impurities such as water and hydrogen from entering the semiconductor layer 230 through conductive layers 240a2 and 240b2. Note that conductive layers 240a2 and 240b2 may be made of the same conductive materials that can be used for the conductive layers 240a and 240b described above.

Also, as shown in FIG. 6B, the upper surfaces of conductive layer 240a and conductive layer 240b can be formed so that they coincide or nearly coincide with the upper surface of insulating layer 285. Also, as shown in FIG. 7, the lower part of conductive layer 240a may be formed so that it is embedded in conductive layer 242a. Similarly, the lower part of conductive layer 240b may be formed so that it is embedded in conductive layer 242b.

The insulating layers 241a and 241b may be made of a barrier insulator that can be used for the insulating layer 275, etc. For example, silicon nitride may be used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, and 275, as well as the insulating layers 271a and 271b, respectively. This prevents impurities such as water and hydrogen contained in the insulating layer 280 from entering the semiconductor layer 230 through the conductive layers 240a and 240b. Silicon nitride is particularly suitable because it has high blocking properties against hydrogen. It also prevents oxygen contained in the insulating layer 280 from being absorbed by the conductive layers 240a and 240b.

The conductive layer 260 functions as the gate electrode of the transistor 200. Here, as shown in Figures 6A and 6C, the conductive layer 260 is preferably provided so as to extend in the channel width direction. With this configuration, when multiple transistors are provided, the conductive layer 260 functions as wiring.

The conductive layer 260 may have a layered structure. Figure 7 shows an example in which the conductive layer 260 has a conductive layer 260a located on the side in contact with the insulating layer 250 and a conductive layer 260b above it. In this case, it is preferable to use a conductive material that is resistant to oxidation, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, or a conductive material that has the function of suppressing oxygen diffusion, for the conductive layer 260a. It is also preferable to use a low-resistance conductive material such as tungsten, copper, or aluminum for the conductive layer 260b.

The insulating layer 280 preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film reduces the parasitic capacitance that occurs between wiring. For example, the insulating layer 280 preferably contains one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide with vacancies. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they allow for the easy formation of regions containing oxygen that is released by heating.

[Modification]
The following describes an example in which the configuration is partially different from the above example, and the description of the same parts as above will be omitted.

[Variation 1]
8 illustrates an example in which the transistor 200 includes a conductive layer 205 that functions as a back gate. The structure illustrated in FIG. 8 includes the conductive layer 205 and the insulating layer 202.

The conductive layer 205 is embedded in the insulating layer 202. The insulating layer 201 is provided to cover the insulating layer 202 and the conductive layer 205.

The conductive layer 205 functions as a second gate (back gate) of the transistor 200. The conductive layer 205 is provided in a region that overlaps with the conductive layer 260 with the semiconductor layer 230 interposed therebetween. By providing the conductive layer 205 and applying an appropriate potential to the conductive layer 205, the threshold voltage of the transistor 200 can be controlled. Furthermore, since the potential on the back channel side of the semiconductor layer 230 can be fixed, variation in the electrical characteristics of the transistor 200 can be reduced. The conductive layer 205 may be applied with the same potential or signal as any one of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260.

The conductive layer 205 can be made of any material that can be used for the conductive layer 260. The conductive layer 205 may also have a layered structure.

In this case, the insulating layer 201 functions as a second gate insulating layer.

A silicon oxide film can be used for the insulating layer 202. Note that it is preferable to provide an insulating film, such as silicon nitride or aluminum oxide, that has barrier properties against oxygen between the insulating layer 202 and the conductive layer 205, because this can prevent oxidation of the conductive layer 205.

[Variation 2]
9A to 9D show examples of a transistor 200 that is partially different from the above-described structure. FIG. 9A is a top view, and FIGS. 9B to 9D are cross-sectional views, respectively. The structures shown in FIGS. 9A to 9D differ from the above-described structure mainly in that an insulating layer 255 is included. Furthermore, the insulating layer 250 is in contact with a side surface of the insulating layer 255.

Note that here, each of the conductive layers 242a and 242b is shown as having a two-layer structure. The conductive layer 242a has a stacked structure of a conductive layer 242a1 and a conductive layer 242a2 on the conductive layer 242a1. The conductive layer 242b has a stacked structure of a conductive layer 242b1 and a conductive layer 242b2 on the conductive layer 242b1.

Insulating layer 255 is disposed inside an opening formed in insulating layer 280 or the like, and contacts the side of insulating layer 280, the side of conductive layer 242a2, the side of conductive layer 242b2, the top surface of conductive layer 242a1, the top surface of conductive layer 242b1, and the top surface of insulating layer 201 in the opening. In other words, insulating layer 255 can be said to be formed in the shape of a sidewall, contacting the side wall of the opening formed in insulating layer 280 or the like. Here, the side wall of the opening corresponds, for example, to the side of insulating layer 280 or the like in the opening.

The insulating layer 255 preferably has a barrier property against oxygen. The insulating layer 255 having a barrier property against oxygen can prevent the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and an oxide film from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200. The insulating layer 255 can be made of a barrier insulator that can be used for the insulating layer 275, for example. For example, silicon nitride can be used for the insulating layer 255.

The opening in insulating layer 280 overlaps the region between conductive layer 242a2 and conductive layer 242b2. In a top view, the side surfaces of insulating layer 280 at the opening coincide or substantially coincide with the side surfaces of conductive layer 242a2 and conductive layer 242b2. Furthermore, portions of conductive layer 242a1 and conductive layer 242b1 are formed to protrude into the opening. In other words, the portion of conductive layer 242a1 on which insulating layer 255 is formed (hereinafter, sometimes referred to as the protruding portion of conductive layer 242a1) protrudes toward conductive layer 260 beyond conductive layer 242a2. Similarly, the portion of conductive layer 242b1 on which insulating layer 255 is formed (hereinafter, sometimes referred to as the protruding portion of conductive layer 242b1) protrudes toward conductive layer 260 beyond conductive layer 242b2.

Here, a portion of the upper surface of conductive layer 242a1 contacts conductive layer 242a2, and a portion of the upper surface of conductive layer 242b1 contacts conductive layer 242b2. Therefore, inside the opening, insulating layer 255 contacts another portion of the upper surface of conductive layer 242a1, another portion of the upper surface of conductive layer 242b1, the side surface of conductive layer 242a2, and the side surface of conductive layer 242b2. Furthermore, insulating layer 250 contacts the upper surface of semiconductor layer 230, the side surface of conductive layer 242a1, the side surface of conductive layer 242b1, and the side surface of insulating layer 255.

The insulating layer 255 is formed in a sidewall shape by anisotropic etching, in contact with the sidewall of the opening provided in the insulating layer 280. The insulating layer 255 is formed in contact with the side surface of the conductive layer 242a2 and the side surface of the conductive layer 242b2, and functions to protect the conductive layer 242a2 and the conductive layer 242b2.

[Variation 3]
10A to 10D show examples of the structure of a transistor 200. The structure shown in FIG. 10A to 10D differs from the second modification mainly in that the insulating layer 255 is not provided.

In a configuration in which insulating layer 255 is not provided, a portion of insulating layer 250 is arranged overlapping the protruding portions of conductive layer 242a1 and conductive layer 242b1. Also, a portion of conductive layer 260 may be arranged overlapping the protruding portions of conductive layer 242a1 and conductive layer 242b1. Here, the protruding portions of conductive layer 242a1 and conductive layer 242b1 contact insulating layer 250. Furthermore, the side of insulating layer 250 contacts the side of insulating layer 280, the side of conductive layer 242a2, and the side of conductive layer 242b2.

The portion of insulating layer 250 that is placed in the opening provided in insulating layer 280 is formed to reflect the shape of the opening. Therefore, insulating layer 250 is formed to reflect the shapes of conductive layer 242a1 and conductive layer 242b1 that protrude into the opening.

As shown in Figure 10B, in a cross-sectional view of transistor 200 in the channel length direction, the distance between conductive layer 242a1 and conductive layer 242b1 is smaller than the distance between conductive layer 242a2 and conductive layer 242b2. This configuration makes it possible to shorten the distance between the source and drain, and accordingly shorten the channel length. This improves the frequency characteristics of transistor 200. In this way, miniaturization of semiconductor devices can provide semiconductor devices with improved operating speeds.

[Example of manufacturing method]
An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below, taking the transistor 200 illustrated in the above "Structure example of a semiconductor device" and in FIGS.

11A1, 11B1, 11C1, 11D1, 12A1, 12B1, and 12C1 are schematic cross-sectional views at each stage of the exemplary fabrication method illustrated below, while 11A2, 11B2, 11C2, 11D2, 12A2, 12B2, and 12C2 are perspective views. Note that the perspective views are partially cut away. Also, in the perspective views, only the outlines of some components (such as insulating layers) are shown with dashed lines.

First, a structure is prepared in which semiconductor film 230f is formed on insulating layer 201. Insulating layer 201 corresponds to substrate 11 or base film 12 in embodiment 1. Semiconductor film 230f corresponds to semiconductor film 21f in embodiment 1, and its fabrication method can be referenced. Note that this point corresponds to the stage shown in Figure 1B in embodiment 1.

It is preferable to perform heat treatment on the semiconductor film 230f. For example, the heat treatment can be performed at a temperature of 450°C for one hour with a nitrogen gas to oxygen gas flow ratio of 4:1. Heat treatment can improve the crystallinity of the semiconductor film 230f. Furthermore, heat treatment can supply oxygen into the semiconductor film 230f and reduce oxygen vacancies in the semiconductor film 230f. This can improve the reliability of the transistor 200. Heat treatment can also remove hydrogen from the semiconductor film 230f.

Next, conductive film 242f is formed on semiconductor film 230f (Figures 11A1 and 11A2). After the formation of semiconductor film 230f, conductive film 242f is formed on and in contact with semiconductor film 230f without an etching process or the like, thereby protecting the top surface of semiconductor film 230f with conductive film 242f. This makes it possible to prevent impurities from diffusing into semiconductor layer 230, which constitutes the transistor, and improves the electrical characteristics and reliability of the semiconductor device.

The conductive film 242f can be formed using sputtering, CVD, MBE, PLD, or ALD.

In this embodiment, tantalum nitride is deposited as the conductive film 242f by sputtering. Note that heat treatment may be performed before the deposition of the conductive film 242f. The heat treatment may be performed under reduced pressure, and the conductive film 242f may be deposited successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the semiconductor film 230f can be removed, and the moisture and hydrogen concentrations in the semiconductor film 230f can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

Next, the semiconductor film 230f and the conductive film 242f are processed into island shapes using lithography to form the semiconductor layer 230 and the conductive layer 242 (Figures 11B1 and 11B2).

The above processing can be performed using dry etching or wet etching. Dry etching is suitable for fine processing. Furthermore, the semiconductor film 230f and the conductive film 242f may be processed under different conditions.

Alternatively, a layer that functions as a hard mask may be formed on the conductive film 242f. Using a hard mask is preferable because it improves processability and makes it easier to process into the desired shape.

Here, it is preferable to process the semiconductor layer 230 and the conductive layer 242 together into an island shape. In this case, it is preferable that the side edge of the conductive layer 242 coincides or substantially coincides with the side edge of the semiconductor layer 230. With such a structure, the number of steps required for manufacturing a semiconductor device according to one embodiment of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

As shown in FIG. 11B1, the side surfaces of the semiconductor layer 230 and the conductive layer 242 may be tapered. The taper angle of the side surfaces of the semiconductor layer 230 and the conductive layer 242 may be, for example, greater than or equal to 60° and less than 90°. By tapering the side surfaces in this way, the coverage of the insulating layer 275 and the like can be improved in subsequent processes, and defects such as voids can be reduced.

In lithography, the resist is first exposed through a mask. The exposed areas are then removed or left using a developer to form a resist mask. Next, etching is performed through the resist mask to process conductors, semiconductors, insulators, etc. into the desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Immersion technology can also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens before exposure. An electron beam or ion beam can also be used instead of the light mentioned above. When using an electron beam or ion beam, a mask may not be required.

In addition, resist masks that are no longer needed after processing can be removed by performing a dry etching process such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film that will serve as the hard mask material is formed on the conductive film 242f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of the desired shape. For example, tungsten may be used as the hard mask material. Etching of the conductive film 242f, etc. may be performed after removing the resist mask, or may be performed while leaving the resist mask in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the semiconductor film 230f, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

Alternatively, an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film may be formed between the workpiece and the resist mask. Using an SOC film and an SOG film as a mask improves adhesion with the resist mask and increases the durability of the mask pattern. For example, an SOC film, an SOG film, and a resist mask may be formed in this order on the workpiece, and then lithography may be performed.

Next, an insulating layer 275 is formed to cover the semiconductor layer 230 and the conductive layer 242, and an insulating layer 280 is then formed on the insulating layer 275 (Figures 11C1 and 11C2).

For the insulating layer 280, it is preferable to form an insulating film that will become the insulating layer 280 and then perform CMP processing on the insulating film to form an insulator with a flat upper surface. Alternatively, a silicon nitride film may be formed on the insulating layer 280 by, for example, sputtering, and then CMP processing may be performed on the silicon nitride until it reaches the insulating layer 280.

Insulating layer 275 and insulating layer 280 can each be formed using, for example, sputtering, CVD, MBE, PLD, or ALD.

For the insulating layer 275, it is preferable to use an insulator that has the function of suppressing oxygen permeation. For example, it is preferable to form a silicon nitride film as the insulating layer 275 using the PEALD method. Alternatively, the insulating layer 275 may be formed by forming an aluminum oxide film using the sputtering method and then forming a silicon nitride film thereon using the PEALD method. By forming the insulating layer 275 in the above structure, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

It is also preferable to form the insulating layer 280 using silicon oxide by sputtering. By forming the insulating film that will become the insulating layer 280 by sputtering in an oxygen-containing atmosphere, the insulating layer 280 can be formed to contain excess oxygen. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. Heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulating layer 275, etc., can be removed. The heat treatment conditions described above can be used for the heat treatment.

Next, the conductive layer 242, insulating layer 275, and insulating layer 280 are processed using lithography to form openings (also called grooves) that reach the semiconductor layer 230 and insulating layer 201 (Figures 11D1 and 11D2). Here, the conductive layer 242 is divided to form conductive layers 242a and 242b. The openings formed in the insulating layer 280 and insulating layer 275 overlap with the semiconductor layer 230.

Next, insulating layer 250 is formed so as to cover the openings formed in insulating layer 280, etc. Here, insulating layer 250 is formed along the openings in insulating layer 280. In addition, insulating layer 250 contacts insulating layer 280, conductive layer 242a, conductive layer 242b, insulating layer 201, and semiconductor layer 230.

The insulating layer 250 can be formed using sputtering, CVD, MBE, PLD, or ALD. Since it is preferable to form the insulating layer 250 with a thin film thickness, it is preferable to form it using the ALD method, which has excellent coverage and easy film thickness control.

When the insulating layer 250 is formed by the ALD method, ozone ( _O3 ), oxygen ( _O2 ), water ( _H2O ), or the like can be used as an oxidizing agent. By using ozone ( _O3 ), oxygen ( _O2 ), or the like that does not contain hydrogen as an oxidizing agent, the amount of hydrogen that diffuses into the semiconductor layer 230 can be reduced.

It is also preferable to perform microwave treatment before, after, or during the formation of the insulating layer 250.

More specifically, it is preferable to perform microwave treatment in an atmosphere containing oxygen. Here, microwave treatment refers to treatment using, for example, a device equipped with a power source that generates high-density plasma using microwaves. Furthermore, in this specification and elsewhere, microwaves refer to electromagnetic waves with a frequency of 300 MHz or higher and 300 GHz or lower.

For microwave processing, it is preferable to use a microwave processing device having a power supply that generates high-density plasma using microwaves. The frequency of the microwave processing device can typically be 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves in the microwave processing device is preferably 1000 W or more and 10,000 W or less, and preferably 2000 W or more and 5,000 W or less. The microwave processing device may also have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the semiconductor layer 230.

Furthermore, the microwave treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, and more preferably being 300 Pa or higher and 700 Pa or lower. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out consecutively without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, and more preferably 300°C or higher and 500°C or lower.

Next, a conductive film that will become the conductive layer 260 is formed. This conductive film can be formed using sputtering, CVD, MBE, PLD, plating, or ALD. For example, a titanium nitride film and a tungsten film can be stacked and formed using CVD.

Next, the conductive film that will become insulating layer 250 and conductive layer 260 is polished by CMP until insulating layer 280 is exposed. In other words, the insulating layer 250 and the portions of the conductive film exposed through the opening are removed. This forms insulating layer 250 and conductive layer 260 in the opening that reaches semiconductor layer 230 (Figures 12A1 and 12A2).

As a result, the insulating layer 250 is provided in the opening in contact with the conductive layer 242a, the conductive layer 242b, the semiconductor layer 230, and the insulating layer 201. Furthermore, the conductive layer 260 is disposed so as to fill the opening via the insulating layer 250. In this manner, the transistor 200 is formed.

Next, insulating layer 282 is formed on insulating layer 250, conductive layer 260, and insulating layer 280. Insulating layer 282 can be formed using, for example, sputtering, CVD, MBE, PLD, or ALD. Sputtering is preferably used to form insulating layer 282. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in insulating layer 282 can be reduced.

Here, by using a sputtering method to deposit the insulating layer 282 in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 280 while the layer is being deposited. This allows the insulating layer 280 to contain excess oxygen.

Next, insulating layer 285 is formed on insulating layer 282 (Figures 12B1 and 12B2). Insulating layer 285 can be formed using sputtering, CVD, MBE, PLD, or ALD. Sputtering is preferably used to form insulating layer 285. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in insulating layer 285 can be reduced.

Next, openings are formed in insulating layer 275, insulating layer 280, insulating layer 282, and insulating layer 285, reaching conductive layers 242a and 242b, respectively. The openings may be formed using lithography. When forming the openings, it is preferable to process the workpiece using dry etching. Note that the shape of the openings when viewed from above can be a circle, an approximately circular shape such as an ellipse, a polygonal shape such as a square, or a polygonal shape with rounded corners such as a square.

Next, after the openings are formed, heat treatment can be performed. The temperature for the heat treatment is 100°C to 600°C, preferably 250°C to 550°C, and more preferably 350°C to 450°C. The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. Furthermore, since the conductive layers 242a and 242b are exposed, the heat treatment is preferably performed in an atmosphere that does not contain oxidizing gas or oxygen gas. For example, the heat treatment is preferably performed in a nitrogen gas atmosphere at 400°C for one hour. The heat treatment may be performed under reduced pressure. The heat treatment allows oxygen contained in the insulating layer 280 to be supplied to the semiconductor layer 230 through the insulating layer 250. Furthermore, by performing the heat treatment after the openings are formed in the insulating layer 280, some of the oxygen contained in the insulating layer 280 can be released, thereby adjusting the amount of oxygen contained in the insulating layer 280. This prevents reliability from being impaired by excess oxygen.

Next, insulating films that will become insulating layers 241a and 241b are formed according to the shape of the openings. These insulating films can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Because the insulating films that will become insulating layers 241a and 241b are formed in openings with a large aspect ratio, they are preferably formed using an ALD method. Furthermore, it is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film that will become insulating layers 241a and 241b. For example, it is preferable to form a silicon nitride film using a PEALD method. Silicon nitride is preferable because it has high blocking properties against hydrogen.

Next, the insulating film is anisotropically etched to form insulating layers 241a and 241b. Here, insulating layer 241a is formed to cover the sidewalls of the openings on conductive layer 242a, and insulating layer 241b is formed to cover the sidewalls of the openings on conductive layer 242b. Dry etching or the like can be used for anisotropically etching the insulating films that will become insulating layers 241a and 241b. For example, reactive ion etching is preferably used. By providing insulating layers 241a and 241b on the sidewalls of the openings, oxygen penetration from the outside can be suppressed, preventing oxidation of conductive layers 240a and 240b, which will be formed next. Furthermore, impurities such as water and hydrogen contained in insulating layer 280 can be prevented from diffusing into conductive layers 240a and 240b. Note that this anisotropic etching may form recesses in parts of the top surfaces of conductive layers 242a and 242b.

Next, a conductive film that will become conductive layer 240a and conductive layer 240b is formed. It is desirable that the conductive film have a layered structure that includes a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become conductive layer 240a and conductive layer 240b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, CMP processing is performed to remove portions of the conductive film that will become conductive layers 240a and 240b, exposing the upper surface of insulating layer 285 (Figures 12C1 and 12C2). As a result, the conductive film remains only in the openings, allowing conductive layers 240a and 240b to be formed with flat upper surfaces. Note that the CMP processing may remove portions of the upper surface of insulating layer 285.

Furthermore, heat treatment may be performed after the conductive layers 240a and 240b are formed. The heat treatment can be performed under the same conditions as the above-described heat treatment. By performing the heat treatment, the amount of oxygen supplied to the semiconductor layer 230 can be adjusted. This can improve the electrical characteristics and reliability of the transistor 200.

In this manner, the transistor 200 shown in Figures 6A to 6D can be fabricated.

The transistor 200 described in this embodiment can be replaced with the transistor 10 described in Embodiment 1. This makes it possible to realize a semiconductor device in which a transistor whose channel is formed in a single crystal substrate and a transistor whose channel is formed in an oxide semiconductor film are stacked.

This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.

(Embodiment 3)
In this embodiment, a memory device of one embodiment of the present invention will be described with reference to FIGS. 13 to 16. In this embodiment, a configuration example of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided will be described.

The transistor in which a channel is formed in a single crystal substrate (referred to as a Si transistor), as exemplified in Embodiment 1, can be used as a transistor included in a driver circuit including a sense amplifier, as exemplified below. The transistor in which a channel is formed in a single crystal oxide semiconductor (referred to as an OS transistor), as exemplified in Embodiment 1, can be used as a transistor included in a memory cell.

<Configuration example of storage device>
13 is a block diagram illustrating a configuration example of a memory device 480 according to one embodiment of the present invention. The memory device 480 illustrated in FIG. 13 includes a layer 420 and a stacked layer 470.

Layer 420 is a layer including a Si transistor. In layer 470, element layers 430[1] to 430[m] (m is an integer of 2 or more) are stacked. Element layers 430[1] to 430[m] are layers including an OS transistor. Layer 470, which includes a stack of layers including an OS transistor, can be stacked on layer 420.

Elements such as OS transistors and capacitors included in the element layers 430[1] to 430[m] constitute memory cells. Figure 13 shows an example in which the element layers 430[1] to 430[m] have multiple memory cells 432 arranged in a matrix of m rows and n columns (n is an integer greater than or equal to 2).

In FIG. 13, memory cell 432 in the first row and first column is indicated as memory cell 432[1,1], and memory cell 432 in the mth row and nth column is indicated as memory cell 432[m,n]. Furthermore, in this embodiment and the like, an arbitrary row may be referred to as row i. Furthermore, an arbitrary column may be referred to as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. Furthermore, in this embodiment and the like, memory cell 432 in the ith row and jth column is indicated as memory cell 432[i,j]. Furthermore, in this embodiment and the like, when it is indicated as "i+α" (α is a positive or negative integer), "i+α" is not less than 1 or more than m. Similarly, when it is indicated as "j+α", "j+α" is not less than 1 or more than n.

13 illustrates, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n]. Note that the number of element layers 430[1] to 430[m] and the number of wirings WL (and wirings PL) do not have to be the same.

The multiple memory cells 432 provided in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The multiple memory cells 432 provided in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on/off (conducting or non-conducting) of an access transistor that functions as a switch. The wiring PL functions as a constant potential line connected to a capacitor. Note that a separate wiring can be provided to transmit the back gate potential.

The memory cells 432 included in each of the element layers 430[1] to 430[m] are connected to a sense amplifier 446 via wiring BL. The wiring BL can be arranged parallel to or perpendicular to the substrate surface on which the layer 420 is provided. By configuring the wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] with wiring arranged vertically in addition to wiring arranged horizontally on the substrate surface, the length of the wiring between the element layer 430 and the sense amplifier 446 can be shortened. The signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line are significantly reduced, thereby achieving reduced power consumption and signal delay. This reduces the power consumption and signal delay of the memory device 480. Furthermore, it is possible to operate even if the capacitance of the capacitor included in the memory cell 432 is reduced. This allows the memory device 480 to be made smaller.

Layer 420 has PSW 471 (power switch), PSW 472, and peripheral circuit 422. Peripheral circuit 422 has drive circuit 440, control circuit 473, and voltage generation circuit 474. Each circuit in layer 420 has a Si transistor.

In the memory device 480, each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal.

Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by control circuit 473.

The control circuit 473 is a logic circuit that has the function of controlling the overall operation of the memory device 480. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operating mode (e.g., write operation, read operation) of the memory device 480. Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 so that this operating mode is executed.

Voltage generation circuit 474 has the function of generating a negative voltage. Signal WAKE has the function of controlling the input of signal CLK to voltage generation circuit 474. For example, when a high-level signal is applied to signal WAKE, signal CLK is input to voltage generation circuit 474, causing voltage generation circuit 474 to generate a negative voltage.

The drive circuit 440 is a circuit for writing and reading data to and from the memory cells 432. The drive circuit 440 includes a row decoder 442, a column decoder 444, a row driver 443, a column driver 445, an input circuit 447, an output circuit 448, and the aforementioned sense amplifier 446.

The row decoder 442 and column decoder 444 have the function of decoding the signal ADDR. The row decoder 442 is a circuit for specifying the row to access, and the column decoder 444 is a circuit for specifying the column to access. The row driver 443 has the function of selecting the wiring WL specified by the row decoder 442. The column driver 445 has the function of writing data to the memory cell 432, reading data from the memory cell 432, and retaining the read data.

The input circuit 447 has the function of holding the signal WDA. The data held by the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is the data (Din) to be written to the memory cell 432. The data (Dout) read from the memory cell 432 by the column driver 445 is output to the output circuit 448. The output circuit 448 has the function of holding Dout. The output circuit 448 also has the function of outputting Dout to the outside of the memory device 480. The data output from the output circuit 448 is the signal RDA.

PSW471 has the function of controlling the supply of VDD to the peripheral circuit 422. PSW472 has the function of controlling the supply of VHM to the row driver 443. Here, the high power supply potential of the memory device 480 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to set the word line to a high level, and is higher than VDD. The on/off of PSW471 is controlled by signal PON1, and the on/off of PSW472 is controlled by signal PON2. In Figure 13, the number of power domains to which VDD is supplied in the peripheral circuit 422 is one, but there can be multiple. In this case, a power switch can be provided for each power domain.

Element layers 430[1] to 430[m] can be stacked on layer 420. Figure 14A shows a perspective view of a memory device 480 in which five (m = 5) element layers 430[1] to 430[5] are stacked on layer 420.

In Figure 14A, the element layer 430 provided in the first layer is shown as element layer 430[1], the element layer 430 provided in the second layer is shown as element layer 430[2], and the element layer 430 provided in the fifth layer is shown as element layer 430[5]. Also shown in Figure 14A are wiring WL and wiring PL extending in the X direction, and wiring BL and wiring BLB extending in the Y direction and Z direction (directions perpendicular to the substrate surface on which the driver circuit is provided). Wiring BLB is an inverted bit line. Note that to make the drawing easier to understand, the wiring WL and wiring PL of each element layer 430 have been partially omitted.

Figure 14B is a schematic diagram illustrating a configuration example of the sense amplifier 446 connected to the wiring BL and wiring BLB shown in Figure 14A, and the memory cells 432 included in the element layers 430[1] to 430[5] connected to the wiring BL and wiring BLB. Note that a configuration in which multiple memory cells (memory cells 432) are electrically connected to one wiring BL and wiring BLB is also referred to as a "memory string."

Figure 14B shows an example of the circuit configuration of a memory cell 432 connected to wiring BLB. The memory cell 432 includes a transistor 437 and a capacitor 438. The transistor 437, the capacitor 438, and each wiring (BL, WL, etc.) may also be referred to as wiring BL and wiring WL, for example, instead of wiring BL[1] and wiring WL[1].

In the memory cell 432, one of the source and drain of the transistor 437 is connected to the wiring BL. The other of the source and drain of the transistor 437 is connected to one electrode of the capacitor 438. The other electrode of the capacitor 438 is connected to the wiring PL. The gate of the transistor 437 is connected to the wiring WL.

The wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitor 438. By connecting multiple wirings PL together and using them as a single wiring, the number of wirings can be reduced.

In one embodiment of the present invention, OS transistors are stacked, and wirings that function as bit lines are arranged perpendicular to the surface of the substrate on which the layer 420 is provided. In addition, the transistor 437 and capacitor 438 included in the memory cell 432 are arranged side by side in the perpendicular direction to the surface of the substrate on which the layer 420 is provided. By arranging each element and each wiring perpendicular to the surface of the substrate, the length of the wiring between element layers can be shortened and the density of elements arranged per unit area can be increased. Therefore, a memory device with excellent storage capacity and reduced power consumption can be obtained.

[Configuration example of memory cell 432 and sense amplifier 446]
15A and 15B show a circuit diagram corresponding to the memory cell 432 described above and a circuit block diagram corresponding to the circuit diagram. As shown in FIGS. 15A and 15B, the memory cell 432 may be represented as a block in the drawings. Note that the wiring BL shown in FIGS. 15A and 15B can be represented in the same manner even when replaced with a wiring BLB.

FIGS. 15C and 15D show a circuit diagram corresponding to the sense amplifier 446 described above, and a circuit block diagram corresponding to the circuit diagram. The sense amplifier 446 includes a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplifier circuit 485. Also shown are wirings BL and BLB, as well as wirings SA_OUT and SA_OUTB that output signals to be read out.

As shown in FIG. 15C, the switch circuit 482 includes, for example, N-type transistors 482_1 and 482_2. The transistors 482_1 and 482_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.

As shown in FIG. 15C, the precharge circuit 483 is composed of N-type transistors 483_1 to 483_3. The precharge circuit 483 is a circuit for precharging the wiring BL and wiring BLB to an intermediate potential VPRE corresponding to a potential VDD/2 in response to a signal EQ.

As shown in FIG. 15C, the precharge circuit 484 is composed of P-type transistors 484_1 to 484_3. The precharge circuit 484 is a circuit for precharging the wiring BL and wiring BLB to an intermediate potential VPRE corresponding to a potential VDD/2 in response to a signal EQB.

As shown in Figure 15C, the amplifier circuit 485 is composed of P-type transistors 485_1 and 485_2 and N-type transistors 485_3 and 485_4 connected to wiring SAP or wiring SAN. The wiring SAP or wiring SAN is a wiring that provides VDD or VSS. The transistors 485_1 to 485_4 are transistors that form an inverter loop.

Furthermore, Figure 15D shows a circuit block diagram corresponding to the sense amplifier 446 described in Figure 15C etc. As shown in Figure 15D, the sense amplifier 446 may be represented as a block in drawings etc.

Figure 16 is a circuit diagram of the memory device 480 in Figure 13. Figure 16 illustrates the circuit blocks described in Figures 15A to 15D.

As shown in FIG. 16, the layer 470 including the element layer 430[m] has a memory cell 432. The memory cell 432 shown in FIG. 16 is connected to a pair of wirings BL[1] and BLB[1], or wirings BL[2] and BLB[2], for example. The memory cell 432 connected to wiring BL is a memory cell to which data is written or read.

Wiring BL[1] and wiring BLB[1] are connected to sense amplifier 446[1], and wiring BL[2] and wiring BLB[2] are connected to sense amplifier 446[2]. Sense amplifier 446[1] and sense amplifier 446[2] can read data in response to the various signals described in Figure 15C.

This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.

(Embodiment 4)
In this embodiment, a structural example of a display device to which a transistor of one embodiment of the present invention can be applied will be described.

Since the transistor of one embodiment of the present invention can be made extremely small, a display device to which the transistor of one embodiment of the present invention is applied can be a display device with extremely high resolution. For example, the display device of one embodiment of the present invention can be used in the display portion of information terminals (wearable devices) such as wristwatches and bracelets, as well as in the display portion of head-mounted displays (HMDs), VR devices such as head-mounted displays, and glasses-type AR devices.

In a display device according to one embodiment of the present invention, a driver circuit and a pixel circuit can be provided so as to overlap each other. In this case, the transistor in which a channel is formed in a single crystal substrate, as exemplified in Embodiment 1, can be used as a transistor constituting the driver circuit, and the transistor in which a channel is formed in a single crystal oxide semiconductor can be used as a transistor constituting the pixel.

[Display module]
17A shows a perspective view of the display module 580. The display module 580 includes a display device 500A and an FPC 590.

Display module 580 has substrate 591 and substrate 592. Display module 580 has display unit 581. Display unit 581 is an area that displays images.

Figure 17B shows a perspective view that schematically illustrates the configuration on the substrate 591 side. Stacked on the substrate 591 are a circuit section 582, a pixel circuit section 583 on the circuit section 582, and a pixel section 584 on the pixel circuit section 583. A terminal section 585 for connecting to the FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel section 584. The terminal section 585 and the circuit section 582 are electrically connected by a wiring section 586 that is composed of multiple wirings.

The pixel section 584 has a plurality of periodically arranged pixels 584a. An enlarged view of one pixel 584a is shown on the right side of Figure 17B. The pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

The pixel circuit section 583 has a plurality of pixel circuits 583a arranged periodically. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices in one pixel 584a. One pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device. For example, the pixel circuit 583a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitance element per light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

The circuit portion 582 has a circuit that drives each pixel circuit 583a in the pixel circuit portion 583. For example, it preferably has one or both of a gate line driver circuit and a source line driver circuit. In addition, it may have at least one of an arithmetic circuit, a memory circuit, a power supply circuit, etc. Furthermore, a transistor provided in the circuit portion 582 may constitute part of the pixel circuit 583a. In other words, the pixel circuit 583a may be composed of a transistor included in the pixel circuit portion 583 and a transistor included in the circuit portion 582.

The FPC 590 functions as wiring for supplying video signals, power supply potential, etc. from the outside to the circuit section 582. An IC may also be mounted on the FPC 590.

The display module 580 can be configured such that one or both of the pixel circuit unit 583 and the circuit unit 582 are overlapped below the pixel unit 584, thereby enabling the aperture ratio (effective display area ratio) of the display unit 581 to be extremely high. For example, the aperture ratio of the display unit 581 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 584a can be arranged at an extremely high density, enabling the resolution of the display unit 581 to be extremely high. For example, it is preferable that the pixels 584a be arranged in the display unit 581 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

Because such a display module 580 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration in which the display section of the display module 580 is viewed through lenses, the display module 580 has an extremely high-resolution display section 581, so even if the display section is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 580 is not limited to this, and can be suitably used in electronic devices with relatively small displays. For example, it can be suitably used in the display section of wearable electronic devices such as wristwatches.

[Display device 500A]
The display device 500A shown in FIG. 18 includes a substrate 301, a light emitting element 110R, a light emitting element 110G, a light emitting element 110B, a capacitor 540, a transistor 310, and a transistor 320.

Transistor 310 corresponds to transistor 50, which is illustrated in embodiment 1 and has a channel formed in a single crystal substrate. Transistor 320 corresponds to transistor 10 or transistor 200, which is illustrated in embodiment 1 and embodiment 2 and has a channel formed in a single crystal oxide semiconductor. Any of the various transistors illustrated in embodiment 2 can be used as transistor 320.

Transistor 310 is a transistor that has a channel formation region in substrate 301. Substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. Transistor 310 has a part of substrate 301, conductive layer 311, low-resistance region 312, insulating layer 313, and insulating layer 314. Conductive layer 311 functions as a gate electrode. Insulating layer 313 is located between substrate 301 and conductive layer 311 and functions as a gate insulating layer. Low-resistance region 312 is a region in which impurities are doped into substrate 301, and functions as either a source or a drain. Insulating layer 314 is provided to cover the side surface of conductive layer 311.

In addition, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301.

The transistor 320 has a semiconductor layer 351, an insulating layer 353, a conductive layer 354, a pair of conductive layers 355, an insulating layer 360, and a conductive layer 357.

Wiring layer 371 and wiring layer 361 are provided between the layer in which transistor 310 is provided and the layer in which transistor 320 is provided. Wiring layer 371 has at least an insulating layer 372 at the top and a conductive layer 373 embedded in insulating layer 372. Wiring layer 361 has at least an insulating layer 362 at the bottom and a conductive layer 363 embedded in insulating layer 362. Display device 500A is manufactured by bonding between wiring layer 361 and wiring layer 371. That is, insulating layer 372, conductive layer 373, insulating layer 362, and conductive layer 363 each have a bonding surface. By connecting conductive layer 363 and conductive layer 373, transistor 310 and transistor 320 can be electrically connected via various wirings.

The layered structure from insulating layer 360 to wiring layer 361 is formed in order from the insulating layer 360 side, and then the surface of wiring layer 361 is used as the bonding surface and bonded to substrate 301. Therefore, the layered structure from insulating layer 360 to wiring layer 361 is upside down relative to transistor 310, etc.

Transistor 320 is sandwiched between insulating layers 352 and 359. Insulating layers 352 and 359 preferably have barrier properties against hydrogen and oxygen, respectively. This prevents impurities from diffusing into transistor 320 and oxygen from being released from semiconductor layer 351. For insulating layers 352 and 359, films that are less susceptible to hydrogen or oxygen diffusion than silicon oxide films, such as aluminum oxide films, hafnium oxide films, and silicon nitride films, can be used.

An insulating layer 356 and a conductive layer 357 embedded in the insulating layer 356 are provided closer to the substrate 301 than the insulating layer 352. An insulating layer 360 is provided between the conductive layer 357 and the semiconductor layer 351. The conductive layer 357 functions as the second gate electrode of the transistor 320, and part of the insulating layer 360 functions as the second gate insulating layer.

The insulating layer 360 contacts the semiconductor layer 351. The insulating layer 360 can correspond to the substrate 11 or the base film 12. Alternatively, the insulating layer 360 may be an insulating film separate from the substrate 11 and the base film 12. Note that if the substrate 11 is used for the insulating layer 360 and it is difficult to reduce its thickness, a configuration without a back gate may be used.

The semiconductor layer 351 is provided on the substrate 301 side of the insulating layer 360. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film that exhibits semiconductor characteristics. A pair of conductive layers 355 is provided in contact with the semiconductor layer 351 and functions as a source electrode and a drain electrode.

Insulating layers 358 and 350 are provided to cover the pair of conductive layers 355 and the semiconductor layer 351. The insulating layer 358 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and prevents oxygen from being released from the semiconductor layer 351. The insulating layer 358 can be made of an insulating film similar to the insulating layer 352. The insulating layer 350 functions as an interlayer insulating layer.

Openings are provided in insulating layer 358 and insulating layer 350, reaching semiconductor layer 351. An insulating layer 353 in contact with the top surface of semiconductor layer 351 and a conductive layer 354 are buried inside the openings. The conductive layer 354 functions as a first gate electrode, and the insulating layer 353 functions as a first gate insulating layer.

The top surfaces (surfaces facing the substrate 301) of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are planarized so that they are at the same or approximately the same height, and an insulating layer 359 is provided to cover them. The insulating layer 359 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 320. The insulating layer 359 can be made of an insulating film similar to the insulating layer 352 described above.

Transistor 320 has a configuration in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the transistor may be driven by supplying the same signal to them. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential to one of the two gates for controlling the threshold voltage and a potential to the other for driving.

Insulating layer 565 is provided covering insulating layer 359. Insulating layer 565 functions as an interlayer insulating layer.

A plug 575 electrically connected to one side of the conductive layer 355 is provided so as to be embedded in the insulating layer 565, the insulating layer 359, the insulating layer 350, and the insulating layer 358. Here, the plug 575 preferably has a conductive layer 575a that covers the side surfaces of the opening in the insulating layer 565, etc., and a portion of the conductive layer 355, and a conductive layer 575b that contacts the conductive layer 575a. In this case, it is preferable to use a conductive material that is difficult for oxygen to diffuse into as the conductive layer 575a.

A conductive layer 364 is provided on the substrate 301 side of the insulating layer 565. A plug 575 connects the conductive layer 355 and the conductive layer 364.

Furthermore, capacitor 540 is provided on insulating layer 564. Capacitor 540 has conductive layer 541, conductive layer 545, and insulating layer 543 located between them. Conductive layer 541 functions as one electrode of capacitor 540, conductive layer 545 functions as the other electrode of capacitor 540, and insulating layer 543 functions as a dielectric of capacitor 540.

The conductive layer 541 is embedded in an insulating layer 554 provided on the insulating layer 564. The conductive layer 541 is electrically connected to the conductive layer 364 via a plug 574. The insulating layer 543 is provided to cover the conductive layer 541. The conductive layer 545 is provided in a region that overlaps with the conductive layer 541 via the insulating layer 543. The conductive layer 541 is connected to the conductive layer 355 of the transistor 320 via the plug 574, the conductive layer 364, and the plug 575.

Plug 574 is embedded in insulating layer 564, insulating layer 352, insulating layer 356, insulating layer 358, insulating layer 350, insulating layer 359, and insulating layer 565, and includes conductive layer 574a and conductive layer 574b. Conductive layer 574a is preferably made of a conductive material that is resistant to oxygen diffusion.

An insulating layer 555a is provided covering the capacitor 540, an insulating layer 555b is provided on the insulating layer 555a, and an insulating layer 555c is provided on the insulating layer 555b.

Insulating layers 555a, 555b, and 555c can each preferably be made of an inorganic insulating film. For example, it is preferable to use silicon oxide films for insulating layers 555a and 555c, and a silicon nitride film for insulating layer 555b. This allows insulating layer 555b to function as an etching protection film. This embodiment shows an example in which part of insulating layer 555c is etched to form a recess, but insulating layer 555c does not necessarily have to have a recess.

Light-emitting elements 110R, 110G, and 110B are provided on insulating layer 555c.

Light-emitting element 110R has pixel electrode 111R, organic layer 112R, common layer 114, and common electrode 113. Light-emitting element 110G has pixel electrode 111G, organic layer 112G, common layer 114, and common electrode 113. Light-emitting element 110B has pixel electrode 111B, organic layer 112B, common layer 114, and common electrode 113. Common layer 114 and common electrode 113 are provided in common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B.

Organic layer 112R of light-emitting element 110R contains a light-emitting organic compound that emits at least red light. Organic layer 112G of light-emitting element 110G contains a light-emitting organic compound that emits at least green light. Organic layer 112B of light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. Organic layer 112R, organic layer 112G, and organic layer 112B can each be referred to as an EL layer, and each contains at least a layer (light-emitting layer) that contains a light-emitting organic compound.

In display device 500A, a separate light-emitting device is created for each emitted color, resulting in little change in chromaticity between light emitted at low and high brightness. Furthermore, because organic layers 112R, 112G, and 112B are spaced apart from each other, crosstalk between adjacent subpixels can be suppressed even in high-resolution display panels. This makes it possible to achieve a display panel that is both high-resolution and has high display quality.

Insulating layer 125, resin layer 126, and layer 128 are provided in the area between adjacent light-emitting elements.

Pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to conductive layer 355 of transistor 320 via plug 556 embedded in insulating layers 555a, 555b, and 555c, conductive layer 541 embedded in insulating layer 554, and plug 574. The height of the top surface of insulating layer 555c and the height of the top surface of plug 556 are the same or approximately the same. Various conductive materials can be used for the plug.

In addition, a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B. A substrate 170 is bonded to the protective layer 121 by an adhesive layer 171.

There is no insulating layer covering the top edge of each of the two adjacent pixel electrodes 111. This allows the distance between adjacent light-emitting elements to be extremely narrow. This allows for a high-definition or high-resolution display device.

This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.

Fifth Embodiment
In this embodiment, a structural example of a display device that can be used for a display device manufactured using a transistor of one embodiment of the present invention will be described. The display device exemplified below can be used for the pixel portion 584 in Embodiment 4, for example.

In one embodiment of the present invention, the EL layer is processed into a fine pattern by photolithography without using a shadow mask such as a fine metal mask (FMM). This makes it possible to realize a display device with high definition and a large aperture ratio, which has been difficult to achieve until now. Furthermore, because the EL layer can be produced separately, it is possible to realize a display device that is extremely vivid, has high contrast, and has high display quality. Note that, for example, the EL layer may be processed into a fine pattern using both a metal mask and photolithography.

Furthermore, part or all of the EL layer can be physically separated. This makes it possible to suppress leakage current between light-emitting elements via a layer shared between adjacent light-emitting elements (also called a common layer). This makes it possible to prevent crosstalk caused by unintended light emission, and realize a display device with extremely high contrast. In particular, it makes it possible to realize a display device with high current efficiency at low luminance.

One embodiment of the present invention can also be a display device that combines a white-emitting light-emitting element with a color filter. In this case, light-emitting elements provided in pixels (sub-pixels) that emit light of different colors can each have the same configuration, and all layers can be common layers. Furthermore, part or all of each EL layer can be separated by photolithography. This suppresses leakage current through the common layer, making it possible to realize a display device with high contrast. In particular, in an element having a tandem structure in which multiple light-emitting layers are stacked via a highly conductive intermediate layer, leakage current through the intermediate layer can be effectively prevented, making it possible to realize a display device that combines high brightness, high definition, and high contrast.

When the EL layer is processed using photolithography, part of the light-emitting layer may be exposed, which may lead to deterioration. For this reason, it is preferable to provide an insulating layer that covers at least the side surfaces of the island-shaped light-emitting layers. The insulating layer may also be configured to cover part of the top surface of the island-shaped EL layer. For the insulating layer, it is preferable to use a material that has barrier properties against water and oxygen. For example, an inorganic insulating film that does not easily diffuse water or oxygen can be used. This suppresses deterioration of the EL layer and enables the realization of a highly reliable display device.

Furthermore, there is a region (recess) between two adjacent light-emitting elements where the EL layer of either light-emitting element is not provided. If a common electrode, or a common electrode and common layer, is formed to cover this recess, a phenomenon occurs in which the common electrode is separated by a step at the edge of the EL layer (also known as a step disconnection), and the common electrode on the EL layer may become insulated. Therefore, it is preferable to use a configuration in which the local step located between two adjacent light-emitting elements is filled with a resin layer that functions as a planarizing film (also known as LFP: Local Filling Planarization). This resin layer functions as a planarizing film. This suppresses step disconnection of the common layer or common electrode, making it possible to realize a highly reliable display device.

Below, a more specific configuration example of a display device according to one embodiment of the present invention will be described with reference to the drawings.

[Configuration Example 1]
19A is a schematic top view of a display device 100 according to one embodiment of the present invention. The display device 100 includes a plurality of red light-emitting elements 110R, a plurality of green light-emitting elements 110G, and a plurality of blue light-emitting elements 110B over a substrate 101. In FIG. 19A , the light-emitting regions of the light-emitting elements are labeled with R, G, and B to easily distinguish the light-emitting elements from one another.

Light-emitting elements 110R, 110G, and 110B are each arranged in a matrix. Figure 19A shows a so-called stripe arrangement, in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement method for the light-emitting elements is not limited to this, and arrangement methods such as an S-stripe arrangement, a delta arrangement, a Bayer arrangement, or a zigzag arrangement may also be used, and a pentile arrangement, diamond arrangement, etc. may also be used.

As light-emitting elements 110R, 110G, and 110B, it is preferable to use, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode). Examples of light-emitting materials that EL elements have include fluorescent materials, phosphorescent materials, and thermally activated delayed fluorescence (TADF materials). As light-emitting materials that EL elements have, not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used.

FIG. 19A also shows a connection electrode 111C that is electrically connected to the common electrode 113. A potential (e.g., an anode potential or a cathode potential) is applied to the connection electrode 111C to be supplied to the common electrode 113. The connection electrode 111C is provided outside the display area where the light-emitting elements 110R and the like are arranged.

The connection electrode 111C can be provided along the periphery of the display area. For example, it may be provided along one side of the periphery of the display area, or it may be provided across two or more sides of the periphery of the display area. In other words, if the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be strip-shaped (rectangular), L-shaped, U-shaped (square bracket shaped), square, or the like.

FIGS. 19B and 19C are schematic cross-sectional views corresponding to dashed dotted lines A1-A2 and A3-A4 in FIG. 19A, respectively. FIG. 19B shows a schematic cross-sectional view of light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B, and FIG. 19C shows a schematic cross-sectional view of connection portion 140 where connection electrode 111C and common electrode 113 are connected.

Light-emitting element 110R has pixel electrode 111R, organic layer 112R, common layer 114, and common electrode 113. Light-emitting element 110G has pixel electrode 111G, organic layer 112G, common layer 114, and common electrode 113. Light-emitting element 110B has pixel electrode 111B, organic layer 112B, common layer 114, and common electrode 113. Common layer 114 and common electrode 113 are provided in common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B.

Organic layer 112R of light-emitting element 110R contains a light-emitting organic compound that emits at least red light. Organic layer 112G of light-emitting element 110G contains a light-emitting organic compound that emits at least green light. Organic layer 112B of light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. Organic layer 112R, organic layer 112G, and organic layer 112B can each be referred to as an EL layer, and each contains at least a layer (light-emitting layer) that contains a light-emitting organic compound.

Hereinafter, when describing matters common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B, they may be referred to as light-emitting element 110. Similarly, when describing matters common to components distinguished by letters, such as organic layer 112R, organic layer 112G, and organic layer 112B, they may be described using symbols without the letters.

The organic layer 112 and the common layer 114 can each independently have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the organic layer 112 can have a layered structure of, from the pixel electrode 111 side, a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer, and the common layer 114 can have an electron injection layer.

Pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are each provided for each light-emitting element. Common electrode 113 and common layer 114 are provided as a continuous layer common to each light-emitting element. A conductive film that is translucent to visible light is used for either each pixel electrode or common electrode 113, and a conductive film that is reflective is used for the other. Making each pixel electrode translucent and the common electrode 113 reflective can result in a bottom-emission display device. Conversely, making each pixel electrode reflective and the common electrode 113 translucent can result in a top-emission display device. Making both each pixel electrode and common electrode 113 translucent can also result in a dual-emission display device.

A protective layer 121 is provided on the common electrode 113, covering the light-emitting elements 110R, 110G, and 110B. The protective layer 121 prevents impurities such as water from diffusing from above into each light-emitting element.

It is preferable that the edge of the pixel electrode 111 has a tapered shape. If the edge of the pixel electrode 111 has a tapered shape, the organic layer 112 provided along the edge of the pixel electrode 111 can also be tapered. By tapering the edge of the pixel electrode 111, the coverage of the organic layer 112 provided over the edge of the pixel electrode 111 can be improved. In addition, tapering the side surface of the pixel electrode 111 makes it easier to remove foreign matter (for example, dust or particles) during the manufacturing process by processes such as cleaning, which is preferable.

For example, it is preferable to have an area where the angle between the inclined side surface and the substrate surface (also called the taper angle) is less than 90°.

The organic layer 112 is processed into an island shape using photolithography. As a result, the angle between the top surface and the side surface of the organic layer 112 at its edges is close to 90 degrees. On the other hand, organic films formed using FMM (Fine Metal Mask) or the like tend to become gradually thinner the closer they are to the edges. For example, the top surface is formed in a sloped shape over a range of 1 μm to 10 μm all the way to the edges, making it difficult to distinguish between the top surface and the side surface.

Between two adjacent light-emitting elements are an insulating layer 125, a resin layer 126, and a layer 128.

Between two adjacent light-emitting elements, the side surfaces of the organic layers 112 face each other with a resin layer 126 sandwiched between them. The resin layer 126 is located between the two adjacent light-emitting elements and is provided so as to fill the ends of each organic layer 112 and the area between the two organic layers 112. The resin layer 126 has a smooth, convex upper surface, and a common layer 114 and a common electrode 113 are provided covering the upper surface of the resin layer 126.

The resin layer 126 functions as a planarization film that fills in the step between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent the common electrode 113 from being separated by the step at the edge of the organic layer 112 (also known as step disconnection), which would otherwise result in insulation of the common electrode on the organic layer 112. The resin layer 126 can also be referred to as an LFP (Local Filling Planarization) layer.

An insulating layer containing an organic material can be suitably used as the resin layer 126. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of these resins can be used as the resin layer 126. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used as the resin layer 126.

In addition, a photosensitive resin can be used as the resin layer 126. Photoresist can also be used as the photosensitive resin. The photosensitive resin can be a positive-type material or a negative-type material.

The resin layer 126 may contain a material that absorbs visible light. For example, the resin layer 126 itself may be made of a material that absorbs visible light, or the resin layer 126 may contain a pigment that absorbs visible light. The resin layer 126 may be, for example, a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light, or a resin that contains carbon black as a pigment and functions as a black matrix.

The insulating layer 125 is provided in contact with the side surface of the organic layer 112. The insulating layer 125 is also provided to cover the upper end portion of the organic layer 112. A portion of the insulating layer 125 is also provided in contact with the upper surface of the substrate 101.

The insulating layer 125 is located between the resin layer 126 and the organic layer 112, and functions as a protective film to prevent the resin layer 126 from coming into contact with the organic layer 112. If the organic layer 112 and the resin layer 126 come into contact, the organic layer 112 may be dissolved by the organic solvent used in forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, it is possible to protect the side surfaces of the organic layer 112.

The insulating layer 125 can be an insulating layer containing an inorganic material. For example, inorganic insulating films such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film can be used for the insulating layer 125. The insulating layer 125 can have a single-layer structure or a stacked structure. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, indium gallium zinc oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, and tantalum oxide films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Examples of nitride oxide insulating films include silicon nitride oxide films and aluminum nitride oxide films. In particular, by using inorganic insulating films such as metal oxide films, such as aluminum oxide films and hafnium oxide films, or silicon oxide films formed by the ALD method as the insulating layer 125, an insulating layer 125 with few pinholes and excellent protection of the EL layer can be formed.

The insulating layer 125 can be formed by sputtering, CVD, PLD, ALD, or other methods. It is preferable to form the insulating layer 125 using the ALD method, which has good coverage.

Furthermore, a reflective film (for example, a metal film containing one or more selected from the group consisting of silver, palladium, copper, titanium, and aluminum) may be provided between the insulating layer 125 and the resin layer 126, and the light emitted from the light-emitting layer may be reflected by the reflective film. This can improve the light extraction efficiency.

Layer 128 is a portion of a protective layer (also called a mask layer or sacrificial layer) that protects organic layer 112 when it is etched. Layer 128 can be made of the same material as that used for insulating layer 125. It is particularly preferable to use the same material for layer 128 and insulating layer 125, as this allows the use of common processing equipment, etc.

In particular, inorganic insulating films such as aluminum oxide films, metal oxide films such as hafnium oxide films, or silicon oxide films formed by the ALD method have few pinholes, making them excellent at protecting the EL layer and suitable for use in insulating layer 125 and layer 128.

The protective layer 121 can have, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of inorganic insulating films include oxide or nitride films such as silicon oxide film, silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, aluminum oxynitride film, and hafnium oxide film. Alternatively, the protective layer 121 may be made of a semiconductor or conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide.

The protective layer 121 can also be a laminated film of an inorganic insulating film and an organic insulating film. For example, it is preferable to have a configuration in which an organic insulating film is sandwiched between a pair of inorganic insulating films. Furthermore, it is preferable that the organic insulating film functions as a planarizing film. This makes it possible to make the upper surface of the organic insulating film flat, improving the coverage of the inorganic insulating film on top of it and increasing the barrier properties. Furthermore, since the upper surface of the protective layer 121 is flat, when a structure (e.g., a color filter, a touch sensor electrode, or a lens array) is provided above the protective layer 121, this is preferable because it reduces the impact of uneven shapes caused by the structure below.

Figure 19C shows a connection portion 140 where the connection electrode 111C and the common electrode 113 are electrically connected. In the connection portion 140, an opening is provided in the insulating layer 125 and the resin layer 126 above the connection electrode 111C. The connection electrode 111C and the common electrode 113 are electrically connected through this opening.

Note that while Figure 19C shows connection portion 140 electrically connecting connection electrode 111C and common electrode 113, common electrode 113 may also be provided on connection electrode 111C via common layer 114. In particular, when a carrier injection layer is used for common layer 114, the electrical resistivity of the material used for common layer 114 is sufficiently low and it can be formed thin, so there are often no problems even if common layer 114 is located at connection portion 140. This allows common electrode 113 and common layer 114 to be formed using the same shielding mask, thereby reducing manufacturing costs.

[Configuration Example 2]
The following describes a display device that has a configuration that is partially different from that of the above-described Configuration Example 1. Note that parts that are common to the above-described Configuration Example 1 will be referred to, and descriptions thereof may be omitted.

Figure 20A shows a schematic cross-sectional view of display device 100a. Display device 100a differs from display device 100 above mainly in that it has a different configuration of light-emitting elements and in that it has a colored layer.

The display device 100a has a light-emitting element 110W that emits white light. The light-emitting element 110W has a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113. The organic layer 112W emits white light. For example, the organic layer 112W can be configured to include two or more light-emitting materials whose emitted light colors are complementary to each other. For example, the organic layer 112W can be configured to include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. It may also be configured to include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.

The organic layers 112W are separated between two adjacent light-emitting elements 110W. This makes it possible to suppress leakage current flowing between adjacent light-emitting elements 110W via the organic layers 112W, thereby suppressing crosstalk caused by this leakage current. This makes it possible to realize a display device with high contrast and color reproducibility.

An insulating layer 122 that functions as a planarizing film is provided on the protective layer 121, and colored layers 116R, 116G, and 116B are provided on the insulating layer 122.

The insulating layer 122 can be an organic resin film or an inorganic insulating film with a flattened top surface. The insulating layer 122 forms the surface on which the colored layers 116R, 116G, and 116B are formed. Therefore, a flat top surface of the insulating layer 122 allows the thickness of the colored layers 116R and others to be uniform, thereby improving color purity. However, if the thickness of the colored layers 116R and others is uneven, the amount of light absorption will vary depending on the location of the colored layer 116R, which could result in a decrease in color purity.

[Configuration Example 3]
FIG. 20B shows a schematic cross-sectional view of the display device 100b.

Light-emitting element 110R has a pixel electrode 111, a conductive layer 115R, an organic layer 112W, and a common electrode 113. Light-emitting element 110G has a pixel electrode 111, a conductive layer 115G, an organic layer 112W, and a common electrode 113. Light-emitting element 110B has a pixel electrode 111, a conductive layer 115B, an organic layer 112W, and a common electrode 113. Conductive layer 115R, conductive layer 115G, and conductive layer 115B are each translucent and function as optical adjustment layers.

By using a film that reflects visible light for the pixel electrode 111 and a film that is both reflective and transparent to visible light for the common electrode 113, a microresonator (microcavity) structure can be realized. In this case, by adjusting the thicknesses of conductive layer 115R, conductive layer 115G, and conductive layer 115B to achieve the optimal optical path length, even when an organic layer 112 that emits white light is used, it is possible to obtain light of different wavelengths that are intensified from light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B.

Furthermore, colored layers 116R, 116G, and 116B are provided on the optical paths of light-emitting elements 110R, 110G, and 110B, respectively, thereby enabling light with high color purity to be obtained.

In addition, an insulating layer 123 is provided to cover the edges of the pixel electrode 111 and the conductive layer 115. The edges of the insulating layer 123 preferably have a tapered shape. By providing the insulating layer 123, it is possible to improve the coverage of the organic layer 112W, common electrode 113, protective layer 121, and the like that are formed on top of it.

The organic layer 112W and the common electrode 113 are each provided as a continuous film common to each light-emitting element. This configuration is preferable because it significantly simplifies the manufacturing process of the display device.

Here, it is preferable that the edges of the pixel electrode 111 are nearly vertical. This allows for the formation of steeply inclined portions on the surface of the insulating layer 123, and makes it possible to form thin portions in the organic layer 112W that covers these portions, or to separate portions of the organic layer 112W. This makes it possible to suppress leakage current that occurs between adjacent light-emitting elements through the organic layer 112W, without processing the organic layer 112W using photolithography or the like.

The above is an explanation of an example configuration of a display device.

This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.

(Embodiment 6)
In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

The electronic device of this embodiment has a display panel (display device) in which the transistor of one embodiment of the present invention is used in a display portion. The display device of one embodiment of the present invention can easily achieve high definition and high resolution and can also achieve high display quality. Therefore, the display device can be used in the display portion of a variety of electronic devices.

Electronic devices include, for example, electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

In particular, the display panel of one embodiment of the present invention can achieve high resolution and is therefore suitable for use in electronic devices with relatively small display areas. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

The display panel of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display panel of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display panel having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, there is no particular limitation on the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention. For example, the display panel can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

The electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).

The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

An example of a wearable device that can be worn on the head will be described using Figures 21A to 21D. These wearable devices have one or both of the functions of displaying AR content and VR content. Note that these wearable devices may also have the function of displaying SR or MR content in addition to AR and VR. By having an electronic device have the function of displaying at least one of AR, VR, SR, and MR content, it is possible to enhance the user's sense of immersion.

Electronic device 700A shown in FIG. 21A and electronic device 700B shown in FIG. 21B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

A display panel according to one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can display images with extremely high resolution.

Electronic device 700A and electronic device 700B can each project an image displayed on display panel 751 onto display area 756 of optical element 753. Because optical element 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visible through optical element 753. Therefore, electronic device 700A and electronic device 700B are each electronic devices capable of AR display.

Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing images in front of them as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

The communication unit has a wireless communication device, which can supply video signals, etc. Note that instead of or in addition to the wireless communication device, a connector may be provided to which a cable through which a video signal and power supply potential can be connected.

In addition, electronic device 700A and electronic device 700B are equipped with batteries that can be charged wirelessly, wired, or both.

The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting when the outer surface of the housing 721 is touched. The touch sensor module can detect tapping or sliding operations by the user and perform various processes. For example, a tapping operation can perform processes such as pausing or resuming a video, and a sliding operation can perform processes such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can expand the range of operations available.

A variety of touch sensors can be used as touch sensor modules. For example, various types can be used, such as capacitance, resistive film, infrared, electromagnetic induction, surface acoustic wave, and optical types. In particular, it is preferable to use capacitance or optical sensors in touch sensor modules.

When using an optical touch sensor, a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light-receiving device (also called a light-receiving element). The active layer of the photoelectric conversion device can be made of either or both an inorganic semiconductor and an organic semiconductor.

Electronic device 800A shown in FIG. 21C and electronic device 800B shown in FIG. 21D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of attachment units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

A display panel according to one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided. This allows the user to feel a high sense of immersion.

The display unit 820 is provided inside the housing 821 in a position that can be seen through the lens 832. Also, by displaying different images on the pair of display units 820, it is possible to perform a three-dimensional display using parallax.

Electronic device 800A and electronic device 800B can each be considered electronic devices for VR. A user wearing electronic device 800A or electronic device 800B can view the image displayed on display unit 820 through lens 832.

Electronic device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. They also preferably have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.

The attachment unit 823 allows the user to wear the electronic device 800A or electronic device 800B on the head. Note that in Figure 21C and other figures, the attachment unit 823 is shown shaped like the temples of glasses, but is not limited to this. The attachment unit 823 may be shaped like a helmet or band, for example, as long as it can be worn by the user.

The imaging unit 825 has the function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Multiple cameras may also be provided to accommodate multiple angles of view, such as telephoto and wide-angle.

Note that while an example having an imaging unit 825 has been shown here, it is also possible to provide a distance measuring sensor (hereinafter also referred to as a detection unit) that can measure the distance to an object. In other words, the imaging unit 825 is one aspect of the detection unit. The detection unit can be, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging). By using images obtained by the camera and the range image sensor, more information can be obtained, enabling more precise gesture operations.

Electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of display unit 820, housing 821, and wearing unit 823. This allows users to enjoy video and audio simply by wearing electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

Electronic device 800A and electronic device 800B may each have an input terminal. The input terminal can be connected to a cable that supplies video signals from a video output device or the like, and power for charging a battery provided within the electronic device.

The electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, the electronic device 700A shown in FIG. 21A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, the electronic device 800A shown in FIG. 21C has a function of transmitting information to the earphone 750 through the wireless communication function.

Furthermore, the electronic device may have an earphone unit. Electronic device 700B shown in FIG. 21B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be located inside the housing 721 or the attachment unit 723.

Similarly, the electronic device 800B shown in FIG. 21D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be located inside the housing 821 or the attachment unit 823. The earphone unit 827 and the attachment unit 823 may also have magnets. This allows the earphone unit 827 to be fixed to the attachment unit 823 by magnetic force, making storage easier and preferable.

The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have either or both an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. Having an audio input mechanism in the electronic device may give it the functionality of a so-called headset.

As such, electronic devices according to one embodiment of the present invention are suitable for both eyeglass-type devices (such as electronic devices 700A and 700B) and goggle-type devices (such as electronic devices 800A and 800B).

The electronic device 6500 shown in Figure 22A is a portable information terminal that can be used as a smartphone.

The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. The display portion 6502 has a touch panel function. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like. Use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.

A display panel according to one embodiment of the present invention can be applied to the display portion 6502.

Figure 22B is a schematic cross-sectional view of the housing 6501, including the end portion on the microphone 6506 side.

A translucent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

The display panel 6511, optical member 6512, and touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).

In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and an FPC 6515 is connected to this folded back portion. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

A display device according to one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

Figure 22C shows an example of a television device. The television device 7100 has a display unit 7000 built into a housing 7101. In this example, the housing 7101 is supported by a stand 7103.

The television set 7100 shown in FIG. 22C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. The channel and volume can be controlled using the operation keys or touch panel provided on the remote control 7111, and the image displayed on the display portion 7000 can be controlled.

The television device 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. In addition, by connecting to a wired or wireless communication network via the modem, it is possible to carry out one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

FIG. 22D shows an example of a laptop personal computer. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, and the like. A display portion 7000 is incorporated in the housing 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 7000, the control device 7216, and the like. Use of the semiconductor device of one embodiment of the present invention for the control device 7216 is preferable because power consumption can be reduced.

Figures 22E and 22F show an example of digital signage.

The digital signage 7300 shown in FIG. 22E includes a housing 7301, a display unit 7000, and a speaker 7303. It may also include LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

Figure 22F shows digital signage 7400 attached to a cylindrical pillar 7401. Digital signage 7400 has a display unit 7000 that is provided along the curved surface of pillar 7401.

The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more likely it is to catch people's attention, which can increase the advertising effectiveness of, for example, advertising.

Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000, but also allows the user to operate it intuitively. Furthermore, when used to provide information such as route information or traffic information, intuitive operation can improve usability.

Furthermore, as shown in Figures 22E and 22F, it is preferable that the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Furthermore, the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.

It is also possible to have the digital signage 7300 or digital signage 7400 run a game using the screen of the information terminal 7311 or information terminal 7411 as the operating means (controller). This allows an unspecified number of users to simultaneously participate in and enjoy the game.

In Figures 22C to 22F, a display panel of one embodiment of the present invention can be applied to the display portion 7000.

The electronic device shown in Figures 23A to 23G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including the function of sensing, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), a microphone 9008, etc.

The electronic devices shown in Figures 23A to 23G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have a variety of functions. The electronic devices may have multiple display units. They may also have a function to include a camera or the like to capture still images or videos and save them on a recording medium (external or built into the camera), and a function to display the captured images on the display unit.

The details of the electronic devices shown in Figures 23A to 23G are described below.

Figure 23A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as a smartphone, for example. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can also display text and image information on multiple surfaces. Figure 23A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and signal strength. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

Figure 23B is a perspective view showing the mobile information terminal 9102. The mobile information terminal 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of their pocket and decide, for example, whether to answer a call.

Figure 23C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications, such as mobile phone calls, e-mail, document browsing and creation, music playback, internet communication, and computer games. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

Figure 23D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used, for example, as a smart watch (registered trademark). The display surface of the display unit 9001 is curved, allowing display along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversations by communicating with, for example, a wirelessly capable headset. The mobile information terminal 9200 can also perform data transmission and charging with other information terminals via the connection terminal 9006. Charging may be performed by wireless power supply.

Figures 23E to 23G are perspective views showing a foldable mobile information terminal 9201. Figure 23E is a perspective view of the mobile information terminal 9201 in an unfolded state, Figure 23G is a folded state, and Figure 23F is a perspective view of a state in the process of changing from one of Figures 23E and 23G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, allowing for excellent display visibility. The display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.

Seventh Embodiment
In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). The electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

An electronic component or the like to which a semiconductor device of one embodiment of the present invention is applied can be applied to the electronic devices exemplified in Embodiment 6.

[Electronic Components]
FIG. 24A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 24A has a semiconductor device 710 inside a mold 711. FIG. 24A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

Semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716. The memory layer 716 is configured with multiple memory cell arrays stacked on top of each other. The stacked configuration of drive circuit layer 715 and memory layer 716 can be a monolithic stacked configuration. A monolithic stacked configuration allows connections between the layers without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring drive circuit layer 715 and memory layer 716 as a monolithic stacked configuration, it is possible to achieve a so-called on-chip memory configuration, in which memory is formed directly on a processor, for example. An on-chip memory configuration enables faster operation of the interface between the processor and memory.

Furthermore, by configuring the memory on-chip, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also known as memory bandwidth).

Furthermore, it is preferable that the multiple memory cell arrays included in the memory layer 716 are formed using OS transistors and that the multiple memory cell arrays are monolithically stacked. By configuring the multiple memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to achieve a monolithic stack configuration than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stack configuration.

Semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

Next, Figure 24B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.

Electronic component 730 shows an example in which semiconductor device 710 is used as a high bandwidth memory (HBM). Semiconductor device 735 can also be used in integrated circuits such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit), or FPGA (Field Programmable Gate Array).

The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and package substrate 732 may be electrically connected using these through electrodes. In addition, with silicon interposers, TSVs may also be used as through electrodes.

In HBM, many wiring connections are required to achieve a wide memory bandwidth. For this reason, the interposer on which HBM is implemented must have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which HBM is implemented.

Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is less likely. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. It is particularly preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSV, or the like, space is required to accommodate the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may become difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure may also be used that combines a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

A heat sink (heat sink) may also be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. Figure 24B shows an example in which electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[Large computer]
25A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

Figure 25B shows a perspective view of an example of a computer 5620. Computer 5620 has a motherboard 5630. Motherboard 5630 has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to motherboard 5630.

Figure 25C shows an example of a PC card 5621. PC card 5621 is a processing board equipped with, for example, a CPU, GPU, and storage device. PC card 5621 has board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on board 5622. Note that Figure 25C also shows components other than electronic components 5626, 5627, and 5628.

The connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. The connection terminal 5629 may conform to, for example, PCIe.

Connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to PC card 5621, inputting signals, etc. They can also be, for example, interfaces for outputting signals calculated by PC card 5621. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Also, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).

Electronic component 5626 has terminals (not shown) for inputting and outputting signals, and by inserting these terminals into sockets (not shown) provided on board 5622, electronic component 5626 and board 5622 can be electrically connected.

Electronic component 5627 and electronic component 5628 have multiple terminals, and can be mounted to wiring on board 5622 by, for example, reflow soldering the terminals. Examples of electronic component 5627 include FPGAs, GPUs, and CPUs. Electronic component 5627 can be, for example, electronic component 730. Electronic component 5628 can be, for example, a memory device. Electronic component 5628 can be, for example, electronic component 700.

The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.

This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.

In this example, a single-crystal oxide semiconductor film was formed on a single-crystal substrate, and its cross section was observed.

A single-crystal YSZ substrate was used as the single-crystal substrate. Two types of substrates were used here: one with a (111) surface and one with a (100) surface.

An indium oxide film was used as the oxide semiconductor film. Here, an indium oxide film approximately 5 nm thick was deposited on a YSZ substrate using the ALD method. The film was deposited using triethylindium as the precursor and ozone as the oxidizing agent at a substrate temperature of 200°C.

Next, cross-sectional observations were performed on the two types of substrates on which the indium oxide film was formed. Cross-sectional observations were performed using HAADF-STEM.

Figure 26A shows a cross-sectional image of a YSZ substrate with a (111) plane and an indium oxide film ( _denoted as _In2O3 ) formed thereon. It can be seen that the indium oxide film is also crystallized, reflecting the crystal lattice of the YSZ substrate. The crystal orientations of the YSZ substrate and the indium oxide film are shown on the right side of the figure. The cross-sectional image confirms that the crystal orientations of the YSZ substrate and the indium oxide film are consistent.

In addition, a low-contrast layer (referred to as a buffer layer) was confirmed between the YSZ substrate and the indium oxide film.

Figure 26B shows an enlarged view of a portion of Figure 26A. It can be seen that the buffer layer is a two-atom layer. Since the HAADF-STEM method superimposes information not only from the sample surface but also from the depth direction, the buffer layer is observed to have a dark contrast, suggesting the presence of sites where no atoms are present. In other words, the buffer layer can be considered a region with a lower density than other regions.

Next, we will focus on the interatomic distances of the YSZ substrate and the indium oxide film. Figure 26B shows the interatomic distances of the YSZ substrate and the indium oxide film as numerical values. The interatomic distances were averaged over 100 periods within the observation range. The interatomic distances in the YSZ substrate were 0.313 nm in the in-plane direction and 0.300 nm in the thickness direction, which are similar to values for an ideal YSZ single crystal. On the other hand, the interatomic distances in the indium oxide film were 0.313 nm in the in-plane direction and 0.291 nm in the thickness direction. While the thickness direction was similar to that of an ideal indium oxide single crystal, the in-plane direction was larger than that of an ideal single crystal. Therefore, it can be seen that, at least within the range observed in this example, the crystal structure of the indium oxide film was distorted only in the in-plane direction.

Figure 27A shows a cross-sectional image of a YSZ substrate with a (100) surface and an indium oxide film formed thereon. Figure 27B shows an enlarged view of the same. It can be seen that even when the substrate surface is different, indium oxide with good crystallinity is obtained.

Focusing on interatomic distances, the interatomic distance in the YSZ substrate was 0.364 nm in the in-plane direction and 0.258 nm in the thickness direction, which was comparable to that of an ideal single crystal. On the other hand, the interatomic distance in the indium oxide film was 0.364 nm in the in-plane direction and 0.252 nm in the thickness direction. While the thickness direction was comparable to that of an ideal indium oxide single crystal, the in-plane direction was larger. In other words, just as when the substrate surface was a (111) plane, compared to ideal indium oxide single crystal, the indium oxide film was distorted so that the interatomic distance increased in the in-plane direction, but there was almost no distortion in the thickness direction.

Furthermore, when we look at the buffer layer, it is two atomic layers thick when the substrate surface is (111), but one atomic layer thick when the substrate surface is (100). This shows that the amount of stress applied to the indium oxide film to be formed varies depending on the crystal orientation of the substrate, and that this difference is related to the number of layers in the buffer layer. These results suggest that, regarding the surface orientation of the YSZ substrate, the (100) plane provides better matching of the crystal structure with the indium oxide film than the (111) plane.

This example confirmed that a single-crystal oxide semiconductor film can be formed by epitaxially growing an oxide semiconductor film on a single-crystal substrate. It also confirmed that a low-density buffer layer can be formed between the single-crystal substrate and the single-crystal oxide semiconductor film. It was also found that the crystal structure of the single-crystal oxide semiconductor film is distorted to the same extent as the substrate in the in-plane direction to alleviate lattice mismatch with the substrate, but the distortion in the thickness direction is small.

10: transistor, 11: substrate, 11a: substrate, 12: base film, 12a: layer, 15f: element, 15m: element, 15s: element, 16: intermediate layer, 21: semiconductor layer, 21f: semiconductor film, 22: insulating layer, 22f: insulating film, 23: conductive layer, 24: conductive layer, 24f: conductive film, 32: insulating layer, 33a: insulating layer, 33b: insulating layer, 33c: insulating layer, 33d: insulating layer, 50: transistor, 51: substrate, 51c: semiconductor body region, 52: insulating layer, 53: conductive layer, 54: low resistance region, 61a: plug, 61b: plug, 61c: plug, 61d: plug, 71a: conductive layer, 71b: conductive layer, 71c: conductive layer, 71d: conductive layer, 81: element isolation layer, 82: insulating layer, 83a: insulating layer, 83b: insulating layer, 83c: insulating layer, 83d: insulating layer, 100: display device, 100a: display device, 100b: display device, 101: substrate, 110: emitter Optical element, 110B: light-emitting element, 110G: light-emitting element, 110R: light-emitting element, 110W: light-emitting element, 111: pixel electrode, 111B: pixel electrode, 111C: connection electrode, 111G: pixel electrode, 111R: pixel electrode, 112: organic layer, 112B: organic layer, 112G: organic layer, 112R: organic layer, 112W: organic layer, 113: common electrode, 114: common layer, 115: conductive layer, 115B: conductive layer, 115G: conductive layer, 115R: conductive layer, 116B: colored layer, 116G: colored layer, 116R: colored layer, 121: protective layer, 122: insulating layer, 123: insulating layer, 125: insulating layer, 126: resin layer, 128: layer, 140: connecting portion, 170: substrate, 171: adhesive layer, 200: transistor, 201: insulating layer, 202: insulating layer, 205: conductive layer, 230: semiconductor layer, 230f: semiconductor film, 240a: conductive layer, 240b: conductive layer, 241 a: insulating layer, 241b: insulating layer, 242: conductive layer, 242a: conductive layer, 242b: conductive layer, 242f: conductive film, 250: insulating layer, 255: insulating layer, 260: conductive layer, 260a: conductive layer, 260b: conductive layer, 271a: insulating layer, 271b: insulating layer, 275: insulating layer, 280: insulating layer, 282: insulating layer, 283: insulating layer, 285: insulating layer, 301: substrate, 310: transistor, 311: conductive layer, 312: Low resistance region, 313: insulating layer, 314: insulating layer, 315: element isolation layer, 320: transistor, 350: insulating layer, 351: semiconductor layer, 352: insulating layer, 353: insulating layer, 354: conductive layer, 355: conductive layer, 356: insulating layer, 357: conductive layer, 358: insulating layer, 359: insulating layer, 360: insulating layer, 361: wiring layer, 362: insulating layer, 363: conductive layer, 364: conductive layer, 371: wiring layer, 372: insulating layer, 373: conductive layer, 420: layer, 422: peripheral circuit, 430[1]: element layer, 430[2]: element layer, 430[5]: element layer, 430[m]: element layer, 430[m]m: element layer, 430: element layer, 432[1,1]: memory cell, 432[i,j]: memory cell, 432[m,n]: memory cell, 432: memory cell, 437: transistor, 438: capacitance element, 440: driver circuit, 442: row decoder ,443: Row driver, 444: Column decoder, 445: Column driver, 446[1]: Sense amplifier, 446[2]: Sense amplifier, 446: Sense amplifier, 447: Input circuit, 448: Output circuit, 470: Layer, 471: PSW, 472: PSW, 473: Control circuit, 474: Voltage generation circuit, 480: Memory device, 482: Switch circuit, 482_1: Transistor, 482_2: Transistor, 483: precharge circuit, 483_1: transistor, 483_3: transistor, 484: precharge circuit, 484_1: transistor, 484_3: transistor, 485: amplifier circuit, 485_1: transistor, 485_2: transistor, 485_3: transistor, 485_4: transistor, 500A: display device, 540: capacitor, 541: conductive layer, 543: insulating layer, 545: conductive layer, 554: insulating layer, 555a: insulating layer, 555b: insulating layer, 555c: insulating layer, 556: plug, 564: insulating layer, 565: insulating layer, 574: plug, 574a: conductive layer, 574b: conductive layer, 575: plug, 575a: conductive layer, 575b: conductive layer, 580: display module, 581: display section, 582: circuit section, 583: pixel circuit section, 583a: pixel circuit, 584: pixel section, 584a: pixel, 585: terminal Sub-part, 586: wiring part, 590: FPC, 591: substrate, 592: substrate, 700: electronic component, 700A: electronic device, 700B: electronic device, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 721: housing, 723: wearing part, 727: earphone part, 730: electronic component, 7 31: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 750: Earphone, 751: Display panel, 753: Optical member, 756: Display area, 757: Frame, 758: Nose pad, 800A: Electronic device, 800B: Electronic device, 820: Display unit, 821: Housing, 822: Communication unit, 823: Wearing unit, 824: Control unit, 825: Imaging unit, 827: Earphone unit, 832: Lens, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: electronic component, 5627: electronic component, 5628: electronic component, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6 504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6509: Control device, 6510: Protective member, 6511: Display panel, 6512: Optical member, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7000: Display unit, 7100: Television device, 7101: Housing, 7103: Stand, 7111: remote control device, 7200: notebook personal computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7216: control device, 7300: digital signage, 7301: housing, 7303: speaker, 7311: information terminal, 7400: digital signage, 7401: pillar, 7411: information terminal, 9000: housing, 90 01: Display, 9002: Camera, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Mobile information terminal, 9102: Mobile information terminal, 9103: Tablet terminal, 9200: Mobile information terminal, 9201: Mobile information terminal

Claims (10)

a first transistor, a second transistor, a first insulating layer, a second insulating layer, a first single crystal substrate, and a second single crystal substrate;
the first transistor has a channel formed in a first single-crystal semiconductor included in the first single-crystal substrate,
the second transistor is located above the first transistor and has a channel formed in a second single-crystal semiconductor in contact with the second single-crystal substrate;
the second single-crystal substrate is located above the second transistor;
the first insulating layer is located between the first transistor and the second transistor;
the second insulating layer is located between the first insulating layer and the second transistor and has a first junction surface in contact with the first insulating layer;
the first single-crystal semiconductor includes silicon;
the second single crystal semiconductor includes a metal oxide;
Semiconductor device. In claim 1,
the second single crystal substrate has a cubic crystal structure;
the second single crystal semiconductor has a cubic crystal structure;
Semiconductor device. In claim 1,
the second single crystal substrate has an oxide containing yttrium and zirconium;
the second single crystal semiconductor includes indium oxide;
Semiconductor device. In claim 1,
the second single crystal semiconductor has a lattice mismatch of −5% or more and 5% or less with respect to the second single crystal substrate;
Semiconductor device. In claim 1,
a first conductive layer and a second conductive layer;
the first conductive layer is connected to one of a source electrode and a drain electrode of the first transistor and is embedded in the first insulating layer;
the second conductive layer is connected to one of a source electrode and a drain electrode of the second transistor, is embedded in the second insulating layer, and has a second junction surface in contact with the first conductive layer;
Semiconductor device. preparing a first single-crystal substrate including a first single-crystal semiconductor, the first single-crystal substrate including a first transistor and a first insulating layer on the first transistor;
providing a second single crystal substrate;
forming a semiconductor film containing a second single crystal semiconductor on the second single crystal substrate;
a step of processing the semiconductor film into an island shape to form a semiconductor layer;
forming a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on the semiconductor layer to fabricate a second transistor;
forming a second insulating layer over the second transistor;
and joining an upper surface of the first insulating layer to an upper surface of the second insulating layer.
A method for manufacturing a semiconductor device. In claim 6,
the first single-crystal semiconductor includes silicon;
the second single-crystal semiconductor includes a metal oxide;
A method for manufacturing a semiconductor device. In claim 6,
the second single crystal substrate has a cubic crystal structure;
the second single crystal semiconductor has a cubic crystal structure;
A method for manufacturing a semiconductor device. In claim 6,
the second single crystal substrate has an oxide containing yttrium and zirconium;
the second single crystal semiconductor includes indium oxide;
A method for manufacturing a semiconductor device. In claim 6,
the second single crystal semiconductor has a lattice mismatch of −5% or more and 5% or less with respect to the second single crystal substrate;
A method for manufacturing a semiconductor device.