WO2025187276A1 - Display apparatus and electronic device - Google Patents

Abstract

The purpose of the present invention is to provide a display device and an electronic apparatus that make it possible to suppress leakage power, for example.　Provided is a display device having a plurality of circuit blocks that operate at the time of display operation, the plurality of circuit blocks having a first circuit block for which a power supply is controlled to be off at the time of standby. The display device includes, for example, a switch provided between a power supply line of the power supply and the first circuit block, and a control unit for controlling the switch to be off when the standby state and the operation of the first circuit block are unnecessary.

Description

Display devices and electronic devices

This technology relates to display devices and electronic devices.

Technologies for reducing power consumption in display devices are known. For example, Patent Document 1 below discloses a technology that reduces the power consumption of a display IF circuit by configuring the registers of the display IF circuit with non-volatile memory and reducing the number of register accesses after restarting the power supply. Furthermore, Patent Document 2 discloses a technology that performs waveform adjustment processing on the gate waveform when the power is turned on and does not perform waveform adjustment processing when the power is turned off, thereby suppressing the voltage applied to pixels when the power is off.

Meanwhile, Patent Document 3 discloses a technology related to microprocessor power gating, which involves inserting a circuit between blocks to fix the input of the circuit when power is cut off, thereby maintaining the output even when power is stopped, thereby reducing power consumption while suppressing malfunctions and increases in area.

JP 2023-153768 A Japanese Patent Application Laid-Open No. 2015-197484 JP 2012-094171 A

Incidentally, as semiconductor process generations advance, the leakage current of individual transistors tends to increase. Furthermore, as semiconductor processes become more miniaturized and the amount of logic incorporated increases, the leakage current also increases accordingly.

One of the objectives of this technology is to provide, for example, display devices and electronic devices that can suppress leakage power.

This technology is, for example,
It has a plurality of circuit blocks that operate during display operation,
The display device includes a first circuit block whose power supply is controlled to be turned off during standby.

This technology is, for example,
An electronic device having a display device according to the present technology.

FIG. 1 is a diagram showing a schematic configuration example of a display device to which the present technology can be applied. FIG. 2 is a diagram showing an example of the configuration of main power supply paths in a display device according to a comparative example. FIG. 3 is a diagram showing an example of the configuration of main power supply paths of the display device according to the first embodiment. FIG. 4 is a diagram illustrating an example of the configuration of a switch circuit. FIG. 5 is a diagram showing another example of the configuration of the switch circuit. FIG. 6 is a diagram illustrating the layout of the switch circuit. FIG. 7 is a diagram illustrating an example of the configuration of the control circuit. FIG. 8 is a diagram showing another example of the configuration of the control circuit. FIG. 9 is a diagram illustrating an example of the configuration of a display device according to the second embodiment. FIG. 10 is a diagram illustrating the layout of the switch circuit according to the third embodiment. FIG. 11 is a diagram illustrating an example of the configuration of a display device according to the fourth embodiment. FIG. 12 is a diagram illustrating an example of the configuration of a display device according to the fifth embodiment. FIG. 13A shows a plan view of a pixel, and FIG. 13B shows an example of a configuration for dissipating leakage current between pixels. FIG. 14 is a diagram illustrating an example of the configuration of a display device according to the sixth embodiment. FIG. 15 is a conceptual diagram illustrating an example of the configuration of a substrate to which the present technology can be applied. FIG. 16 is a diagram illustrating an example of the configuration of a display device according to the seventh embodiment. FIG. 17 is a diagram showing an example of the configuration of a pixel circuit. FIG. 18 is a diagram showing an example of the configuration of a pixel circuit. FIG. 19 is a diagram showing an example of the configuration of a pixel circuit. FIG. 20 is a diagram showing an example of the configuration of a pixel circuit. FIG. 21 is a diagram showing an example of the configuration of a pixel circuit. FIG. 22 is a diagram showing an example of the configuration of a pixel circuit. FIG. 23 is a diagram showing an example of the configuration of a pixel circuit. FIG. 24 is a diagram showing an example of the configuration of a pixel circuit. FIG. 25 is a diagram showing an example of the configuration of a pixel circuit. FIG. 26 is a perspective view showing an example of the appearance of a head-mounted display. FIG. 27 is a perspective view showing an example of the appearance of another head-mounted display. 28A and 28B are front and rear views showing an example of the external appearance of a digital still camera. FIG. 29 is a perspective view showing an example of the appearance of a television device. FIG. 30 is a perspective view showing an example of the appearance of a smartphone. 31A and 31B are diagrams illustrating an example of the interior of a vehicle viewed from the rear to the front of the vehicle, respectively, and are diagrams illustrating an example of the interior of a vehicle viewed from diagonally rear to diagonally front of the vehicle.

Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be given in the following order. In this specification and the drawings, components having substantially the same functions or configurations are designated by the same reference numerals, and redundant description will be omitted as appropriate. Furthermore, the shapes, sizes, positional relationships, etc. of components shown in each drawing may be exaggerated depending on the content of the description, and hatching, reference numerals, etc. may be omitted.
<1. Overview of this technology>
2. First embodiment
3. Second embodiment
4. Third embodiment
5. Fourth embodiment
6. Fifth embodiment
7. Sixth embodiment
8. Seventh embodiment
9. Example of pixel circuit configuration
10. Modifications
<11. Application Examples>

<1. Overview of this technology>
First, an overview of a display device to which the present technology can be applied will be described. FIG. 1 is a diagram showing a schematic configuration example of a display device to which the present technology can be applied. The display device 1 shown in FIG. 1 is a device that displays images and the like using light-emitting elements. The light-emitting elements are, for example, LEDs (Light Emitting Diodes). LEDs include LEDs used in micro LED displays and OLEDs (Organic Light Emitting Diodes) used in organic EL (Electro-Luminescence) displays. Hereinafter, the display device 1 will be described as employing LEDs as light-emitting elements. The display device 1 is, for example, a display mounted in an electronic device. Specific examples of electronic devices to which the display device 1 can be applied will be described later.

The display device 1 has the following component circuit blocks: an input/output unit (IO) 2, a gamma processing unit 3, a power supply processing unit 4, an interface unit (IF) 5, a timing controller (TCON) 6, a pixel unit 7, a horizontal logic unit (HLOGIC) 8, a horizontal analog unit (HANALOG) 9, a vertical logic unit (VLOGIC) 10, and a vertical analog unit (VANALOG) 11. The display device 1 has these circuit blocks mounted on a substrate, for example. The substrate may include a semiconductor substrate such as silicon.

The input/output unit 2 inputs and outputs various types of data, and is composed of, for example, an externally connectable FPC (Flexible Printed Circuits). The input/output unit 2 is connected to the gamma processing unit 3, power supply processing unit 4, and interface unit 5. The gamma processing unit 3 performs gamma correction processing. The gamma processing unit 3 is connected to the input/output unit 2 and horizontal analog unit 9, and sets gamma correction based on the gamma correction setting values input via the input/output unit 2, and gamma-corrects the pixel signals output from the horizontal analog unit 9 to the pixel unit 7.

The power supply processing unit 4 is a circuit that outputs power to drive the pixel unit 7 and is configured to include, for example, an LDO (Low Drop Out) regulator. The power supply processing unit 4 is connected to the input/output unit 2 and pixel unit 7, and converts the supply power input via the input/output unit 2 into a power supply voltage to drive the pixel unit 7 and supplies it to the pixel unit 7. The interface unit 5 is connected to the input/output unit 2 and timing controller 6. The interface unit 5 is an interface for inputting and outputting image data, etc. to and from the outside via the input/output unit 2. For example, a high-speed interface standard such as MIPI (Mobile Industry Processor Interface) can be used as this interface.

The timing controller 6 controls the operation timing of each circuit block. The timing controller 6 is connected to the interface unit 5, horizontal logic unit 8, horizontal analog unit 9, vertical logic unit 10, and vertical analog unit 11. The timing controller 6 outputs image data input via the input/output unit 2 and interface unit 5 to the horizontal logic unit 8 based on a clock signal supplied from an oscillator unit (not shown in Figure 1) or the like, and outputs signals as needed to the horizontal logic unit 8 and horizontal analog unit 9. The timing controller 6 also outputs signals as needed to the vertical logic unit 10 and vertical analog unit 11 based on the above-mentioned clock signals.

The pixel unit 7, not shown here, has a plurality of pixels (pixel circuits) arranged in a matrix of m rows and n columns (m and n are natural numbers). The pixel unit 7 is provided with pixels that represent the three primary colors of R (red), G (green), and B (blue), for example, and expresses a color image. However, the color expression of the image is not limited to this, and it may also be configured to express, for example, a monochrome (black and white) image. Specific examples of the pixel configuration and operation will be described later.

The pixel section 7 also has signal lines that extend along the column direction of the pixel array, and control lines that extend along the row direction of the pixel array. A signal line is provided for each pixel column, and a control line is provided for each pixel row. The signal lines are each connected to the output terminal of the corresponding column of the horizontal analog section 9 and to the pixel group of the corresponding column. The control lines are each connected to the output terminal of the corresponding row of the vertical analog section 11 and to the pixel group of the corresponding row.

The horizontal logic unit 8 and horizontal analog unit 9 make up the horizontal driver. The horizontal driver can be configured, for example, as a RAMPDAC circuit that uses a ramp waveform analog signal to generate the pixel signals to be output to the signal lines. The horizontal driver is not limited to this, and can also be configured, for example, as a voltage follower circuit that has a voltage follower circuit in the output section to the signal line. The horizontal logic unit 8 distributes the image data input from the timing controller 6 to each signal line. The horizontal analog unit 9 converts the distributed image data into gamma-corrected pixel signals and outputs them to the corresponding signal lines of the pixel unit 7.

The vertical logic unit 10 and vertical analog unit 11 make up the vertical driver. The vertical driver can be configured, for example, as a shift register-type circuit having a shift register circuit in the signal input section. However, the vertical driver is not limited to this and may also be configured, for example, as an address decoder-type circuit having an address decoder in the signal input section. The vertical logic unit 10 generates shift signals for each pixel row from signals input from the timing controller 6. The vertical analog unit 11 uses these shift signals to generate control signals that drive control lines and output them to the pixel unit 7.

This technology relates to power supply control of circuit blocks that make up the display device 1, such as the timing controller 6, horizontal logic unit 8, and vertical logic unit 10.

(Configuration example of a display device of a comparative example)
Before describing power supply control of a display device 1 according to an embodiment of the present technology, a comparative example will be described. Fig. 2 is a diagram showing an example of the configuration of main power supply paths of a display device 1A in the comparative example. Note that the display device 1A in Fig. 2 includes the above-described input/output unit 2, gamma processing unit 3, power supply processing unit 4, interface unit 5, timing controller 6, pixel unit 7, horizontal logic unit 8, horizontal analog unit 9, vertical logic unit 10, and vertical analog unit 11.

The display device 1A has an oscillator 12. The oscillator 12 is composed of, for example, an oscillator, and generates the clock signal described above. The oscillator 12 is connected to the timing controller 6, and the clock signal generated by the oscillator 12 is output to the timing controller 6.

The timing controller 6 has a CLK+EN control unit 211, a timing generator 22, a signal processing unit 23, and a register 24. The circuit blocks of the CLK+EN control unit 211, the timing generator 22, the signal processing unit 23, and the register 24 are each connected to the gamma processing unit 3, the power supply processing unit 4, the interface unit 5, the horizontal logic unit 8, the horizontal analog unit 9, the vertical logic unit 10, and the vertical analog unit 11. The horizontal logic unit 8 is connected to the horizontal analog unit 9, and the vertical logic unit 10 is connected to the vertical analog unit 11.

The CLK+EN control unit 211 controls the clock signals and various enable signals used appropriately in each circuit block. The CLK+EN control unit 211 outputs the clock signal output by the oscillator unit 12 to a predetermined circuit block. The CLK+EN control unit 211 also generates various enable signals and outputs them to a predetermined circuit block. The timing generator 22 controls the operation timing of each circuit block. The timing generator 22 generates signals such as start pulses and outputs them to a predetermined circuit block. The signal processing unit 23 performs signal processing on image data input via the interface unit 5 and outputs the processed image data to the horizontal logic unit 8. This signal processing includes, for example, resolution conversion processing and interpolation of color information for each pixel. The register 24 inputs and outputs data to the signal processing unit 23 via buffers 30 and 31, and stores information processed by the signal processing unit 23.

The display device 1A has power supply lines VDD1IF and VSSIF, power supply lines VDD1 and VSSD, power supply lines VDD2 and VSSA, and power supply lines VCCP and Vcath. Power supply lines VDD1IF and VSSIF are connected to the interface unit 5 and apply a predetermined power supply voltage to the interface unit 5. Power supply lines VDD1 and VSSD are connected to the interface unit 5, oscillator unit 12, CLK+EN control unit 211, timing generator 22, signal processing unit 23, register 24, horizontal logic unit 8, and vertical logic unit 10, and apply a predetermined power supply voltage to each connection block. Power supply lines VDD2 and VSSA are connected to the oscillator unit 12, horizontal analog unit 9, vertical analog unit 11, gamma processing unit 3, and power supply processing unit 4, and apply a predetermined power supply voltage to each connection block. The power supply line VCCP and power supply line Vcath are connected to the pixel unit 7 and apply a predetermined power supply voltage to the pixel unit 7.

The display device 1A is capable of standby operation, which pauses display by the pixel unit 7. This standby state caused by standby operation is a state in which the pixel unit 7 is on standby so that it can immediately display. In the display device 1A of the comparative example, power supply voltage is constantly applied to each circuit block, so even during standby, standby current occurs in each circuit block due to leakage current.

The arrows in Figure 2 represent the main standby current generated during standby. As semiconductor process generations advance, this standby current becomes more pronounced. As semiconductor processes become more miniaturized, an increase in onboard logic can be expected, but this increase in leakage current also leads to an increase in standby power. Increased standby power has a significant impact on battery life, particularly in mobile products. Therefore, the following embodiments aim to suppress this leakage power.

2. First embodiment
3 is a diagram showing an example of the configuration of main power supply paths of the display device 1 according to the first embodiment. The display device 1 shown in FIG. 3 includes an input/output unit 2 (not shown in FIG. 3), a gamma processing unit 3, a power supply processing unit 4, an interface unit 5, a timing controller 6, a pixel unit 7, a horizontal logic unit 8, a horizontal analog unit 9, a vertical logic unit 10, a vertical analog unit 11, and an oscillator unit 12. The oscillator unit 12 is connected to the timing controller 6, and a clock signal generated by the oscillator unit 12 is output to the timing controller 6.

The timing controller 6 has a CLK+EN control unit 21, a timing generator 22, a signal processing unit 23, and a register 24. The circuit blocks of the CLK+EN control unit 21, timing generator 22, signal processing unit 23 (IN), and register 24 are connected to the interface unit 5, horizontal analog unit 9, vertical analog unit 11, gamma processing unit 3, and power supply processing unit 4, respectively. In addition, the signal processing unit 23 (OUT) is connected to the register 24 via the control circuit 50a, and the register 24 is connected to the signal processing unit 23 via a buffer 31.

The signal processing unit 23 (OUT) is connected to the horizontal logic unit 8 (IN) and the vertical logic unit 10 (IN), and is also connected to the horizontal analog unit 9 via a control circuit 50b. The horizontal logic unit 8 (OUT) is connected to the horizontal analog unit 9 via a control circuit 50c, and the vertical logic unit 10 (OUT) is connected to the vertical analog unit 11 via a control circuit 50d. The control circuits 50a to 50d will be described later.

The CLK+EN control unit 21 controls the clock signals and various enable signals used appropriately in each circuit block. The CLK+EN control unit 21 outputs the clock signal output by the oscillator unit 12 to a specified circuit block. The CLK+EN control unit 21 also generates various enable signals and outputs them to a specified circuit block. Note that the CLK+EN control unit 21 differs from the CLK+EN control unit 211 of the comparative example in that it generates and outputs signals used for the power supply control described above.

The timing generator 22 controls the operation timing of each circuit block. The timing generator 22 generates signals such as start pulses and outputs them to specified circuit blocks. The signal processing unit 23 performs signal processing on image data input via the interface unit 5, and outputs the processed image data to the horizontal logic unit 8. The register 24 inputs and outputs signals to and from the signal processing unit 23, and stores information processed by the signal processing unit 23.

The display device 1 has power supply lines VDD1IF and VSSIF, power supply lines VDD1 and VSSD, power supply lines VDD2 and VSSA, and power supply lines VCCP and Vcath. Power supply lines VDD1IF and VSSIF are connected to the interface unit 5 and apply a predetermined power supply voltage (specifically, the power supply voltage for the interface) to the interface unit 5. The potential of power supply line VDD1IF is higher than that of VSSIF.

The power supply lines VDD1 and VSSD are connected to the interface unit 5, oscillator unit 12, CLK+EN control unit 21, timing generator 22, signal processing unit 23, register 24, horizontal logic unit 8, and vertical logic unit 10, and apply a predetermined power supply voltage (specifically, the power supply voltage for digital circuits) to each connection block. However, the power supply line VDD1 is connected to the signal processing unit 23 via the switch circuit 40a, and the power supply voltage is applied to the signal processing unit 23 when the switch circuit 40a is on (conductive state), but not when the switch circuit 40a is off (non-conductive state). Furthermore, the power supply line VDD1 is connected to the horizontal logic unit 8 via the switch circuit 40b, and the power supply voltage is applied to the horizontal logic unit 8 when the switch circuit 40b is on (conductive state), but not when the switch circuit 40b is off (non-conductive state). Furthermore, the power supply line VDD1 is connected to the vertical logic unit 10 via a switch circuit 40c. When the switch circuit 40c is on (conductive), a power supply voltage is applied to the vertical logic unit 10, and when the switch circuit 40c is off (non-conductive), no power supply voltage is applied. The potential of the power supply line VDD1 is higher than that of the power supply line VSSD.

Power supply line VDD2 and power supply line VSSA are connected to the oscillator unit 12, horizontal analog unit 9, vertical analog unit 11, gamma processing unit 3, and power supply processing unit 4, and apply a predetermined power supply voltage (specifically, the power supply voltage for the analog circuits) to each connection block. The potential of power supply line VDD2 is higher than that of power supply line VSSA. Power supply line VCCP and power supply line Vcath are connected to the pixel unit 7, and apply a predetermined power supply voltage (specifically, the power supply voltage for the pixel circuits) to the pixel unit 7. The potential of power supply line VCCP is higher than that of power supply line Vcath.

The display device 1 is capable of standby operation, and during standby, the gamma processing unit 3, power supply processing unit 4, pixel unit 7, horizontal logic unit 8, horizontal analog unit 9, vertical logic unit 10, vertical analog unit 11, and signal processing unit 23 of the timing controller 6 are circuit blocks that do not need to be operated. Among these, the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10 are circuit blocks in the logic area that contain logic circuits, memory, etc., have large circuit scales, and have high leakage currents. Therefore, in this embodiment, the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10 are circuit blocks that are subject to power control (first circuit blocks), and power control is performed by the above-mentioned switch circuits 40a to 40c. Note that, as with the comparative example, all circuit blocks other than the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10 are always powered on (second circuit blocks).

(Example of switch circuit configuration)
FIG. 4 is a diagram showing an example of the configuration of the switch circuit 40a. While the switch circuit 40a connected to the signal processing unit 23 will be described here, the configuration of the switch circuits 40b and 40c is similar. The switch circuit 40a includes a plurality of switches 41(1) to 41(n) and buffers 42(1) to 42(n), each of which constitutes a plurality of delay circuits. The switches 41(1) to 41(n) are, for example, transistors. One end of each of the switches 41(1) to 41(n) is connected to the power supply line VDD1, and the other end is connected to the signal processing unit 23. The control terminals of the switches 41(1) to 41(n) are sequentially connected to the CLK+EN control unit 21 via the buffers 42(1) to 42(n), respectively.

The CLK+EN control unit 21 functions as a switch control unit that controls the switch circuit 40a. The CLK+EN control unit 21 generates an XNOSIG_STATE signal as an enable signal to control each switch 41(1) to 41(n) and outputs it to the control terminal of each switch 41(1) to 41(n). When not in standby mode, the CLK+EN control unit 21 sets the XNOSIG_STATE signal to, for example, a high level to turn on each switch 41(1) to 41(n). When in standby mode, the CLK+EN control unit 21 sets the XNOSIG_STATE signal to, for example, a low level to turn off each switch 41(1) to 41(n). Whether or not the device is in standby mode can be determined, for example, by an external input signal (e.g., a standby instruction signal) via the input/output unit 2 and the interface unit 5.

The CLK+EN control unit 21 not only controls the switch circuit 40a depending on whether it is in standby mode, but also whether the circuit block being powered on needs to be operated. When the circuit block being powered on needs to be operated, the CLK+EN control unit 21 turns on each of the switches 41(1) to 41(n) by setting the XNOSIG_STATE signal, for example, to high level. Furthermore, when the circuit block being powered on does not need to be operated, the CLK+EN control unit 21 turns off each of the switches 41(1) to 41(n) by setting the XNOSIG_STATE signal, for example, to low level. Whether operation is required can be determined, for example, by an external input signal (e.g., a signal indicating various setting modes) via the input/output unit 2 and the interface unit 5. For example, by using a different XNOSIG_STATE signal for each of the switch circuits 40a to 40c, power on/off control can be performed for each circuit block.

With the buffer connections described above, the XNOSIG_STATE signal output from the CLK+EN control unit 21 is buffered and delayed by buffers 42(1) to 42(n) and output sequentially to switches 41(1) to 41(n). As a result, switches 41(1) to 41(n) switch their conduction state (on/off state) sequentially in response to the XNOSIG_STATE signal. In this way, by using the buffer delay of buffers 42(1) to 42(n) to control switches 41(1) to 41(n) in a time-division manner, switches 41(1) to 41(n) can be turned on in stages during startup, thereby suppressing peak current. The order in which the switches are switched is not particularly limited, but, for example, switching from the upstream operating circuit first can be used to ensure smooth startup. The numerical values n (n is a natural number) of switches 41(1) to 41(n) and buffers 42(1) to 42(n), and the delay amounts in each buffer 42(1) to 42(n) are appropriately designed in advance according to the circuit scale of signal processing unit 23. Similarly, appropriately designed switch circuits 40b and 40c are also used.

(Another example of a switch circuit configuration)
The switch circuits 40a to 40c are not limited to those using buffer delay. For example, the switch circuit 40a may have the configuration shown in FIG. 5. The same applies to the switch circuits 40b and 40c. The switch circuit 40a shown in FIG. 5 has flip-flops 43(1) to 43(n) instead of the buffers 42(1) to 42(n) described above. That is, the switch circuit 40a has multiple switches 41(1) to 41(n) and flip-flops 43(1) to 43(n) constituting multiple delay circuits. One end of each of the switches 41(1) to 41(n) is connected to the power supply line VDD1, and the other end is connected to the signal processing unit 23. The control terminals of the switches 41(1) to 41(n) are sequentially connected to the CLK+EN control unit 21 via the flip-flops 43(1) to 43(n), respectively.

The CLK+EN control unit 21 generates the XNOSIG_STATE signal as an enable signal to control each switch 41(1) to 41(n) and outputs it to the control terminal of each switch 41(1) to 41(n). The CLK+EN control unit 21 is also connected to the clock input terminals of each flip-flop 43(1) to 43(n) and outputs a clock signal to each clock input terminal. As a result, the XNOSIG_STATE signal output from the CLK+EN control unit 21 is synchronized with the clock signal by the flip-flops 43(1) to 43(n) and output sequentially to the switches 41(1) to 41(n). As a result, the switches 41(1) to 41(n) are switched between conductive states (on/off states) sequentially in response to the XNOSIG_STATE signal. In this way, the processing delay of flip-flops 43(1) to 43(n) can be used to control switches 41(1) to 41(n) in a time-division manner. In this case, the delay can be managed using a clock signal, and peak current can be suppressed by gradually turning on switches 41(1) to 41(n) when signal processing unit 23 is started.

(Example of switch circuit layout structure)
FIG. 6 is a diagram illustrating the layout of switch circuits 40a to 40c. As shown in FIG. 6, switch circuits 40a to 40c are provided between the power supply line VDD1 and a circuit block (referred to as a power cutoff circuit block in the figure) that is a power supply control target. This creates a virtual VDD between the power supply line VDD1 and each of the power supply control target circuit blocks. In this way, when switch circuits 40a to 40c are header-type switches capable of cutting off connection to the power supply line VDD1 on the power supply side (high-potential side) of the power supply path, they are compatible with a twin-well structure of a P-type semiconductor substrate (PSUB: P-Substrate) as shown in the figure. Therefore, in the case of these switch circuits 40a to 40c, for example, manufacturing efficiency can be improved by using a PSUB twin-well structure for the substrate and configuring switch circuits 40a to 40c with P-type transistors, as shown in the figure.

(Example of control circuit configuration)
7 is a diagram showing an example of the configuration of the control circuit 50a described above. The power gating compatible logic 23a in FIG. 7 is a circuit of the signal processing unit 23 whose power supply is controlled by the switch circuit 40a, and the always-on logic 24a is a circuit of the register 24 to which power is always supplied. Note that while the control circuit 50a provided between the signal processing unit 23 and the register 24 will be described here, the control circuits 50b to 50d have the same configuration.

As shown in the figure, if there is a signal transmission path from power gating-enabled logic 23a to always-on logic 24a, power gating-enabled logic 23a may output an undefined signal to always-on logic 24a when the power is off, and always-on logic 24a may be affected by this undefined signal. Control circuit 50a uses a logic gate to avoid this undefined output.

As shown in the figure, the control circuit 50a can be configured, for example, by providing an AND element 51 between the wiring connecting the power gating-enabled logic 23a (OUT) and the always-on logic 24a. Specifically, one input of the AND element 51 is connected to the XNOSIG_STATE signal output terminal of the CLK+EN control unit 21, and the other input is connected to the power gating-enabled logic 23a (OUT). The output of the AND element 51 is also connected to the always-on logic 24a. By providing the AND element 51 on the signal transmission path from the power gating-enabled logic 23a to the always-on logic 24a in this way, the signal from the power gating-enabled logic 23a (OUT) is output to the always-on logic 24a when the switch circuit 40a is on, but is not output when it is off. This makes it possible to avoid undefined output propagation when the power is off.

(Another example of the control circuit configuration)
The control circuits 50a to 50d are not limited to those using logic gates. For example, the control circuit 50a may have the configuration shown in FIG. 8. The control circuits 50b to 50d have a similar configuration. The control circuit 50a shown in FIG. 8 has a flip-flop 52 instead of the above-mentioned AND element 51, and further has a flip-flop 53 as an enabler for the flip-flop 52.

If there is a signal transmission path from the power gating-enabled logic 23a to the always-on logic 24a, the control circuit 50a, for example, provides a flip-flop 52 between the wiring connecting the power gating-enabled logic 23a (OUT) and the always-on logic 24a. Specifically, the input of the flip-flop 52 is connected to the power gating-enabled logic 23a (OUT), and the output is connected to the always-on logic 24a. The input of the flip-flop 53 is connected to the XNOSIG_STATE signal output terminal of the CLK+EN control unit 21, and the output is connected to the clock input terminal of the flip-flop 52. The clock input terminal of the flip-flop 53 is then connected to the clock signal output terminal of the CLK+EN control unit 21. As a result, when the switch circuit 40a is on, the signal from the power gating-enabled logic 23a (OUT) is output to the always-on logic 24a, but is not output when the switch circuit 40a is off. This prevents undefined output propagation when the power is off. Using flip-flops 52 as the control circuits 50a-50d makes it possible to reduce the influence of coupling between other circuits, such as the power supply/GND (low-potential power supply) and other signals. Note that if the logic gates described above are used as the control circuits 50a-50d, the circuit area can be made smaller than when flip-flops 52 are used.

As explained above, in this embodiment, the display device 1 has multiple circuit blocks that operate during display operation. These multiple circuit blocks include the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10, which are powered off during standby and when operation is not required. By powering off the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10 in this way during standby and when operation is not required, no leakage current occurs during standby or when operation is not required, as indicated by the dashed arrows in FIG. 3, in the signal processing unit 23, horizontal logic unit 8, and vertical logic unit 10, making it possible to suppress leakage power. By providing switch circuits 40a-40c in the internal power supply circuit of the display device 1, operation can be completed within the display device 1, enabling detailed power supply control of the circuit blocks. Furthermore, power supply control (power on/off) by an external power supply is not required, peak current during startup can be suppressed, and startup can be sped up.

3. Second embodiment
In the first embodiment described above, a configuration was described in which leakage current is suppressed by cutting off the power supply voltage to logic with large gate sizes during standby. However, if necessary, it is also possible to cut off the power supply voltage to analog blocks during standby or when operation is not required, thereby suppressing leakage current.

FIG. 9 is a diagram showing an example configuration of a display device 1 according to a second embodiment of the present technology. As described above, the gamma processing unit 3, power supply processing unit 4, horizontal analog unit 9, and vertical analog unit 11 are blocks that do not need to operate in standby mode. Therefore, in this embodiment, the following configuration is used to perform power control on the gamma processing unit 3, power supply processing unit 4, horizontal analog unit 9, and vertical analog unit 11 as blocks subject to power control.

As shown in FIG. 9, power supply line VDD2 and power supply line VSSA are connected to the oscillator unit 12, horizontal analog unit 9, vertical analog unit 11, gamma processing unit 3, and power supply processing unit 4, and apply a predetermined power supply voltage (specifically, the power supply voltage for the analog circuits) to each connection block. However, power supply line VDD2 is connected to the horizontal analog unit 9 via switch circuit 40d, and the power supply voltage is applied to the horizontal analog unit 9 when switch circuit 40d is on (conductive state), and the power supply voltage is not applied when switch circuit 40d is off (non-conductive state). Furthermore, power supply line VDD2 is connected to the vertical analog unit 11 via switch circuit 40e, and the power supply voltage is applied to the vertical analog unit 11 when switch circuit 40e is on (conductive state), and the power supply voltage is not applied when switch circuit 40e is off (non-conductive state). Furthermore, power supply line VDD2 is connected to gamma processing unit 3 via switch circuit 40f. When switch circuit 40f is on (conductive), power supply voltage is applied to gamma processing unit 3, and when switch circuit 40f is off (non-conductive), power supply voltage is not applied. Furthermore, power supply line VDD2 is connected to power supply processing unit 4 via switch circuit 40g. When switch circuit 40g is on (conductive), power supply voltage is applied to power supply processing unit 4, and when switch circuit 40g is off (non-conductive), power supply voltage is not applied. Switch circuits 40d to 40g are similar to switch circuits 40a to 40c described above.

As a result, the display device 1 shown in FIG. 9 achieves the same effects as the first embodiment, and is also able to reduce leakage power by cutting off power to the analog blocks of the gamma processing unit 3, power supply processing unit 4, horizontal analog unit 9, and vertical analog unit 11 during standby or when operation is not required.

4. Third embodiment
In the first embodiment described above, the switch circuits 40a to 40c are arranged on the power supply line VDD1 side, that is, on the power supply side, but the switch circuits 40a to 40c may be arranged on the power supply line VSSD side, that is, on the GND side.

Figure 10 is a diagram illustrating the layout of switch circuits 40a to 40c in this embodiment. As shown in Figure 10, switch circuits 40a to 40c may be provided between the power supply control target circuit block (represented as a power supply cutoff circuit block in the figure) and the power supply line VSSD. In other words, the power supply line VSSD may be connected to the signal processing unit 23 via switch circuit 40a, to the horizontal logic unit 8 via switch circuit 40b, and to the vertical logic unit 10 via switch circuit 40c. This creates a virtual VSS between the power supply line VSSD and each power supply control target circuit block. In this way, if switch circuits 40a to 40c are footer-type switches capable of cutting off connection to the power supply line VSSD on the ground side (low potential side) of the power supply path, they are compatible with the triple-well structure of a P-type semiconductor substrate (PSUB) as shown in the figure. Therefore, in the case of these switch circuits 40a-40c, for example, as shown in the figure, manufacturing efficiency can be improved by using a PSUB triple-well structure for the substrate and configuring the switch circuits 40a-40c with N-type transistors. In this way, the switch circuits 40a-40c can be used as either a header type or a footer type depending on the layout structure.

5. Fourth embodiment
In the first embodiment described above, the switch circuits 40a to 40c are provided in the internal power supply path of the display device 1 to cut off the power supplied to each power supply control target block during standby. However, this power cut-off may also be performed on the external power supply side of the display device 1.

FIG. 11 shows an example configuration of a display device 1 according to a fourth embodiment of the present technology. Note that FIG. 11 describes the power supply circuits for the power gating-enabled logic 23a of the signal processing unit 23 and the always-on logic 24a of the register 24, but the other circuit blocks have similar configurations.

The external power supply (external VDD1 power supply) 60 is an external power supply for the display device 1 connected to the display device 1 via the input/output unit 2 (not shown in Figure 11). The external power supply 60 supplies power via the always-on power line VDD1 to the always-on logic 24a of the register 24 via the input/output unit 2. The external power supply 60 is connected to the CLK+EN control unit 21 via the input/output unit 2, and the CLK+EN control unit 21 outputs an XNOSIG_STATE signal to the external power supply 60. This signal output can be performed, for example, by providing a control terminal in the input/output unit 2 that controls the external power supply 60. In response to this XNOSIG_STATE signal, the external power supply 60 supplies power to the power gating-compatible logic 23a of the signal processing unit 23 via the power supply control power line VDD1. For example, when the XNOSIG_STATE signal is at a high level, power is supplied to the power gating compatible logic 23a (power on), and when it is at a low level, power to the power gating compatible logic 23a is cut off (power off).

In this way, even with a configuration in which power is controlled by the external power supply 60 of the display device 1, the same effects as in the first embodiment can be achieved. Furthermore, by performing substantial power control on the external power supply 60 side, it is possible to simplify the power control circuitry on the display device 1 side.

6. Fifth embodiment
In the fourth embodiment described above, power supply control is performed by an external power supply of the display device 1, but power supply control may also be performed by an internal power supply of the display device 1.

FIG. 12 shows an example configuration of a display device 1 according to a fifth embodiment of the present technology. Note that FIG. 12 describes the power supply circuits for the power gating-enabled logic 23a of the signal processing unit 23 and the always-on logic 24a of the register 24, but the other circuit blocks have similar configurations.

The internal power supply (internally generated VDD1 power supply) 70 is a chip internal power supply (power supply block) provided inside the display device 1. The internal power supply 70 supplies power to the always-on logic 24a of the register 24 via the always-on power line VDD1. The internal power supply 70 is connected to the CLK+EN control unit 21, which outputs an XNOSIG_STATE signal to the internal power supply 70. In response to this XNOSIG_STATE signal, the internal power supply 70 supplies power to the power gating-compatible logic 23a of the signal processing unit 23 via the power control power line VDD1. For example, when the XNOSIG_STATE signal is high level, power is supplied to the power gating-compatible logic 23a (power on), and when it is low level, power to the power gating-compatible logic 23a is cut off (power off).

In this way, even with a configuration in which power is controlled by the internal power supply 70 of the display device 1, the same effects as in the first embodiment can be achieved. Furthermore, by performing substantial power control with the internal power supply 70, the power control circuitry of the display device 1 can be simplified. Furthermore, the control terminals that were required when power was controlled by the external power supply 60 are no longer necessary.

7. Sixth embodiment
Fig. 13 is a diagram for explaining a configuration for dissipating leakage current between pixels. Fig. 13A shows a plan view of a pixel, and Fig. 13B is a diagram showing an example of a configuration for dissipating leakage current between pixels. In Figs. 13A and 13B, "R" denotes a pixel from which red wavelength light is obtained, "G" denotes a pixel from which green wavelength light is obtained, and "B" denotes a pixel from which blue wavelength light is obtained. An insulating film 80 is provided between each pixel. The insulating film 80 is made of an insulator such as silicon oxide (SiOx).

As shown in Figure 13B, by wiring the insulating film node between pixels and applying a negative power supply (power supply for pixel isolation) to the insulating film 80 via the power supply line VISO, the leakage current between adjacent pixels can be diverted to the electrode side, preventing leakage current from flowing into the pixel. This technology can be applied not only to circuit blocks that drive circuits, but also to circuit blocks such as shields for maintaining characteristics.

14 is a diagram showing an example configuration of a display device 1 according to a sixth embodiment of the present technology. In the display device 1 of this embodiment, a switch circuit 81 is provided between the insulating film 80 between each pixel in the pixel section 7 and the power line VSIO, forming a virtual VISO. The switch circuit 81 is capable of cutting off the power supply in response to an ISOEN signal serving as an enable signal. The switch circuit 81 corresponds to the switch circuits 40a to 40c in the first embodiment, and the ISOEN signal corresponds to the XNOSIG_STATE signal in the first embodiment. In other words, in this embodiment, the power supply is controlled by a circuit block that applies an insulation voltage to the insulating film 80 that insulates the pixels, acting as the first circuit block. The switch circuit 81 is controlled to be on when contrast needs to be increased (for example, when light emission is not desired, such as in black display) in response to the ISOEN signal, and is controlled to be off during standby or when increased contrast is not required. This display device 1 can also reduce standby power consumption.

<8. Seventh embodiment)
In the first embodiment described above, it is assumed that the switch circuits 40a to 40c are formed on a silicon (Si) substrate, but the substrate on which the switch circuits 40a to 40c are formed is not limited to a silicon (Si) substrate.

Figure 15 is a conceptual diagram illustrating an example of the configuration of a substrate to which this technology can be applied. Substrate P, shown in the lower part of Figure 15, has a structure in which an oxide semiconductor is layered on a silicon (Si) substrate. The silicon substrate contains, for example, amorphous silicon or polycrystalline silicon. The oxide semiconductor contains, for example, indium gallium zinc oxide (IGZO), and forms a TFT (Thin Film Transistor) layer.

Pixel transistors are formed in the pixel region of the oxide semiconductor layer. The area of the oxide semiconductor layer other than the pixel region is a dummy region in which dummy patterns are formed. High-voltage transistors are formed in the pixel region of the silicon substrate, and low-voltage transistors are formed in the area other than the pixel region as a logic region. The logic region is, for example, an area where logic blocks driven by a power supply voltage for digital circuits are arranged. This technology can also be applied, for example, to a display device having a substrate P with such a structure.

FIG. 16 is a diagram showing an example configuration of a display device 1 according to a seventh embodiment of the present technology. The display device 1 shown in FIG. 16 has the footer-type switch circuits 40a-40c (see FIG. 10) described in the third embodiment above. In this display device 1, the switch circuits 40a-40c, which are power gating switches, are formed using oxide semiconductor transistors, specifically TFTs, in the dummy region of the substrate P described above, i.e., in the oxide semiconductor layer in the area overlapping with the logic region. This achieves the same effects as the first embodiment described above, while also reducing leakage current due to the oxide semiconductor, contributing to process planarization and improved process characteristics. The switch circuits 40a-40c may also be formed in empty areas of the pixel region in the oxide semiconductor layer.

9. Example of pixel circuit configuration
The following describes an example of the configuration of the pixel (pixel circuit) included in the pixel section 7 of the display device 1. Note that the following example of the configuration is merely an example and does not exclude other configurations.

(First configuration example)
17 shows an example of the configuration of pixel PIX. Pixel PIX has a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. Transistors MN02 and MN03 are N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The gate of transistor MN02 is connected to a control line WSL, its drain is connected to a signal line SGL, and its source is connected to the gate of transistor MN03 and capacitor C01. One end of capacitor C01 is connected to the source of transistor MN02 and the gate of transistor MN03, and the other end is connected to the source of transistor MN03 and the anode of light-emitting element EL. The gate of transistor MN03 is connected to the source of transistor MN02 and one end of capacitor C01, its drain is connected to the power supply line VCCP, and its source is connected to the other end of capacitor C01 and the anode of light-emitting element EL. The anode of the light-emitting element EL is connected to the source of the transistor MN03 and the other end of the capacitor C01, and the cathode is connected to the power supply line Vcath. The voltage of the power supply line VCCP is appropriately switched between a first voltage and a second voltage lower than the first voltage.

With this configuration, in pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During the period when the voltage of power supply line VCCP is the first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, pixel PIX emits light at a brightness corresponding to the pixel signal. Note that during the period when the voltage of power supply line VCCP is the second voltage, the light-emitting element EL is extinguished.

(Second configuration example)
18 shows another example of the configuration of pixel PIX. This pixel PIX has capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, the source is connected to the power supply line VCCP, and the drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, the source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the drain is connected to the anode of the light-emitting element EL and the source of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, the source is connected to the drain of transistor MP14 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS. The anode of the light-emitting element EL is connected to the drain of transistor MP14 and the source of transistor MP15, and the cathode is connected to the power supply line Vcath.

With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 turns on and off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current to the light-emitting element EL that corresponds to the voltage across capacitor C12. The light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, pixel PIX emits light at a brightness that corresponds to the pixel signal. Transistor MP15 turns on and off based on the signal on control line AZSL. While transistor MP15 is on, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

Note that transistors MP12 to MP15 may be transistors using low temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

(Third Configuration Example)
19 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and the other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN24. The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the drain is connected to the source of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and the source is connected to power supply line VSS. The anode of light-emitting element EL is connected to the source of transistor MN24, the drain of transistor MN25, and the other end of capacitor C21, and the cathode is connected to power supply line Vcath.

With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 turns on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current to light-emitting element EL that corresponds to the voltage across capacitor C21. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a brightness that corresponds to the pixel signal. Transistor MN25 turns on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

Note that transistors MN22 to MN25 may be transistors using low temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

(Fourth Configuration Example)
20 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the gate of transistor MP33, the drain of transistor MP34, and capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP32, the gate of transistor MP33, and the drain of transistor MP34. The gate of transistor MP33 is connected to the drain of transistor MP32, the drain of transistor MP34, and the other end of capacitor C31, its source is connected to the power supply line VCCP, and its drain is connected to the sources of transistor MP34 and transistor MP35. The gate of transistor MP34 is connected to control line AZSL1, its source is connected to the drain of transistor MP33 and the source of transistor MP35, and its drain is connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to control line DSL, its source is connected to the drain of transistor MP33 and the source of transistor MP34, and its drain is connected to the source of transistor MP36 and the anode of light-emitting element EL. The gate of transistor MP36 is connected to control line AZSL2, its source is connected to the drain of transistor MP35 and the anode of light-emitting element EL, and its drain is connected to power supply line VSS. The anode of light-emitting element EL is connected to the drain of transistor MP35 and the source of transistor MP36, and its cathode is connected to power supply line Vcath.

With this configuration, in pixel PIX, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 turns on and off based on the signal on control line DSL. While transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, pixel PIX emits light at a brightness corresponding to the pixel signal. Transistor MP34 turns on and off based on the signal on control line AZSL1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 turns on and off based on the signal on control line AZSL2. While transistor MP36 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

Note that transistors MP32 to MP36 may be transistors using low temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

(Fifth Configuration Example)
21 shows another example of the configuration of pixel PIX. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, and its gate is connected to control line WSL2, its source is connected to signal line SGL1, and its drain is connected to signal line SGL2.

Pixel PIX has a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to control line WSL1, its source is connected to signal line SGL2, and its drain is connected to the gate of transistor MP43 and capacitor C41. One end of capacitor C41 is connected to power supply line VCCP, and the other end is connected to the drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the drain of transistor MP42 and the other end of capacitor C41, its source is connected to power supply line VCCP, and its drain is connected to the sources of transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, its source is connected to the drain of transistor MP43 and the source of transistor MP45, and its drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, its source is connected to the drain of transistor MP43 and the source of transistor MP44, and its drain is connected to the source of transistor MP46 and the anode of light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, its source is connected to the drain of transistor MP45 and the anode of light-emitting element EL, and its drain is connected to power supply line VSS. The anode of light-emitting element EL is connected to the drain of transistor MP45 and the source of transistor MP46, and its cathode is connected to power supply line Vcath.

With this configuration, in pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 turns on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current to the light-emitting element EL that corresponds to the voltage across capacitor C41. The light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a brightness that corresponds to the pixel signal. Transistor MP44 turns on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 turns on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

Note that transistors MP42 to MP46 and MP49 may be transistors using low temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

(Sixth Configuration Example)
22 shows another example of the configuration of the pixel PIX. A plurality of pixels PIX are arranged in a matrix in a display area 100, and the display area 100 is provided between a first control unit 91 and a second control unit 92.

The first control unit 91 has transmission gates TG45 and TG46, transistors MP50 and MP51, and a capacitor C50. Transistors MP50 and MP51 are P-type MOSFETs. A pixel signal is supplied to the input terminal of transmission gate TG45, and the output terminal of transmission gate TG45 is connected to one end of signal line 93a. The input terminal of transmission gate TG46 is connected to signal line 93b, and the output terminal of transmission gate TG46 is connected to power supply line Vorst. One end of capacitor C50 is connected to signal line 93a, and the other end is connected to power supply line VSS1. The gate of transistor MP50 is connected to control line INIL, the source is connected to power supply line Vini, and the drain is connected to signal line 93b. The gate of transistor MP51 is connected to control line ELL, the source is connected to power supply line Vel, and the drain is connected to signal line 93b.

The second control unit 92 has a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. The input terminal of the transmission gate TG72 is connected to the other end of the signal line 93a, and the output terminal is connected to the drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, the source is connected to the power supply line Vref, and the drain is connected to the output terminal of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the output terminal of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of the signal line 93b.

Pixel PIX has a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to control line WSL, its source is connected to signal line 93b, and its drain is connected to the gate of transistor MP121 and capacitor C132. One end of capacitor C132 is connected to power supply line Vel, and the other end is connected to the drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the drain of transistor MP122 and the other end of capacitor C132, its source is connected to power supply line Vel, and its drain is connected to the sources of transistors MP123 and MP124. The gate of transistor MP123 is connected to control line AZSL, its source is connected to the drain of transistor MP121 and the source of transistor MP124, and its drain is connected to signal line 93b. The gate of transistor MP124 is connected to control line DSL, its source is connected to the drain of transistor MP121 and the source of transistor MP123, and its drain is connected to the drain of transistor MP125 and the anode of light-emitting element EL. The gate of transistor MP125 is connected to control line AZSL, its source is connected to power supply line Vorst, and its drain is connected to the drain of transistor MP124 and the anode of light-emitting element EL. The anode of light-emitting element EL is connected to the drains of transistor MP124 and transistor MP125, and its cathode is connected to power supply line Vcath.

With this configuration, in pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, signal line 93a, transmission gate TG72, capacitor C82, and signal line 93b. Transistor MP124 turns on and off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current to light-emitting element EL that corresponds to the voltage across capacitor C132. The light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, pixel PIX emits light at a brightness that corresponds to the pixel signal. Transistors MP123 and MP125 turn on and off based on the signal on control line AZSL. While transistor MP123 is on, the drain of transistor MP121 and the source of transistor MP124 are connected to signal line 93b. During the period when transistor MP125 is in the ON state, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP50 turns on and off based on the signal on control line INIL, transistor MP51 turns on and off based on the signal on control line ELL, and transistor MP73 turns on and off based on the signal on control line REFL. When transistor MP50 is in the ON state, signal line 93b is set to the voltage of power supply line Vini, and when transistor MP51 is in the ON state, signal line 93b is set to the voltage of power supply line Vel. When transistor MP73 is in the ON state, one end of capacitor C82 is initialized by being set to the voltage of power supply line Vref.

Note that transistors MP121 to MP125, MP50, and MP51 may be transistors using low temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

(Seventh Configuration Example)
23 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the drain of transistor MP53 and the source of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, its source is connected to a power supply line VCCP, and its drain is connected to the drain of transistor MP52 and the source of transistor MP54. The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51, its source is connected to the drains of transistors MP52 and MP53, and its drain is connected to the sources of transistors MP58 and MP59. One end of capacitor C51 is connected to the power supply line VCCP, and the other end is connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. Transistor MP55 has a gate connected to control line AZSL1, a source connected to the gate of transistor MP54, the drain of transistor MP57, and the other end of capacitor C51, and a drain connected to the source of transistor MP56. Transistor MP56 has a gate connected to control line AZSL1, a source connected to the drain of transistor MP55, and a drain connected to power supply line VSS. Transistor MP57 has a gate connected to control line WSL, a drain connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and a source connected to the drain of transistor MP58. The gate of transistor MP58 is connected to the control line WSL, the drain is connected to the source of transistor MP57, and the source is connected to the drain of transistor MP54 and the source of transistor MP59. The gate of transistor MP59 is connected to the control line DSL, the source is connected to the drain of transistor MP54 and the source of transistor MP58, and the drain is connected to the source of transistor MP60 and the anode of the light-emitting element EL. The gate of transistor MP60 is connected to the control line AZSL2, the source is connected to the drain of transistor MP59 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS. The anode of the light-emitting element EL is connected to the drain of transistor MP59 and the source of transistor MP60, and the cathode is connected to the power supply line Vcath.

With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a brightness corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. While transistor MP60 is in the on state, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

Note that transistors MP52 to MP60 may be transistors using low temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

(Eighth Configuration Example)
24 shows another example of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

Pixel PIX has capacitors C61 and C62, transistors MN63, MP64, MN65 to MN67, and a light-emitting element EL. Transistors MN63, MN65 to MN67 are N-type MOSFETs, and transistor MP64 is a P-type MOSFET. The gate of transistor MN63 is connected to control line WSNL, the drain is connected to signal line SGL and the source of transistor MP64, and the source is connected to the drain of transistor MP64, capacitors C61 and C62, and the gate of transistor MN65. The gate of transistor MP64 is connected to control line WSPL, the source is connected to signal line SGL and the drain of transistor MN63, and the drain is connected to the source of transistor MN63, capacitors C61 and C62, and the gate of transistor MN65. The capacitor C61 is configured, for example, using a MOM (Metal Oxide Metal) capacitor, and one end is connected to the source of the transistor MN63, the drain of the transistor MP64, the capacitor C62, and the gate of the transistor MN65, and the other end is connected to the power supply line VSS2. The capacitor C61 may be configured, for example, using a MOS capacitor or a MIM (Metal Insulator Metal) capacitor. The capacitor C62 is configured, for example, using a MOS capacitor, and one end is connected to the source of the transistor MN63, the drain of the transistor MP64, one end of the capacitor C61, and the gate of the transistor MN65, and the other end is connected to the power supply line VSS2. The capacitor C62 may be configured, for example, using a MOM capacitor or a MIM capacitor. The other end of the capacitor C62 may be connected to the power supply line VSS3 (not shown). The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, its drain is connected to the power supply line VCCP, and its source is connected to the drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, its drain is connected to the source of transistor MN65 and the drain of transistor MN67, and its source is connected to power supply line VSS1. The gate of transistor MN67 is connected to control line DSL, its drain is connected to the source of transistor MN65 and the drain of transistor MN66, and its source is connected to the anode of light-emitting element EL. The anode of light-emitting element EL is connected to the source of transistor MN67, and its cathode is connected to the power supply line Vcath. Note that transistor MN67 and control line DSL may be omitted, and the source of transistor MN65 may be connected to the drain of transistor MN66 and the anode of light-emitting element EL.

With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 turns on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current to light-emitting element EL that corresponds to the voltage across capacitors C61 and C62. The light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, pixel PIX emits light at a brightness that corresponds to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value that corresponds to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

Note that transistors MN63, MP64, MN65 to MN67 may be transistors using low temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

(Ninth Configuration Example)
25 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the source of transistor MN74 and the drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and the source of transistor MN76, and the other end is connected to the drain of transistor MN77, the source of transistor MN75, and the anode of light-emitting element EL. The gate of transistor MN73 is connected to control line DSL1, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN74 and the drain of transistor MN76. The gate of transistor MN74 is connected to the source of transistor MN76 and one end of capacitor C71, the drain is connected to the source of transistor MN73 and the drain of transistor MN76, and the source is connected to the source of transistor MN72 and the drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the drain is connected to the source of transistor MN72 and the source of transistor MN74, and the source is connected to the other end of capacitor C71, the drain of transistor MN77, and the anode of light-emitting element EL. The gate of transistor MN76 is connected to control line AZSL, the drain is connected to the source of transistor MN73 and the drain of transistor MN74, and the source is connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to control line AZSL, the drain is connected to the other end of capacitor C71, the source of transistor MN75, and the anode of light-emitting element EL, and the source is connected to power supply line VSS. The anode of the light emitting element EL is connected to the source of the transistor MN75, the drain of the transistor MN77 and the other end of the capacitor C71, and the cathode is connected to the power supply line Vcath.

With this configuration, in pixel PIX, transistors MN72, MN74, and MN76 are turned on, and the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL. Transistor MN73 turns on and off based on the signal on control line DSL1, and transistor MN75 turns on and off based on the signal on control line DSL2. While transistors MN73 and MN75 are on, transistor MN74 passes a current to light-emitting element EL that corresponds to the voltage across capacitor C71. Light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, pixel PIX emits light at a brightness that corresponds to the pixel signal. Transistor MN77 turns on and off based on the signal on control line AZSL. While transistor MN77 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

Note that transistors MN72 to MN77 may be transistors using low temperature polycrystalline silicon (LTPS). Transistor MN76 may also be a transistor using an oxide semiconductor.

10. Modifications
Although the embodiments of the present technology have been specifically described above, the content of the present technology is not limited to the above-described embodiments, and various modifications based on the technical concept of the present technology are possible. For example, the configurations, methods, processes, materials, shapes, and numerical values of the above-described embodiments can be combined or substituted with each other as long as they do not deviate from the spirit of the present technology. Furthermore, one thing can be divided into two or more parts, and some parts can be omitted. Furthermore, as long as the present technology is applicable, the above-described configurations may be appropriately deleted, modified, or added with other configurations, or may be replaced with alternative configurations. Furthermore, the present technology may be an appropriate combination of the above-described embodiments.

For example, the circuit blocks subject to power control and the circuit blocks that are always powered on are merely illustrative and can be changed as appropriate depending on the circuit blocks that make up the display device 1. The constituent units of the circuit blocks can also be changed as appropriate. Furthermore, the XNOSIG_STATE signal and ISOEN signal described above are not limited to one type each, and there can be multiple types. This allows for fine-grained power control, such as power control for logic and analog circuits, for each circuit block, or for each display setting mode. Leakage power can be reduced by turning off the power not only during standby but also when various circuit blocks do not need to operate.

For example, this technology can be applied to a variety of displays. This technology can be applied to display panels such as SXRD (Silicon X-tal Reflective Display: registered trademark) used in projectors, etc., and phase modulation panels that use SLM (Spatial Light Modulator) for displaying holograms. This technology can also be applied to panels such as LCOS (Liquid crystal on silicon; LCoS is a trademark) and HTPS (High Temperature Poly-Silicon). The above-mentioned XNOSIG_STATE signal and ISOEN signal may be obtained from outside via the input/output unit 2.

<11. Application Examples>
Next, application examples of the display systems described in the above embodiments and modifications will be described.

(Application example 1)
26 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

(Application example 2)
FIG. 27 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

Note that the head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. This birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

(Application Example 3)
28A and 28B show an example of the appearance of a digital still camera 130, with FIG. 28A showing a front view and FIG. 28B showing a rear view. This digital still camera 130 is an interchangeable-lens single-lens reflex camera and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 131. The grip 133 is provided on the left side of the front of the camera body 131, and is held by the photographer. The monitor 134 is provided on the left side of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

(Application Example 4)
29 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

(Application Example 5)
30 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

(Application Example 6)
31A and 31B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where FIG. 31A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and FIG. 31B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

The vehicle in Figures 31A and 31B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 206.

The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and passenger seat 263. While FIG. 31A shows an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 is capable of displaying information detected by various sensors. As a specific example, the center display 201 can display images captured by an image sensor, distance images to obstacles in front of and to the sides of the vehicle measured by a ToF sensor, and the body temperature of occupants detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication/identification-related information, and entertainment-related information.

Safety-related information is information based on sensor detection results, such as detection of drowsiness, distraction, tampering by children in the vehicle, whether seat belts are fastened, and whether a passenger has been abandoned. Operation-related information is information about gestures related to passenger operations detected using sensors. Gestures may include operations of various equipment within the vehicle, such as operations of air conditioning equipment, navigation equipment, AV (Audio-Visual) equipment, and lighting equipment. Life logs include life logs of all passengers. For example, life logs include records of the behavior of each passenger. By acquiring and saving life logs, it is possible to determine the condition of passengers at the time of an accident. Health-related information includes the body temperature of passengers detected using a temperature sensor and information about the passenger's health condition estimated based on the detected body temperature. Alternatively, information about the passenger's health condition may be estimated based on the passenger's face captured by an image sensor. Information about the passenger's health condition may also be estimated based on the passenger's responses obtained by conversation with the passenger using an automated voice. Authentication/identification-related information includes information such as the keyless entry function that uses sensors to perform facial recognition, and the function that automatically adjusts seat height and position using facial recognition. Entertainment-related information includes information on AV device operation by occupants detected by sensors, and information on content to be displayed that is appropriate for occupants detected and recognized by sensors.

The console display 202 can be used to display life log information, for example. The console display 202 is located near the shift lever 265 on the center console 264 between the driver's seat 262 and the passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the area around the vehicle captured by an image sensor, or an image showing the distance to obstacles around the vehicle.

The head-up display 203 is virtually displayed behind the windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication/identification-related information, and entertainment-related information. Because the head-up display 203 is often virtually positioned in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as vehicle speed, remaining fuel, and remaining battery charge.

The digital rearview mirror 204 can not only display the view behind the vehicle, but also the status of rear seat passengers, and can therefore be used, for example, to display life log information of rear seat passengers.

The steering wheel display 205 is located near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located close to the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

The rear entertainment display 206 is attached to the back of the driver's seat 262 and passenger seat 263, and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, life logs, health-related information, authentication/identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located directly in front of the rear seat passengers, information relevant to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may, for example, display information relating to the operation of AV equipment or air conditioning equipment, or may display the body temperature of the rear seat passengers measured by a temperature sensor.

The technologies relating to the above-described embodiments can be applied to the center display 201, console display 202, head-up display 203, digital rearview mirror 204, steering wheel display 205, and rear entertainment display 206.

The present technology can also be configured as follows.
(1)
It has a plurality of circuit blocks that operate during display operation,
The display device, wherein the plurality of circuit blocks includes a first circuit block whose power supply is controlled to be turned off during standby.
(2)
a switch provided between a power supply line of the power supply and the first circuit block;
and a switch control unit that controls the switch to be turned off during the standby state and when the operation of the first circuit block is not required.
(3)
A plurality of the switches;
and a delay circuit that turns on the plurality of switches in a stepwise manner.
(4)
The display device according to (3), wherein the delay circuit is configured by a buffer.
(5)
The display device according to (3), wherein the delay circuit is configured by a flip-flop.
(6)
the plurality of circuit blocks includes a second circuit block that operates during the standby state;
The display device according to any one of (1) to (5), further comprising a control circuit in a signal transmission path from the first circuit block to the second circuit block, the control circuit controlling an output signal of the first circuit block during standby.
(7)
The display device according to (6), wherein the control circuit is configured by a logic gate.
(8)
The display device according to (6), wherein the control circuit is configured by a flip-flop.
(9)
a power supply path for supplying the power from an external power supply to the first circuit block;
The display device according to any one of (1), (6) to (9), wherein the external power supply is turned off during the standby state and when the operation of the first circuit block is not required.
(10)
an internal power supply that supplies the power to the first circuit block;
The display device according to any one of (1), (6) to (9), wherein the internal power supply is turned off during the standby state and when the operation of the first circuit block is not required.
(11)
a plurality of pixels each having a light-emitting element;
The display device according to any one of (1) to (10), wherein the first circuit block includes a logic unit that drives the pixels, or a signal processing unit that performs signal processing on image data output to the logic unit.
(12)
The display device according to any one of (2) to (8) and (11), wherein the power supply line is a power supply line on a high potential side in a power supply path of the power supply.
(13)
The display device according to any one of (2) to (8) and (11), wherein the power supply line is a power supply line on a low potential side in a power supply path of the power supply.
(14)
a plurality of pixels each having a light-emitting element;
The display device according to any one of (2) to (8) and (11) to (13), wherein the first circuit block is a circuit block that applies an insulating voltage to an insulator that insulates the pixels from each other.
(15)
The display device according to any one of (2) to (8) and (11) to (14), wherein the switch is formed using an oxide semiconductor transistor.
(16)
An electronic device having the display device according to any one of (1) to (15).

1: Display device, 2: Input/output unit, 3: Gamma processing unit, 4: Power supply processing unit, 5: Interface unit, 6: Timing controller, 7: Pixel unit, 8: Horizontal logic unit, 9: Horizontal analog unit, 10: Vertical logic unit, 11: Vertical analog unit, 21: CLK+EN control unit, 22: Timing generator, 23: Signal processing unit, 24: Register, 40a-40g, 81: Switch circuit, 50a-50d: Control circuit, 60: External power supply, 70: Internal power supply

Claims (16)

It has a plurality of circuit blocks that operate during display operation,
The display device, wherein the plurality of circuit blocks includes a first circuit block whose power supply is controlled to be turned off during standby. a switch provided between a power supply line of the power supply and the first circuit block;
The display device according to claim 1 , further comprising: a switch control unit that controls the switch to be turned off during the standby state and when the operation of the first circuit block is not required. A plurality of the switches;
The display device according to claim 2 , further comprising: a delay circuit that turns on the plurality of switches in a stepwise manner. The display device according to claim 3 , wherein the delay circuit is configured by a buffer. The display device according to claim 3 , wherein the delay circuit is configured by a flip-flop. the plurality of circuit blocks includes a second circuit block that operates during the standby state;
The display device according to claim 1 , further comprising a control circuit for controlling an output signal of the first circuit block during the standby state, the control circuit being provided in a signal transmission path from the first circuit block to the second circuit block. The display device according to claim 6 , wherein the control circuit is configured with a logic gate. The display device according to claim 6 , wherein the control circuit is configured by a flip-flop. a power supply path for supplying the power from an external power supply to the first circuit block;
The display device according to claim 1 , wherein the external power supply is turned off during the standby state and when the operation of the first circuit block is not required. an internal power supply that supplies the power to the first circuit block;
The display device according to claim 1 , wherein the internal power supply is turned off during the standby state and when the operation of the first circuit block is not required. a plurality of pixels each having a light-emitting element;
The display device according to claim 1 , wherein the first circuit block includes a logic unit that drives the pixels, or a signal processing unit that performs signal processing on image data output to the logic unit. The display device according to claim 2 , wherein the power supply line is a power supply line on a high potential side in a power supply path of the power supply. The display device according to claim 2 , wherein the power supply line is a power supply line on a low potential side in a power supply path of the power supply. a plurality of pixels each having a light-emitting element;
The display device according to claim 2 , wherein the first circuit block is a circuit block that applies an insulating voltage to an insulator that insulates the pixels from each other. The display device according to claim 2 , wherein the switch is formed using an oxide semiconductor transistor. An electronic device comprising the display device according to claim 1 .