WO2025112490A1 - Dc-dc converter, chip and electronic device - Google Patents

Abstract

Provided in the present disclosure are a DC-DC converter, a chip and an electronic device. The DC-DC converter comprises a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit, a low-side drive circuit, a high-side power transistor and a low-side power transistor; the bootstrap boost circuit provides a first boost voltage for the high-side drive circuit; on the basis of the first boost voltage, the high-side drive circuit outputs a first high-side drive voltage to a control electrode of the high-side power transistor; the charge pump boost circuit generates a second boost voltage by means of a charge pump and, on the basis of the second boost voltage, outputs a second high-side drive voltage to the control electrode of the high-side power transistor, the second boost voltage being greater than the first boost voltage; a first electrode of the high-side power transistor is coupled to an input voltage terminal, while a second electrode thereof is coupled to a first electrode of the low-side power transistor by means of a switch node; the high-side power transistor is turned on or off on the basis of the first high-side drive voltage and the second high-side drive voltage; one end of the bootstrap boost circuit and one end of the charge pump booster circuit are both coupled to the switch node.

Description

DC-DC converter, chip and electronic device

CROSS-REFERENCE TO RELATED APPLICATIONS

This disclosure claims priority to a Chinese patent application filed with the Chinese Patent Office on November 27, 2023, with application number 2023115959918 and invention name “DC-DC converter and chip”, the entire contents of which are incorporated by reference in this disclosure.

Technical Field

The present disclosure relates to the technical field of integrated circuits, and in particular to a DC-DC converter, a chip and an electronic device.

Background Art

With the increasing expansion of the integrated circuit market, direct current to direct current (DC-DC) converters have developed rapidly. As a switching power supply technology, DC-DC converters have the advantages of fast dynamic response and simple control, and have a wide range of applications.

At present, when NMOS is selected as the power tube in a BUCK type DC-DC converter, a bootstrap capacitor is required to power the driving part of the power tube. However, in order to obtain a lower high-side power tube on-resistance in the related technology, the capacitance value and area of the bootstrap capacitor are often large, resulting in a higher chip cost.

Currently, no effective technical solution has been proposed to solve the problem that the capacitance value and area of the bootstrap capacitor in a BUCK type DC-DC converter are large, resulting in high chip cost.

Summary of the invention

The embodiments described in the present disclosure provide a DC-DC converter, a chip, and an electronic device.

The first aspect of the present disclosure provides a DC-DC converter, including a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit, a low-side drive circuit, a high-side power tube and a low-side power tube; The boost circuit is configured to provide a first boost voltage for the high-side driving circuit based on the input voltage at the input voltage terminal; the high-side driving circuit is configured to output the first high-side driving voltage to the control electrode of the high-side power tube according to the first boost voltage based on the pulse width modulation signal at the modulation signal terminal; the charge pump boost circuit is configured to generate a second boost voltage through a charge pump, and output a second high-side driving voltage to the control electrode of the high-side power tube according to the second boost voltage, wherein the second boost voltage is greater than the first boost voltage; the low-side driving circuit is configured to output a low-side driving voltage to the control electrode of the low-side power tube based on the pulse width modulation signal at the modulation signal terminal; the first electrode of the high-side power tube is coupled to the input voltage terminal, the second electrode of the high-side power tube is coupled to the first electrode of the low-side power tube via the switch node, the high-side power tube is configured to be turned on or off according to the first high-side driving voltage and the second high-side driving voltage, and the low-side power tube is configured to be turned on or off according to the low-side driving voltage; one end of the bootstrap boost circuit and one end of the charge pump boost circuit are respectively coupled to the switch node.

In an optional embodiment of the present disclosure, the bootstrap boost circuit includes a first diode and a first bootstrap capacitor; the first end of the first diode is coupled to the input voltage end, and the second end of the first diode is respectively coupled to the first end of the first bootstrap capacitor and the first end of the high-side drive circuit via the first bootstrap node; the second end of the first bootstrap capacitor is respectively coupled to the switching node and the second end of the high-side drive circuit, and the first bootstrap capacitor is configured to be charged based on the input voltage when the pulse width modulation signal is at a low level, and to provide a first boost voltage to the high-side drive circuit when the pulse width modulation signal is at a high level.

In an optional embodiment of the present disclosure, the charge pump boost circuit includes a charge pump, a unidirectional rectifier circuit, a second bootstrap capacitor and a high-voltage drive circuit; the charge pump is configured to charge the second bootstrap capacitor to N times the input voltage via the unidirectional rectifier circuit, wherein N is a positive integer greater than 1; the first end of the unidirectional rectifier circuit is coupled to the charge pump, and the second end of the unidirectional rectifier circuit is coupled to the first end of the second bootstrap capacitor and the first end of the high-voltage drive circuit via the second bootstrap node, respectively; the second end of the second bootstrap capacitor is coupled to the switch node, and the second bootstrap capacitor is configured to be charged based on the charge pump when the pulse width modulation signal is at a low level, and to provide a second boost voltage to the high-voltage drive circuit when the pulse width modulation signal is at a high level and the voltage of the switch node rises to the input voltage; the second end of the high-voltage drive circuit is coupled to the control electrode of the high-side power tube, and the high-voltage drive circuit is configured to charge the high-side power tube based on the second boost voltage. The control electrode of the tube outputs a second high-side driving voltage.

In an optional implementation of the present disclosure, the unidirectional rectifier circuit includes a unidirectional conducting switch tube.

In an optional implementation of the present disclosure, the unidirectional rectifier circuit includes a second diode.

In an optional embodiment of the present disclosure, when N is 3, the charge pump includes a digital receiver, a first transistor, a second transistor and a third transistor; the first end of the digital receiver is coupled to the modulation signal end, the second end of the digital receiver is coupled to the bootstrap control signal end, the third end of the digital receiver is coupled to the control electrode of the first transistor, and the fourth end of the digital receiver is coupled to the control electrode of the second transistor. The digital receiver is configured to control the opening or closing of the first transistor and the second transistor according to the pulse width modulation signal of the modulation signal end and the bootstrap control signal of the bootstrap control signal end; the first electrode of the first transistor is respectively coupled to the first electrode of the second transistor, the first electrode of the third transistor and the second end of the first bootstrap capacitor, the second electrode of the first transistor is respectively coupled to the input voltage end and the first end of the first diode, and the second electrode of the second transistor is grounded; the control electrode of the third transistor is coupled to the modulation signal end, the second electrode of the third transistor is coupled to the switch node, and the opening or closing of the third transistor is controlled by the pulse width modulation signal of the modulation signal end.

In an optional embodiment of the present disclosure, the high-voltage drive circuit includes a fourth transistor, a third diode, a fourth diode and a third bootstrap capacitor; the first end of the third bootstrap capacitor is respectively coupled to the second end of the third diode, the first end of the fourth diode and the control electrode of the fourth transistor, the second end of the third bootstrap capacitor is grounded, and the third bootstrap capacitor is configured to output a signal to the control electrode of the fourth transistor; the first electrode of the fourth transistor is coupled to the control electrode of the high-side power tube, the second electrode of the fourth transistor is coupled to the second bootstrap node, and the fourth transistor is configured to be turned on or off according to the voltage difference between the control electrode voltage and the second electrode voltage of the fourth transistor; the first end of the third diode is respectively coupled to the first bootstrap node and the first end of the second diode, and the second end of the fourth diode is respectively coupled to the second end of the second diode and the second bootstrap node.

In an optional embodiment of the present disclosure, when the pulse width modulation signal at the modulation signal end is at a low level, the bootstrap control signal at the bootstrap control signal end is a square wave signal, the first transistor and the second transistor are turned on, the third transistor is turned off, the high-side power tube is turned off, the low-side power tube is turned on, and the first bootstrap capacitor is configured to charge the second bootstrap capacitor to twice the input voltage via the second diode, and via The third diode charges the third bootstrap capacitor to twice the input voltage, and the fourth transistor is turned off; when the pulse width modulation signal at the modulation signal end is at a high level, the first transistor and the second transistor are turned off, the third transistor is turned on, the high-side power tube is turned on, the low-side power tube is turned off, and the switch node voltage increases; when the switch node voltage increases to a preset threshold, the fourth transistor is turned on, and when the switch node voltage increases to the input voltage, the upper plate voltage of the second bootstrap capacitor is raised to three times the input voltage, wherein the preset threshold is less than the input voltage.

In an optional embodiment of the present disclosure, the DC-DC converter also includes an output circuit, one end of the output circuit is coupled to the switch node, and the output circuit is configured to generate an output voltage; the output circuit includes an inductor, an output capacitor, an equivalent series resistor and an output resistor; the first end of the inductor is coupled to the switch node, the second end of the inductor is respectively coupled to the first end of the equivalent series resistor, the first end of the output resistor and the output voltage end, and the output voltage is generated at the output voltage end according to the inductor current flowing through the inductor; the second end of the equivalent series resistor is coupled to the first end of the output capacitor, and the second end of the output capacitor and the second end of the output resistor are respectively grounded.

In an optional embodiment of the present disclosure,

The pulse width modulated signal is directly output to the control electrode of the high-side power tube; or

The pulse width modulation signal is matched to the level converter of the high-side power tube and is output to the control electrode of the high-side power tube via the level converter.

In an optional implementation of the present disclosure, the second high-side driving voltage is greater than the first high-side driving voltage.

In an optional implementation of the present disclosure, the first diode is a Schottky diode.

In an optional implementation of the present disclosure, the first transistor is an enhancement-mode MOS transistor with P-type compensation.

In an optional implementation of the present disclosure, the fourth transistor is an enhancement MOS transistor with P-type compensation, and the fourth transistor is a high-voltage PMOS transistor.

A second aspect of the present disclosure provides a chip, which includes the DC-DC converter of any one of the first aspects.

A third aspect of the present disclosure provides an electronic device, which includes the chip of the second aspect.

In the DC-DC converter provided by the embodiment of the present disclosure, a charge pump boost circuit is introduced to generate a second boost voltage, which is greater than the first boost voltage provided by the bootstrap boost circuit; the high-side drive circuit outputs the first high-side drive voltage to the control electrode of the high-side power tube according to the first boost voltage, and the charge pump boost circuit outputs the second high-side drive voltage to the control electrode of the high-side power tube according to the second boost voltage, and the output second high-side drive voltage is greater than the first high-side drive voltage, thereby increasing the control electrode voltage of the high-side power tube. The present disclosure generates a second boost voltage greater than the first boost voltage through the charge pump boost circuit, thereby increasing the control electrode voltage of the high-side power tube, so that a smaller bootstrap capacitor obtains a higher gate-source voltage of the high-side power tube, reduces the capacitance value of the built-in bootstrap capacitor of the DC-DC converter, reduces the area of the built-in bootstrap capacitor, and thereby reduces the chip cost, thereby solving the problem that the capacitance value and area of the bootstrap capacitor in the BUCK type DC-DC converter are large, resulting in a high chip cost.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific implementation methods of the present disclosure or the technical solutions in the related technologies, the drawings required for use in the specific implementation methods or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, rather than limitations of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a circuit diagram of a BUCK type DC-DC converter in the related art;

FIG2 is an exemplary block diagram of a DC-DC converter provided by an embodiment of the present disclosure;

FIG3 is an exemplary circuit diagram of a DC-DC converter provided in an embodiment of the present disclosure;

FIG. 4 is an exemplary circuit diagram of a DC-DC converter provided in yet another embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Embodiments, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

In all embodiments of the present disclosure, since the source and drain of the metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of the N-type transistor and the P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle end of the MOS transistor is referred to as the control electrode, and the remaining two ends of the MOS transistor are referred to as the first electrode and the second electrode, respectively. The transistors used in the embodiments of the present disclosure are mainly switching transistors. In addition, for the convenience of unified expression, in the context, the base of the bipolar junction transistor (BJT) is referred to as the control electrode, the emitter of the BJT is referred to as the first electrode, and the collector of the BJT is referred to as the second electrode. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

At present, when NMOS is selected as the power tube in the BUCK type DC-DC converter, a bootstrap capacitor (BST capacitor) is required to power the driving part of the power tube. FIG1 shows a circuit diagram of a low-voltage BUCK type DC-DC converter in the related art, wherein the PWM signal is a pulse width modulation signal, Vin is an input voltage, the input voltage is a low voltage, and the magnitude is 2.5V to 5.5V, Vout is an output voltage, SBD is a Schottky diode, BST and SW respectively represent a bootstrap node and a switch node in the circuit, Cbst is a bootstrap capacitor, Driver_Hside is a high-side driving circuit, HS is a high-side power tube, Driver_Lside is a low-side driving circuit, LS is a low-side power tube, L is an inductor, Cout is an output capacitor, Resr is an equivalent series resistance, and _RL is an output resistance;

In order to obtain a lower on-resistance of the high-side power tube HS, the capacitance value of the bootstrap capacitor Cbst is usually The traditional solution is to add a bootstrap capacitor Cbst. In this case, the chip needs to add a BST pin. In order to avoid adding a BST pin, the bootstrap capacitor Cbst is built-in in the related art.

Since the on-resistance of the MOS tube is inversely proportional to its gate-source voltage Vgs, a higher gate-source voltage Vgs is required to obtain a lower on-resistance of the MOS tube under the same MOS tube area. The gate-source voltage Vgs of the high-side power tube HS in the BUCK type DC-DC converter with built-in bootstrap capacitor Cbst can be obtained by the following calculation method:

1: Assuming that the total charge of the high-side power tube HS is Qt, and the voltage after driving is Vgs, then Qt = Vgs*Cgs, and an equivalent gate capacitance Cgs can be obtained;

2: After the bootstrap capacitor Cbst is charged by the input voltage Vin, the voltage is Vin. Assuming that the driver stage loss is ignored, the bootstrap capacitor Cbst is used directly to provide the driving voltage to the HS gate, a charge sharing process can be obtained:

Vin*Cbst＝Vgs*(Cgs+Cbst), that is, the gate-source voltage Vgs is Vgs＝Vin*Cbst/(Cgs+Cbst);

It can be seen that if Cgs = Cbst, then Vgs = 1/2*Vin can be obtained. If a higher Vgs is to be obtained, a larger bootstrap capacitor Cbst is required;

However, since the capacitance value is proportional to the area of the capacitor plate, the larger the capacitance value of the bootstrap capacitor Cbst, the larger the area of the bootstrap capacitor Cbst. A larger area of the bootstrap capacitor Cbst will result in a higher chip cost.

The inventors have found that in order to reduce the chip cost, it is necessary to reduce or optimize the area of the built-in bootstrap capacitor, reduce or avoid increasing the capacitance value of the bootstrap capacitor Cbst, and obtain a higher high-side power tube HS gate-source voltage Vgs with a smaller bootstrap capacitor Cbst, thereby obtaining a lower high-side power tube HS on-resistance; therefore, how to obtain a higher high-side power tube HS gate-source voltage Vgs with a smaller bootstrap capacitor Cbst is urgently needed.

Regarding the charge sharing process in the above calculation method, if the capacitance of the bootstrap capacitor Cbst is doubled, that is, Cbst = 2*Cgs, then Vgs = 2/3*Vin can be obtained; if the initial voltage of the bootstrap capacitor Cbst is doubled, that is, the initial voltage is 2*Vin, then Vgs = 2*Vin*Cbst/(Cgs+Cbst) = Vin can be obtained, and the gate-source voltage Vgs is also doubled;

Through the above analysis, it can be seen that increasing the initial voltage of the bootstrap capacitor Cbst is more effective than increasing the area of the bootstrap capacitor Cbst for increasing the gate-source voltage Vgs of the high-side power tube HS;

Therefore, the embodiment of the present disclosure adds a built-in second bootstrap capacitor C_BST2 on the basis of the original first bootstrap capacitor C_BST1. Compared with the initial voltage of the original first bootstrap capacitor C_BST1, the initial voltage of the second bootstrap capacitor C_BST2 is increased by the charge pump Chargepump in the charge pump boost circuit. The second bootstrap capacitor C_BST2 uses a higher initial voltage, and can share more charges during the driving process under the same capacitor area, and the driving voltage of the gate of the high-side power tube HS is higher; the embodiment of the present disclosure provides a higher initial voltage for the second bootstrap capacitor C_BST2, so that under the premise of obtaining the same high-side power tube HS gate-source voltage Vgs, the area of the second bootstrap capacitor C_BST2 is smaller, thereby realizing the optimized design of the built-in bootstrap capacitor area, thereby reducing the chip cost.

An embodiment of the present disclosure provides a DC-DC converter, an exemplary block diagram of which is shown in FIG2 , including a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit Driver_Hside, a low-side drive circuit Driver_Lside, a high-side power tube HS, and a low-side power tube LS;

The bootstrap boost circuit is configured to provide a first boost voltage for the high-side driving circuit Driver_Hside based on an input voltage Vin at the input voltage terminal;

The high-side driving circuit Driver_Hside is configured to output a first high-side driving voltage to the control electrode of the high-side power tube HS based on a pulse width modulation PWM signal at the modulation signal end according to the first boost voltage; the PWM signal can be directly output to the control electrode of the high-side power tube HS, and can also be matched to the level converter of the high-side power tube HS, and output to the control electrode of the high-side power tube HS via the level converter, and the control electrode corresponds to the gate of the MOS tube;

The charge pump boost circuit is configured to generate a second boost voltage through a charge pump Charge pump, and output a second high-side driving voltage to the control electrode of the high-side power tube HS according to the second boost voltage, wherein the second boost voltage is greater than the first boost voltage; a second boost voltage greater than the first boost voltage is generated through the charge pump boost circuit, so that a smaller bootstrap capacitor value obtains a higher high-side power tube HS gate-source voltage Vgs, thereby obtaining a lower high-side power tube HS on-resistance; the second high-side driving voltage output to the control electrode of the high-side power tube HS according to the second boost voltage is greater than the gate-source voltage Vgs output to the high-side power tube HS according to the first boost voltage A first high-side driving voltage output by the control electrode;

The low-side driving circuit Driver_Lside is configured to output a low-side driving voltage to the control electrode of the low-side power tube LS based on the pulse width modulation PWM signal at the modulation signal terminal;

The first pole of the high-side power tube HS is coupled to the input voltage terminal, the second pole of the high-side power tube HS is coupled to the first pole of the low-side power tube LS via the switch node, the high-side power tube HS is configured to be turned on or off according to the first high-side driving voltage and the second high-side driving voltage, and the low-side power tube LS is configured to be turned on or off according to the low-side driving voltage; the second pole of the low-side power tube LS is grounded;

One end of the bootstrap boost circuit and one end of the charge pump boost circuit are respectively coupled to a switch node SW.

The DC-DC converter shown in FIG. 2 further includes an output circuit, one end of which is coupled to the switch node SW, and the output circuit is configured to generate an output voltage.

Under the premise of obtaining the same high-side power tube gate-source voltage, the disclosed embodiment can greatly reduce the area of the bootstrap capacitor by increasing the starting voltage through the charge pump in the charge pump boost circuit, obtain the same high-side power tube gate-source voltage with the smallest bootstrap capacitor, realize the optimized design of the built-in bootstrap capacitor area, and reduce the chip cost.

An exemplary circuit diagram of a DC-DC converter provided by an embodiment of the present disclosure is shown in FIG3 , wherein the bootstrap boost circuit includes a first diode D1 and a first bootstrap capacitor C_BST1 ; wherein the first diode D1 may be a Schottky diode;

A first end of the first diode D1 is coupled to the input voltage end, and a second end of the first diode D1 is respectively coupled to a first end of the first bootstrap capacitor C_BST1 and a first end of the high-side driving circuit Driver_Hside via a first bootstrap node BST1;

The second end of the first bootstrap capacitor C_BST1 is respectively coupled to the switch node SW and the second end of the high-side driving circuit Driver_Hside. The first bootstrap capacitor C_BST1 is configured to be charged based on the input voltage Vin when the pulse width modulation PWM signal is at a low level, and to provide a first boost voltage for the high-side driving circuit Driver_Hside when the pulse width modulation PWM signal is at a high level.

The first diode D1 plays a rectifying role. When the pulse width modulation PWM signal is at a high level, the high-side power tube HS is turned on, the low-side power tube LS is turned off, and the voltage at the switch node SW is Vin. The voltage of the upper plate of the bootstrap capacitor C_BST1 is raised to be greater than Vin, and the first diode D1 can prevent the upper plate of the first bootstrap capacitor C_BST1 from discharging to the input voltage terminal.

In FIG3 , the charge pump boost circuit includes a charge pump Charge pump, a unidirectional rectifier circuit, a second bootstrap capacitor C_BST2 and a high-voltage drive circuit;

The charge pump Charge pump is configured to charge the second bootstrap capacitor C_BST2 to N times of the input voltage Vin via a unidirectional rectifier circuit, wherein N is a positive integer greater than 1; under the premise of obtaining the same high-side power tube HS gate-source voltage Vgs, the higher the initial voltage N*Vin charged by the charge pump Charge pump for the second bootstrap capacitor C_BST2, the smaller the area of the second bootstrap capacitor C_BST2;

A first end of the unidirectional rectifier circuit is coupled to a charge pump Charge pump, and a second end of the unidirectional rectifier circuit is respectively coupled to a first end of a second bootstrap capacitor C_BST2 and a first end of a high-voltage drive circuit via a second bootstrap node BST2;

The second end of the second bootstrap capacitor C_BST2 is coupled to the switch node SW, and the second bootstrap capacitor C_BST2 is configured to be charged based on the charge pump Charge pump when the pulse width modulation PWM signal is at a low level, and to provide a second boost voltage for the high voltage driving circuit when the pulse width modulation PWM signal is at a high level and the voltage of the switch node SW rises to the input voltage Vin;

The second end of the high-voltage driving circuit is coupled to the control electrode of the high-side power tube HS, and the high-voltage driving circuit is configured to output a second high-side driving voltage to the control electrode of the high-side power tube HS based on the second boost voltage.

Specifically, when the pulse width modulation PWM signal is at a low level, the charge pump Charge pump charges the second bootstrap capacitor C_BST2; when the pulse width modulation PWM signal is at a high level, the first bootstrap capacitor C_BST1 initially supplies power to the high-side drive circuit Driver_Hside, providing the high-side drive circuit Driver_Hside with a first boost voltage, thereby driving the high-side power tube HS, so that the high-side power tube HS is turned on, the low-side power tube LS is turned off, the voltage at the switch node SW starts to rise, and the voltage at the first bootstrap node BST1 and the voltage at the second bootstrap node BST2 are gradually raised;

When the pulse width modulation PWM signal is at a high level and the voltage at the switch node SW rises to Vin, the second bootstrap capacitor C_BST2 supplies power to the high-voltage drive circuit, providing the high-voltage drive circuit with a second boost voltage, and the high-voltage drive circuit then outputs the second high-side drive voltage to the control electrode of the high-side power tube HS. The high-side power tube HS is driven to raise the voltage at the first bootstrap node BST1 and the voltage at the second bootstrap node BST2 by 1 Vin.

In an optional embodiment of the present disclosure, the unidirectional rectifier circuit includes a unidirectional conduction switch tube. The unidirectional rectifier circuit can be a unidirectional conduction switch tube controlled by appropriate logic.

In Fig. 3, the unidirectional rectifying circuit includes a second diode D2. The unidirectional rectifying circuit may also be the second diode D2.

In FIG3 , the output circuit includes an inductor L, an output capacitor Cout, an equivalent series resistor Resr and an output resistor _RL ; wherein the equivalent series resistor Resr is a parasitic resistor of the output capacitor Cout;

A first end of the inductor L is coupled to the switch node SW, a second end of the inductor L is respectively coupled to a first end of an equivalent series resistor Resr, a first end of an output resistor _RL and an output voltage end, and an output voltage Vout is generated at the output voltage end according to an inductor current flowing through the inductor L;

A second end of the equivalent series resistor Resr is coupled to a first end of the output capacitor Cout, and a second end of the output capacitor Cout and a second end of the output resistor _RL are grounded respectively.

The working principle of the DC-DC converter is described below with reference to the exemplary circuit diagram of the DC-DC converter in FIG. 3 .

During the Toff period, the PWM signal is at a low level, the high-side power tube HS is turned off, the low-side power tube LS is turned on, the voltage at the switch node SW is 0, and the charge pump Chargepump charges the second bootstrap capacitor C_BST2 to N*Vin, where N is a positive number greater than 1, such as 2, 3, 4 or 5; wherein, under the premise of obtaining the same gate-source voltage Vgs of the high-side power tube HS, the higher the initial voltage N*Vin charged by the charge pump Chargepump for the second bootstrap capacitor C_BST2, the smaller the area of the second bootstrap capacitor C_BST2;

During the Ton period, the PWM signal is at a high level, the high-side power tube HS is turned on, and the low-side power tube LS is turned off. Initially, the first bootstrap capacitor C_BST1 provides the first boost voltage for the high-side drive circuit Driver_Hside to power the high-side drive circuit Driver_Hside. The high-side drive circuit Driver_Hside outputs the first high-side drive voltage to the gate of the high-side power tube HS until the voltage at the switch node SW rises. To Vin, at this time, the second bootstrap capacitor C_BST2 provides a second boost voltage for the high-voltage drive circuit to power the high-voltage drive circuit, and the high-voltage drive circuit outputs a second high-side drive voltage to the gate of the high-side power tube HS.

On the premise of obtaining the same high-side power tube HS gate-source voltage Vgs, the second bootstrap capacitor C_BST2 is charged to N*Vin through the charge pump Chargepump to increase the starting voltage of the second bootstrap capacitor C_BST2, which can greatly reduce the area of the second bootstrap capacitor C_BST2. The same high-side power tube HS gate-source voltage Vgs is obtained with the smallest second bootstrap capacitor C_BST2, thereby realizing the optimized design of the area of the built-in second bootstrap capacitor C_BST2, that is, completing the optimized design of the area of the built-in bootstrap capacitor.

In an optional embodiment of the present disclosure, for the initial voltage N*Vin for charging the second bootstrap capacitor C_BST2, when N is 3, an exemplary circuit diagram of the DC-DC converter is shown in FIG4 , wherein the charge pump Charge pump includes a digital receiver DR, a first transistor P1, a second transistor P2, and a third transistor P3;

Specifically, the first transistor P1 is an enhanced MOS tube with P-type compensation, which separates the P-type background region and the N-type channel region, thereby preventing the reverse breakdown of the PN junction and improving the stability and controllability of the MOS tube;

A first terminal of the digital receiver DR is coupled to the modulation signal terminal, a second terminal of the digital receiver DR is coupled to the bootstrap control signal terminal, a third terminal of the digital receiver DR is coupled to the control electrode of the first transistor P1, and a fourth terminal of the digital receiver DR is coupled to the control electrode of the second transistor P2. The digital receiver DR is configured to control the first transistor P1 and the second transistor P2 to be turned on or off according to the pulse width modulation PWM signal of the modulation signal terminal and the bootstrap control signal BST_Control of the bootstrap control signal terminal;

The first electrode of the first transistor P1 is respectively coupled to the first electrode of the second transistor P2, the first electrode of the third transistor P3 and the second end of the first bootstrap capacitor C_BST1, the second electrode of the first transistor P1 is respectively coupled to the input voltage end and the first end of the first diode D1, and the second electrode of the second transistor P2 is grounded;

The control electrode of the third transistor P3 is coupled to the modulation signal terminal, the second electrode of the third transistor P3 is coupled to the switch node SW, and the pulse width modulation PWM signal of the modulation signal terminal controls the switch of the third transistor P3. Enable or disable.

In FIG4 , the high-voltage driving circuit includes a fourth transistor P4, a third diode D3, a fourth diode D4 and a third bootstrap capacitor C_BST3; wherein the fourth transistor P4 is an enhanced MOS tube with P-type compensation, which separates the P-type background region and the N-type channel region, thereby preventing the reverse breakdown of the PN junction and improving the stability and controllability of the MOS tube; and the fourth transistor P4 is a high-voltage PMOS tube (HVPMOS tube); in the embodiment of the present disclosure, it is assumed that the forward voltage drop of each diode is 0. When the application scenario requires accurate calculation, the forward voltage drop of each diode can be assigned a value;

A first end of the third bootstrap capacitor C_BST3 is respectively coupled to the second end of the third diode D3, the first end of the fourth diode D4 and the control electrode of the fourth transistor P4, a second end of the third bootstrap capacitor C_BST3 is grounded, and the third bootstrap capacitor C_BST3 is configured to output a signal to the control electrode of the fourth transistor P4;

A first electrode of the fourth transistor P4 is coupled to the control electrode of the high-side power transistor HS, a second electrode of the fourth transistor P4 is coupled to the second bootstrap node BST2, and the fourth transistor P4 is configured to be turned on or off according to a voltage difference between a control electrode voltage and a second electrode voltage of the fourth transistor P4;

A first end of the third diode D3 is coupled to the first bootstrap node BST1 and a first end of the second diode D2 , respectively. A second end of the fourth diode D4 is coupled to the second end of the second diode D2 and the second bootstrap node BST2 , respectively.

In an optional embodiment of the present disclosure, when the pulse width modulation PWM signal at the modulation signal end is at a low level, the bootstrap control signal BST_Control at the bootstrap control signal end is a square wave signal, the first transistor P1 and the second transistor P2 are turned on, the third transistor P3 is turned off, the high-side power tube HS is turned off, the low-side power tube LS is turned on, the first bootstrap capacitor C_BST1 is configured to charge the second bootstrap capacitor C_BST2 to twice the input voltage Vin via the second diode D2, and charge the third bootstrap capacitor C_BST3 to twice the input voltage Vin via the third diode D3, and the fourth transistor P4 is turned off;

When the pulse width modulation PWM signal at the modulation signal end is at a high level, the first transistor P1 and the second transistor P2 are turned off, the third transistor P3 is turned on, the high-side power tube HS is turned on, the low-side power tube LS is turned off, and the voltage of the switch node SW increases; when the voltage of the switch node SW increases to a preset threshold, the fourth transistor P3 is turned on. The transistor P4 is turned on, and when the voltage of the switch node SW increases to the input voltage Vin, the upper plate voltage of the second bootstrap capacitor C_BST2 is raised to 3 times of the input voltage Vin, wherein the preset threshold is less than the input voltage Vin.

The working principle of the DC-DC converter is described below with reference to the exemplary circuit diagram of the DC-DC converter in FIG. 4 .

In FIG4 , it is assumed that the forward voltage drop of each diode is 0. When the application scenario requires accurate calculation of the forward voltage drop of each diode, the forward voltage drop of each diode can be assigned a value. In the low-voltage BUCK DC-DC converter, the input voltage Vin is 2.5V to 5V. For the initial voltage N*Vin charged to the second bootstrap capacitor C_BST2, when the initial voltage N*Vin is 3*Vin, the working principle of the DC-DC converter is:

During the Toff period, the PWM signal is at a low level, the bootstrap control signal BST_Control is set to a square wave signal, the first transistor P1 and the second transistor P2 are turned on, the third transistor P3 is turned off, the high-side power tube HS is turned off, and the low-side power tube LS is turned on; the first bootstrap capacitor C_BST1 charges the second bootstrap capacitor C_BST2 and the third bootstrap capacitor C_BST3 to 2*Vin, the upper plate voltages of the second bootstrap capacitor C_BST2 and the third bootstrap capacitor C_BST3 are both the voltage at the first bootstrap node BST1, that is, 2*Vin, the third bootstrap capacitor C_BST3 controls the gate voltage Vg of the fourth transistor P4, and the gate-source voltage Vgs of the fourth transistor P4 is 0, so it is always in a closed state;

At the beginning of Ton, after the PWM signal changes from a low level to a high level, the first transistor P1 and the second transistor P2 are turned off, and the third transistor P3 is turned on. The first bootstrap capacitor C_BST1 supplies power to the driving stage of the high-side power tube HS, thereby outputting a driving voltage to the gate of the high-side power tube HS, the high-side power tube HS is turned on, the low-side power tube LS is turned off, and the voltage at the switch node SW gradually increases until it increases to Vin; while the voltage at the switch node SW increases, the voltage at the second bootstrap node BST2 is raised. When the voltage at the second bootstrap node BST2 is higher than the gate voltage Vg of the third transistor P4 by a preset threshold value Vgs(th), the fourth transistor P4 is turned on, and the second bootstrap capacitor C_BST2 outputs a driving voltage to the gate of the high-side power tube HS. The voltage at the second bootstrap node BST2 can reach up to 3*Vin. At this time, the upper plate voltage of the second bootstrap capacitor C_BST2 is raised to 3*Vin, and the upper plate voltage of the third bootstrap capacitor C_BST3 is still 2*Vin.

The disclosed embodiment adopts an extremely simple circuit structure to meet the requirement of 3*Vin to provide driving voltage for the high-side power tube HS. Under the premise of obtaining the same gate-source voltage Vgs of the high-side power tube HS, the area of the bootstrap capacitor Cbst can be greatly reduced to reduce the chip cost.

The embodiment of the present disclosure also provides a chip, which includes a DC-DC converter according to the embodiment of the present disclosure, and the chip can be a chip with embedded efuse IP.

The embodiment of the present disclosure further provides an electronic device, which includes the chip according to the embodiment of the present disclosure. The electronic device may be a programming device.

From the above description, it can be seen that the present disclosure achieves the following technical effects:

The present invention generates a second boost voltage greater than the first boost voltage through a charge pump boost circuit, thereby increasing the control electrode voltage of the high-side power tube, so that a smaller bootstrap capacitor obtains a higher gate-source voltage of the high-side power tube, thereby reducing the capacitance value of the built-in bootstrap capacitor of the DC-DC converter, reducing the area of the built-in bootstrap capacitor, and thus reducing the chip cost, thereby solving the problem that the capacitance value and area of the bootstrap capacitor in the BUCK type DC-DC converter are large, resulting in a higher chip cost;

Under the premise of obtaining the same high-side power tube gate-source voltage, the present invention can reduce the capacitance value of the bootstrap capacitor by increasing the starting voltage of the bootstrap capacitor through a charge pump. Since the capacitance value is proportional to the area of the capacitor plate, the area of the bootstrap capacitor can be reduced, the area of the built-in bootstrap capacitor can be optimized, and the chip cost can be reduced.

The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the device and method according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, a program segment or an instruction, and a part of a module, a program segment or an instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and/or flow chart, and the combination of the square boxes in the block diagram and/or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of special hardware and computer instructions.

Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is placed after a group of terms, "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

Further aspects and scopes become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present disclosure.

Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations are all within the scope defined by the appended claims.

Claims (16)

A DC-DC converter comprises a bootstrap boost circuit, a charge pump boost circuit, a high-side drive circuit, a low-side drive circuit, a high-side power tube and a low-side power tube; The bootstrap boost circuit is configured to provide a first boost voltage to the high-side drive circuit based on an input voltage at the input voltage terminal; The high-side driving circuit is configured to output a first high-side driving voltage to the control electrode of the high-side power tube according to the first boost voltage based on the pulse width modulation signal at the modulation signal terminal; The charge pump boost circuit is configured to generate a second boost voltage through a charge pump, and output a second high-side driving voltage to the control electrode of the high-side power tube according to the second boost voltage, wherein the second boost voltage is greater than the first boost voltage; The low-side driving circuit is configured to output a low-side driving voltage to the control electrode of the low-side power tube based on the pulse width modulation signal of the modulation signal terminal; The first pole of the high-side power tube is coupled to the input voltage terminal, the second pole of the high-side power tube is coupled to the first pole of the low-side power tube via a switch node, the high-side power tube is configured to be turned on or off according to the first high-side driving voltage and the second high-side driving voltage, and the low-side power tube is configured to be turned on or off according to the low-side driving voltage; One end of the bootstrap boost circuit and one end of the charge pump boost circuit are respectively coupled to the switch node. The DC-DC converter according to claim 1, wherein the bootstrap boost circuit comprises a first diode and a first bootstrap capacitor; A first end of the first diode is coupled to the input voltage end, and a second end of the first diode is respectively coupled to a first end of the first bootstrap capacitor and a first end of the high-side driving circuit via a first bootstrap node; The second end of the first bootstrap capacitor is respectively coupled to the switch node and the second end of the high-side drive circuit, and the first bootstrap capacitor is configured to be charged based on the input voltage when the pulse width modulation signal is at a low level, and to provide a first boost voltage for the high-side drive circuit when the pulse width modulation signal is at a high level. The DC-DC converter according to claim 2, wherein the charge pump boost circuit comprises the charge pump, a unidirectional rectifier circuit, a second bootstrap capacitor and a high-voltage drive circuit; The charge pump is configured to charge the second bootstrap capacitor to N times the input voltage via the unidirectional rectifier circuit, wherein N is a positive integer greater than 1; A first end of the unidirectional rectifying circuit is coupled to the charge pump, and a second end of the unidirectional rectifying circuit is coupled to a first end of the second bootstrap capacitor and a first end of the high-voltage driving circuit via a second bootstrap node; The second end of the second bootstrap capacitor is coupled to the switch node, and the second bootstrap capacitor is configured to be charged based on the charge pump when the pulse width modulation signal is at a low level, and to provide a second boost voltage for the high-voltage driving circuit when the pulse width modulation signal is at a high level and the voltage of the switch node rises to the input voltage; The second end of the high-voltage driving circuit is coupled to the control electrode of the high-side power tube, and the high-voltage driving circuit is configured to output the second high-side driving voltage to the control electrode of the high-side power tube based on the second boost voltage. The DC-DC converter according to claim 3, wherein the unidirectional rectifying circuit comprises a unidirectional conducting switch tube. The DC-DC converter according to claim 3, wherein the unidirectional rectifying circuit comprises a second diode. The DC-DC converter according to claim 5, wherein when N is 3, the charge pump comprises a digital receiver, a first transistor, a second transistor, and a third transistor; A first terminal of the digital receiver is coupled to the modulation signal terminal, a second terminal of the digital receiver is coupled to the bootstrap control signal terminal, a third terminal of the digital receiver is coupled to the control electrode of the first transistor, and a fourth terminal of the digital receiver is coupled to the control electrode of the second transistor. The digital receiver is configured to control the opening or closing of the first transistor and the second transistor according to the pulse width modulation signal of the modulation signal terminal and the bootstrap control signal of the bootstrap control signal terminal; The first electrode of the first transistor is respectively coupled to the first electrode of the second transistor, the first electrode of the third transistor and the second end of the first bootstrap capacitor, the second electrode of the first transistor is respectively coupled to the input voltage end and the first end of the first diode, and the second electrode of the second transistor is grounded; The control electrode of the third transistor is coupled to the modulation signal terminal, the second electrode of the third transistor is coupled to the switch node, and the pulse width modulation signal of the modulation signal terminal controls the on or off of the third transistor. The DC-DC converter according to claim 6, wherein the high voltage driving circuit comprises a fourth transistor, a third diode, a fourth diode and a third bootstrap capacitor; The first end of the third bootstrap capacitor is respectively coupled to the second end of the third diode, the first end of the fourth diode and the control electrode of the fourth transistor, the second end of the third bootstrap capacitor is grounded, and the third bootstrap capacitor is configured to output a signal to the control electrode of the fourth transistor; A first electrode of the fourth transistor is coupled to the control electrode of the high-side power transistor, a second electrode of the fourth transistor is coupled to the second bootstrap node, and the fourth transistor is configured to be turned on or off according to a voltage difference between a control electrode voltage and a second electrode voltage of the fourth transistor; A first end of the third diode is coupled to the first bootstrap node and a first end of the second diode, respectively. A second end of the fourth diode is coupled to the second end of the second diode and the second bootstrap node, respectively. The DC-DC converter according to claim 7, wherein: When the pulse width modulation signal at the modulation signal end is at a low level, the bootstrap control signal at the bootstrap control signal end is a square wave signal, the first transistor and the second transistor are turned on, the third transistor is turned off, the high-side power tube is turned off, the low-side power tube is turned on, the first bootstrap capacitor is configured to charge the second bootstrap capacitor to twice the input voltage via the second diode, and to charge the third bootstrap capacitor to twice the input voltage via the third diode, and the fourth transistor is turned off; When the pulse width modulation signal at the modulation signal end is at a high level, the first transistor and the second transistor are turned off, the third transistor is turned on, the high-side power tube is turned on, the low-side power tube is turned off, and the switch node voltage increases; when the switch node voltage increases to a preset threshold, the fourth transistor is turned on, and when the switch node voltage increases to the input voltage, the upper plate voltage of the second bootstrap capacitor is raised to 3 times the input voltage, wherein the preset threshold is less than the input voltage. The DC-DC converter according to claim 1, wherein the DC-DC converter further comprises an output circuit, one end of the output circuit is coupled to the switch node, and the output circuit is configured to generate an output voltage; The output circuit includes an inductor, an output capacitor, an equivalent series resistor and an output resistor; The first end of the inductor is coupled to the switch node, the second end of the inductor is respectively coupled to the first end of the equivalent series resistor, the first end of the output resistor and the output voltage end, and an output voltage is generated at the output voltage end according to the inductor current flowing through the inductor; The second end of the equivalent series resistor is coupled to the first end of the output capacitor, and the second end of the output capacitor and the second end of the output resistor are grounded respectively. The DC-DC converter according to claim 1, wherein: The pulse width modulation signal is directly output to the control electrode of the high-side power tube; or The pulse width modulation signal is matched to the level converter of the high-side power tube, and is output to the control electrode of the high-side power tube via the level converter. The DC-DC converter according to claim 1, wherein the second high-side driving voltage is greater than the first high-side driving voltage. The DC-DC converter according to claim 2, wherein the first diode is a Schottky diode. The DC-DC converter according to claim 6, wherein the first transistor is an enhancement mode MOS transistor with P-type compensation. The DC-DC converter according to claim 7, wherein the fourth transistor is an enhancement MOS transistor with P-type compensation, and the fourth transistor is a high-voltage PMOS transistor. A chip comprising the DC-DC converter according to any one of claims 1 to 14. An electronic device comprising the chip according to claim 15.