WO2025063259A1 - Template substrate, method for producing same, semiconductor substrate, method for producing same, apparatus for producing template substrate, and method for producing semiconductor device - Google Patents

Abstract

The present invention reduces the silicon concentration of a nitride semiconductor region when the nitride semiconductor region is formed by using a template substrate. This template substrate comprises: a base substrate; a mask pattern located on the base substrate and including a silicon-containing silicon-based mask and a first opening; an aluminum-containing semiconductor mask located on the silicon-based mask; and a seed part having an Al-based semiconductor layer that includes a main component of the semiconductor mask and overlaps the first opening.

Description

Template substrate and method for manufacturing same, semiconductor substrate and method for manufacturing same, template substrate manufacturing apparatus, and method for manufacturing semiconductor device

This disclosure relates to template substrates, etc.

Patent Document 1 discloses a method (ELO method) in which a mask pattern including a mask portion and an opening is formed on a base substrate including a seed layer, and a nitride semiconductor layer is grown laterally on the mask portion, using the seed layer exposed in the opening as the growth starting point.

Japanese Patent Application Publication No. 2013-251304

In one embodiment of the present disclosure, the template substrate comprises a base substrate, a mask pattern located on the base substrate and including a first mask containing silicon and a first opening, a second mask located on the first mask and including aluminum and a semiconductor, and a seed portion having a semiconductor layer that contains the main component of the second mask and overlaps the first opening.

FIG. 1 is a cross-sectional view illustrating a configuration of a template substrate according to an embodiment of the present disclosure. FIG. 2 is a plan view illustrating a configuration of a template substrate according to an embodiment of the present disclosure. 1 is a flowchart illustrating an example of a method for manufacturing a template substrate according to an embodiment of the present disclosure. 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a template substrate according to an embodiment of the present disclosure. FIG. 1 is a block diagram showing a template substrate manufacturing apparatus according to an embodiment of the present disclosure. 1 is a cross-sectional view illustrating a configuration of a semiconductor substrate according to an embodiment of the present disclosure. FIG. 1 is a plan view illustrating a configuration of a semiconductor substrate according to an embodiment of the present disclosure. 1 is a flowchart illustrating an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. 1 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 1 is a cross-sectional view illustrating a schematic configuration of a template substrate in Example 1. FIG. FIG. 2 is a cross-sectional view showing an example of the configuration of a base substrate. 1 is a cross-sectional view showing an example of the configuration of a template substrate. FIG. 2 is a cross-sectional view showing an example of lateral growth of a nitride semiconductor portion. FIG. 11 is a cross-sectional view illustrating a schematic configuration of a template substrate in Example 2. FIG. 11 is a cross-sectional view illustrating a schematic configuration of a template substrate in Example 3. FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor substrate according to a fourth embodiment. FIG. 13 is a plan view illustrating a schematic configuration of a semiconductor substrate according to a fourth embodiment. 11A to 11C are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate in Example 4. FIG. 13 is a cross-sectional view showing another configuration of a semiconductor substrate in the fourth embodiment. FIG. 13 is a cross-sectional view showing another configuration of a semiconductor substrate in the fifth embodiment. FIG. 13 is a cross-sectional view showing another configuration of a semiconductor substrate in the fifth embodiment. FIG. 13 is a cross-sectional view showing another configuration of a semiconductor substrate in the fifth embodiment. 13A to 13C are plan views showing an example of a method for manufacturing a semiconductor substrate and a semiconductor device according to a sixth embodiment. 13A to 13C are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate and a semiconductor device according to a sixth embodiment. FIG. 1 is a schematic diagram illustrating a configuration example of an electronic device. FIG. 13 is a schematic diagram showing another configuration example of the electronic device.

[Template substrate]
FIG. 1 is a cross-sectional view showing the configuration of a template substrate in an embodiment of the present disclosure. FIG. 2 is a plan view showing the configuration of a template substrate in an embodiment of the present disclosure. As shown in FIG. 1 and FIG. 2, the template substrate TS includes a base substrate BS, a mask pattern 6 including a silicon-based mask 5 (sometimes referred to as a first mask) and a first opening K1, a semiconductor mask SM (sometimes referred to as a second mask) including aluminum and a semiconductor, and a seed portion S including a semiconductor layer AS including a main component of the semiconductor mask SM and overlapping with the first opening K1. In the following, a case where the main component of the semiconductor mask SM is a semiconductor including aluminum will be described. The semiconductor layer AS in this case will be referred to as an aluminum-based semiconductor layer AS (hereinafter, abbreviated as an Al-based semiconductor layer AS). The main component refers to the component (molecule, single atom) of a member that has the maximum content (molar number) (when the member has only one component, that component). The semiconductor mask SM may be mainly composed of a nitride semiconductor, and the semiconductor mask SM and the Al-based semiconductor layer AS may contain aluminum gallium nitride (regardless of the composition ratio of gallium and aluminum) or may contain aluminum nitride as the main component. By using the template substrate TS, a nitride semiconductor portion with a low silicon concentration can be obtained.

In the template substrate TS of this embodiment, the seed portion S may include a covering layer C that includes a nitride semiconductor and covers the upper surface AST of the Al-based semiconductor layer AS. The template substrate TS can be used to grow a GaN-based semiconductor by, for example, an ELO (Epitaxial Lateral Overgrowth) method to form a semiconductor portion (nitride semiconductor portion) that includes a nitride semiconductor. The template substrate TS can also be referred to as a growth substrate.

Nitride semiconductors can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors that contain gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

The mask pattern 6 may include a first opening K1 and a second opening K2 adjacent to each other in the first direction (X direction), and a silicon-based mask 5 located between the first opening K1 and the second opening K2. The template substrate TS may have a first seed portion S1 overlapping the first opening K1 and a second seed portion S2 overlapping the second opening K2 located on a base substrate BS. In the template substrate TS of this embodiment, the first seed portion S1 may include a first covering layer C1 covering the upper surface AST of the first Al-based semiconductor layer AS1, and the second seed portion S2 may include a second covering layer C2 covering the upper surface AST of the second Al-based semiconductor layer AS2.

In the following, the first opening K1 and the second opening K2 may be collectively referred to as opening K, the first Al-based semiconductor layer AS1 and the second Al-based semiconductor layer AS2 as Al-based semiconductor layer AS, the first seed portion S1 and the second seed portion S2 as seed portion S, and the first covering layer C1 and the second covering layer C2 as covering layer C.

In the template substrate TS shown in FIG. 1, multiple layers are stacked on the main substrate 1, and the stacking direction (thickness direction) can be considered to be the "upward direction" (Z direction). In other words, the direction from the base substrate BS to the semiconductor mask SM is considered to be "upward." In addition, viewing a substrate-shaped object such as the template substrate TS with a line of sight parallel to the substrate normal (including perspective cases) can be referred to as a "planar view."

In FIG. 1, the mask pattern 6 has a first opening K1 and a second opening K2 whose longitudinal direction is a second direction (Y direction) perpendicular to the first direction (X direction). The number and shape of the openings K in the mask pattern 6 are not particularly limited. The mask pattern 6 may have a plurality of openings K periodically arranged in the <11-20> direction (a-axis direction) of the nitride semiconductor.

In the example shown in FIG. 1, the base substrate BS may include a main substrate 1 and an underlayer 4 located on the main substrate 1. The template substrate TS may include an Al-based semiconductor layer AS located on the underlayer 4.

The base substrate BS is a substrate that serves as a support base (base) for various upper layers. The main substrate 1 may be, for example, a heterogeneous substrate having a lattice constant different from that of a nitride semiconductor. Examples of the heterogeneous substrate include a silicon substrate, a silicon carbide substrate, a sapphire substrate, an aluminum nitride substrate, and a _ScAlMgO4 substrate.

1, for example, aluminum nitride is used for the underlayer 4, an inorganic compound film containing silicon is used for the silicon-based mask 5, the underlayer 4 is exposed in the opening K, and a seed portion S is provided at a position overlapping the opening K in a planar view. Using the ELO method, a nitride semiconductor can be grown laterally (X direction) above the semiconductor mask SM located on the silicon-based mask 5, with the seed portion S as the growth starting point. The surface of the seed portion S may be the seed region J (growth starting point of the semiconductor layer), and the surface (upper surface SMT) of the semiconductor mask SM may be the growth inhibition region DA. The growth inhibition region DA and the seed portion S may be aligned in the a-axis direction of the nitride semiconductor. The width (length in the a-axis direction) of the growth inhibition region DA may be five times or more the width (length in the a-axis direction) of the upper surface of the seed portion S.

The underlayer 4 has a function of, for example, reducing the melting of the main substrate 1 and the seed portion S when they come into contact with each other. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is located on the surface of the seed portion S facing the main substrate 1, the silicon substrate and the GaN-based semiconductor melt when they come into contact with each other, so by providing the underlayer 4 between them, melting is reduced. The underlayer 4 may have at least one of the effects of increasing the crystallinity of the seed portion S and the effect of alleviating the internal stress of the seed portion S. The underlayer 4 may have a single layer structure, a multilayer structure, or a multilayer structure including a periodic structure. For example, a GaN-based semiconductor containing Al, aluminum nitride (AlN), and silicon carbide (SiC) may be used for the underlayer 4.

In one embodiment, the template substrate TS may have a main substrate 1 that is a silicon wafer, a silicon carbide wafer, or a sapphire wafer, and an underlayer 4 that includes aluminum nitride. The template substrate TS may have a mask pattern 6 that includes a second opening K2, and a silicon-based mask 5 and a semiconductor mask SM that are located between the first opening K1 and the second opening K2 in a plan view.

The silicon-based mask 5 may be, for example, a silicon oxide film or a silicon nitride film. Silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxide (SiO ₂ ), silicon oxynitride (SiON), etc. may be used as the material of the silicon-based mask 5. The silicon-based mask 5 may be a single layer film of these materials, or may be a multilayer film (laminate film) that combines these materials.

The Al-based semiconductor layer AS and the semiconductor mask SM may be formed, for example, after forming a mask pattern 6 on the base substrate BS, as follows. That is, a film formation process is performed using a raw material gas of a material (a material containing aluminum) that is relatively easy to grow crystals on the surface of the base substrate BS exposed at the opening K, but is relatively difficult to grow crystals on the silicon-based mask 5. The Al-based semiconductor layer AS may be formed with high crystallinity by the crystal growth of the material on the surface of the base substrate BS exposed at the opening K, while the semiconductor mask SM may be formed with low crystallinity by the deposition of the material on the silicon-based mask 5. The Al-based semiconductor layer AS and the semiconductor mask SM may be formed by a sputtering method or the like.

While the Al-based semiconductor layer AS and the semiconductor mask SM have the same main component, their properties differ due to the different conditions during growth as described above. Therefore, the Al-based semiconductor layer AS may be thicker than the semiconductor mask SM. The Al-based semiconductor layer AS may have a thickness of, for example, 10 nm or more, or may have a thickness of 50 nm or more, and the upper limit of the thickness may be, for example, 1000 nm. The semiconductor mask SM may have a thickness of, for example, about 10 nm, or may have a thickness of 1 nm or more, and the upper limit of the thickness may be, for example, 100 nm. The ratio of the thickness of the Al-based semiconductor layer AS to the thickness of the semiconductor mask SM may be 5 or more, or may be 10 to 200.

The semiconductor mask SM is formed on the silicon-based mask 5 on which crystal growth is difficult, and thus has a rougher surface than the Al-based semiconductor layer AS and the silicon-based mask 5. Therefore, the surface roughness of the semiconductor mask SM may be greater than that of the Al-based semiconductor layer AS. The surface roughness of the semiconductor mask SM may be greater than that of the silicon-based mask 5. The semiconductor mask SM may have a lower crystallinity than the Al-based semiconductor layer AS. The semiconductor mask SM may include an amorphous structure. The surface roughness of the semiconductor mask SM and the Al-based semiconductor layer AS can be evaluated, for example, by capturing an electron microscope (TEM, etc.) image of a cross section perpendicular to the X-direction or Y-direction of the template substrate TS and based on the image. For example, it can be confirmed by image analysis that the surface roughness of the semiconductor mask SM on the template substrate TS is greater than that of the Al-based semiconductor layer AS. It can also be confirmed that the surface roughness of the semiconductor mask SM on the template substrate TS is greater than that of the silicon-based mask 5.

The Al-based semiconductor layer AS may be shaped to fill the first opening K1. Since the Al-based semiconductor layer AS is shaped to fill the opening K, the upper surface AST of the Al-based semiconductor layer AS may be higher than the upper surface 5T of the silicon-based mask 5. In the template substrate TS, the semiconductor mask SM and the Al-based semiconductor layer AS may be connected to each other. The relative positional relationship between the upper surface AST of the Al-based semiconductor layer AS and the upper surface 5T of the silicon-based mask 5 may change depending on the thickness of the silicon-based mask 5. In the example shown in FIG. 1, the upper surface AST of the Al-based semiconductor layer AS is higher than the upper surface 5T of the silicon-based mask 5, but this is not limited thereto, and the upper surface AST of the Al-based semiconductor layer AS may be lower than the upper surface 5T of the silicon-based mask 5. The semiconductor mask SM and the Al-based semiconductor layer AS may be connected to each other by forming the semiconductor mask SM on the sidewall of the silicon-based mask 5 that forms the opening K.

In the template substrate TS of FIG. 1, the upper surface of the seed portion S may be the upper surface CT of the covering layer C. Not limited to the example shown in FIG. 1, the template substrate TS may not have a covering layer C, in which case the upper surface of the seed portion S may be the upper surface AST of the Al-based semiconductor layer AS. In addition, the template substrate TS may have a covering layer C that connects to the surface of the base substrate BS exposed at the opening K, and the Al-based semiconductor layer AS may be located on the covering layer C.

In the template substrate TS, the top surface (top surface CT or top surface AST) of the seed portion S may be located higher than the top surface SMT of the semiconductor mask SM. The relative positional relationship between the top surface AST of the Al-based semiconductor layer AS and the top surface SMT of the semiconductor mask SM may vary depending on the thickness of the silicon-based mask 5. By providing the seed portion S with the covering layer C, it is possible to easily position the top surface (top surface CT or top surface AST) of the seed portion S higher than the top surface SMT of the semiconductor mask SM.

The surface roughness of the coating layer C may be smaller than the surface roughness of the Al-based semiconductor layer AS. The smaller surface roughness of the coating layer C makes it easier to effectively improve the quality of the semiconductor layer that grows from the seed portion S as a growth starting point. In a plan view, the coating layer C may be contained within the opening K, or may protrude slightly laterally from the opening K. As described above, the surface roughness of the coating layer C and the Al-based semiconductor layer AS can also be evaluated based on an electron microscope (TEM, etc.) image taken of a cross section perpendicular to the X-direction or Y-direction of the template substrate TS, for example.

The coating layer C may not contain aluminum, or may have a lower aluminum content than the Al-based semiconductor layer AS. The coating layer C may be made of a material that grows on the Al-based semiconductor layer AS and that serves as the growth starting point for the semiconductor layer. For the coating layer C, for example, a GaN-based semiconductor such as GaN, AlGaN, AlInN, or AlGaInN may be used. The method for forming the coating layer C is not particularly limited, and for example, the coating layer C may be formed using the MOCVD method, the sputtering method, the PSD (Pulse Sputter Deposition) method, or the laser ablation method.

The covering layer C may be thicker than the Al-based semiconductor layer AS. Since the semiconductor mask SM is formed with the formation of the Al-based semiconductor layer AS, when the thickness of the Al-based semiconductor layer AS is increased, the thickness of the semiconductor mask SM also increases. If the thick semiconductor mask SM interferes with the lateral growth of the semiconductor layer starting from the seed portion S, the quality of the semiconductor layer may be reduced. By adjusting the height of the upper surface of the seed portion S with the covering layer C, the thickness of the Al-based semiconductor layer AS can be made relatively thin, and as a result, the thickness of the semiconductor mask SM can be made relatively thin. The covering layer C may have a thickness of, for example, 10 nm or more, or may have a thickness of 100 nm or more, and the upper limit of the thickness may be, for example, 3 μm. The ratio of the thickness of the covering layer C to the thickness of the Al-based semiconductor layer AS may be greater than 1, and may be 1.5 to 100.

When the template substrate TS in this embodiment is used to grow a semiconductor layer laterally using the seed portion S as the growth starting point, the semiconductor mask SM is positioned on the silicon-based mask 5, so that the amount of silicon incidentally incorporated (autodoped) into the semiconductor layer from the silicon-based mask 5 can be effectively reduced.

The constituent materials of the Al-based semiconductor layer AS and the semiconductor mask SM may not contain silicon or may be substantially free of silicon. With respect to a certain material, "substantially free of silicon" means that a small amount of silicon may be unavoidably mixed into the material due to inevitable impurities in the source gas and contamination in the film forming apparatus. Furthermore, the constituent materials of the Al-based semiconductor layer AS and the semiconductor mask SM may contain silicon within an acceptable concentration range as long as they have the function of reducing the amount of silicon taken into the semiconductor layer from the silicon-based mask 5 by the semiconductor mask SM being positioned on the silicon-based mask 5. For example, the constituent materials of the Al-based semiconductor layer AS and the semiconductor mask SM may contain 1% or less silicon in molar ratio in the composition.

The silicon-based mask 5 may include at least one of silicon nitride and silicon oxide, and the semiconductor mask SM and the Al-based semiconductor layer AS may include aluminum gallium nitride. In aluminum gallium nitride, the composition ratio of Al to Ga and Al may be 0.01 or more. In aluminum gallium nitride, the composition ratio of Al to Ga and Al may be 0.01 or more and 1.0 or less, or 0.05 or more and 0.5 or less. By increasing the composition ratio of Al in aluminum gallium nitride, the thickness of the semiconductor mask SM formed on the silicon-based mask 5 becomes relatively large. As a result, the effect of reducing the amount of silicon incidentally taken into the semiconductor layer from the silicon-based mask 5 can be increased. The aluminum gallium nitride may have a graded structure in which the Al composition changes stepwise in the thickness direction. The semiconductor mask SM and the Al-based semiconductor layer AS may be mainly composed of aluminum gallium nitride. The semiconductor mask SM and the Al-based semiconductor layer AS may be made of the same material (for example, aluminum-based nitride semiconductor such as AlGaN).

The materials constituting the semiconductor mask SM and the Al-based semiconductor layer AS are not particularly limited as long as they have a seed region J in the seed portion S as described above and the surface of the semiconductor mask SM functions as a growth inhibition region DA, but examples include AlGaN, AlInN, AlGaInN, and AlN.

[Manufacturing of template substrate]
3 is a flowchart showing an example of a method for manufacturing a template substrate in an embodiment of the present disclosure. FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a template substrate in an embodiment of the present disclosure. In the method for manufacturing a template substrate in the example shown in FIG. 3 and FIG. 4, a step S10 of preparing a base substrate BS, a step S20 of forming a mask pattern 6 including a silicon-based mask 5 containing silicon and a first opening K1 located on the base substrate BS, and a step S30 of forming a semiconductor mask SM containing aluminum located on the silicon-based mask 5 and a seed portion S having an Al-based semiconductor layer AS containing a main component of the semiconductor mask SM and overlapping with the first opening K1 are performed. As shown in the figure indicated by the reference numeral 3002 in FIG. 3, in the method for manufacturing a template substrate, the above step S30 may include a step S31 of forming a semiconductor mask SM and an Al-based semiconductor layer AS, and a step S32 of forming a covering layer C containing a nitride semiconductor and covering an upper surface AST of the Al-based semiconductor layer AS.

FIG. 5 is a block diagram showing a template substrate manufacturing apparatus in one embodiment of the present disclosure. The template substrate manufacturing apparatus 30 includes an apparatus M10 that performs step S10 in FIG. 3, an apparatus M20 that performs step S20 in FIG. 3, an apparatus M30 that performs step S30 in FIG. 3, and a control device MC that controls the apparatus M10, the apparatus M20, and the apparatus M30. The apparatus M10 and the apparatus M20 may each include a sputtering apparatus. The apparatus M30 may include a MOCVD (Metal-Organic Chemical Vapor Deposition) apparatus. The apparatus M30 may perform the above steps S31 and S32.

[Semiconductor Substrate]
Fig. 6 is a cross-sectional view showing a configuration of a semiconductor substrate according to an embodiment of the present disclosure. Fig. 7 is a plan view showing a configuration of a semiconductor substrate according to an embodiment of the present disclosure. As shown in Figs. 6 and 7, the semiconductor substrate 10 includes a template substrate TS, and a first nitride semiconductor portion 8A located above a first opening K1 and a semiconductor mask SM.

The first nitride semiconductor portion 8A contains a nitride semiconductor as a main component. The first nitride semiconductor portion 8A may be doped (e.g., n-type containing a donor) or non-doped. The semiconductor substrate means a substrate containing a nitride semiconductor, and the base substrate BS of the template substrate TS may contain a semiconductor other than a nitride semiconductor (e.g., silicon, silicon carbide), or may not contain a semiconductor. An example of a main substrate 1 that does not contain a semiconductor is a sapphire substrate.

As described above, in the template substrate TS, the surface (upper surface SMT) of the semiconductor mask SM has a relatively low crystallinity and therefore functions as a growth inhibition region DA. On the other hand, the surface of the seed portion S is composed of an Al-based semiconductor layer AS containing the main component of the semiconductor mask SM or a covering layer C containing a nitride semiconductor, and has a relatively high crystallinity and therefore functions as a seed region J. The template substrate TS may have a shape in which the growth inhibition region DA and the seed region J (the surface of the seed portion S) aligned in the first direction (X direction) each have a longitudinal direction in the second direction (Y direction).

In the semiconductor substrate 10, the first nitride semiconductor portion 8A has a first base portion B1 located above the first seed portion S1, and a first wing portion F1 connected to the first base portion B1 and located above the semiconductor mask SM. In the first nitride semiconductor portion 8A, the first base portion B1 located above the first seed portion S1 (in other words, above the first opening K1) is a dislocation inheritance portion having many threading dislocations, and the first wing portion F1 located above the semiconductor mask SM is a low defect portion having a threading dislocation density lower than that of the dislocation inheritance portion. The threading dislocation density of the first wing portion F1 may be, for example, 1/10 or less than that of the first base portion B1 which is the dislocation inheritance portion. The threading dislocation density of the first wing portion F1 which is the low defect portion may be, for example, 5×10 ⁶ [pieces/cm ² ] or less.

Threading dislocations are dislocations (defects) that extend in the c-axis direction (<0001> direction) in the first nitride semiconductor portion 8A (nitride semiconductor portion 8 described below). The threading dislocation density can be determined, for example, by subjecting the surface of the first nitride semiconductor portion 8A to CL (Cathode Luminescence) measurement and counting the number of black dots in the CL measurement image.

In the semiconductor substrate 10 of this embodiment, the mask pattern 6 includes the second opening K2, and in a plan view, the silicon-based mask 5 and the semiconductor mask SM are located between the first and second openings K1 and K2, and a second nitride semiconductor portion 8C is provided located above the second opening K2 and the semiconductor mask SM, and a gap GP may be located between the first and second nitride semiconductor portions 8A and 8C. The second nitride semiconductor portion 8C has a second base portion B2 located above the second seed portion S2 and a second wing portion F2 connected to the second base portion B2 and located above the semiconductor mask SM. The first wing portion F1 and the second wing portion F2 may be aligned in the first direction (X direction) via the gap GP.

In the following, the first nitride semiconductor portion 8A and the second nitride semiconductor portion 8C may be collectively referred to as the nitride semiconductor portion 8, the first base portion B1 and the second base portion B2 may be collectively referred to as the base portion B, and the first wing portion F1 and the second wing portion F2 may be collectively referred to as the wing portion F.

The first direction (X direction) may be the a-axis direction (<11-20> direction) of the nitride semiconductor portion 8 (nitride semiconductor crystal such as GaN). The second direction (Y direction) perpendicular to the first direction may be the m-axis direction (<1-100> direction) of the nitride semiconductor portion 8. The thickness direction (Z direction) of the semiconductor substrate 10 may be the c-axis direction (<0001> direction) of the nitride semiconductor portion 8.

In the semiconductor substrate 10 of this embodiment, the nitride semiconductor portion 8 (first nitride semiconductor portion 8A) may have a silicon concentration of 5×10 ¹⁸ /cm ³ or less in the back surface portion BP facing the semiconductor mask SM. The nitride semiconductor portion 8 is formed by lateral growth with the seed portion S as the growth starting point, in a state in which the semiconductor mask SM is located on the silicon-based mask 5. This makes it possible to suppress the phenomenon in which impurities liberated from the silicon-based mask 5 are taken into the growing nitride semiconductor portion 8. Therefore, the amount of silicon liberated from the silicon-based mask 5 and taken into the nitride semiconductor portion 8 is effectively reduced.

Furthermore, for example, if impurities segregate on the surface of the nitride semiconductor portion 8, problems may arise, such as making it difficult to form an upper layer film on the nitride semiconductor portion 8, and defects occurring at the interface with the upper layer film. If the film formation conditions for lateral growth are restricted to avoid these problems, it may become difficult to form a semiconductor portion with a large aspect ratio (ratio of width to thickness), and the degree of freedom of the semiconductor portion shape for device design is reduced. In contrast, the semiconductor substrate 10 in this embodiment has a semiconductor mask SM located on the silicon-based mask 5, which effectively reduces the possibility that impurities liberated from the silicon-based mask 5 will segregate on the surface of the nitride semiconductor portion 8. The aspect ratio of the nitride semiconductor portion 8 can be, for example, 5.0 or more, 10.0 or more, or 20.0 or more.

As described below, when an active section (active layer) including, for example, a light emitting section is formed above the nitride semiconductor section 8, the light emitting section can be disposed above the wing section F, which is a low defect section (so as to overlap with the wing section F in a plan view).

[Manufacturing of semiconductor substrates and semiconductor devices]
8 is a flowchart showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. As shown in FIG. 8, the method for manufacturing a semiconductor substrate 10 includes a step S110 of preparing a template substrate TS and a step S120 of forming a first opening K1 and a first nitride semiconductor portion 8A located above a semiconductor mask SM.

9 is a flowchart showing an example of a method for manufacturing a semiconductor device 25 according to an embodiment of the present disclosure. FIG. 10 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device 25 according to an embodiment of the present disclosure. As shown in FIGS. 9 and 10, the semiconductor substrate 10 may be located on the first nitride semiconductor portion 8A and may include a functional layer (device layer) 9 including an active layer. The method for manufacturing the semiconductor device 25 includes a step S210 of preparing the semiconductor substrate 10 and a step S220 of forming the functional layer 9 including the active layer on the first nitride semiconductor portion 8A. The functional layer 9 may include an active layer, a p-type layer, and electrodes (e.g., an anode and a cathode). The active layer may have a quantum well structure. The nitride semiconductor portion 8 and the active layer and the p-type layer may be GaN-based semiconductors, and may be formed continuously in an MOCVD apparatus.

The width of the gap GP between the first nitride semiconductor portion 8A and the second nitride semiconductor portion 8C of the semiconductor substrate 10 may be 10 μm or less, 4 μm or less, or 3 μm or less. By having the gap GP, the semiconductor substrate 10 can reduce the internal stress of the nitride semiconductor portion 8. This can reduce cracks and defects (dislocations) that occur in the nitride semiconductor portion 8. This effect is particularly effective when the main substrate 1 is a heterogeneous substrate.

Specific examples of the semiconductor device 25 include a light emitter (such as an LED chip or semiconductor laser chip), a light emitting element in which a light emitter is submounted, and a light emitting module in which a light emitting element is packaged. The semiconductor device is not limited to light emitting semiconductor devices, and may be, for example, a light receiving element (photodiode) or a transistor (including a power transistor or a high electron mobility transistor).

Example 1
Fig. 11 is a cross-sectional view showing a schematic configuration of a template substrate in Example 1. As shown in Fig. 11, the template substrate TS in Example 1 includes a base substrate BS, a mask pattern 6 located on the base substrate BS, a semiconductor mask SM located on a silicon-based mask 5, and a seed portion S overlapping with an opening K.

FIG. 12 is a cross-sectional view showing an example of the configuration of a base substrate. The base substrate BS may include a main substrate 1 and an underlayer 4 on the main substrate 1. The base substrate BS may also have a metal layer (Al layer) between the main substrate 1 and the underlayer 4. The Al layer and an AlN layer as the underlayer 4 may be formed continuously by a sputtering method. The base substrate BS may be composed of a free-standing single crystal substrate (e.g., a wafer cut from a bulk crystal) such as GaN or SiC, in which case a mask pattern 6 may be arranged on the single crystal substrate.

The main substrate 1 may be a silicon substrate, a silicon carbide substrate (4H-SiC, 6H-SiC substrate), a sapphire substrate, a nitride substrate (GaN, AlN substrate, etc.), a ScMgAlO substrate, etc. The surface orientation of the main substrate 1 may be, for example, the (111) surface of a silicon substrate, or the 6H-SiC (0001) or 4H-SiC (0001) surface of a SiC substrate. The main substrate 1 may be 3C-SiC. These are merely examples, and the main substrate 1 may have a material and surface orientation that satisfy the following two conditions, and the specific material and surface orientation of the main substrate 1 are not necessarily limited. That is, the main substrate 1 may be, first, capable of manufacturing a template substrate TS by forming a seed portion S including a mask pattern 6, a semiconductor mask SM, and an Al-based semiconductor layer AS above a base substrate BS including the main substrate 1. The main substrate 1 may be, second, capable of growing a nitride semiconductor portion 8 using the template substrate TS. By using an inexpensive substrate as the main substrate 1, the manufacturing costs of the template substrate TS and the semiconductor substrate 10 can be effectively reduced.

The underlayer 4 may be a GaN-based semiconductor containing aluminum, aluminum nitride (AlN), silicon carbide (SiC), AlScN, graphene, or the like. An AlN layer, which is an example of the underlayer 4, can be formed to a thickness of about 10 nm to 5 μm using, for example, an MOCVD apparatus. The underlayer 4 may be a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, AlGaInN, Al, or the like formed at a low temperature (500° C. or less). When a silicon substrate is used for the main substrate 1, it is desirable that the underlayer 4 in contact with the silicon substrate does not contain gallium in order to suppress meltback. The underlayer 4 may be formed by a sputtering method. The production process can be made more efficient by forming the film using a sputtering apparatus (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.).

The mask pattern 6 in the template substrate TS is formed on the base substrate BS using a material that suppresses the vertical growth (growth in the c-axis direction) of the nitride semiconductor. Then, a low-crystalline semiconductor mask SM is formed on the silicon-based mask 5, and the seed portion S is positioned so as to fill the opening K. This realizes lateral growth (for example, growth in the a-axis direction) of the nitride semiconductor from the seed portion S over the semiconductor mask SM. In the mask pattern 6, as the silicon-based mask 5, for example, a single layer film including any one of a silicon oxide film (SiOx), a silicon nitride film (SiNx), and a silicon oxynitride film (SiON), or a laminated film including at least two of these can be used. The thickness of the silicon-based mask 5 may be, for example, 0.1 nm or more and 5 μm or less, and may be, for example, 10 nm or more and 1 μm or less. The width Wm (size in the X direction) of the silicon-based mask 5 may be, for example, 10 μm or more and may be 20 μm or more and 500 μm or less.

The opening K of the mask pattern 6 may have a longitudinal shape with the first direction (X direction) as the width direction and the second direction (Y direction) as the length direction. The mask pattern 6 may have a plurality of openings K arranged in the first direction. The opening K may have a tapered shape (a shape in which the width narrows downward). The width Wk of the opening K may be, for example, 0.1 μm or more and 20 μm or less. The width Wk of the opening K may be smaller than the width Wm of the silicon-based mask 5. The ratio of the thickness of the silicon-based mask 5 to the width Wk of the opening K (size in the X direction) may be 3.0 or less. The smaller the width Wk of the opening K, the fewer the number of threading dislocations propagating from the opening K to the nitride semiconductor portion 8. In addition, the wing portion F (low defect portion) can be made larger.

In the template substrate TS, the seed portion S is positioned so as to fill the opening K of the mask pattern 6. The seed portion S is formed above the main substrate 1, and serves as the starting point for the growth of the nitride semiconductor portion 8. The seed portion S includes at least an Al-based semiconductor layer AS, and may also have a covering layer C (see FIG. 1). The top surface ST of the seed portion S is higher than the top surface SMT of the semiconductor mask SM, and has a relatively high degree of flatness. This makes it easier to improve the quality of the nitride semiconductor portion 8 grown from the seed portion S. The seed portion S may be contained within the opening K in a plan view, or may protrude slightly laterally from the opening K.

The Al-based semiconductor layer AS and the semiconductor mask SM included in the seed portion S are made of the same material, and in the first embodiment, Al _x Ga _1-x N (x: 0.05 or more) can be used as the material containing aluminum. For example, the thickness of the semiconductor mask SM can be about 10 nm, and the thickness of the Al-based semiconductor layer AS can be about 300 nm.

13 is a cross-sectional view showing an example of the configuration of a template substrate. As shown in FIG. 13, the template substrate TS may be configured such that a base layer 4 (e.g., AlN) and a mask pattern 6 are formed in this order on a main substrate 1 (e.g., a silicon substrate). The template substrate TS may also be configured such that a multi-layer base layer 4 (including a lower layer portion 2 and an upper layer portion 3) and a mask pattern 6 are formed in this order on a main substrate 1. The base layer 4 may be formed locally (e.g., in a stripe shape) so as to overlap an opening K of the mask pattern 6 in a plan view. The template substrate TS may be configured such that a mask pattern 6 is formed on a main substrate 1 (e.g., a SiC bulk crystal substrate, a GaN bulk crystal substrate). The template substrate TS has a seed portion S at a position overlapping the opening K, and a semiconductor mask SM is positioned on a silicon-based mask 5.

For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the upper layer 3, a lower layer 2 including at least one of an AlN layer and a SiC (silicon carbide) layer may be provided to reduce the possibility of the two (main substrate and seed portion) melting together. The lower layer 2 improves the crystallinity and flatness of the upper layer 3. The lower layer 2 may be planar as shown in FIG. 13, or may be patterned. The thickness of the lower layer 2 may be, for example, about 10 nm to 500 nm. The silicon carbide used for the lower layer 2 may be hexagonal (6H-SiC, 4H-SiC) or cubic (4C-SiC).

The upper layer 3 may be made of a GaN-based semiconductor, AlN, SiC, or the like. By having the upper layer 3, the crystallinity and flatness of the seed portion S can be improved. The upper layer 3 may be made of a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, an AlGaInN layer, or the like formed at a low temperature (500°C or less). The thickness of the upper layer 3 may be about 10 nm to 500 nm. At least one of the lower layer 2 (e.g., aluminum nitride) and the upper layer 3 (e.g., GaN-based semiconductor) may be formed using a sputtering device.

The underlayer 4 may include a strain relaxation layer. Examples of the strain relaxation layer include an AlGaN superlattice structure and a graded structure in which the Al composition of AlGaN is changed in stages. The strain relaxation layer can relieve stress in the longitudinal direction of the nitride semiconductor portion 8. At least one of the lower layer portion 2 and the upper layer portion 3 may include a strain relaxation layer.

If a main substrate 1 that does not melt with the upper layer 3 is used, it is possible to configure the structure without providing the lower layer 2. Also, if an upper layer 3 that is less reactive with the main substrate 1 is used, it is possible to configure the structure without providing the lower layer 2. Similarly, if the seed portion S and the main substrate 1 are made of materials that do not melt with each other, it is also possible to configure the structure without providing the base layer 4.

Materials for forming the seed region J (see FIG. 2) in the seed portion S include, for example, GaN-based semiconductors, aluminum nitride (AlN), silicon carbide (SiC), graphene, etc. Silicon carbide is preferably hexagonal 6H-SiC or 4H-SiC. The seed portion S may contain a nitride semiconductor formed at a low temperature of 600° or less. This can reduce warping of the semiconductor substrate 10 caused by the stress of the seed portion S. The seed portion S can also be formed using a sputtering device. Using a sputtering device has the advantages of low-temperature film formation, large-area film formation, and reduced costs.

As an example of the template substrate TS, a silicon substrate can be used for the main substrate 1, an AlN layer (about 30 nm to 300 nm, for example 150 nm) can be used for the lower layer 2 of the underlayer 4, a GaN-based graded layer can be used for the underlayer 4, and a silicon oxide film (SiO ₂ ) can be used for the silicon-based mask 5. The GaN-based graded layer can include, for example, a first layer of an Al _0.6 Ga _0.4 N layer (for example, 300 nm) and a second layer of a GaN layer (for example, 1 to 2 μm).

For example, a silicon oxide film with a thickness of about 100 nm to 4 μm (preferably about 150 nm to 2 μm) is formed over the entire surface of the underlayer 4 using a sputtering method, and a resist is applied over the entire surface of the silicon oxide film. The resist is then patterned using a photolithography method to form a resist with multiple stripe-shaped openings. Parts of the silicon oxide film are then removed using a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form multiple openings K, and the resist is then removed by organic cleaning to form the mask pattern 6. The silicon-based mask 5 can also be formed using a sputtering device or an EBD (Electron Beam Deposition) device.

Here, a small amount of silicon oxide film may decompose and evaporate during the formation of the nitride semiconductor portion 8, and may end up being incorporated into the nitride semiconductor portion 8. However, the template substrate TS has a semiconductor mask SM (e.g., a low-crystalline AlGaN layer) on the silicon-based mask 5, which effectively reduces the amount of silicon that is incorporated into the nitride semiconductor portion 8.

Since silicon nitride film and silicon oxynitride film are less likely to decompose or evaporate under high temperature conditions than silicon oxide film, the silicon-based mask 5 may be a single layer film of silicon nitride film or silicon oxynitride film, or may be a laminate film in which a silicon oxide film and a silicon nitride film are formed in that order on the base substrate BS. In addition, the oxygen and nitrogen composition of SiON may be controlled to form the desired oxynitride film.

For example, the silicon-based mask 5 may be a laminated mask in which a silicon oxide film (SiO ₂ ) and a silicon nitride film (SiN) are formed in this order. The silicon oxide film and the silicon nitride film are each formed by CVD (plasma enhanced chemical vapor deposition), and the thickness of the silicon oxide film may be, for example, 0.3 μm, and the thickness of the silicon nitride film may be, for example, 70 nm. As another example, the silicon nitride film may be formed by using a sputtering device or a PECVD device. The thickness of the silicon nitride film may be about 5 nm to 4 μm.

For example, by using a GaN substrate (bulk crystal of GaN) or a 6H-SiC substrate as the main substrate 1, the main substrate 1 can be used as the base substrate BS without providing the underlayer 4. In this case, a mask pattern 6 can be formed on the main substrate 1, and a seed portion S can be formed so as to connect to the upper surface of the main substrate 1 exposed at the opening K.

FIG. 14 is a cross-sectional view showing an example of lateral growth of a nitride semiconductor portion. FIG. 14 shows an example in which a mask pattern 6 has a tapered opening K. The semiconductor substrate 10 in Example 1 has a first nitride semiconductor portion 8A and a second nitride semiconductor portion 8C formed by the ELO method above a template substrate TS.

The nitride semiconductor portion 8 can be grown laterally as follows. An initial growth portion SL may be formed on the seed portion S located overlapping the opening K, and then the nitride semiconductor portion 8 may be grown laterally from the initial growth portion SL. The initial growth portion SL serves as the starting point for the lateral growth of the nitride semiconductor portion 8. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the nitride semiconductor portion 8 in the Z direction (c-axis direction) or the X direction (a-axis direction). The initial growth portion SL may have a thickness of, for example, 0.5 μm or more and 4.0 μm or less.

14, the back surface portion BP of the nitride semiconductor portion 8 is in contact with the semiconductor mask SM, but this is not limited thereto, and the semiconductor substrate 10 may have a gap between the back surface portion BP and the semiconductor mask SM. The first nitride semiconductor portion 8A may have a first base portion B1 located above the opening K, and a first wing portion F1 connected to the first base portion B1, separated from the growth inhibition region DA, and located above the gap. When the top surface ST of the seed portion S is higher than the top surface SMT of the semiconductor mask SM, depending on the position of the top surface ST, the initial growth portion SL may not be in contact with the semiconductor mask SM on the side surface of the seed portion S, and the nitride semiconductor portion 8 may grow laterally from the initial growth portion SL.

The covering layer C (see FIG. 6) on the seed portion S may function as the initial growth portion SL. The nitride semiconductor covering layer C may be formed, for example, so that the seed portion S protrudes from the silicon-based mask 5, and the nitride semiconductor portion 8 may grow laterally from the covering layer C.

In the semiconductor substrate 10, by adjusting the growth conditions, the nitride semiconductor portion 8 can be grown laterally at high speed and with high crystallinity while suppressing growth in the c-axis direction (thickness direction). This allows the nitride semiconductor portion 8 (crystal of a nitride semiconductor such as GaN) with low defects to be formed thinly and widely at low cost, and the consumption of raw materials can also be reduced.

For the wing portion F, the ratio (WF/d1) of the width WF (size in the X direction) to the thickness d1 can be, for example, 2.0 or more. WF/d1 can be 2.0 or more, 4.0 or more, 5.0 or more, 7.0 or more, or 10.0 or more. By making WF/d1 2.0 or more, it is easy to reduce the internal stress of the nitride semiconductor portion 8. As a result, it is possible to reduce the warpage of the wafer. The width WF of the wing portion F can be, for example, 7.0 μm or more, 10.0 μm or more, 20.0 μm or more, or 40.0 μm or more. The thickness d1 can be 10.0 μm or less, 5.0 μm or less, or 2.0 μm or less.

In Example 1, the width Wm of the silicon-based mask 5 was 50 μm, the width Wk of the opening K was 5 μm, the horizontal width of the nitride semiconductor portion 8 was 53 μm, the width (size in the X direction) of the wing portion F was 24 μm, and the layer thickness of the nitride semiconductor portion 8 was 5 μm. The aspect ratio of the nitride semiconductor portion 8 was 53 μm/5 μm = 10.6, which is an extremely high aspect ratio.

Example 2
15 is a cross-sectional view showing a schematic configuration of a template substrate in Example 2. As shown in FIG. 15, the template substrate TS in Example 2 may not have a covering layer C on the seed portion S. The template substrate TS may have an exposed Al-based semiconductor layer AS. For example, by using AlGaN as the constituent material of the semiconductor mask SM and the Al-based semiconductor layer AS, the Al-based semiconductor layer AS can be an AlGaN layer having a relatively high crystallinity. The nitride semiconductor portion 8 can be grown using this Al-based semiconductor layer AS as a growth starting point.

In the example shown in FIG. 15, the top surface AST of the Al-based semiconductor layer AS is higher than the top surface SMT of the semiconductor mask SM, but this is not limited thereto, and the top surface AST may be lower than the top surface SMT. The top surface AST may be lower than the top surface 5T of the silicon-based mask 5. The top surface AST of the Al-based semiconductor layer AS can be used as a seed region J to grow the nitride semiconductor portion 8 by the ELO method.

Example 3
Fig. 16 is a cross-sectional view that illustrates a schematic configuration of a template substrate in Example 3. As illustrated in Fig. 16, in Example 3, the seed portion S may include a covering layer C located on a base substrate BS and an Al-based semiconductor layer AS that covers an upper surface CT of the covering layer C. The upper surface CT of the covering layer C may be located lower or higher than an upper surface SMT of the semiconductor mask SM.

The template substrate TS in Example 3 may be manufactured, for example, by forming a mask pattern 6 on a base substrate BS, growing a coating layer C on the surface of the base substrate BS exposed at an opening K, and then forming an Al-based semiconductor layer AS and a semiconductor mask SM.

As in the second embodiment, for example, by using AlGaN as the constituent material of the semiconductor mask SM and the Al-based semiconductor layer AS, the nitride semiconductor portion 8 can be grown using the Al-based semiconductor layer AS as the growth starting point.

Example 4
Fig. 17 is a cross-sectional view that shows a schematic configuration of a semiconductor substrate in Example 4. Fig. 18 is a cross-sectional view that shows a schematic configuration of a semiconductor substrate in Example 4. In Fig. 17, a black dot shown at a position indicated by a lead line of the symbol JD indicates a space (gap JD) between the wing portion F and the template substrate TS.

17 and 18, in the semiconductor substrate 10 in Example 4, a gap JD may exist between the semiconductor mask SM and the first nitride semiconductor portion 8A. The gap JD can also be said to be a space sandwiched between the growth inhibition region DA and the first wing portion F1. The first wing portion F1 is spaced apart from the semiconductor mask SM that functions as the growth inhibition region DA. The seed region J (upper surface ST of the seed portion S) is located above the growth inhibition region DA, and the first nitride semiconductor portion 8A has a first base portion B1 located on the seed portion S and a first wing portion F1 connected to the first base portion B1 and facing the growth inhibition region DA via the gap JD. The first wing portion F1 may have an edge E1 located above the semiconductor mask SM.

The semiconductor substrate 10 may include a growth inhibition film 7 in contact with the seed portion S at a position above the semiconductor mask SM. The growth inhibition film 7 may be in contact with the upper surface SMT (growth inhibition area DA) of the semiconductor mask SM. The growth inhibition film 7 may also be in contact with the side surface SS of the seed portion S. This inhibits the growth of the nitride semiconductor portion 8 from the side surface SS, making it easier for a void JD to form.

The growth suppression film 7 may include a first film portion 71 in contact with the side surface SS of the seed portion S and a second film portion 72 in contact with the upper surface ST of the seed portion S. The seed portion S includes an Al-based semiconductor layer AS (see FIG. 1, etc.). In this way, the semiconductor substrate 10 may include at least one of a growth suppression film (second film portion 72) located above the Al-based semiconductor layer AS and a growth suppression film (first film portion 71) located on the side surface of the Al-based semiconductor layer AS. The growth suppression film 7 does not need to be a complete film, and may be a film including one or more minute openings (a film with an incomplete shape). The growth suppression film 7 may have a uniform shape within the surface, or may have a shape with partial defects (holes or a shape that is significantly thinner than the surroundings). By forming the second film portion 72, the second film portion 72 suppresses threading dislocations passing through the seed portion S, and the surface flatness and crystallinity of the upper surface ST of the seed portion S are improved.

The top surface ST of the seed portion S has a growth origin PG of the nitride semiconductor portion 8, and the growth origin PG may not be in contact with the growth inhibition film 7 or may be in contact with a portion where the growth inhibition film 7 is locally thin. The growth origin PG may include a corner SC where the top surface ST and side surface SS of the seed portion S intersect. The corner SC may be located above the semiconductor mask SM. That is, the seed portion S may protrude laterally from the opening K in a planar view, and the corner SC and the semiconductor mask SM may overlap in a planar view.

The thickness of the growth inhibition film 7 may be thinner than the silicon-based mask 5 and thinner than the semiconductor mask SM. This makes it easier for the wing portion F to grow from the seed portion S while suppressing growth on the semiconductor mask SM. The thickness of the growth inhibition film 7 may be 1/3 or less of the thickness of the silicon-based mask 5. The thickness of the growth inhibition film 7 may be 1/3 or less of the thickness of the semiconductor mask SM. The growth inhibition film 7 may be about 1 nm thick, and can be formed as a very thin film.

Growth-inhibiting film 7 may be made of, for example, SiN, and depending on the deposition conditions, SiON, SiGaO, or SiGaON may also be used. In Example 4, growth-inhibiting film 7 may contain silicon, and in this case, it was found that the evaporation of silicon from growth-inhibiting film 7 during deposition of nitride semiconductor portion 8 is limited. This is believed to be because, as described above, the thickness of growth-inhibiting film 7 is thin, and the constituent material of semiconductor mask SM and the constituent material of growth-inhibiting film 7 can form a mixed crystal on semiconductor mask SM.

The ratio of the width WJ of the gap JD in the X-direction to the thickness TJ (aspect ratio of the gap) may be 5.0 or more, in which case the first wing portion F1 having high crystallinity (low defect density) and a wide width can be formed quickly. The flatness of the first wing portion F1 is also improved. The silicon concentration of the back surface portion BP of the first wing portion F1 can be set to 5×10 ¹⁸ /cm ³ or less.

The thickness (height) TJ of the gap JD is the distance from the top surface of the growth suppression film 7 on the semiconductor mask SM (equivalent to the top surface SMT of the semiconductor mask SM) to the bottom surface (back surface) of the nitride semiconductor portion 8. The width WJ of the gap JD is the distance in the X direction from the side surface of the seed portion S to the edge E1 of the nitride semiconductor portion 8.

The thickness TJ of the gap JD may be 5 μm or less, 2 μm or less, 1 μm or less, 0.6 μm or less, or 0.3 μm or less. The thickness TJ of the gap JD is preferably 0.05 μm (50 nm) or more. The aspect ratio of the gap JD can be 5.0 or more, 10 or more, 20 or more, 30 or more, 50 or more, or 100 or more. In this way, the functional layer 9 (see FIG. 10) can be formed on the wide wing portion F while suppressing the back-rolling phenomenon, and a high-quality (e.g., high light extraction efficiency) semiconductor device can be formed. The aspect ratio of the gap J may be, for example, 100 to 1000. This can reduce the risk of the nitride semiconductor portion 8 warping upward due to gravity. The width of the gap GP may be greater than the thickness of the gap JD. In addition, the back-rolling phenomenon can be more effectively suppressed by setting the width of the gap GP to 30 μm or less, or 10 μm or less.

The first wing portion F1 may have the same shape as in the first embodiment described above. The width of the first wing portion F1 may be 80.0 μm or less. This reduces the risk of the nitride semiconductor portion 8 warping upward due to gravity.

19 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate in Example 4. As shown in FIG. 19, first, a template substrate TS is prepared. Next, for example, a MOCVD apparatus is used to deposit a thin SiN film (for example, about 1 nm) at a deposition temperature of about 1000° C. or less and to supply SiH ₄ (silane) and NH ₃ (ammonia). As a result, a growth suppression film 7 is formed on the upper surface ST and side surface SS of the seed portion S.

Then, the deposition temperature is raised to 250°C and TMG (trimethylgallium) and ammonia are supplied to deposit the nitride semiconductor portion 8. At this time, the deposition of the nitride semiconductor portion 8 is significantly affected by the growth suppression film 7, and the wing portion F is formed in a state where it is floating above the semiconductor mask SM. In other words, the back surface of the wing portion F of the nitride semiconductor portion 8 is completely separated from the semiconductor mask SM.

Also, for example, both corners (two corners SC aligned in the X direction) of the seed portion S become growth starting points PG, and lateral film growth occurs from both sides. In this case, a void can be formed in the first base portion B1 (particularly the central portion). In this way, the first base portion B1 may include a void, which relieves stress from the template substrate TS. The void may be located above the second film portion 72 of the growth suppression film 7.

After forming the seed portion S on the template substrate TS using an MOCVD apparatus, the growth suppression film 7 may be subsequently formed.

FIG. 20 is a cross-sectional view showing another configuration of the semiconductor substrate in Example 4. In the example shown in FIG. 17, the height of the back surface BP of the nitride semiconductor portion 8 is formed at approximately the same height as the top surface ST of the seed portion S, but in the example shown in FIG. 20, the height of the back surface BP of the nitride semiconductor portion 8 is at a position (lower position) below the top surface ST of the seed portion S. By controlling the film formation conditions of the nitride semiconductor portion 8 (film formation temperature, film formation time, gas flow rate, etc.), the shape of the formed nitride semiconductor portion 8 can be changed. The effects of Example 4 can be obtained in both the examples shown in FIG. 17 and FIG. 20.

Example 5
21 to 23 are cross-sectional views showing another configuration of the semiconductor substrate in the fifth embodiment. As shown in FIG. 21 to FIG. 23, the semiconductor substrate 10 may include a template substrate TS and a nitride semiconductor portion 8. The template substrate TS includes a base substrate BS, a mask pattern 6 including a silicon-based mask 5 and a first opening K1, which is located on the base substrate BS, a semiconductor mask SM including aluminum, which is located on the silicon-based mask 5, and a seed portion S having an Al-based semiconductor layer AS including a main component of the semiconductor mask SM and overlapping the first opening K1. By forming a continuous layer SF including an Al-based nitride semiconductor (e.g., aluminum gallium nitride) and covering the mask pattern 6, a semiconductor mask SM (low crystallinity) on the silicon-based mask 5 and an Al-based semiconductor layer AS (high crystallinity) that overlaps the first opening K1 and is thicker than the semiconductor mask SM may be formed. A covering portion C may be provided to cover the upper surface of the Al-based semiconductor layer AS. An edge 8E of the nitride semiconductor portion 8 may be located above the semiconductor mask SM.

22, a raised portion 8R rising from a seed portion S is provided in the nitride semiconductor portion 8, and a growth suppression film 7 is provided in contact with the side and top surface of the raised portion 8R, so that the wing F of the nitride semiconductor portion 8 is raised above the semiconductor mask SM (a gap JD may be provided between the wing F and the semiconductor mask SM). This reduces warping of the semiconductor substrate 10. As shown in FIG. 23, a raised portion 4T is formed on the surface of the underlayer 4, and the side surface of the raised portion 8R is covered with a mask portion 5. The wing F of the nitride semiconductor portion 8 is raised above the semiconductor mask SM by using a template substrate TS on which a continuous layer SF of an Al-based nitride semiconductor (semiconductor mask SM and Al-based semiconductor layer AS) is formed.

Example 6
FIG. 24 is a plan view showing an example of a method for manufacturing a semiconductor substrate and a semiconductor device in Example 6. FIG. 25 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate and a semiconductor device in Example 6. In Example 6, an example of manufacturing a semiconductor device 25 using the semiconductor substrate 10 in Example 4 will be described. When manufacturing a semiconductor substrate 10 and a semiconductor device 25 using the template substrate TS in Examples 1 to 3, a known method can be used, and this can be easily understood by referring to the following description. For example, the base portion B and the functional layer 9 on the seed portion S are removed, and the growth suppression film 7, the semiconductor mask SM, and the silicon-based mask 5 are removed to separate the semiconductor device 25 from the template substrate TS.

As shown in Figures 24 and 25, a functional layer (device layer) 9 may be formed on the first nitride semiconductor portion 8A. For example, the functional layer 9, such as an LED, Laser, PD (light receiving element), or Power device, may be formed using MOCVD, MBE, sputtering, or the like. The active region (e.g., light emitting region ES) of the functional layer 9 may be formed above (so as to overlap with) the first wing portion F1 (device region), which is a low defect portion (low dislocation portion) in a plan view.

Next, electrodes EA and EC (e.g., anode and cathode) are formed on the functional layer 9, and predetermined portions of the first nitride semiconductor portion 8A and the functional layer 9 are removed to separate the elements. Specifically, a separation groove BM parallel to the X direction is formed in the first nitride semiconductor portion 8A and the functional layer 9, and the first nitride semiconductor portion 8A and the functional layer 9 located on the seed portion S are removed leaving behind two paired tether portions TZ to form the element region PA. The two tether portions TZ are the portions of the element region PA that are connected to the seed portion S at both ends facing each other in the Y direction.

Then, the element region PA (including the wing portion F, the functional layer 9, and the electrodes EA and EC) is separated from the template substrate TS to form the semiconductor device 25. Because there is a gap JD below the wing portion F, by applying downward pressure to the element region PA with a pressure member YS (adhesive plate, adhesive sheet, adhesive substrate, etc.) having adhesive properties, the two tether portions TZ easily break, and the semiconductor device 25 is separated from the template substrate TS.

Specifically, the semiconductor device 25 is peeled off from the template substrate TS while being held by the pressing body YS. In this way, the gap JD also functions effectively in element isolation, allowing the semiconductor device 25 to be peeled off from the template substrate TS without being damaged.

[Other configuration examples]
In the above-mentioned Examples 1 to 6, an example was described in which there is a gap GP between the first nitride semiconductor portion 8A and the second nitride semiconductor portion 8C, but this is not limiting, and the nitride semiconductor portions 8 (first wing portion F1 and second wing portion F2) grown from adjacent seed portions S may be in contact (meet) with each other on the semiconductor mask SM. The semiconductor substrate 10 may not have a gap GP. A plurality of nitride semiconductor portions 8 may be formed by removing the semiconductor crystal at the meeting portion.

26 is a schematic diagram showing one example of the configuration of an electronic device. The electronic device 55 in FIG. 26 includes a semiconductor device 25 including a nitride semiconductor portion 8, a drive substrate 23 on which the semiconductor device 25 is mounted, and a control circuit 27 that controls the drive substrate 23. FIG. 27 is a schematic diagram showing another example of the configuration of an electronic device. The element region (element portion) PA does not need to be peeled off from the template substrate TS. The electronic device 55 in FIG. 27 includes a semiconductor substrate 10 including the template substrate TS and the element region PA, a drive substrate 23 on which the semiconductor substrate 10 is mounted, and a control circuit 27 that controls the drive substrate 23. In this case, the main substrate 1 included in the template substrate TS may be a light-transmitting substrate (e.g., a sapphire substrate). Examples of the electronic device 55 include a light-emitting device, a display device, a laser emission device (including a Fabry-Perot type and a surface emission type), a measuring device, a lighting device, a communication device, an information processing device, and a power control device.

[Additional Notes]
The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-mentioned embodiments and examples. That is, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments and examples are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure.

〔summary〕
The template substrate in aspect 1 of the present disclosure comprises a base substrate, a mask pattern located on the base substrate and including a silicon-based mask containing silicon and a first opening, a semiconductor mask located on the silicon-based mask containing aluminum, and a seed portion having an Al-based semiconductor layer that contains a main component of the semiconductor mask and overlaps the first opening.

The template substrate in aspect 2 of the present disclosure is the same as in aspect 1, except that the Al-based semiconductor layer is thicker than the semiconductor mask.

The template substrate in aspect 3 of the present disclosure is the same as in aspect 1 or 2, in which the seed portion includes a covering layer that includes a nitride semiconductor and covers the upper surface of the Al-based semiconductor layer.

The template substrate in aspect 4 of the present disclosure is any one of aspects 1 to 3, in which the Al-based semiconductor layer is shaped to fill the first opening.

The template substrate in aspect 5 of the present disclosure is any one of aspects 1 to 4, in which the base substrate comprises a main substrate and an underlayer located on the main substrate, and the Al-based semiconductor layer is located on the underlayer.

The template substrate in aspect 6 of the present disclosure is any one of aspects 1 to 5, in which the surface roughness of the semiconductor mask is greater than the surface roughness of the Al-based semiconductor layer.

The template substrate in aspect 7 of the present disclosure is any one of aspects 1 to 6, in which the surface roughness of the semiconductor mask is greater than the surface roughness of the silicon-based mask.

The template substrate in aspect 8 of the present disclosure is any one of aspects 1 to 7, in which the upper surface of the seed portion is located at a higher position than the upper surface of the semiconductor mask.

The template substrate in aspect 9 of the present disclosure is any one of aspects 1 to 8, in which the seed portion includes a covering layer that includes a nitride semiconductor and covers the upper surface of the Al-based semiconductor layer, and the surface roughness of the covering layer is smaller than the surface roughness of the Al-based semiconductor layer.

The template substrate in aspect 10 of the present disclosure is any one of aspects 1 to 9, in which the semiconductor mask has lower crystallinity than the Al-based semiconductor layer.

The template substrate in aspect 11 of the present disclosure is any one of aspects 1 to 10, in which the semiconductor mask includes an amorphous structure.

The template substrate in aspect 12 of the present disclosure is any one of aspects 1 to 11, in which the seed portion includes a covering layer that includes a nitride semiconductor and covers the upper surface of the Al-based semiconductor layer, and the covering layer does not include aluminum or has a lower aluminum content than the Al-based semiconductor layer.

The template substrate in aspect 13 of the present disclosure is any one of aspects 1 to 12, in which the seed portion includes a covering layer that includes a nitride semiconductor and covers the upper surface of the Al-based semiconductor layer, and the covering layer is thicker than the Al-based semiconductor layer.

The template substrate in aspect 14 of the present disclosure is any one of aspects 1 to 13, in which the semiconductor mask and the Al-based semiconductor layer are connected.

The template substrate in aspect 15 of the present disclosure is any one of aspects 1 to 14, in which the Al-based semiconductor layer is exposed.

The template substrate in aspect 16 of the present disclosure is any one of aspects 1 to 15, in which the silicon-based mask includes at least one of silicon nitride and silicon oxide, and the semiconductor mask and the Al-based semiconductor layer include aluminum gallium nitride.

The template substrate in aspect 17 of the present disclosure is any one of aspects 1 to 16, in which the base substrate comprises a main substrate and an underlayer located on the main substrate, the main substrate being any one of a silicon wafer, a silicon carbide wafer, and a sapphire wafer, and the underlayer includes aluminum nitride.

The template substrate in aspect 18 of the present disclosure is any one of aspects 1 to 17, in which the mask pattern includes a second opening, and the silicon-based mask and the semiconductor mask are positioned between the first and second openings in a plan view.

The template substrate in aspect 19 of the present disclosure is any one of aspects 1 to 18, in which the semiconductor mask and the Al-based semiconductor layer contain aluminum gallium nitride, and the aluminum gallium nitride has a composition ratio of Al to Ga and Al of 0.05 or more.

The semiconductor substrate in aspect 20 of the present disclosure comprises a template substrate in any one of aspects 1 to 19, and a first nitride semiconductor portion located above the first opening and the semiconductor mask.

The semiconductor substrate in aspect 21 of the present disclosure is the same as aspect 20, except that the mask pattern includes a second opening, the silicon-based mask and the semiconductor mask are located between the first and second openings in a plan view, a second nitride semiconductor portion is located above the second opening and the semiconductor mask, and a gap is located between the first and second nitride semiconductor portions.

The semiconductor substrate in aspect 22 of the present disclosure is the same as in aspect 20 or 21, except that a gap exists between the semiconductor mask and the first nitride semiconductor portion.

The semiconductor substrate in aspect 23 of the present disclosure is any one of aspects 20 to 22, and includes at least one of a growth inhibition film located above the Al-based semiconductor layer and a growth inhibition film located on a side of the Al-based semiconductor layer.

A semiconductor substrate according to Aspect 24 of the present disclosure is any one of Aspects 20 to 23, wherein in the first nitride semiconductor portion, a back surface portion facing the semiconductor mask has a silicon concentration of 5×10 ¹⁸ /cm ³ or less.

The semiconductor substrate in aspect 25 of the present disclosure is any one of aspects 20 to 24, and is located on the first nitride semiconductor portion and has a functional layer including an active layer.

The method for manufacturing a template substrate in aspect 26 of the present disclosure includes the steps of preparing a base substrate, forming a mask pattern located on the base substrate and including a silicon-based mask containing silicon and a first opening, and forming a semiconductor mask located on the silicon-based mask, including aluminum, and a seed portion having an Al-based semiconductor layer that contains the main component of the semiconductor mask and overlaps with the first opening.

The method for manufacturing a template substrate in aspect 27 of the present disclosure includes forming a covering layer that contains a nitride semiconductor and covers the upper surface of the Al-based semiconductor layer in the above-mentioned aspect 26.

The template substrate manufacturing apparatus in aspect 28 of the present disclosure performs each of the steps in aspect 26 or 27.

The method for manufacturing a semiconductor substrate in aspect 29 of the present disclosure includes a step of preparing a template substrate in any one of aspects 1 to 19, and a step of forming a first nitride semiconductor portion located above the first opening and the semiconductor mask.

The method for manufacturing a semiconductor substrate in aspect 30 of the present disclosure includes a step of preparing a semiconductor substrate in any one of aspects 20 to 25, and a step of forming a functional layer located on the first nitride semiconductor portion and including an active layer.

REFERENCE SIGNS LIST 1 Main substrate 4 Undercoat layer 5 Silicon-based mask 6 Mask pattern 7 Growth inhibition film 8 Nitride semiconductor portion 8A First nitride semiconductor portion 8C Second nitride semiconductor portion 9 Functional layer 10 Semiconductor substrate 25 Semiconductor device 30 Template substrate manufacturing apparatus AS Al-based semiconductor layer BS Base substrate B1 First base portion B2 Second base portion C1 First covering layer C2 Second covering layer DA Growth inhibition region F1 First wing portion F2 Second wing portion J Seed region JD Void K1 First opening K2 Second opening SM Semiconductor mask S1 First seed portion S2 Second seed portion TS Template substrate

Claims (30)

A base substrate;
a first mask overlying a base substrate, the first mask including silicon and a mask pattern including a first opening;
a second mask overlying the first mask, the second mask comprising aluminum and a semiconductor;
a seed portion having a semiconductor layer including a main component of the second mask and overlapping the first opening. The template substrate of claim 1, wherein the semiconductor layer is thicker than the second mask. The template substrate according to claim 1 or 2, wherein the seed portion includes a covering layer that includes a nitride semiconductor and covers an upper surface of the semiconductor layer. The template substrate according to any one of claims 1 to 3, wherein the semiconductor layer is shaped to fill the first opening. The base substrate includes a main substrate and a foundation layer located on the main substrate,
The template substrate according to claim 1 , wherein the semiconductor layer is located on the underlayer. The template substrate according to any one of claims 1 to 5, wherein the surface roughness of the second mask is greater than the surface roughness of the semiconductor layer. The template substrate according to any one of claims 1 to 6, wherein the surface roughness of the second mask is greater than the surface roughness of the first mask. The template substrate according to any one of claims 1 to 7, wherein the upper surface of the seed portion is located higher than the upper surface of the second mask. The template substrate of claim 3, wherein the surface roughness of the coating layer is smaller than the surface roughness of the semiconductor layer. The template substrate according to any one of claims 1 to 9, wherein the second mask has lower crystallinity than the semiconductor layer. The template substrate according to any one of claims 1 to 10, wherein the second mask includes an amorphous structure. The template substrate of claim 3, wherein the coating layer does not contain aluminum or has a lower aluminum content than the semiconductor layer. The template substrate of claim 3, wherein the covering layer is thicker than the semiconductor layer. The template substrate according to any one of claims 1 to 13, wherein the second mask and the semiconductor layer are connected. The template substrate according to any one of claims 1 to 14, wherein the semiconductor layer is exposed. the first mask includes at least one of silicon nitride and silicon oxide;
The template substrate of claim 1 , wherein the second mask and the semiconductor layer comprise aluminum gallium nitride. The main substrate is any one of a silicon wafer, a silicon carbide wafer, and a sapphire wafer;
The template substrate of claim 5 , wherein the underlayer comprises aluminum nitride. the mask pattern includes a second opening;
The template substrate according to claim 1 , wherein the first mask and the second mask are located between the first and second openings in a plan view. The template substrate of claim 16, wherein the aluminum gallium nitride has a composition ratio of Al to Ga and Al of 0.05 or more. A template substrate according to any one of claims 1 to 19;
a first nitride semiconductor portion located above the first opening and the second mask. the mask pattern includes a second opening;
the first mask and the second mask are located between the first and second openings in a plan view;
a second nitride semiconductor portion located above the second opening and the second mask;
The semiconductor substrate of claim 20 , wherein a gap is located between the first and second nitride semiconductor portions. The semiconductor substrate according to claim 20 or 21, wherein a gap exists between the second mask and the first nitride semiconductor portion. The semiconductor substrate according to any one of claims 20 to 22, comprising at least one of a growth inhibition film located above the semiconductor layer and a growth inhibition film located on a side surface of the semiconductor layer. 24. The semiconductor substrate according to claim 20, wherein in the first nitride semiconductor portion, a back surface portion facing the second mask has a silicon concentration of ^5x1018 /cm3 or ^less . The semiconductor substrate according to any one of claims 20 to 24, which is located on the first nitride semiconductor portion and has a functional layer including an active layer. providing a base substrate;
forming a mask pattern including a first mask and a first opening over a base substrate, the first mask including silicon;
and forming a second mask located on the first mask and including aluminum and a semiconductor, and a seed portion having a semiconductor layer including a main component of the second mask and overlapping the first opening. The method for manufacturing the template substrate according to claim 26, comprising the step of forming a covering layer that includes a nitride semiconductor and covers the upper surface of the semiconductor layer. A template substrate manufacturing apparatus that performs each step described in claim 26 or 27. Providing a template substrate according to any one of claims 1 to 19;
forming a first nitride semiconductor portion located above the first opening and the second mask. Providing a semiconductor substrate according to any one of claims 20 to 25;
and forming a functional layer including an active layer, the functional layer being located on the first nitride semiconductor portion.

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