WO2025050312A1 - Driving circuit, display substrate, and display device - Google Patents
Driving circuit, display substrate, and display device Download PDFInfo
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- WO2025050312A1 WO2025050312A1 PCT/CN2023/117183 CN2023117183W WO2025050312A1 WO 2025050312 A1 WO2025050312 A1 WO 2025050312A1 CN 2023117183 W CN2023117183 W CN 2023117183W WO 2025050312 A1 WO2025050312 A1 WO 2025050312A1
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- transistor
- node
- electrically connected
- control
- circuit
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- 239000000758 substrate Substances 0.000 title claims abstract description 28
- 238000004146 energy storage Methods 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 31
- 102220516735 Protease-associated domain-containing protein 1_M16A_mutation Human genes 0.000 description 9
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- 239000002184 metal Substances 0.000 description 5
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- 102100026388 L-amino-acid oxidase Human genes 0.000 description 3
- 101100102598 Mus musculus Vgll2 gene Proteins 0.000 description 3
- 101100012902 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FIG2 gene Proteins 0.000 description 3
- 101100102583 Schizosaccharomyces pombe (strain 972 / ATCC 24843) vgl1 gene Proteins 0.000 description 3
- 102100023478 Transcription cofactor vestigial-like protein 1 Human genes 0.000 description 3
- 102100023477 Transcription cofactor vestigial-like protein 2 Human genes 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
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- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 2
- 206010047571 Visual impairment Diseases 0.000 description 2
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Definitions
- the present disclosure relates to the field of display technology, and in particular to a driving circuit, a display substrate and a display device.
- the driving capability of display panels also needs to be upgraded accordingly, and high-mobility oxide transistors have emerged.
- its electrical characteristics are more negative than the threshold voltage of traditional transistors.
- Some transistors in the driving circuit work for a long time with a gate-source voltage of 0V, which increases the leakage current and leads to increased power consumption.
- the related technology cannot reasonably arrange the transistors in the driving circuit, cannot effectively prevent leakage of the first node, and cannot improve the driving capability of the display product.
- the related driving circuit cannot prevent the noise of the control node from being introduced into the first node through leakage, cannot improve the stability of the driving circuit, and cannot prevent multiple outputs.
- an embodiment of the present disclosure provides a driving circuit, including an input circuit, a reset circuit, a first node reset circuit, and a control node control circuit;
- the input circuit is electrically connected to the input control terminal, the input terminal and the first node respectively, and is used to control the connection or disconnection between the input terminal and the first node under the control of the input control signal provided by the input control terminal;
- the reset circuit is electrically connected to the reset terminal, the first node and the first voltage line respectively, and is used to control the connection or disconnection between the first node and the first voltage line under the control of the reset signal provided by the reset terminal;
- the first node reset circuit is electrically connected to the second node, the first node and the first voltage line respectively, and is used to control the connection or disconnection between the first node and the first voltage line under the control of the potential of the second node;
- the control node control circuit is electrically connected to the first node, the third voltage line and the control node respectively, and is used to control the connection or disconnection between the control node and the third voltage line under the control of the potential of the first node;
- the transistor included in the input circuit, the transistor included in the reset circuit and the transistor included in the first node reset circuit are arranged in sequence along a direction away from the display area;
- a ratio of a channel width-to-length ratio of a transistor whose gate is electrically connected to the second node and included in the first node reset circuit to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.
- the driving circuit described in at least one embodiment of the present disclosure further includes a frame reset circuit
- the frame reset circuit is electrically connected to the frame reset line, the first node and the second voltage line respectively, and is used to control the connection or disconnection between the first node and the second voltage line under the control of the frame reset signal provided by the frame reset line;
- the transistor included in the frame reset circuit is arranged on a side of the transistor included in the first node reset circuit away from the display area.
- the input circuit includes at least two input transistors connected in series
- the reset circuit includes at least two reset transistors connected in series.
- the first node reset circuit includes at least two transistors connected in series with their gates electrically connected to the second node; or,
- the second node includes a first second node and a second second node;
- the first node reset circuit includes at least two transistors connected in series with their gates electrically connected to the first second node, and at least two transistors connected in series with their gates electrically connected to the second second node.
- the frame reset circuit includes at least two frame reset transistors connected in series.
- the transistor included in the control node control circuit is arranged on a side of the transistor included in the input circuit close to the display area.
- control node control circuit includes a control transistor
- a gate of the control transistor is electrically connected to the first node, a first electrode of the control transistor is electrically connected to the third voltage line, and a second electrode of the control transistor is electrically connected to the control node.
- the driving circuit described in at least one embodiment of the present disclosure further includes a shutdown reset circuit
- the shutdown reset circuit is electrically connected to the fourth voltage line and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the fourth voltage line under the control of a fourth voltage signal provided by the fourth voltage line.
- the transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit close to the display area.
- the shutdown reset circuit includes a shutdown reset transistor
- the gate of the shutdown reset transistor and the first electrode of the shutdown reset transistor are electrically connected to the fourth voltage line, and the second electrode of the shutdown reset transistor is electrically connected to the driving signal output terminal.
- the input circuit includes a first input transistor and a second input transistor
- the gate of the first input transistor is electrically connected to the input control terminal, the first electrode of the first input transistor is electrically connected to the input terminal, and the second electrode of the first input transistor is electrically connected to the control node;
- a gate of the second input transistor is electrically connected to the input control terminal, a first electrode of the second input transistor is electrically connected to the control node, and a second electrode of the second input transistor is electrically connected to the first node.
- the input control terminal is a carry signal output terminal of an adjacent previous stage driving circuit, and the input terminal is a drive signal output terminal of an adjacent previous stage driving circuit;
- the input control terminal and the input terminal are both carry signal output terminals of the adjacent previous stage driving circuit.
- the reset circuit includes a first reset transistor and a second reset transistor
- the gate of the first reset transistor is electrically connected to the reset terminal, the first electrode of the first reset transistor is electrically connected to the first node, and the second electrode of the first reset transistor is electrically connected to the control node;
- a gate of the second reset transistor is electrically connected to the reset terminal, a first electrode of the second reset transistor is electrically connected to the control node, and a second electrode of the second reset transistor is electrically connected to the first voltage line.
- a channel width-to-length ratio of a transistor included in the control node control circuit is smaller than a channel width-to-length ratio of the second reset transistor.
- the first node reset circuit includes a first pull-down transistor and a second pull-down transistor;
- the gate of the first pull-down transistor is electrically connected to the second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node;
- a gate of the second pull-down transistor is electrically connected to the second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line.
- a ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.
- a channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor.
- the second node includes a first second node and a second second node
- the first node reset circuit includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor and a fourth pull-down transistor;
- the gate of the first pull-down transistor is electrically connected to the first second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node;
- the gate of the second pull-down transistor is electrically connected to the first second node, the first electrode of the second pull-down transistor is electrically connected to the control node, and the second electrode of the second pull-down transistor is electrically connected to the first voltage line;
- the gate of the third pull-down transistor is electrically connected to the second second node, the first electrode of the third pull-down transistor is electrically connected to the first node, and the second electrode of the third pull-down transistor is electrically connected to the control node;
- a gate of the fourth pull-down transistor is electrically connected to the second second node, a first electrode of the fourth pull-down transistor is electrically connected to the control node, and a second electrode of the fourth pull-down transistor is electrically connected to the first voltage line.
- a channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor, and a channel width-to-length ratio of the fourth pull-down transistor is greater than a channel width-to-length ratio of the third pull-down transistor.
- a ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24;
- a ratio of a channel width-to-length ratio of the fourth pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.
- the frame reset circuit includes a first frame reset transistor and a second frame reset transistor;
- the gate of the first frame reset transistor is electrically connected to the frame reset line, the first electrode of the first frame reset transistor is electrically connected to the first node, and the second electrode of the first frame reset transistor is electrically connected to the control node;
- a gate of the second frame reset transistor is electrically connected to the frame reset line, a first electrode of the second frame reset transistor is electrically connected to the control node, and a second electrode of the second frame reset transistor is electrically connected to the second voltage line.
- the driving circuit described in at least one embodiment of the present disclosure further includes a carry signal output circuit, a driving signal output circuit and an energy storage circuit;
- the carry signal output circuit is electrically connected to the first node, the second node, the carry signal output terminal, the clock signal terminal and the second voltage line respectively, and is used to control the connection or disconnection between the carry signal output terminal and the clock signal terminal under the control of the potential of the first node, and control the carry signal output terminal to be connected or disconnected under the control of the potential of the second node.
- the terminal is connected or disconnected with the second voltage line;
- the drive signal output circuit is electrically connected to the first node, the second node, the drive signal output terminal, the clock signal terminal and the fourth voltage line respectively, and is used to control the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and control the connection or disconnection between the drive signal output terminal and the fourth voltage line under the control of the potential of the second node;
- the energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used for storing electric energy.
- the fourth voltage line is used to provide a fourth voltage signal
- the second voltage line is used to provide a second voltage signal
- the voltage value of the fourth voltage signal is equal to the voltage value of the second voltage signal, or the voltage value of the second voltage signal is smaller than the voltage value of the fourth voltage signal.
- the driving circuit described in at least one embodiment of the present disclosure further includes a second node control circuit
- the second node control circuit is electrically connected to the input control terminal, the first node, the second node and the second voltage line, respectively, and is used to control the connection or disconnection between the second node and the second voltage line under the control of the input control signal provided by the input control terminal, and to control the potential of the second node under the control of the potential of the first node.
- an embodiment of the present disclosure provides a display substrate, including a base and the above-mentioned driving circuit disposed on the base.
- the display substrate described in at least one embodiment of the present disclosure further includes an electrostatic protection circuit disposed on the base;
- the first end of the electrostatic protection circuit is electrically connected to the driving signal line, the second end of the electrostatic protection circuit is electrically connected to the common electrode voltage terminal through a short-circuit line, and the electrostatic protection circuit is used for electrostatic protection;
- the driving signal lines include a DC voltage line, a clock signal line, a control voltage line and a frame reset line.
- the electrostatic protection circuit includes a first protection transistor, a second protection transistor and a third protection transistor;
- the gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;
- the first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor;
- the gate of the third protection transistor and the first electrode of the third protection transistor are both electrically connected to the short-circuit line, and the second electrode of the third protection transistor is electrically connected to the gate of the second protection transistor;
- the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor.
- the electrostatic protection circuit includes a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor and a fifth protection transistor;
- the gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;
- the first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor.
- the second electrode of the body transistor is electrically connected to the gate of the third protection transistor;
- a first electrode of the third protection transistor is electrically connected to a gate of the second protection transistor, and a second electrode of the third protection transistor is electrically connected to a gate of the fourth protection transistor;
- a first electrode of the fourth protection transistor is electrically connected to a gate of the third protection transistor, and a second electrode of the fourth protection transistor is electrically connected to a gate of the fifth protection transistor;
- the gate of the fifth protection transistor and the first electrode of the fifth protection transistor are both electrically connected to the short-circuit line, and the second electrode of the fifth protection transistor is electrically connected to the gate of the fourth protection transistor;
- the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;
- the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;
- the channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor.
- an embodiment of the present disclosure provides a display device, comprising the above-mentioned display substrate.
- FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
- FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
- FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
- FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
- FIG5 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
- FIG. 6 is a waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG. 5 operates in the touch scanning stage SC;
- FIG. 7 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG. 5 is in operation when in a normal display state;
- FIG. 8 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG. 5 is in operation during the touch control stage;
- FIG9 is a timing diagram of the operation of at least one embodiment of the driving circuit shown in FIG5 ;
- FIG10 is a layout diagram of at least one embodiment of the driving circuit shown in FIG5 ;
- FIG11 is a layout diagram of the gate metal layer in FIG10 ;
- FIG12 is a layout diagram of the semiconductor layer in FIG10;
- FIG13 is a layout diagram of the conductive layer in FIG10;
- FIG14 is a layout diagram of the source/drain metal layer in FIG10 ;
- FIG15 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
- FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
- FIG17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
- FIG18 is a circuit diagram of at least one embodiment of an electrostatic protection circuit
- FIG. 19 is a layout diagram of at least one embodiment of an electrostatic protection circuit
- FIG20 is a circuit diagram of at least one embodiment of an electrostatic protection circuit
- FIG. 21 is a layout diagram of at least one embodiment of an electrostatic protection circuit.
- the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
- one of the electrodes is called the first electrode and the other is called the second electrode.
- the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
- the input circuit 11 is electrically connected to the input control terminal IK1, the input terminal I1 and the first node PU respectively, and is used to control the connection or disconnection between the input terminal I1 and the first node PU under the control of the input control signal provided by the input control terminal IK1;
- the first node reset circuit 13 is electrically connected to the second node PD, the first node PU and the first voltage line V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage line V1 under the control of the potential of the second node PD;
- the control node control circuit 31 is electrically connected to the first node PU, the third voltage line V3 and the control node N0 respectively, and is used to control the connection or disconnection between the control node N0 and the third voltage line V3 under the control of the potential of the first node PU;
- the transistors included in the input circuit 11, the transistors included in the reset circuit 12, and the transistors included in the first node reset circuit 13 are arranged in sequence along a direction away from the display area;
- the third voltage line may be a high voltage line.
- the input circuit includes at least two input transistors connected in series
- the reset circuit includes at least two reset transistors connected in series
- the input circuit may include at least two transistors in series with their gates electrically connected to the input control terminal
- the reset circuit may include at least two transistors in series with their gates electrically connected to the reset terminal, so as to replace the transistor in which the first pole or the second pole is electrically connected to the first node with at least two transistors in series, so as to reduce the leakage current of the first node and improve the stability of the driving circuit.
- the first node reset circuit includes at least two transistors connected in series with their gates electrically connected to the second node; or,
- the second node includes a first second node and a second second node;
- the first node reset circuit includes two transistors connected in series with the gate being electrically connected to the first second node, and a transistor with the gate being electrically connected to the second second node.
- the node is electrically connected to at least two transistors connected in series with each other.
- the first node reset circuit may include at least two transistors whose gates are electrically connected to the second node;
- the first node reset circuit may include two transistors connected in series with the gate being electrically connected to the first second node, and at least two transistors connected in series with the gate being electrically connected to the second second node;
- the transistor electrically connected to the first electrode or the second electrode and the first node is replaced by at least two transistors connected in series, so as to reduce the leakage current of the first node and improve the stability of the driving circuit.
- the driving circuit according to at least one embodiment of the present disclosure further includes a frame reset circuit 21 ;
- the frame reset circuit 21 is electrically connected to the frame reset line STV0, the first node PU and the second voltage line V2 respectively, and is used to control the connection or disconnection between the first node PU and the second voltage line V2 under the control of the frame reset signal provided by the frame reset line STV0;
- the transistor included in the frame reset circuit 21 is arranged on a side of the transistor included in the first node reset circuit 13 away from the display area.
- the second voltage line may be a second low voltage line, but is not limited thereto.
- the driving circuit described in at least one embodiment of the present disclosure may further include a frame reset circuit 21, which controls the resetting of the potential of the first node PU under the control of a frame reset signal during a blank period between two frames of display time; the transistor included in the frame reset circuit 21 is arranged on the side of the transistor included in the first node reset circuit 13 away from the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the lateral space of the border of the display substrate.
- a frame reset circuit 21 which controls the resetting of the potential of the first node PU under the control of a frame reset signal during a blank period between two frames of display time
- the transistor included in the frame reset circuit 21 is arranged on the side of the transistor included in the first node reset circuit 13 away from the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the lateral space of the border of the display substrate.
- the frame reset circuit includes at least two frame reset transistors connected in series.
- the frame reset circuit may include at least two transistors whose gates are electrically connected to the frame reset line and are connected in series. At least one embodiment of the present disclosure replaces the transistor whose first electrode or the second electrode is electrically connected to the first node with at least two transistors connected in series to reduce the leakage current of the first node and improve the stability of the driving circuit.
- the transistor included in the control node control circuit is arranged on a side of the transistor included in the input circuit close to the display area.
- the transistor included in the control node control circuit can be arranged on a side of the transistor included in the input circuit close to the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the lateral space of the frame of the display substrate.
- control node control circuit includes a control transistor
- a gate of the control transistor is electrically connected to the first node, a first electrode of the control transistor is electrically connected to the third voltage line, and a second electrode of the control transistor is electrically connected to the control node.
- the driving circuit described in at least one embodiment of the present disclosure further includes a shutdown reset circuit
- the shutdown reset circuit is electrically connected to the fourth voltage line and the drive signal output terminal respectively, and is used for Under the control of a fourth voltage signal provided by the line, the drive signal output terminal is controlled to be connected or disconnected with the fourth voltage line.
- the fourth voltage line may be a first low voltage line.
- the driving circuit may further include a shutdown reset circuit, and the shutdown reset circuit controls the connection or disconnection between the driving signal output terminal and the fourth voltage line under the control of the fourth voltage signal.
- the driving circuit described in at least one embodiment of the present disclosure further includes a shutdown reset circuit 41 ;
- the shutdown reset circuit 41 is electrically connected to the fourth voltage line V4 and the drive signal output terminal GT respectively, and is used to control the connection or disconnection between the drive signal output terminal GT and the fourth voltage line V4 under the control of the fourth voltage signal provided by the fourth voltage line V4.
- the transistor included in the shutdown reset circuit 41 when the transistor included in the shutdown reset circuit 41 is an n-type transistor, when the display panel displays normally, the fourth voltage line V4 provides a low voltage signal, and when the display panel is ready to shut down, the voltage signal provided by the fourth voltage line V4 has a high voltage. Under the control of the fourth voltage signal, the shutdown reset circuit 41 controls the connection between the drive signal output terminal GT and the fourth voltage line V4, so that the drive signal output terminal GT outputs a high voltage signal, which can release the residual charge in the pixel, and can effectively improve the opening ability of the drive signal output terminal GT to avoid poor afterimage.
- At least one embodiment of the present disclosure controls the drive signal output terminal GT to output a high voltage signal under the control of the fourth voltage signal when the power is turned off to release the residual charge in the pixel, which can effectively improve the opening capability of the drive signal output terminal GT and avoid poor residual images.
- the transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit close to the display area.
- the transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit close to the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the lateral space of the frame of the display substrate.
- the shutdown reset circuit includes a shutdown reset transistor
- the gate of the shutdown reset transistor and the first electrode of the shutdown reset transistor are electrically connected to the fourth voltage line, and the second electrode of the shutdown reset transistor is electrically connected to the driving signal output terminal.
- the input circuit includes a first input transistor and a second input transistor
- the gate of the first input transistor is electrically connected to the input control terminal, the first electrode of the first input transistor is electrically connected to the input terminal, and the second electrode of the first input transistor is electrically connected to the control node;
- the gate of the second input transistor is electrically connected to the input control terminal, and the first electrode of the second input transistor The first electrode of the second input transistor is electrically connected to the control node, and the second electrode of the second input transistor is electrically connected to the first node.
- the input control terminal is a carry signal output terminal of an adjacent previous stage driving circuit, and the input terminal is a drive signal output terminal of an adjacent previous stage driving circuit;
- the input control terminal and the input terminal are both carry signal output terminals of the adjacent previous stage driving circuit.
- the input control terminal can be the carry signal output terminal of the adjacent previous level driving circuit, and the input terminal can be the drive signal output terminal of the adjacent previous level driving circuit; or, the input control terminal and the input terminal can both be the carry signal output terminal of the adjacent previous level driving circuit.
- the reset circuit includes a first reset transistor and a second reset transistor
- the gate of the first reset transistor is electrically connected to the reset terminal, the first electrode of the first reset transistor is electrically connected to the first node, and the second electrode of the first reset transistor is electrically connected to the control node;
- a gate of the second reset transistor is electrically connected to the reset terminal, a first electrode of the second reset transistor is electrically connected to the control node, and a second electrode of the second reset transistor is electrically connected to the first voltage line.
- control node control circuit includes a transistor having a channel width-to-length ratio that is smaller than a channel width-to-length ratio of the second reset transistor.
- the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the second reset transistor can be adjusted.
- the competitiveness of the second reset transistor is improved, so that the potential of the control node and the potential of the first node are quickly reduced to a low voltage, ensuring that the potential of the second node can be synchronously increased to a high voltage to start noise reduction.
- the channel width-to-length ratio of the transistor included in the control node control circuit may be 5/12, and the channel width-to-length ratio of the second reset transistor may be 5/6, but is not limited thereto.
- the first node reset circuit includes a first pull-down transistor and a second pull-down transistor;
- the gate of the first pull-down transistor is electrically connected to the second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node;
- a gate of the second pull-down transistor is electrically connected to the second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line.
- a ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.
- the ratio of the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the transistor included in the control node control circuit can be adjusted to prevent the noise of the control node from being introduced into the first node through leakage, thereby improving the stability of the driving circuit and preventing multiple outputs.
- the channel width-to-length ratio of the transistor included in the control node control circuit may be 5/12
- the channel width-to-length ratio of the second pull-down transistor may be 30/6
- the ratio between the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the second pull-down transistor is 1:12, but is not limited thereto.
- a channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor.
- the channel width-to-length ratio of the second pull-down transistor may be greater than the channel width-to-length ratio of the first pull-down transistor.
- the channel width-to-length ratio of the first pull-down transistor may be 15/6
- the channel width-to-length ratio of the second pull-down transistor may be 30/6, but is not limited thereto.
- the first node reset circuit includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor and a fourth pull-down transistor;
- the gate of the second pull-down transistor is electrically connected to the first second node, the first electrode of the second pull-down transistor is electrically connected to the control node, and the second electrode of the second pull-down transistor is electrically connected to the first voltage line;
- the gate of the third pull-down transistor is electrically connected to the second second node, the first electrode of the third pull-down transistor is electrically connected to the first node, and the second electrode of the third pull-down transistor is electrically connected to the control node;
- a gate of the fourth pull-down transistor is electrically connected to the second second node, a first electrode of the fourth pull-down transistor is electrically connected to the control node, and a second electrode of the fourth pull-down transistor is electrically connected to the first voltage line.
- the channel width-to-length ratio of the first pull-down transistor and the channel width-to-length ratio of the third pull-down transistor may be 15/6
- the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the fourth pull-down transistor may be 30/6, but is not limited thereto.
- a ratio of a channel width-to-length ratio of the fourth pull-down transistor to a channel width-to-length ratio of the control transistor is greater than or equal to 6 and less than or equal to 24.
- the ratio of the channel width-to-length ratio of the second pull-down transistor to the channel width-to-length ratio of the transistor included in the control node control circuit can be adjusted, and the ratio of the channel width-to-length ratio of the fourth pull-down transistor to the channel width-to-length ratio of the transistor included in the control node control circuit can be adjusted to prevent the noise of the control node from being introduced into the first node through leakage, thereby improving the driving efficiency. Circuit stability to prevent multiple outputs.
- the channel width-to-length ratio of the transistor included in the control node control circuit may be 5/12
- the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the fourth pull-down transistor may be 30/6
- the ratio between the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the second pull-down transistor is 1:12
- the ratio between the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the fourth pull-down transistor is 1:12, but is not limited to this.
- the gate of the first frame reset transistor is electrically connected to the frame reset line, the first electrode of the first frame reset transistor is electrically connected to the first node, and the second electrode of the first frame reset transistor is electrically connected to the control node;
- a frame reset circuit electrically connected to the first node may be configured to include a first frame reset transistor and a second frame reset transistor connected in series to reduce leakage of the first node.
- the driving circuit described in at least one embodiment of the present disclosure further includes a carry signal output circuit, a driving signal output circuit and an energy storage circuit;
- the carry signal output circuit is electrically connected to the first node, the second node, the carry signal output terminal, the clock signal terminal and the second voltage line respectively, and is used to control the connection or disconnection between the carry signal output terminal and the clock signal terminal under the control of the potential of the first node, and to control the connection or disconnection between the carry signal output terminal and the second voltage line under the control of the potential of the second node;
- the drive signal output circuit is electrically connected to the first node, the second node, the drive signal output terminal, the clock signal terminal and the fourth voltage line respectively, and is used to control the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and control the connection or disconnection between the drive signal output terminal and the fourth voltage line under the control of the potential of the second node;
- the energy storage circuit is electrically connected to the first node and the driving signal output terminal respectively, and is used for storing electric energy.
- the second voltage line may be a second low voltage line
- the fourth voltage line may be a first low voltage line
- the fourth voltage line is used to provide a fourth voltage signal
- the second voltage line is used to provide a second voltage signal
- the voltage value of the fourth voltage signal is equal to the voltage value of the second voltage signal, or the voltage value of the second voltage signal is smaller than the voltage value of the fourth voltage signal.
- the drive circuit may further include a carry signal output circuit and a drive signal output circuit.
- the carry signal output circuit controls the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and controls the connection or disconnection between the drive signal output terminal and the third voltage line under the control of the potential of the second node;
- the drive signal output circuit controls the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and controls the connection or disconnection between the drive signal output terminal and the third voltage line under the control of the potential of the second node.
- the driving circuit described in at least one embodiment of the present disclosure further includes a second node control circuit
- the second node control circuit is electrically connected to the input control terminal, the first node, the second node and the second voltage line, respectively, and is used to control the connection or disconnection between the second node and the second voltage line under the control of the input control signal provided by the input control terminal, and to control the potential of the second node under the control of the potential of the first node.
- the driving circuit may include a second node control circuit, which controls the connection or disconnection between the second node and the fourth voltage line under the control of an input control signal, and controls the potential of the second node under the control of the potential of the first node.
- the driving circuit described in at least one embodiment of the present disclosure includes a first second node PD1, a second second node PD2, a second node control circuit 43, a tank circuit 40, a carry signal output circuit 44, and a driving signal output circuit 45;
- the first node reset circuit 13 is electrically connected to the first second node PD1, the second second node PD2, the first node PU and the first voltage line V1, respectively, and is used to control the connection between the first node PU and the first voltage line V1 under the control of the potential of the first second node PD1, and control the connection between the first node PU and the first voltage line V1 under the control of the potential of the second second node PD2;
- the second node control circuit 43 is electrically connected to the input control terminal IK1, the first node PU, the first second node PD1, the second second node PD2 and the second voltage line V2, respectively, and is used to control the connection between the first second node PD1 and the second voltage line V2, and the connection between the second second node PD2 and the second voltage line V2 under the control of the input control signal provided by the input control terminal IK1, and control the potential of the first second node PD1 and the potential of the second second node PD2 under the control of the potential of the first node PU;
- the first end of the energy storage circuit 40 is electrically connected to the first node PU, the second end of the energy storage circuit 40 is electrically connected to the driving signal output terminal GT, and the energy storage circuit 40 is used to store electrical energy;
- the carry signal output circuit 44 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the carry signal output terminal OC, the clock signal terminal CLK and the second voltage line V2 respectively, and is used to control the communication between the carry signal output terminal OC and the clock signal terminal CLK under the control of the potential of the first node PU, control the communication between the carry signal output terminal OC and the second voltage line V2 under the control of the potential of the first second node PD1, and control the communication between the carry signal output terminal OC and the second voltage line V2 under the control of the potential of the second second node PD2;
- the drive signal output circuit 45 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the drive signal output terminal GT, the clock signal terminal CLK and the fourth voltage line V4, respectively, and is used to control the connection between the drive signal output terminal GT and the clock signal terminal CLK under the control of the potential of the first node PU, and to control the connection between the drive signal output terminal GT and the clock signal terminal CLK under the control of the potential of the first second node PD1.
- the four voltage lines V4 are connected to each other, and under the control of the potential of the second second node PD2, the driving signal output terminal GT is controlled to be connected to the fourth voltage line V4.
- the shutdown reset circuit includes a shutdown reset transistor M14;
- the gate of the shutdown reset transistor M14 and the source of the shutdown reset transistor M14 are electrically connected to the first low voltage line VGL, and the drain of the shutdown reset transistor M14 is electrically connected to the drive signal output terminal GT;
- the control node control circuit includes a control transistor M0;
- the gate of the control transistor M0 is electrically connected to the first node PU, the source of the control transistor M0 is electrically connected to the high voltage line VGH, and the drain of the control transistor M0 is electrically connected to the control node N0;
- the input circuit includes a first input transistor M1A and a second input transistor M1B;
- the gate of the first input transistor M1A is electrically connected to the input control terminal IK1, the source of the first input transistor M1A is electrically connected to the input terminal I0, and the drain of the first input transistor M1A is electrically connected to the control node N0;
- the gate of the second input transistor M1B is electrically connected to the input control terminal IK1, the source of the second input transistor M1B is electrically connected to the control node N0, and the drain of the second input transistor M1B is electrically connected to the first node PU;
- the reset circuit includes a first reset transistor M2A and a second reset transistor M2B;
- the gate of the first reset transistor M2A is electrically connected to the reset terminal R1, the source of the first reset transistor M2A is electrically connected to the first node PU, and the drain of the first reset transistor M2A is electrically connected to the control node N0;
- a gate of the second reset transistor M2B is electrically connected to the reset terminal R1, a source of the second reset transistor M2B is electrically connected to the control node N0, and a drain of the second reset transistor M2B is electrically connected to the first low voltage line VGL;
- the first node reset circuit includes a first pull-down transistor M8A, a second pull-down transistor M8C, a third pull-down transistor M8B and a fourth pull-down transistor M8D;
- the gate of the first pull-down transistor M8A is electrically connected to the first second node PD1, the source of the first pull-down transistor M8A is electrically connected to the first node PU, and the drain of the first pull-down transistor M8A is electrically connected to the control node N0;
- the gate of the second pull-down transistor M8C is electrically connected to the first second node PD1, the source of the second pull-down transistor M8C is electrically connected to the control node N0, and the drain of the second pull-down transistor M8C is electrically connected to the first low voltage line VGL;
- the gate of the third pull-down transistor M8B is electrically connected to the second second node PD2, the source of the third pull-down transistor M8B is electrically connected to the first node PU, and the drain of the third pull-down transistor M8B is electrically connected to the control node N0;
- the gate of the fourth pull-down transistor M8D is electrically connected to the second second node PD2.
- the source of the transistor M8D is electrically connected to the control node N0, and the drain of the fourth pull-down transistor M8D is electrically connected to the first low voltage line VGL;
- the frame reset circuit includes a first frame reset transistor M15A and a second frame reset transistor M15B;
- the gate of the first frame reset transistor M15A is electrically connected to the frame reset line STV0, the source of the first frame reset transistor M15A is electrically connected to the first node PU, and the drain of the first frame reset transistor M15A is electrically connected to the control node N0;
- the gate of the second frame reset transistor M15B is electrically connected to the frame reset line STV0, the source of the second frame reset transistor M15B is electrically connected to the control node N0, and the drain of the second frame reset transistor M15B is electrically connected to the second low voltage line LVGL;
- the second node control circuit includes a first control transistor M5A, a second control transistor M6A, a third control transistor M16A, a fourth control transistor M5B, a fifth control transistor M6B and a sixth control transistor M16B;
- the gate of the first control transistor M5A and the source of the first control transistor M5A are both electrically connected to the first control voltage line VDDO, and the drain of the first control transistor M5A is electrically connected to the first second node PD1;
- the gate of the second control transistor M6A is electrically connected to the first node PU, the source of the second control transistor M6A is electrically connected to the first second node PD1, and the drain of the second control transistor M6A is electrically connected to the second low voltage line LVGL;
- the gate of the third control transistor M16A is electrically connected to the input control terminal IK1, the source of the third control transistor M16A is electrically connected to the first second node PD1, and the drain of the third control transistor M16A is electrically connected to the second low voltage line LVGL;
- the gate of the fourth control transistor M5B and the source of the second control transistor M5B are both electrically connected to the second control voltage line VDDE, and the drain of the second control transistor M5B is electrically connected to the second second node PD2;
- the gate of the fifth control transistor M6B is electrically connected to the first node PU, the source of the fifth control transistor M6B is electrically connected to the second second node PD2, and the drain of the fifth control transistor M6B is electrically connected to the second low voltage line LVGL;
- the gate of the sixth control transistor M16B is electrically connected to the input control terminal IK1, the source of the sixth control transistor M16B is electrically connected to the second second node PD2, and the drain of the sixth control transistor M16B is electrically connected to the second low voltage line LVGL;
- the energy storage circuit includes a storage capacitor C0;
- the first electrode plate of C0 is electrically connected to the first node PU, and the second electrode plate of C0 is electrically connected to the driving signal output terminal GT;
- the carry signal output circuit includes a carry output transistor M11, a first carry reset transistor M12A and a second carry reset transistor M12B, and the drive signal output circuit includes a drive output transistor M3, a first drive reset transistor M13A, a second drive reset transistor M13B and an output reset transistor M4;
- the gate of the carry output transistor M11 is electrically connected to the first node PU, the source of the carry output transistor M11 is electrically connected to the clock signal terminal CLK, and the drain of the carry output transistor M11 is electrically connected to the carry signal output terminal OC;
- the gate of the second carry reset transistor M12B is electrically connected to the second second node PD2, the source of the second carry reset transistor M12B is electrically connected to the carry signal output terminal OC, and the drain of the second carry reset transistor M12B is electrically connected to the second low voltage line LVGL;
- the gate of the driving output transistor M3 is electrically connected to the first node PU, the source of the driving output transistor M3 is electrically connected to the clock signal terminal CLK, and the drain of the driving output transistor M3 is electrically connected to the driving signal output terminal GT;
- the gate of the second driving reset transistor M13B is electrically connected to the second second node PD2, the source of the second driving reset transistor M13B is electrically connected to the driving signal output terminal GT, and the drain of the second driving reset transistor M13B is electrically connected to the first low voltage line VGL;
- the gate of the output reset transistor M4 is electrically connected to the reset control signal terminal R0, the source of the output reset transistor M4 is electrically connected to the drive signal output terminal GT, and the drain of the output reset transistor M4 is electrically connected to the first low voltage line VGL.
- the input control terminal IK1 is a carry signal output terminal of the adjacent previous stage driving circuit, and the input terminal I0 is a drive signal output terminal of the adjacent previous stage driving circuit;
- all transistors are n-type transistors, but the present invention is not limited thereto.
- a control transistor M0 is used to control the potential of the control node N0.
- the potential of the first node PU is a high voltage
- the potential of the control node N0 is charged to a high voltage.
- the leakage path of the first node PU is from PU to N0, so as to effectively prevent the leakage of the first node PU and improve the driving capability of the display product.
- the drain of the first input transistor M1A is electrically connected to the control node N0; the source of the second input transistor M1B is electrically connected to the control node N0; the drain of the first reset transistor M2A is electrically connected to the control node N0; the source of the second reset transistor M2B is electrically connected to the control node N0; the drain of the first pull-down transistor M8A is electrically connected to the control node N0; the source of the second pull-down transistor M8C is electrically connected to the control node N0; the drain of the third pull-down transistor M8B is electrically connected to the control node N0; the source of the fourth pull-down transistor M8D is electrically connected to the control node N0; the drain of the first frame reset transistor M15A is electrically connected to the control node N0; the source of the second frame reset transistor M15B is electrically connected to the control node N0; at least one embodiment of the present disclosure sets the transistor whose source or drain is electrically connected to the first no
- M0, M2B, M8C, M8D, M15B, M16A and M16B together constitute a PU voltage ensuring unit; when I1 provides a high voltage signal to charge the first node PU of the driving circuit at this level, M16A and M16B are turned on, at this time, the potential of PD1 and the potential of PD2 are quickly pulled down, M8A, M8B, M8C and M8D are turned off, and at the same time, the potential of PU rises, M0 is turned on, and the potential of N0 is charged to a high voltage.
- the leakage path of PU is PU-N0, and the drain-source voltage of M1A, the drain-source voltage of M2A, the drain-source voltage of M8A, the drain-source voltage of M8B and the drain-source voltage of M15A are greatly reduced, close to or equal to 0V, effectively preventing leakage of the first node PU and improving the driving capability of the display product.
- the channel width-to-length ratio of M0 and the channel width-to-length ratio of M2B are adjusted.
- the competitiveness of M2B is improved, so that the potential of N0 and the voltage of the first node PU are quickly pulled down, ensuring that the potential of the pull-down node can be synchronously increased to a high voltage, and starting to reduce the noise of the drive signal and the carry signal.
- the channel width-to-length ratio of M0 may be 5/12
- the channel width-to-length ratio of M2B may be 5/6
- the channel width-to-length ratio of M8C may be 30/6
- the channel width-to-length ratio of M8D may be 30/6
- the channel width-to-length ratio of M8A and the channel width-to-length ratio of M8B may be 15/6;
- the drain of the first carry reset transistor M12A is electrically connected to the second low voltage line LVGL; the drain of the second carry reset transistor M12B is electrically connected to the second low voltage line LVGL; the drain of the first drive reset transistor M13A is electrically connected to the first low voltage line VGL; the drain of the second drive reset transistor M13B is electrically connected to the first low voltage line VGL;
- the first low voltage line VGL is used to provide a first low voltage signal
- the second low voltage line LVGL is used to provide a second low voltage signal
- the voltage value of the second low voltage signal can be smaller than the voltage value of the first low voltage signal.
- the drain of M2B is electrically connected to the first low voltage line VGL, the voltage value of the second low voltage signal provided by the second low voltage line is less than the voltage value of the first low voltage signal provided by the first low voltage line, the gate-source voltage of M2B, the gate-source voltage of M8C and the gate-source voltage of M8D are all less than 0V.
- the working state of M2B, the working state of M8C and the working state of M8D change from the subthreshold region to the off state, and the leakage current is greatly reduced.
- the first low voltage line VGL provides a low voltage signal.
- M14 is turned on, and the drive signal output terminal GT is controlled to output a high voltage signal, which can release the residual charge in the pixel, effectively improve the opening ability of the drive signal output terminal GT, and avoid poor afterimage.
- FIG. 7 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG. 5 is in operation when in a normal display state;
- FIG8 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG5 is in operation during the touch stage; at this time, the highest potential of PU may be around 16.95V.
- FIG. 9 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 5 .
- the channel width-to-length ratio of M14 can be selected according to actual conditions.
- the channel width-to-length ratio of M14 is usually close to the channel width-to-length ratio of M4, ensuring that when the display panel is ready to shut down, the potential of the driving signal provided by GT can be sufficiently and quickly pulled up to a high level.
- the first control voltage provided by VDDO and the second control voltage provided by VDDE may be square wave signals, and the first control voltage and the second control voltage are inversely phased to each other, so that PD1 and PD2 work alternately.
- FIG. 10 is a layout diagram of at least one embodiment of the driving circuit shown in FIG. 5 , wherein the driving circuit is disposed on a substrate.
- FIG. 11 is a layout diagram of the gate metal layer in FIG. 10
- FIG. 12 is a layout diagram of the semiconductor layer in FIG. 10
- FIG. 13 is a layout diagram of the conductive layer in FIG. 10
- FIG. 14 is a layout diagram of the source/drain metal layer in FIG. 10 .
- CLKA is the first clock signal line
- CLKB is the second clock signal line
- CLKC is the third clock signal line
- CLKD is the fourth clock signal line
- STV is the start voltage line
- VDDO is the first control voltage line
- VDDE is the second control voltage line
- STV0 is the frame reset line
- LVGL is the second low voltage line
- VGL1 is the first low voltage line
- VGL2 is the second low voltage line
- VGH is the high voltage line
- CLKA, CLKB, CLKC, CLKD, STV, VDDO, VDDE, STV0, LVGL and VGL1 extend in a vertical direction;
- CLKA, CLKB, CLKC, CLKD, STV, VDDO, VDDE, STV0, LVGL and VGL1 are arranged on a side of the driving circuit away from the display area;
- VGL2 and VGH extend in the vertical direction
- VGL2 and VGH are arranged on a side of the driving circuit close to the display area.
- the transistor included in the input circuit, the transistor included in the reset circuit, and the transistor included in the first node reset circuit are arranged in sequence along a direction away from the display area;
- M14 is arranged on a side of M0 away from the display area, and M0 is arranged on a side of M1A and M1B away from the display area;
- the orthographic projection of the active pattern of M11 on the substrate, the orthographic projection of the first electrode plate of C0 on the substrate, and the orthographic projection of the active pattern of M1A on the substrate are arranged in sequence along the vertical direction;
- the orthographic projection of the active pattern of M11 on the substrate, the orthographic projection of the first electrode plate of C0 on the substrate, and the orthographic projection of the active pattern of M1B on the substrate are arranged in sequence along the vertical direction;
- M11, C0, M1A and M1B are arranged in a longitudinal space to facilitate the realization of a narrow frame;
- M1A and M1B are arranged side by side, M1A and M1B are arranged in a horizontal direction, and M1B is arranged on a side of M1A away from the display area;
- M14 and M4 are arranged in sequence along the vertical direction to utilize the longitudinal space layout of M14 and M4, which is conducive to achieving a narrow frame;
- M3 and M0 are arranged in sequence along the vertical direction to utilize the longitudinal space to layout M3 and M0, which is conducive to achieving a narrow frame;
- M3 is set between M14 and M11;
- M2A and M2B are arranged side by side, and M2B and M2A are arranged in the horizontal direction;
- M8D, M8B and M7A are arranged in sequence along the vertical direction, and M8D, M8B and M7B are arranged in sequence along the vertical direction, so as to utilize the longitudinal space to arrange M8D, M8B, M7A and M7B, which is conducive to achieving a narrow frame;
- M8C and M8A are arranged in sequence along the vertical direction to utilize the vertical space to layout M8C and M8A, which is conducive to narrow bezels;
- M8D and M8C are arranged side by side
- M8B and M8A are arranged side by side
- M8C and M8D are arranged in a horizontal direction
- M8A and M8B are arranged in a horizontal direction
- M8D is arranged on a side of M8C away from the display area
- M8B is arranged on a side of M8A away from the display area
- M12B, M13B, M13A and M12A are arranged in sequence along the vertical direction, so as to utilize the vertical space to arrange M12B, M13B, M13A and M12A, which is conducive to achieving a narrow frame;
- M13B is arranged on a side of M8D away from the display area
- M6B, M15A and M16A are arranged in sequence along the vertical direction, and M6B, M15B and M16A are arranged in sequence along the vertical direction to utilize the vertical space to set M6B, M15A, M15B and M16A;
- the M15A and M15B are set side by side horizontally;
- M6B is arranged on a side of M12B away from the display area
- M5B and M5A are arranged in sequence along the vertical direction; M5A is arranged on a side of M6A away from the display area.
- CLKA1 is a first clock signal line portion included in CLKA
- CLKB1 is a first clock signal line portion included in CLKB
- CLKD1 is a first clock signal line portion included in CLKD
- CLKD1 is a first clock signal line portion included in CLKD.
- A8D is an active pattern of M8D
- A8C is an active pattern of M8C
- A8B is an active pattern of M8B
- A8A is an active pattern of M8A.
- CLKA2 is a second clock signal line portion included in CLKA
- CLKB2 is a second clock signal line portion included in CLKB
- CLKD2 is a second clock signal line portion included in CLKD
- CLKD2 is a second clock signal line portion included in CLKD;
- CLKA2 may be electrically connected to CLKA1
- CLKB2 may be electrically connected to CLKB1
- CLKC2 may be electrically connected to CLKC1
- CLKD2 may be electrically connected to CLKD1 .
- control node N0 are not set
- the drain of the first input transistor M1A is electrically connected to the source of the second input transistor M1B;
- the drain of the first reset transistor M2A is electrically connected to the source of the second reset transistor M2B;
- the drain of the first pull-down transistor M8A is electrically connected to the source of the second pull-down transistor M8C;
- the drain of the third pull-down transistor M8B is electrically connected to the source of the fourth pull-down transistor M8D;
- a drain of the first frame reset transistor M15A is electrically connected to a source of the second frame reset transistor M15B.
- the gate of M1A and the gate of M1B are both electrically connected to I1;
- the drain of M2B is electrically connected to the second low voltage line LVGL
- the drain of M8C is electrically connected to the second low voltage line LVGL
- the drain of M8D is electrically connected to the second low voltage line LVGL.
- the input circuit includes an input transistor M1;
- the gate of the input transistor M1 and the source of the input transistor M1 are both electrically connected to the input terminal I0, and the drain of the input transistor M1 is electrically connected to the first node PU;
- the reset circuit includes a reset transistor M2;
- the gate of the reset transistor M2 is electrically connected to the reset terminal R1, the source of the reset transistor M2 is electrically connected to the first node PU, and the drain of the reset transistor M2 is electrically connected to the first low voltage line VGL;
- the first node reset circuit includes a first pull-down transistor M8A and a third pull-down transistor M8B;
- the gate of the first pull-down transistor M8A is electrically connected to the first second node PD1, the source of the first pull-down transistor M8A is electrically connected to the first node PU, and the drain of the first pull-down transistor M8A is electrically connected to the second low voltage line LVGL;
- the gate of the third pull-down transistor M8B is electrically connected to the second second node PD2, the source of the third pull-down transistor M8B is electrically connected to the first node PU, and the drain of the third pull-down transistor M8B is electrically connected to the second low voltage line LVGL;
- the frame reset circuit includes a frame reset transistor M15;
- a gate of the frame reset transistor M15 is electrically connected to the frame reset line STV0 , a source of the frame reset transistor M15 is electrically connected to the first node PU, and a drain of the frame reset transistor M15 is electrically connected to the second low voltage line LVGL.
- the display substrate described in the embodiment of the present disclosure includes a substrate and the above-mentioned driving circuit arranged on the substrate.
- the display substrate described in at least one embodiment of the present disclosure further includes an electrostatic protection circuit disposed on the substrate;
- the first end of the electrostatic protection circuit is electrically connected to the driving signal line, the second end of the electrostatic protection circuit is electrically connected to the common electrode voltage terminal through a short-circuit line, and the electrostatic protection circuit is used for electrostatic protection;
- the driving signal lines include a DC voltage line, a clock signal line, a control voltage line and a frame reset line.
- the driving signal line is a metal line that runs through the entire display panel and is located on the display surface.
- the edge of the board is very susceptible to high voltage and burnt when static electricity exists in the outside world. Therefore, an electrostatic protection circuit is set between the signal line and the shorting bar to disperse the instantaneous voltage and prevent the driving signal line from being burned.
- At least one embodiment of the present disclosure provides a specific structure of an electrostatic protection circuit, which adopts a mixed design of large and small TFTs (thin film transistors). On the basis of ensuring electrostatic release performance, it can reduce the current between signals and reduce crosstalk. At the same time, due to the small size of TFTs, the layout space is smaller.
- TFTs thin film transistors
- the electrostatic protection circuit includes a first protection transistor, a second protection transistor and a third protection transistor;
- the gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;
- the first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor;
- the gate of the third protection transistor and the first electrode of the third protection transistor are both electrically connected to the short-circuit line, and the second electrode of the third protection transistor is electrically connected to the gate of the second protection transistor;
- the channel width-to-length ratio of the first protection transistor is greater than that of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than that of the second protection transistor.
- the channel width-to-length ratio of the first protection transistor and the channel width-to-length ratio of the third protection transistor may be 3.5/8, and the channel width-to-length ratio of the second protection transistor may be 3.5/50, but is not limited thereto.
- the channel width-to-length ratio of the first protection transistor and the channel width-to-length ratio of the third protection transistor may be greater than or equal to 3.5/12 and less than or equal to 3.5/6
- the channel width-to-length ratio of the second protection transistor may be greater than or equal to 3.5/80 and less than or equal to 3.5/30, but is not limited to this.
- the electrostatic protection circuit includes a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor and a fifth protection transistor;
- the gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;
- the first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor;
- a first electrode of the third protection transistor is electrically connected to a gate of the second protection transistor, and a second electrode of the third protection transistor is electrically connected to a gate of the fourth protection transistor;
- a first electrode of the fourth protection transistor is electrically connected to a gate of the third protection transistor, and a second electrode of the fourth protection transistor is electrically connected to a gate of the fifth protection transistor;
- the gate of the fifth protection transistor and the first electrode of the fifth protection transistor are both electrically connected to the short-circuit line, and the second electrode of the fifth protection transistor is electrically connected to the gate of the fourth protection transistor;
- the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;
- the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;
- the channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor.
- the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor can be 3.5/8
- the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor can be 3.5/50, but are not limited to this.
- the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor may be greater than or equal to 3.5/12 and less than or equal to 3.5/6
- the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor may be greater than or equal to 3.5/80 and less than or equal to 3.5/30, but is not limited to this.
- At least one embodiment of the electrostatic protection circuit may include a first protection transistor T1 , a second protection transistor T2 , a third protection transistor T3 , a fourth protection transistor T4 , and a fifth protection transistor T5 ;
- the gate of the first protection transistor T1 and the source of the first protection transistor T1 are both electrically connected to the driving signal line QX, and the drain of the first protection transistor T1 is electrically connected to the gate of the second protection transistor T2;
- the source of the second protection transistor T2 is electrically connected to the gate of the first protection transistor T1, and the drain of the second protection transistor T2 is electrically connected to the gate of the third protection transistor T3;
- the source of the third protection transistor T3 is electrically connected to the gate of the second protection transistor T2, and the drain of the third protection transistor T3 is electrically connected to the gate of the fourth protection transistor T4;
- the source of the fourth protection transistor T4 is electrically connected to the gate of the third protection transistor T3, and the drain of the fourth protection transistor T4 is electrically connected to the gate of the fifth protection transistor T5;
- the gate of the fifth protection transistor T5 and the source of the fifth protection transistor T5 are both electrically connected to the short-circuit line SR, the drain of the fifth protection transistor T5 is electrically connected to the gate of the fourth protection transistor T4; the gate of T5 is electrically connected to the common electrode voltage terminal CM;
- the channel width-to-length ratio of the first protection transistor T1 is greater than the channel width-to-length ratio of the second protection transistor T2, and the channel width-to-length ratio of the first protection transistor T1 is greater than the channel width-to-length ratio of the fourth protection transistor T4;
- the channel width-to-length ratio of the third protection transistor T3 is greater than the channel width-to-length ratio of the second protection transistor T2, and the channel width-to-length ratio of the third protection transistor T3 is greater than the channel width-to-length ratio of the fourth protection transistor T4;
- the channel width-to-length ratio of the fifth protection transistor T5 is greater than the channel width-to-length ratio of the second protection transistor T2 , and the channel width-to-length ratio of the fifth protection transistor T5 is greater than the channel width-to-length ratio of the fourth protection transistor T4 .
- the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor may be greater than or equal to 3.5/12 and less than or equal to 3.5/6
- the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor may be greater than or equal to 3.5/80 and less than or equal to 3.5/30.
- FIG. 19 is a layout diagram of at least one embodiment of an electrostatic protection circuit.
- CLKA is a first clock signal line
- CLKB is a second clock signal line
- CLKC is a third clock signal line
- CLKD is a fourth clock signal line
- STV is a start voltage line
- VDDO is a first control voltage line
- VDDE is a second control voltage line
- STV0 is a frame reset line
- LVGL is a second low voltage line
- VGL is a first low voltage line
- the one marked SR is a short route
- the one labeled E1 is the first electrostatic protection circuit
- the one labeled E2 is the second electrostatic protection circuit
- the one labeled E3 is the third electrostatic protection circuit
- the one labeled E4 is the fourth electrostatic protection circuit
- the one labeled E5 is the fifth electrostatic protection circuit
- the one labeled E6 is the sixth electrostatic protection circuit
- the one labeled E7 is the seventh electrostatic protection circuit
- the one labeled E8 is the eighth electrostatic protection circuit
- the one labeled E9 is the ninth electrostatic protection circuit
- the one labeled E10 is the tenth electrostatic protection circuit.
- the first protection transistor in E5 is labeled T1
- the second protection transistor in E5 is labeled T2
- the third protection transistor in E5 is labeled T3
- the fourth protection transistor in E5 is labeled T4
- the fifth protection transistor in E5 is labeled T5.
- M2 and M4 are arranged side by side in the horizontal direction
- M1 , M3 and M5 are arranged side by side in the horizontal direction.
- the terminal labeled CM is a common electrode voltage terminal.
- At least one embodiment of the electrostatic protection circuit may include a first protection transistor T1 and a second protection transistor T2 ;
- the gate of T1 and the source of T1 are both electrically connected to the driving signal line QX, and the drain of T1 is electrically connected to the gate of T2;
- the source of T2 is electrically connected to the gate of T1 , and the gate of T1 is electrically connected to the common electrode voltage terminal CM.
- the channel width-to-length ratio of T1 and the channel width-to-length ratio of T2 may be 3.5/180.
- FIG. 21 is a layout diagram of at least one embodiment of an electrostatic protection circuit.
- CLKA is a first clock signal line
- CLKB is a second clock signal line
- CLKC is a third clock signal line
- CLKD is a fourth clock signal line
- STV is a start voltage line
- VDDO is a first control voltage line
- VDDE is a second control voltage line
- STV0 is a frame reset line
- LVGL is a second low voltage line
- VGL is a first low voltage line
- the one marked SR is a short route
- the one labeled E1 is the first electrostatic protection circuit
- the one labeled E2 is the second electrostatic protection circuit
- the one labeled E3 is the third electrostatic protection circuit
- the one labeled E4 is the fourth electrostatic protection circuit
- the one labeled E5 is the fifth electrostatic protection circuit
- the one labeled E6 is the sixth electrostatic protection circuit
- the one labeled E7 is the seventh electrostatic protection circuit
- the one labeled E8 is the eighth electrostatic protection circuit
- the one labeled E9 is the ninth electrostatic protection circuit
- the one labeled E10 is the tenth electrostatic protection circuit.
- the first protection transistor in E5 is labeled T1
- the second protection transistor in E5 is labeled T2;
- the terminal labeled CM is a common electrode voltage terminal.
- the display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.
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Abstract
Description
本公开涉及显示技术领域,尤其涉及一种驱动电路、显示基板和显示装置。The present disclosure relates to the field of display technology, and in particular to a driving circuit, a display substrate and a display device.
近年来随着消费者对显示设备分辨率、刷新率的要求日渐提高,显示面板的驱动能力同样需进行相应的升级,高迁移率的氧化物晶体管应运而生。但其电学特性,较传统的晶体管的阈值电压偏负,驱动电路中部分晶体管长期工作在栅源电压为0V状态下,漏电流增加,导致功耗提升,并且,相关技术中不能合理的布局驱动电路中的晶体管,不能有效防止第一节点漏电,不能提升显示产品的驱动能力。相关的驱动电路不能防止控制节点的噪声通过漏电引入第一节点,不能提升驱动电路的稳定性,不能防止多输出。In recent years, as consumers' requirements for the resolution and refresh rate of display devices have been increasing, the driving capability of display panels also needs to be upgraded accordingly, and high-mobility oxide transistors have emerged. However, its electrical characteristics are more negative than the threshold voltage of traditional transistors. Some transistors in the driving circuit work for a long time with a gate-source voltage of 0V, which increases the leakage current and leads to increased power consumption. In addition, the related technology cannot reasonably arrange the transistors in the driving circuit, cannot effectively prevent leakage of the first node, and cannot improve the driving capability of the display product. The related driving circuit cannot prevent the noise of the control node from being introduced into the first node through leakage, cannot improve the stability of the driving circuit, and cannot prevent multiple outputs.
发明内容Summary of the invention
在一个方面中,本公开实施例提供一种驱动电路,包括输入电路、复位电路、第一节点复位电路和控制节点控制电路;In one aspect, an embodiment of the present disclosure provides a driving circuit, including an input circuit, a reset circuit, a first node reset circuit, and a control node control circuit;
所述输入电路分别与输入控制端、输入端和第一节点电连接,用于在所述输入控制端提供的输入控制信号的控制下,控制所述输入端与所述第一节点之间连通或断开;The input circuit is electrically connected to the input control terminal, the input terminal and the first node respectively, and is used to control the connection or disconnection between the input terminal and the first node under the control of the input control signal provided by the input control terminal;
所述复位电路分别与复位端、所述第一节点和第一电压线电连接,用于在所述复位端提供的复位信号的控制下,控制所述第一节点和第一电压线之间连通或断开;The reset circuit is electrically connected to the reset terminal, the first node and the first voltage line respectively, and is used to control the connection or disconnection between the first node and the first voltage line under the control of the reset signal provided by the reset terminal;
所述第一节点复位电路分别与第二节点、第一节点和第一电压线电连接,用于在所述第二节点的电位的控制下,控制所述第一节点与所述第一电压线之间连通或断开;The first node reset circuit is electrically connected to the second node, the first node and the first voltage line respectively, and is used to control the connection or disconnection between the first node and the first voltage line under the control of the potential of the second node;
所述控制节点控制电路分别与第一节点、第三电压线和控制节点电连接,用于在所述第一节点的电位的控制下,控制所述控制节点与第三电压线之间连通或断开;The control node control circuit is electrically connected to the first node, the third voltage line and the control node respectively, and is used to control the connection or disconnection between the control node and the third voltage line under the control of the potential of the first node;
所述输入电路包括的晶体管、所述复位电路包括的晶体管和所述第一节点复位电路包括的晶体管沿着远离显示区域的方向依次排列;The transistor included in the input circuit, the transistor included in the reset circuit and the transistor included in the first node reset circuit are arranged in sequence along a direction away from the display area;
所述第一节点复位电路包括的栅极与所述第二节点电连接的晶体管的沟道宽长比与所述控制节点控制电路包括的晶体管的沟道宽长比的比值大于或等于6而小于或等于24。A ratio of a channel width-to-length ratio of a transistor whose gate is electrically connected to the second node and included in the first node reset circuit to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.
可选的,本公开至少一实施例所述的驱动电路还包括帧复位电路;Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a frame reset circuit;
所述帧复位电路分别与帧复位线、第一节点和第二电压线电连接,用于在所述帧复位线提供的帧复位信号的控制下,控制所述第一节点与所述第二电压线之间连通或断开;The frame reset circuit is electrically connected to the frame reset line, the first node and the second voltage line respectively, and is used to control the connection or disconnection between the first node and the second voltage line under the control of the frame reset signal provided by the frame reset line;
所述帧复位电路包括的晶体管设置于所述第一节点复位电路包括的晶体管远离显示区域的一侧。The transistor included in the frame reset circuit is arranged on a side of the transistor included in the first node reset circuit away from the display area.
可选的,所述输入电路包括相互串联的至少两个输入晶体管,所述复位电路包括相互串联的至少两个复位晶体管。 Optionally, the input circuit includes at least two input transistors connected in series, and the reset circuit includes at least two reset transistors connected in series.
可选的,所述第一节点复位电路包括栅极与所述第二节点电连接的相互串联的至少两个晶体管;或者,Optionally, the first node reset circuit includes at least two transistors connected in series with their gates electrically connected to the second node; or,
所述第二节点包括第一个第二节点和第二个第二节点;所述第一节点复位电路包括栅极与所述第一个第二节点电连接的相互串联的至少两个晶体管,以及,栅极与所述第二个第二节点电连接的相互串联的至少两个晶体管。The second node includes a first second node and a second second node; the first node reset circuit includes at least two transistors connected in series with their gates electrically connected to the first second node, and at least two transistors connected in series with their gates electrically connected to the second second node.
可选的,所述帧复位电路包括相互串联的至少两个帧复位晶体管。Optionally, the frame reset circuit includes at least two frame reset transistors connected in series.
可选的,所述控制节点控制电路包括的晶体管设置于所述输入电路包括的晶体管靠近显示区域的一侧。Optionally, the transistor included in the control node control circuit is arranged on a side of the transistor included in the input circuit close to the display area.
可选的,所述控制节点控制电路包括控制晶体管;Optionally, the control node control circuit includes a control transistor;
所述控制晶体管的栅极与所述第一节点电连接,所述控制晶体管的第一极与所述第三电压线电连接,所述控制晶体管的第二极与所述控制节点电连接。A gate of the control transistor is electrically connected to the first node, a first electrode of the control transistor is electrically connected to the third voltage line, and a second electrode of the control transistor is electrically connected to the control node.
可选的,本公开至少一实施例所述的驱动电路还包括关机复位电路;Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a shutdown reset circuit;
所述关机复位电路分别与第四电压线和驱动信号输出端电连接,用于在所述第四电压线提供的第四电压信号的控制下,控制所述驱动信号输出端与所述第四电压线之间连通或断开。The shutdown reset circuit is electrically connected to the fourth voltage line and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the fourth voltage line under the control of a fourth voltage signal provided by the fourth voltage line.
可选的,所述关机复位电路包括的晶体管设置于所述输入电路包括的晶体管靠近显示区域的一侧。Optionally, the transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit close to the display area.
可选的,所述关机复位电路包括关机复位晶体管;Optionally, the shutdown reset circuit includes a shutdown reset transistor;
所述关机复位晶体管的栅极和所述关机复位晶体管的第一极与所述第四电压线电连接,所述关机复位晶体管的第二极与所述驱动信号输出端电连接。The gate of the shutdown reset transistor and the first electrode of the shutdown reset transistor are electrically connected to the fourth voltage line, and the second electrode of the shutdown reset transistor is electrically connected to the driving signal output terminal.
可选的,所述输入电路包括第一输入晶体管和第二输入晶体管;Optionally, the input circuit includes a first input transistor and a second input transistor;
所述第一输入晶体管的栅极与所述输入控制端电连接,所述第一输入晶体管的第一极与所述输入端电连接,所述第一输入晶体管的第二极与控制节点电连接;The gate of the first input transistor is electrically connected to the input control terminal, the first electrode of the first input transistor is electrically connected to the input terminal, and the second electrode of the first input transistor is electrically connected to the control node;
所述第二输入晶体管的栅极与所述输入控制端电连接,所述第二输入晶体管的第一极与所述控制节点电连接,所述第二输入晶体管的第二极与所述第一节点电连接。A gate of the second input transistor is electrically connected to the input control terminal, a first electrode of the second input transistor is electrically connected to the control node, and a second electrode of the second input transistor is electrically connected to the first node.
可选的,所述输入控制端为相邻上一级驱动电路的进位信号输出端,所述输入端为相邻上一级驱动电路的驱动信号输出端;或者,Optionally, the input control terminal is a carry signal output terminal of an adjacent previous stage driving circuit, and the input terminal is a drive signal output terminal of an adjacent previous stage driving circuit; or,
所述输入控制端和所述输入端都为相邻上一级驱动电路的进位信号输出端。The input control terminal and the input terminal are both carry signal output terminals of the adjacent previous stage driving circuit.
可选的,所述复位电路包括第一复位晶体管和第二复位晶体管;Optionally, the reset circuit includes a first reset transistor and a second reset transistor;
所述第一复位晶体管的栅极与所述复位端电连接,所述第一复位晶体管的第一极与所述第一节点电连接,所述第一复位晶体管的第二极与控制节点电连接;The gate of the first reset transistor is electrically connected to the reset terminal, the first electrode of the first reset transistor is electrically connected to the first node, and the second electrode of the first reset transistor is electrically connected to the control node;
所述第二复位晶体管的栅极与所述复位端电连接,所述第二复位晶体管的第一极与所述控制节点电连接,所述第二复位晶体管的第二极与所述第一电压线电连接。A gate of the second reset transistor is electrically connected to the reset terminal, a first electrode of the second reset transistor is electrically connected to the control node, and a second electrode of the second reset transistor is electrically connected to the first voltage line.
可选的,所述控制节点控制电路包括的晶体管的沟道宽长比小于所述第二复位晶体管的沟道宽长比。 Optionally, a channel width-to-length ratio of a transistor included in the control node control circuit is smaller than a channel width-to-length ratio of the second reset transistor.
可选的,所述第一节点复位电路包括第一下拉晶体管和第二下拉晶体管;Optionally, the first node reset circuit includes a first pull-down transistor and a second pull-down transistor;
所述第一下拉晶体管的栅极与所述第二节点电连接,所述第一下拉晶体管的第一极与第一节点电连接,所述第一下拉晶体管的第二极与控制节点电连接;The gate of the first pull-down transistor is electrically connected to the second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node;
所述第二下拉晶体管的栅极与所述第二节点电连接,所述第二下拉晶体管的第一极与所述控制节点电连接,所述第二下拉晶体管的第二极与所述第一电压线电连接。A gate of the second pull-down transistor is electrically connected to the second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line.
可选的,所述第二下拉晶体管的沟道宽长比与所述控制节点控制电路包括的晶体管的沟道宽长比的比值大于或等于6而小于或等于24。Optionally, a ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.
可选的,所述第二下拉晶体管的沟道宽长比大于所述第一下拉晶体管的沟道宽长比。Optionally, a channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor.
可选的,所述第二节点包括第一个第二节点和第二个第二节点;Optionally, the second node includes a first second node and a second second node;
所述第一节点复位电路包括第一下拉晶体管、第二下拉晶体管、第三下拉晶体管和第四下拉晶体管;The first node reset circuit includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor and a fourth pull-down transistor;
所述第一下拉晶体管的栅极与所述第一个第二节点电连接,所述第一下拉晶体管的第一极与第一节点电连接,所述第一下拉晶体管的第二极与控制节点电连接;The gate of the first pull-down transistor is electrically connected to the first second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node;
所述第二下拉晶体管的栅极与所述第一个第二节点电连接,所述第二下拉晶体管的第一极与所述控制节点电连接,所述第二下拉晶体管的第二极与所述第一电压线电连接;The gate of the second pull-down transistor is electrically connected to the first second node, the first electrode of the second pull-down transistor is electrically connected to the control node, and the second electrode of the second pull-down transistor is electrically connected to the first voltage line;
所述第三下拉晶体管的栅极与所述第二个第二节点电连接,所述第三下拉晶体管的第一极与第一节点电连接,所述第三下拉晶体管的第二极与控制节点电连接;The gate of the third pull-down transistor is electrically connected to the second second node, the first electrode of the third pull-down transistor is electrically connected to the first node, and the second electrode of the third pull-down transistor is electrically connected to the control node;
所述第四下拉晶体管的栅极与所述第二个第二节点电连接,所述第四下拉晶体管的第一极与所述控制节点电连接,所述第四下拉晶体管的第二极与所述第一电压线电连接。A gate of the fourth pull-down transistor is electrically connected to the second second node, a first electrode of the fourth pull-down transistor is electrically connected to the control node, and a second electrode of the fourth pull-down transistor is electrically connected to the first voltage line.
可选的,所述第二下拉晶体管的沟道宽长比大于所述第一下拉晶体管的沟道宽长比,所述第四下拉晶体管的沟道宽长比大于所述第三下拉晶体管的沟道宽长比。Optionally, a channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor, and a channel width-to-length ratio of the fourth pull-down transistor is greater than a channel width-to-length ratio of the third pull-down transistor.
可选的,所述第二下拉晶体管的沟道宽长比与所述控制节点控制电路包括的晶体管的沟道宽长比的比值大于或等于6而小于或等于24;Optionally, a ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24;
所述第四下拉晶体管的沟道宽长比与所述控制节点控制电路包括的晶体管的沟道宽长比的比值大于或等于6而小于或等于24。A ratio of a channel width-to-length ratio of the fourth pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.
可选的,所述帧复位电路包括第一帧复位晶体管和第二帧复位晶体管;Optionally, the frame reset circuit includes a first frame reset transistor and a second frame reset transistor;
所述第一帧复位晶体管的栅极与所述帧复位线电连接,所述第一帧复位晶体管的第一极与所述第一节点电连接,所述第一帧复位晶体管的第二极与控制节点电连接;The gate of the first frame reset transistor is electrically connected to the frame reset line, the first electrode of the first frame reset transistor is electrically connected to the first node, and the second electrode of the first frame reset transistor is electrically connected to the control node;
所述第二帧复位晶体管的栅极与所述帧复位线电连接,所述第二帧复位晶体管的第一极与所述控制节点电连接,所述第二帧复位晶体管的第二极与所述第二电压线电连接。A gate of the second frame reset transistor is electrically connected to the frame reset line, a first electrode of the second frame reset transistor is electrically connected to the control node, and a second electrode of the second frame reset transistor is electrically connected to the second voltage line.
可选的,本公开至少一实施例所述的驱动电路还包括进位信号输出电路、驱动信号输出电路和储能电路;Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a carry signal output circuit, a driving signal output circuit and an energy storage circuit;
所述进位信号输出电路分别与第一节点、第二节点、进位信号输出端、时钟信号端和第二电压线电连接,用于在所述第一节点的电位的控制下,控制所述进位信号输出端与所述时钟信号端之间连通或断开,在所述第二节点的电位的控制下,控制所述进位信号输出 端与所述第二电压线之间连通或断开;The carry signal output circuit is electrically connected to the first node, the second node, the carry signal output terminal, the clock signal terminal and the second voltage line respectively, and is used to control the connection or disconnection between the carry signal output terminal and the clock signal terminal under the control of the potential of the first node, and control the carry signal output terminal to be connected or disconnected under the control of the potential of the second node. The terminal is connected or disconnected with the second voltage line;
所述驱动信号输出电路分别与第一节点、第二节点、驱动信号输出端、时钟信号端和第四电压线电连接,用于在所述第一节点的电位的控制下,控制所述驱动信号输出端与所述时钟信号端之间连通或断开,在所述第二节点的电位的控制下,控制所述驱动信号输出端与所述第四电压线之间连通或断开;The drive signal output circuit is electrically connected to the first node, the second node, the drive signal output terminal, the clock signal terminal and the fourth voltage line respectively, and is used to control the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and control the connection or disconnection between the drive signal output terminal and the fourth voltage line under the control of the potential of the second node;
所述储能电路分别与所述第一节点和所述驱动信号输出端电连接,用于储存电能。The energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used for storing electric energy.
可选的,所述第四电压线用于提供第四电压信号,所述第二电压线用于提供第二电压信号;Optionally, the fourth voltage line is used to provide a fourth voltage signal, and the second voltage line is used to provide a second voltage signal;
所述第四电压信号的电压值等于所述第二电压信号的电压值,或者,所述第二电压信号的电压值小于所述第四电压信号的电压值。The voltage value of the fourth voltage signal is equal to the voltage value of the second voltage signal, or the voltage value of the second voltage signal is smaller than the voltage value of the fourth voltage signal.
可选的,本公开至少一实施例所述的驱动电路还包括第二节点控制电路;Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a second node control circuit;
所述第二节点控制电路分别与输入控制端、第一节点、第二节点和第二电压线电连接,用于在所述输入控制端提供的输入控制信号的控制下,控制所述第二节点与所述第二电压线之间连通或断开,并在所述第一节点的电位的控制下,控制所述第二节点的电位。The second node control circuit is electrically connected to the input control terminal, the first node, the second node and the second voltage line, respectively, and is used to control the connection or disconnection between the second node and the second voltage line under the control of the input control signal provided by the input control terminal, and to control the potential of the second node under the control of the potential of the first node.
在第二个方面中,本公开实施例提供一种显示基板,包括基底和设置于所述基底上的上述的驱动电路。In a second aspect, an embodiment of the present disclosure provides a display substrate, including a base and the above-mentioned driving circuit disposed on the base.
可选的,本公开至少一实施例所述的显示基板还包括设置于所述基底上的静电防护电路;Optionally, the display substrate described in at least one embodiment of the present disclosure further includes an electrostatic protection circuit disposed on the base;
所述静电防护电路的第一端与驱动信号线电连接,所述静电防护电路的第二端通过短路线与公共电极电压端电连接,所述静电防护电路用于进行静电防护;The first end of the electrostatic protection circuit is electrically connected to the driving signal line, the second end of the electrostatic protection circuit is electrically connected to the common electrode voltage terminal through a short-circuit line, and the electrostatic protection circuit is used for electrostatic protection;
所述驱动信号线包括直流电压线、时钟信号线、控制电压线和帧复位线。The driving signal lines include a DC voltage line, a clock signal line, a control voltage line and a frame reset line.
可选的,所述静电防护电路包括第一防护晶体管、第二防护晶体管和第三防护晶体管;Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor and a third protection transistor;
所述第一防护晶体管的栅极和所述第一防护晶体管的第一极都与所述驱动信号线电连接,所述第一防护晶体管的第二极与所述第二防护晶体管的栅极电连接;The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;
所述第二防护晶体管的第一极与所述第一防护晶体管的栅极电连接,所述第二防护晶体管的的第二极与所述第三防护晶体管的栅极电连接;The first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor;
所述第三防护晶体管的栅极与所述第三防护晶体管的第一极都与所述短路线电连接,所述第三防护晶体管的第二极与所述第二防护晶体管的栅极电连接;The gate of the third protection transistor and the first electrode of the third protection transistor are both electrically connected to the short-circuit line, and the second electrode of the third protection transistor is electrically connected to the gate of the second protection transistor;
所述第一防护晶体管的沟道宽长比大于所述第二防护晶体管的沟道宽长比,所述第三防护晶体管的沟道宽长比大于所述第二防护晶体管的沟道宽长比。The channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor.
可选的,所述静电防护电路包括第一防护晶体管、第二防护晶体管、第三防护晶体管、第四防护晶体管和第五防护晶体管;Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor and a fifth protection transistor;
所述第一防护晶体管的栅极和所述第一防护晶体管的第一极都与所述驱动信号线电连接,所述第一防护晶体管的第二极与所述第二防护晶体管的栅极电连接;The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;
所述第二防护晶体管的第一极与所述第一防护晶体管的栅极电连接,所述第二防护晶 体管的第二极与所述第三防护晶体管的栅极电连接;The first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor. The second electrode of the body transistor is electrically connected to the gate of the third protection transistor;
所述第三防护晶体管的第一极与所述第二防护晶体管的栅极电连接,所述第三防护晶体管的第二极与所述第四防护晶体管的栅极电连接;A first electrode of the third protection transistor is electrically connected to a gate of the second protection transistor, and a second electrode of the third protection transistor is electrically connected to a gate of the fourth protection transistor;
所述第四防护晶体管的第一极与所述第三防护晶体管的栅极电连接,所述第四防护晶体管的第二极与所述第五防护晶体管的栅极电连接;A first electrode of the fourth protection transistor is electrically connected to a gate of the third protection transistor, and a second electrode of the fourth protection transistor is electrically connected to a gate of the fifth protection transistor;
所述第五防护晶体管的栅极与所述第五防护晶体管的第一极都与所述短路线电连接,所述第五防护晶体管的第二极与所述第四防护晶体管的栅极电连接;The gate of the fifth protection transistor and the first electrode of the fifth protection transistor are both electrically connected to the short-circuit line, and the second electrode of the fifth protection transistor is electrically connected to the gate of the fourth protection transistor;
所述第一防护晶体管的沟道宽长比大于所述第二防护晶体管的沟道宽长比,所述第一防护晶体管的沟道宽长比大于所述第四防护晶体管的沟道宽长比;The channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;
所述第三防护晶体管的沟道宽长比大于所述第二防护晶体管的沟道宽长比,所述第三防护晶体管的沟道宽长比大于所述第四防护晶体管的沟道宽长比;The channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;
所述第五防护晶体管的沟道宽长比大于所述第二防护晶体管的沟道宽长比,所述第五防护晶体管的沟道宽长比大于所述第四防护晶体管的沟道宽长比。The channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor.
在第三个方面中,本公开实施例提供一种显示装置,包括上述的显示基板。In a third aspect, an embodiment of the present disclosure provides a display device, comprising the above-mentioned display substrate.
图1是本公开至少一实施例所述的驱动电路的结构图;FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;
图2是本公开至少一实施例所述的驱动电路的结构图;FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;
图3是本公开至少一实施例所述的驱动电路的结构图;FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;
图4是本公开至少一实施例所述的驱动电路的结构图;FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;
图5是本公开至少一实施例所述的驱动电路的电路图;FIG5 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;
图6是当图5所示的驱动电路的至少一实施例工作于触控扫描阶段SC时,第一节点PU的电位的波形图;FIG. 6 is a waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG. 5 operates in the touch scanning stage SC;
图7是当处于正常显示状态时,图5所示的驱动电路的至少一实施例在工作时,第一节点PU的电位的仿真波形图;7 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG. 5 is in operation when in a normal display state;
图8是处于触控阶段时,图5所示的驱动电路的至少一实施例在工作时,第一节点PU的电位的仿真波形图;FIG. 8 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG. 5 is in operation during the touch control stage;
图9是图5所示的驱动电路的至少一实施例的工作时序图;FIG9 is a timing diagram of the operation of at least one embodiment of the driving circuit shown in FIG5 ;
图10是图5所示的驱动电路的至少一实施例的布局图;FIG10 is a layout diagram of at least one embodiment of the driving circuit shown in FIG5 ;
图11是图10中的栅金属层的布局图;FIG11 is a layout diagram of the gate metal layer in FIG10 ;
图12是图10中的半导体层的布局图;FIG12 is a layout diagram of the semiconductor layer in FIG10;
图13是图10中的导电层的布局图;FIG13 is a layout diagram of the conductive layer in FIG10;
图14是图10中的源漏金属层的布局图;FIG14 is a layout diagram of the source/drain metal layer in FIG10 ;
图15是本公开至少一实施例所述的驱动电路的电路图;FIG15 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;
图16是本公开至少一实施例所述的驱动电路的电路图; FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;
图17是本公开至少一实施例所述的驱动电路的电路图;FIG17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;
图18是静电防护电路的至少一实施例的电路图;FIG18 is a circuit diagram of at least one embodiment of an electrostatic protection circuit;
图19是静电防护电路的至少一实施例的布局图;FIG. 19 is a layout diagram of at least one embodiment of an electrostatic protection circuit;
图20是静电防护电路的至少一实施例的电路图;FIG20 is a circuit diagram of at least one embodiment of an electrostatic protection circuit;
图21是静电防护电路的至少一实施例的布局图。FIG. 21 is a layout diagram of at least one embodiment of an electrostatic protection circuit.
下面将结合本公开实施例中的附图,对本公开实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本公开一部分实施例,而不是全部的实施例。基于本公开中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本公开保护的范围。The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中,为区分晶体管除栅极之外的两极,将其中一极称为第一极,另一极称为第二极。The transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is called the first electrode and the other is called the second electrode.
在实际操作时,当所述晶体管为薄膜晶体管或场效应管时,所述第一极可以为漏极,所述第二极可以为源极;或者,所述第一极可以为源极,所述第二极可以为漏极。In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
如图1所示,本公开实施例所述的驱动电路包括输入电路11、复位电路12、第一节点复位电路13和控制节点控制电路31;As shown in FIG1 , the driving circuit described in the embodiment of the present disclosure includes an input circuit 11 , a reset circuit 12 , a first node reset circuit 13 , and a control node control circuit 31 ;
所述输入电路11分别与输入控制端IK1、输入端I1和第一节点PU电连接,用于在所述输入控制端IK1提供的输入控制信号的控制下,控制所述输入端I1与所述第一节点PU之间连通或断开;The input circuit 11 is electrically connected to the input control terminal IK1, the input terminal I1 and the first node PU respectively, and is used to control the connection or disconnection between the input terminal I1 and the first node PU under the control of the input control signal provided by the input control terminal IK1;
所述复位电路12分别与复位端R1、所述第一节点PU和第一电压线V1电连接,用于在所述复位端R1提供的复位信号的控制下,控制所述第一节点PU和第一电压线V1之间连通或断开;The reset circuit 12 is electrically connected to the reset terminal R1, the first node PU and the first voltage line V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage line V1 under the control of the reset signal provided by the reset terminal R1;
所述第一节点复位电路13分别与第二节点PD、第一节点PU和第一电压线V1电连接,用于在所述第二节点PD的电位的控制下,控制所述第一节点PU与所述第一电压线V1之间连通或断开;The first node reset circuit 13 is electrically connected to the second node PD, the first node PU and the first voltage line V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage line V1 under the control of the potential of the second node PD;
所述控制节点控制电路31分别与第一节点PU、第三电压线V3和控制节点N0电连接,用于在所述第一节点PU的电位的控制下,控制所述控制节点N0与第三电压线V3之间连通或断开;The control node control circuit 31 is electrically connected to the first node PU, the third voltage line V3 and the control node N0 respectively, and is used to control the connection or disconnection between the control node N0 and the third voltage line V3 under the control of the potential of the first node PU;
所述输入电路11包括的晶体管、所述复位电路12包括的晶体管和所述第一节点复位电路13包括的晶体管沿着远离显示区域的方向依次排列;The transistors included in the input circuit 11, the transistors included in the reset circuit 12, and the transistors included in the first node reset circuit 13 are arranged in sequence along a direction away from the display area;
所述第一节点复位电路包括的栅极与所述第二节点电连接的晶体管的沟道宽长比与所述控制节点控制电路包括的晶体管的沟道宽长比的比值大于或等于6而小于或等于24。A ratio of a channel width-to-length ratio of a transistor whose gate is electrically connected to the second node and included in the first node reset circuit to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.
可选的,所述第一电压线可以为第一低电压线或第二低电压线,但不以此为限。 Optionally, the first voltage line may be a first low voltage line or a second low voltage line, but is not limited thereto.
在具体实施时,本公开实施例所述的驱动电路可以包括输入电路11、复位电路12和第一节点复位电路13,输入电路11在输入控制信号的控制下,控制所述输入端I1与所述第一节点PU之间连通或断开,复位电路12在复位信号的控制下,控制所述第一节点PU和第一电压线V1之间连通或断开,第一节点复位电路13在所述第二节点PD的电位的控制下,控制所述第一节点PU与所述第一电压线V1之间连通或断开;所述输入电路11包括的晶体管、所述复位电路12包括的晶体管和所述第一节点复位电路13包括的晶体管可以沿着远离显示区域的方向依次排列,以合理的布局各电路包括的晶体管,很好的利用显示基板的边框的横向空间。In a specific implementation, the driving circuit described in the embodiment of the present disclosure may include an input circuit 11, a reset circuit 12 and a first node reset circuit 13. The input circuit 11 controls the connection or disconnection between the input terminal I1 and the first node PU under the control of an input control signal. The reset circuit 12 controls the connection or disconnection between the first node PU and the first voltage line V1 under the control of a reset signal. The first node reset circuit 13 controls the connection or disconnection between the first node PU and the first voltage line V1 under the control of the potential of the second node PD. The transistors included in the input circuit 11, the transistors included in the reset circuit 12 and the transistors included in the first node reset circuit 13 can be arranged in sequence along a direction away from the display area to reasonably layout the transistors included in each circuit and make good use of the lateral space of the frame of the display substrate.
可选的,所述第三电压线可以为高电压线。Optionally, the third voltage line may be a high voltage line.
本公开至少一实施例所述的驱动电路增设控制节点控制电路31,在第一节点PU的电位为高电压时,控制节点N0的电位被充电至高电压,此时第一节点PU的漏电途径为PU至N0,以有效防止第一节点PU漏电,提升显示产品的驱动能力。The driving circuit described in at least one embodiment of the present disclosure adds a control node control circuit 31. When the potential of the first node PU is a high voltage, the potential of the control node N0 is charged to a high voltage. At this time, the leakage path of the first node PU is from PU to N0, so as to effectively prevent the leakage of the first node PU and improve the driving capability of the display product.
在具体实施时,可以通过调整所述第一节点复位电路包括的栅极与所述第二节点电连接的晶体管的沟道宽长比和所述控制节点控制电路包括的晶体管的沟道宽长比的比值,防止控制节点的噪声通过漏电引入第一节点,提升驱动电路的稳定性,防止多输出。In a specific implementation, by adjusting the ratio of the channel width-to-length ratio of the transistor whose gate is electrically connected to the second node and included in the first node reset circuit and the channel width-to-length ratio of the transistor included in the control node control circuit, the noise of the control node can be prevented from being introduced into the first node through leakage, thereby improving the stability of the driving circuit and preventing multiple outputs.
可选的,所述控制节点控制电路包括的晶体管的沟道宽长比可以为5/12,所述第一节点复位电路包括的栅极与所述第二节点电连接的晶体管的沟道宽长比可以为30/6,所述控制节点控制电路包括的晶体管的沟道宽长比与所述第一节点复位电路包括的栅极与所述第二节点电连接的晶体管的沟道宽长比之间的比值为1:12,但不以此为限。Optionally, the channel width-to-length ratio of the transistor included in the control node control circuit can be 5/12, the channel width-to-length ratio of the transistor included in the first node reset circuit and whose gate is electrically connected to the second node can be 30/6, and the ratio between the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the transistor included in the first node reset circuit and whose gate is electrically connected to the second node is 1:12, but is not limited to this.
在本公开至少一实施例中,所述输入电路可以分别与输入控制端IK1和输入端I1电连接,用于在所述输入控制端IK1提供的输入控制信号的控制下,控制所述输入端I1与所述第一节点PU之间连通或断开。In at least one embodiment of the present disclosure, the input circuit may be electrically connected to the input control terminal IK1 and the input terminal I1, respectively, and is used to control the connection or disconnection between the input terminal I1 and the first node PU under the control of the input control signal provided by the input control terminal IK1.
在具体实施时,所述输入控制端IK1和所述输入端I1可以为不同的信号端,分别接入不同的信号;或者,In a specific implementation, the input control terminal IK1 and the input terminal I1 may be different signal terminals, which are connected to different signals respectively; or,
所述输入控制端IK1和所述输入端I1也可以为相同的信号端,接入相同的信号。The input control terminal IK1 and the input terminal I1 may also be the same signal terminal, receiving the same signal.
在本公开至少一实施例中,所述输入电路包括相互串联的至少两个输入晶体管,所述复位电路包括相互串联的至少两个复位晶体管。In at least one embodiment of the present disclosure, the input circuit includes at least two input transistors connected in series, and the reset circuit includes at least two reset transistors connected in series.
在具体实施时,所述输入电路可以包括相互串联的至少两个栅极与输入控制端电连接的晶体管,所述复位电路可以包括相互串联的至少两个栅极与复位端电连接的晶体管,以将第一极或第二极与第一节点电连接的晶体管改为串联的至少两个晶体管,以减少第一节点的漏电流,提升驱动电路的稳定性。In a specific implementation, the input circuit may include at least two transistors in series with their gates electrically connected to the input control terminal, and the reset circuit may include at least two transistors in series with their gates electrically connected to the reset terminal, so as to replace the transistor in which the first pole or the second pole is electrically connected to the first node with at least two transistors in series, so as to reduce the leakage current of the first node and improve the stability of the driving circuit.
在本公开至少一实施例中,所述第一节点复位电路包括栅极与所述第二节点电连接的相互串联的至少两个晶体管;或者,In at least one embodiment of the present disclosure, the first node reset circuit includes at least two transistors connected in series with their gates electrically connected to the second node; or,
所述第二节点包括第一个第二节点和第二个第二节点;所述第一节点复位电路包括栅极与所述第一个第二节点电连接的相互串联的两个晶体管,以及,栅极与所述第二个第二 节点电连接的相互串联的至少两个晶体管。The second node includes a first second node and a second second node; the first node reset circuit includes two transistors connected in series with the gate being electrically connected to the first second node, and a transistor with the gate being electrically connected to the second second node. The node is electrically connected to at least two transistors connected in series with each other.
在具体实施时,当所述驱动电路采用一个第二节点时,所述第一节点复位电路可以包括至少两个栅极与该第二节点电连接的晶体管;In a specific implementation, when the driving circuit adopts a second node, the first node reset circuit may include at least two transistors whose gates are electrically connected to the second node;
当所述驱动电路采用两个第二节点时,所述第一节点复位电路可以包括栅极与所述第一个第二节点电连接的相互串联的两个晶体管,以及,栅极与所述第二个第二节点电连接的相互串联的至少两个晶体管;When the driving circuit uses two second nodes, the first node reset circuit may include two transistors connected in series with the gate being electrically connected to the first second node, and at least two transistors connected in series with the gate being electrically connected to the second second node;
本公开至少一实施例将第一极或第二极与第一节点电连接的晶体管改为串联的至少两个晶体管,以减少第一节点的漏电流,提升驱动电路的稳定性。In at least one embodiment of the present disclosure, the transistor electrically connected to the first electrode or the second electrode and the first node is replaced by at least two transistors connected in series, so as to reduce the leakage current of the first node and improve the stability of the driving circuit.
如图2所示,在图1所示的驱动电路的实施例的基础上,本公开至少一实施例所述的驱动电路还包括帧复位电路21;As shown in FIG2 , based on the embodiment of the driving circuit shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure further includes a frame reset circuit 21 ;
所述帧复位电路21分别与帧复位线STV0、第一节点PU和第二电压线V2电连接,用于在所述帧复位线STV0提供的帧复位信号的控制下,控制所述第一节点PU与所述第二电压线V2之间连通或断开;The frame reset circuit 21 is electrically connected to the frame reset line STV0, the first node PU and the second voltage line V2 respectively, and is used to control the connection or disconnection between the first node PU and the second voltage line V2 under the control of the frame reset signal provided by the frame reset line STV0;
所述帧复位电路21包括的晶体管设置于所述第一节点复位电路13包括的晶体管远离显示区域的一侧。The transistor included in the frame reset circuit 21 is arranged on a side of the transistor included in the first node reset circuit 13 away from the display area.
可选的,所述第二电压线可以为第二低电压线,但不以此为限。Optionally, the second voltage line may be a second low voltage line, but is not limited thereto.
在具体实施时,本公开至少一实施例所述的驱动电路还可以包括帧复位电路21,所述帧复位电路21在两帧显示时间之间的空白时间段,在帧复位信号的控制下,控制对所述第一节点PU的电位进行复位;所述帧复位电路21包括的晶体管设置于所述第一节点复位电路13包括的晶体管远离显示区域的一侧,以合理的布局各电路包括的晶体管,很好的利用显示基板的边框的横向空间。In a specific implementation, the driving circuit described in at least one embodiment of the present disclosure may further include a frame reset circuit 21, which controls the resetting of the potential of the first node PU under the control of a frame reset signal during a blank period between two frames of display time; the transistor included in the frame reset circuit 21 is arranged on the side of the transistor included in the first node reset circuit 13 away from the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the lateral space of the border of the display substrate.
可选的,所述帧复位电路包括相互串联的至少两个帧复位晶体管。Optionally, the frame reset circuit includes at least two frame reset transistors connected in series.
在本公开至少一实施例中,所述帧复位电路可以包括相互串联的至少两个栅极与帧复位线电连接的晶体管,本公开至少一实施例将第一极或第二极与第一节点电连接的晶体管改为串联的至少两个晶体管,以减少第一节点的漏电流,提升驱动电路的稳定性。In at least one embodiment of the present disclosure, the frame reset circuit may include at least two transistors whose gates are electrically connected to the frame reset line and are connected in series. At least one embodiment of the present disclosure replaces the transistor whose first electrode or the second electrode is electrically connected to the first node with at least two transistors connected in series to reduce the leakage current of the first node and improve the stability of the driving circuit.
在本公开至少一实施例中,所述控制节点控制电路包括的晶体管设置于所述输入电路包括的晶体管靠近显示区域的一侧。In at least one embodiment of the present disclosure, the transistor included in the control node control circuit is arranged on a side of the transistor included in the input circuit close to the display area.
在具体实施时,所述控制节点控制电路包括的晶体管可以设置于所述所述输入电路包括的晶体管靠近显示区域的一侧,以合理的布局各电路包括的晶体管,很好的利用显示基板的边框的横向空间。In a specific implementation, the transistor included in the control node control circuit can be arranged on a side of the transistor included in the input circuit close to the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the lateral space of the frame of the display substrate.
可选的,所述控制节点控制电路包括控制晶体管;Optionally, the control node control circuit includes a control transistor;
所述控制晶体管的栅极与所述第一节点电连接,所述控制晶体管的第一极与所述第三电压线电连接,所述控制晶体管的第二极与所述控制节点电连接。A gate of the control transistor is electrically connected to the first node, a first electrode of the control transistor is electrically connected to the third voltage line, and a second electrode of the control transistor is electrically connected to the control node.
本公开至少一实施例所述的驱动电路还包括关机复位电路;The driving circuit described in at least one embodiment of the present disclosure further includes a shutdown reset circuit;
所述关机复位电路分别与第四电压线和驱动信号输出端电连接,用于在所述第四电压 线提供的第四电压信号的控制下,控制所述驱动信号输出端与所述第四电压线之间连通或断开。The shutdown reset circuit is electrically connected to the fourth voltage line and the drive signal output terminal respectively, and is used for Under the control of a fourth voltage signal provided by the line, the drive signal output terminal is controlled to be connected or disconnected with the fourth voltage line.
可选的,所述第四电压线可以为第一低电压线。Optionally, the fourth voltage line may be a first low voltage line.
在具体实施时,所述驱动电路还可以包括关机复位电路,所述关机复位电路在第四电压信号的控制下,控制所述驱动信号输出端与所述第四电压线之间连通或断开。In a specific implementation, the driving circuit may further include a shutdown reset circuit, and the shutdown reset circuit controls the connection or disconnection between the driving signal output terminal and the fourth voltage line under the control of the fourth voltage signal.
如图3所示,在图2所示的驱动电路的至少一实施例的基础上,本公开至少一实施例所述的驱动电路还包括关机复位电路41;As shown in FIG3 , based on at least one embodiment of the driving circuit shown in FIG2 , the driving circuit described in at least one embodiment of the present disclosure further includes a shutdown reset circuit 41 ;
所述关机复位电路41分别与第四电压线V4和驱动信号输出端GT电连接,用于在所述第四电压线V4提供的第四电压信号的控制下,控制所述驱动信号输出端GT与所述第四电压线V4之间连通或断开。The shutdown reset circuit 41 is electrically connected to the fourth voltage line V4 and the drive signal output terminal GT respectively, and is used to control the connection or disconnection between the drive signal output terminal GT and the fourth voltage line V4 under the control of the fourth voltage signal provided by the fourth voltage line V4.
在本公开至少一实施例中,当所述关机复位电路41包括的晶体管为n型晶体管时,在显示面板正常显示时,第四电压线V4提供低电压信号,在显示面板准备关机时,第四电压线V4提供的电压信号的电位置高,所述关机复位电路41在第四电压信号的控制下,控制所述驱动信号输出端GT与第四电压线V4之间连通,使得所述驱动信号输出端GT输出高电压信号,可以释放像素中的残留电荷,可以有效提升所述驱动信号输出端GT的开启能力,避免残像不良。In at least one embodiment of the present disclosure, when the transistor included in the shutdown reset circuit 41 is an n-type transistor, when the display panel displays normally, the fourth voltage line V4 provides a low voltage signal, and when the display panel is ready to shut down, the voltage signal provided by the fourth voltage line V4 has a high voltage. Under the control of the fourth voltage signal, the shutdown reset circuit 41 controls the connection between the drive signal output terminal GT and the fourth voltage line V4, so that the drive signal output terminal GT outputs a high voltage signal, which can release the residual charge in the pixel, and can effectively improve the opening ability of the drive signal output terminal GT to avoid poor afterimage.
在相关技术中,在显示面板关机时,各直流电压线提供的电压信号的电位被拉高为高电平,第四电压线V4通过驱动电路包括的输出复位晶体管将高电压信号输入至AA区(有效显示区域),完成像素放电,但由于显示产品信赖性后,输出复位晶体管的漂移输出能力下降,导致栅线开启不充分,像素电荷释放不完全,形成残像。基于此,本公开至少一实施例通过所述关机复位电路41在关机时,在第四电压信号的控制下,控制所述驱动信号输出端GT输出高电压信号,以释放像素中的残留电荷,可以有效提升所述驱动信号输出端GT的开启能力,避免残像不良。In the related art, when the display panel is turned off, the potential of the voltage signal provided by each DC voltage line is pulled up to a high level, and the fourth voltage line V4 inputs the high voltage signal to the AA area (effective display area) through the output reset transistor included in the driving circuit to complete the pixel discharge. However, due to the reliability of the display product, the drift output capability of the output reset transistor decreases, resulting in insufficient gate line opening, incomplete pixel charge release, and the formation of residual images. Based on this, at least one embodiment of the present disclosure controls the drive signal output terminal GT to output a high voltage signal under the control of the fourth voltage signal when the power is turned off to release the residual charge in the pixel, which can effectively improve the opening capability of the drive signal output terminal GT and avoid poor residual images.
在本公开至少一实施例中,所述关机复位电路包括的晶体管设置于所述输入电路包括的晶体管靠近显示区域的一侧。In at least one embodiment of the present disclosure, the transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit close to the display area.
在具体实施时,所述关机复位电路包括的晶体管设置于所述输入电路包括的晶体管靠近显示区域的一侧,以合理的布局各电路包括的晶体管,很好的利用显示基板的边框的横向空间。In a specific implementation, the transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit close to the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the lateral space of the frame of the display substrate.
可选的,所述关机复位电路包括关机复位晶体管;Optionally, the shutdown reset circuit includes a shutdown reset transistor;
所述关机复位晶体管的栅极和所述关机复位晶体管的第一极与所述第四电压线电连接,所述关机复位晶体管的第二极与所述驱动信号输出端电连接。The gate of the shutdown reset transistor and the first electrode of the shutdown reset transistor are electrically connected to the fourth voltage line, and the second electrode of the shutdown reset transistor is electrically connected to the driving signal output terminal.
可选的,所述输入电路包括第一输入晶体管和第二输入晶体管;Optionally, the input circuit includes a first input transistor and a second input transistor;
所述第一输入晶体管的栅极与所述输入控制端电连接,所述第一输入晶体管的第一极与所述输入端电连接,所述第一输入晶体管的第二极与控制节点电连接;The gate of the first input transistor is electrically connected to the input control terminal, the first electrode of the first input transistor is electrically connected to the input terminal, and the second electrode of the first input transistor is electrically connected to the control node;
所述第二输入晶体管的栅极与所述输入控制端电连接,所述第二输入晶体管的第一极 与所述控制节点电连接,所述第二输入晶体管的第二极与所述第一节点电连接。The gate of the second input transistor is electrically connected to the input control terminal, and the first electrode of the second input transistor The first electrode of the second input transistor is electrically connected to the control node, and the second electrode of the second input transistor is electrically connected to the first node.
在本公开至少一实施例中,所述输入控制端为相邻上一级驱动电路的进位信号输出端,所述输入端为相邻上一级驱动电路的驱动信号输出端;或者,In at least one embodiment of the present disclosure, the input control terminal is a carry signal output terminal of an adjacent previous stage driving circuit, and the input terminal is a drive signal output terminal of an adjacent previous stage driving circuit; or,
所述输入控制端和所述输入端都为相邻上一级驱动电路的进位信号输出端。The input control terminal and the input terminal are both carry signal output terminals of the adjacent previous stage driving circuit.
在具体实施时,所述输入控制端可以为相邻上一级驱动电路的进位信号输出端,所述输入端可以为相邻上一级驱动电路的驱动信号输出端;或者,所述输入控制端和所述输入端可以都为相邻上一级驱动电路的进位信号输出端。In a specific implementation, the input control terminal can be the carry signal output terminal of the adjacent previous level driving circuit, and the input terminal can be the drive signal output terminal of the adjacent previous level driving circuit; or, the input control terminal and the input terminal can both be the carry signal output terminal of the adjacent previous level driving circuit.
可选的,所述复位电路包括第一复位晶体管和第二复位晶体管;Optionally, the reset circuit includes a first reset transistor and a second reset transistor;
所述第一复位晶体管的栅极与所述复位端电连接,所述第一复位晶体管的第一极与所述第一节点电连接,所述第一复位晶体管的第二极与控制节点电连接;The gate of the first reset transistor is electrically connected to the reset terminal, the first electrode of the first reset transistor is electrically connected to the first node, and the second electrode of the first reset transistor is electrically connected to the control node;
所述第二复位晶体管的栅极与所述复位端电连接,所述第二复位晶体管的第一极与所述控制节点电连接,所述第二复位晶体管的第二极与所述第一电压线电连接。A gate of the second reset transistor is electrically connected to the reset terminal, a first electrode of the second reset transistor is electrically connected to the control node, and a second electrode of the second reset transistor is electrically connected to the first voltage line.
在本公开至少一实施例中,所述控制节点控制电路包括的晶体管的沟道宽长比小于所述第二复位晶体管的沟道宽长比。In at least one embodiment of the present disclosure, the control node control circuit includes a transistor having a channel width-to-length ratio that is smaller than a channel width-to-length ratio of the second reset transistor.
在具体实施时,可以调整所述控制节点控制电路包括的晶体管的沟道宽长比和第二复位晶体管的沟道宽长比,在复位端提供的复位信号到来时,提升第二复位晶体管的竞争力,使得控制节点的电位和第一节点的电位迅速降低至低电压,确保第二节点的电位可以同步升高至高电压,开始降噪。In a specific implementation, the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the second reset transistor can be adjusted. When the reset signal provided by the reset end arrives, the competitiveness of the second reset transistor is improved, so that the potential of the control node and the potential of the first node are quickly reduced to a low voltage, ensuring that the potential of the second node can be synchronously increased to a high voltage to start noise reduction.
例如,所述控制节点控制电路包括的晶体管的沟道宽长比可以为5/12,所述第二复位晶体管的沟道宽长比可以为5/6,但不以此为限。For example, the channel width-to-length ratio of the transistor included in the control node control circuit may be 5/12, and the channel width-to-length ratio of the second reset transistor may be 5/6, but is not limited thereto.
可选的,所述第一节点复位电路包括第一下拉晶体管和第二下拉晶体管;Optionally, the first node reset circuit includes a first pull-down transistor and a second pull-down transistor;
所述第一下拉晶体管的栅极与所述第二节点电连接,所述第一下拉晶体管的第一极与第一节点电连接,所述第一下拉晶体管的第二极与控制节点电连接;The gate of the first pull-down transistor is electrically connected to the second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node;
所述第二下拉晶体管的栅极与所述第二节点电连接,所述第二下拉晶体管的第一极与所述控制节点电连接,所述第二下拉晶体管的第二极与所述第一电压线电连接。A gate of the second pull-down transistor is electrically connected to the second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line.
在本公开至少一实施例中,所述第二下拉晶体管的沟道宽长比与所述控制节点控制电路包括的晶体管的沟道宽长比的比值大于或等于6而小于或等于24。In at least one embodiment of the present disclosure, a ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.
在具体实施时,可以通过调整第二下拉晶体管的沟道宽长比和所述控制节点控制电路包括的晶体管的沟道宽长比的比值,防止控制节点的噪声通过漏电引入第一节点,提升驱动电路的稳定性,防止多输出。In a specific implementation, the ratio of the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the transistor included in the control node control circuit can be adjusted to prevent the noise of the control node from being introduced into the first node through leakage, thereby improving the stability of the driving circuit and preventing multiple outputs.
可选的,所述控制节点控制电路包括的晶体管的沟道宽长比可以为5/12,所述第二下拉晶体管的沟道宽长比可以为30/6,所述控制节点控制电路包括的晶体管的沟道宽长比与所述第二下拉晶体管的沟道宽长比之间的比值为1:12,但不以此为限。Optionally, the channel width-to-length ratio of the transistor included in the control node control circuit may be 5/12, the channel width-to-length ratio of the second pull-down transistor may be 30/6, and the ratio between the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the second pull-down transistor is 1:12, but is not limited thereto.
可选的,所述第二下拉晶体管的沟道宽长比大于所述第一下拉晶体管的沟道宽长比。Optionally, a channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor.
在具体实施时,所述第二下拉晶体管的沟道宽长比可以大于所述第一下拉晶体管的沟 道宽长比,通过调整第一下拉晶体管的沟道宽长比和第二下拉晶体管的沟道宽长比,可以防止控制节点的噪声通过漏电引入第一节点,提升驱动电路的稳定性,防止多输出。In a specific implementation, the channel width-to-length ratio of the second pull-down transistor may be greater than the channel width-to-length ratio of the first pull-down transistor. By adjusting the channel width-to-length ratio of the first pull-down transistor and the channel width-to-length ratio of the second pull-down transistor, the noise of the control node can be prevented from being introduced into the first node through leakage, thereby improving the stability of the driving circuit and preventing multiple outputs.
例如,所述第一下拉晶体管的沟道宽长比可以为15/6,所述第二下拉晶体管的沟道宽长比可以为30/6,但不以此为限。For example, the channel width-to-length ratio of the first pull-down transistor may be 15/6, and the channel width-to-length ratio of the second pull-down transistor may be 30/6, but is not limited thereto.
可选的,所述第二节点包括第一个第二节点和第二个第二节点;Optionally, the second node includes a first second node and a second second node;
所述第一节点复位电路包括第一下拉晶体管、第二下拉晶体管、第三下拉晶体管和第四下拉晶体管;The first node reset circuit includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor and a fourth pull-down transistor;
所述第一下拉晶体管的栅极与所述第一个第二节点电连接,所述第一下拉晶体管的第一极与第一节点电连接,所述第一下拉晶体管的第二极与控制节点电连接;The gate of the first pull-down transistor is electrically connected to the first second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node;
所述第二下拉晶体管的栅极与所述第一个第二节点电连接,所述第二下拉晶体管的第一极与所述控制节点电连接,所述第二下拉晶体管的第二极与所述第一电压线电连接;The gate of the second pull-down transistor is electrically connected to the first second node, the first electrode of the second pull-down transistor is electrically connected to the control node, and the second electrode of the second pull-down transistor is electrically connected to the first voltage line;
所述第三下拉晶体管的栅极与所述第二个第二节点电连接,所述第三下拉晶体管的第一极与第一节点电连接,所述第三下拉晶体管的第二极与控制节点电连接;The gate of the third pull-down transistor is electrically connected to the second second node, the first electrode of the third pull-down transistor is electrically connected to the first node, and the second electrode of the third pull-down transistor is electrically connected to the control node;
所述第四下拉晶体管的栅极与所述第二个第二节点电连接,所述第四下拉晶体管的第一极与所述控制节点电连接,所述第四下拉晶体管的第二极与所述第一电压线电连接。A gate of the fourth pull-down transistor is electrically connected to the second second node, a first electrode of the fourth pull-down transistor is electrically connected to the control node, and a second electrode of the fourth pull-down transistor is electrically connected to the first voltage line.
在本公开至少一实施例中,所述第二下拉晶体管的沟道宽长比大于所述第一下拉晶体管的沟道宽长比,所述第四下拉晶体管的沟道宽长比大于所述第三下拉晶体管的沟道宽长比。In at least one embodiment of the present disclosure, the channel width-to-length ratio of the second pull-down transistor is greater than that of the first pull-down transistor, and the channel width-to-length ratio of the fourth pull-down transistor is greater than that of the third pull-down transistor.
在本公开至少一实施例中,所述第二下拉晶体管的沟道宽长比大于所述第一下拉晶体管的沟道宽长比,所述第四下拉晶体管的沟道宽长比大于所述第三下拉晶体管的沟道宽长比。In at least one embodiment of the present disclosure, the channel width-to-length ratio of the second pull-down transistor is greater than that of the first pull-down transistor, and the channel width-to-length ratio of the fourth pull-down transistor is greater than that of the third pull-down transistor.
在具体实施时,所述第二下拉晶体管的沟道宽长比可以大于所述第一下拉晶体管的沟道宽长比,所述第四下拉晶体管的沟道宽长比可以大于所述第三下拉晶体管的沟道宽长比,通过如上设置,可以防止控制节点的噪声通过漏电引入第一节点,提升驱动电路的稳定性,防止多输出。In a specific implementation, the channel width-to-length ratio of the second pull-down transistor may be greater than the channel width-to-length ratio of the first pull-down transistor, and the channel width-to-length ratio of the fourth pull-down transistor may be greater than the channel width-to-length ratio of the third pull-down transistor. By setting as above, the noise of the control node can be prevented from being introduced into the first node through leakage, thereby improving the stability of the driving circuit and preventing multiple outputs.
例如,所述第一下拉晶体管的沟道宽长比和所述第三下拉晶体管的沟道宽长比可以为15/6,所述第二下拉晶体管的沟道宽长比和所述第四下拉晶体管的沟道宽长比可以为30/6,但不以此为限。For example, the channel width-to-length ratio of the first pull-down transistor and the channel width-to-length ratio of the third pull-down transistor may be 15/6, and the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the fourth pull-down transistor may be 30/6, but is not limited thereto.
可选的,所述第二下拉晶体管的沟道宽长比与所述控制节点控制电路包括的晶体管的沟道宽长比的比值大于或等于6而小于或等于24;Optionally, a ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24;
所述第四下拉晶体管的沟道宽长比与所述控制晶体管的沟道宽长比的比值大于或等于6而小于或等于24。A ratio of a channel width-to-length ratio of the fourth pull-down transistor to a channel width-to-length ratio of the control transistor is greater than or equal to 6 and less than or equal to 24.
在具体实施时,可以通过调整第二下拉晶体管的沟道宽长比和控制节点控制电路包括的晶体管的沟道宽长比的比值,调整第四下拉晶体管的沟道宽长比和控制节点控制电路包括的晶体管的沟道宽长比的比值,防止控制节点的噪声通过漏电引入第一节点,提升驱动 电路的稳定性,防止多输出。In a specific implementation, the ratio of the channel width-to-length ratio of the second pull-down transistor to the channel width-to-length ratio of the transistor included in the control node control circuit can be adjusted, and the ratio of the channel width-to-length ratio of the fourth pull-down transistor to the channel width-to-length ratio of the transistor included in the control node control circuit can be adjusted to prevent the noise of the control node from being introduced into the first node through leakage, thereby improving the driving efficiency. Circuit stability to prevent multiple outputs.
可选的,所述控制节点控制电路包括的晶体管的沟道宽长比可以为5/12,所述第二下拉晶体管的沟道宽长比和所述第四下拉晶体管的沟道宽长比可以为30/6,所述控制节点控制电路包括的晶体管的沟道宽长比与所述第二下拉晶体管的沟道宽长比之间的比值为1:12,所述控制节点控制电路包括的晶体管的沟道宽长比与所述第四下拉晶体管的沟道宽长比之间的比值为1:12,但不以此为限。Optionally, the channel width-to-length ratio of the transistor included in the control node control circuit may be 5/12, the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the fourth pull-down transistor may be 30/6, the ratio between the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the second pull-down transistor is 1:12, and the ratio between the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the fourth pull-down transistor is 1:12, but is not limited to this.
可选的,所述帧复位电路包括第一帧复位晶体管和第二帧复位晶体管;Optionally, the frame reset circuit includes a first frame reset transistor and a second frame reset transistor;
所述第一帧复位晶体管的栅极与所述帧复位线电连接,所述第一帧复位晶体管的第一极与所述第一节点电连接,所述第一帧复位晶体管的第二极与控制节点电连接;The gate of the first frame reset transistor is electrically connected to the frame reset line, the first electrode of the first frame reset transistor is electrically connected to the first node, and the second electrode of the first frame reset transistor is electrically connected to the control node;
所述第二帧复位晶体管的栅极与所述帧复位线电连接,所述第二帧复位晶体管的第一极与所述控制节点电连接,所述第二帧复位晶体管的第二极与所述第二电压线电连接。A gate of the second frame reset transistor is electrically connected to the frame reset line, a first electrode of the second frame reset transistor is electrically connected to the control node, and a second electrode of the second frame reset transistor is electrically connected to the second voltage line.
在本公开至少一实施例中,可以将与第一节点电连接的用于帧复位电路设置为包括相互串联的第一帧复位晶体管和第二帧复位晶体管,以减小第一节点的漏电。In at least one embodiment of the present disclosure, a frame reset circuit electrically connected to the first node may be configured to include a first frame reset transistor and a second frame reset transistor connected in series to reduce leakage of the first node.
本公开至少一实施例所述的驱动电路还包括进位信号输出电路、驱动信号输出电路和储能电路;The driving circuit described in at least one embodiment of the present disclosure further includes a carry signal output circuit, a driving signal output circuit and an energy storage circuit;
所述进位信号输出电路分别与第一节点、第二节点、进位信号输出端、时钟信号端和第二电压线电连接,用于在所述第一节点的电位的控制下,控制所述进位信号输出端与所述时钟信号端之间连通或断开,在所述第二节点的电位的控制下,控制所述进位信号输出端与所述第二电压线之间连通或断开;The carry signal output circuit is electrically connected to the first node, the second node, the carry signal output terminal, the clock signal terminal and the second voltage line respectively, and is used to control the connection or disconnection between the carry signal output terminal and the clock signal terminal under the control of the potential of the first node, and to control the connection or disconnection between the carry signal output terminal and the second voltage line under the control of the potential of the second node;
所述驱动信号输出电路分别与第一节点、第二节点、驱动信号输出端、时钟信号端和第四电压线电连接,用于在所述第一节点的电位的控制下,控制所述驱动信号输出端与所述时钟信号端之间连通或断开,在所述第二节点的电位的控制下,控制所述驱动信号输出端与所述第四电压线之间连通或断开;The drive signal output circuit is electrically connected to the first node, the second node, the drive signal output terminal, the clock signal terminal and the fourth voltage line respectively, and is used to control the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and control the connection or disconnection between the drive signal output terminal and the fourth voltage line under the control of the potential of the second node;
所述储能电路分别与所述第一节点和所述驱动信号输出端电连接,用于储存电能。The energy storage circuit is electrically connected to the first node and the driving signal output terminal respectively, and is used for storing electric energy.
可选的,所述第二电压线可以为第二低电压线,所述第四电压线可以为第一低电压线。Optionally, the second voltage line may be a second low voltage line, and the fourth voltage line may be a first low voltage line.
在本公开至少一实施例中,所述第四电压线用于提供第四电压信号,所述第二电压线用于提供第二电压信号;In at least one embodiment of the present disclosure, the fourth voltage line is used to provide a fourth voltage signal, and the second voltage line is used to provide a second voltage signal;
所述第四电压信号的电压值等于所述第二电压信号的电压值,或者,所述第二电压信号的电压值小于所述第四电压信号的电压值。The voltage value of the fourth voltage signal is equal to the voltage value of the second voltage signal, or the voltage value of the second voltage signal is smaller than the voltage value of the fourth voltage signal.
在具体实施时,所述驱动电路还可以包括进位信号输出电路和驱动信号输出电路,进位信号输出电路在第一节点的电位的控制下,控制所述驱动信号输出端与所述时钟信号端之间连通或断开,在所述第二节点的电位的控制下,控制所述驱动信号输出端与所述第三电压线之间连通或断开;所述驱动信号输出电路在所述第一节点的电位的控制下,控制所述驱动信号输出端与所述时钟信号端之间连通或断开,在所述第二节点的电位的控制下,控制所述驱动信号输出端与所述第三电压线之间连通或断开。 In a specific implementation, the drive circuit may further include a carry signal output circuit and a drive signal output circuit. The carry signal output circuit controls the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and controls the connection or disconnection between the drive signal output terminal and the third voltage line under the control of the potential of the second node; the drive signal output circuit controls the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and controls the connection or disconnection between the drive signal output terminal and the third voltage line under the control of the potential of the second node.
在具体实施时,所述第二电压信号的电压值可以小于所述第四电压信号的电压值,当所述输入控制端为相邻上一级驱动电路的进位信号输出端,所述输入端为相邻上一级驱动电路的驱动信号输出端时,用于输入的晶体管的栅源电压小于0V,用于输入的晶体管的工作状态由亚阈值区变为关态,第一节点的电位二阶抬升时漏电减少。In a specific implementation, the voltage value of the second voltage signal may be smaller than the voltage value of the fourth voltage signal. When the input control terminal is the carry signal output terminal of the adjacent previous-level driving circuit and the input terminal is the drive signal output terminal of the adjacent previous-level driving circuit, the gate-source voltage of the transistor used for input is smaller than 0V, the working state of the transistor used for input changes from the subthreshold region to the off state, and the leakage current is reduced when the potential of the first node is raised in the second order.
本公开至少一实施例所述的驱动电路还包括第二节点控制电路;The driving circuit described in at least one embodiment of the present disclosure further includes a second node control circuit;
所述第二节点控制电路分别与输入控制端、第一节点、第二节点和第二电压线电连接,用于在所述输入控制端提供的输入控制信号的控制下,控制所述第二节点与所述第二电压线之间连通或断开,并在所述第一节点的电位的控制下,控制所述第二节点的电位。The second node control circuit is electrically connected to the input control terminal, the first node, the second node and the second voltage line, respectively, and is used to control the connection or disconnection between the second node and the second voltage line under the control of the input control signal provided by the input control terminal, and to control the potential of the second node under the control of the potential of the first node.
在具体实施时,所述驱动电路可以包括第二节点控制电路,第二节点控制电路在输入控制信号的控制下,控制第二节点与所述第四电压线之间连通或断开,并在所述第一节点的电位的控制下,控制所述第二节点的电位。In a specific implementation, the driving circuit may include a second node control circuit, which controls the connection or disconnection between the second node and the fourth voltage line under the control of an input control signal, and controls the potential of the second node under the control of the potential of the first node.
如图4所示,在图3所示的驱动电路的至少一实施例的基础上,本公开至少一实施例所述的驱动电路包括第一个第二节点PD1、第二个第二节点PD2、第二节点控制电路43、储能电路40、进位信号输出电路44和驱动信号输出电路45;As shown in FIG. 4 , based on at least one embodiment of the driving circuit shown in FIG. 3 , the driving circuit described in at least one embodiment of the present disclosure includes a first second node PD1, a second second node PD2, a second node control circuit 43, a tank circuit 40, a carry signal output circuit 44, and a driving signal output circuit 45;
所述第一节点复位电路13分别与第一个第二节点PD1、第二个第二节点PD2、第一节点PU和第一电压线V1电连接,用于在所述第一个第二节点PD1的电位的控制下,控制所述第一节点PU与所述第一电压线V1之间连通,在所述第二个第二节点PD2的电位的控制下,控制所述第一节点PU与第一电压线V1之间连通;The first node reset circuit 13 is electrically connected to the first second node PD1, the second second node PD2, the first node PU and the first voltage line V1, respectively, and is used to control the connection between the first node PU and the first voltage line V1 under the control of the potential of the first second node PD1, and control the connection between the first node PU and the first voltage line V1 under the control of the potential of the second second node PD2;
所述第二节点控制电路43分别与输入控制端IK1、第一节点PU、第一个第二节点PD1、第二个第二节点PD2和第二电压线V2电连接,用于在所述输入控制端IK1提供的输入控制信号的控制下,控制所述第一个第二节点PD1与所述第二电压线V2之间连通,控制所述第二个第二节点PD2与所述第二电压线V2之间连通,并在所述第一节点PU的电位的控制下,控制所述第一个第二节点PD1的电位和所述第二个第二节点PD2的电位;The second node control circuit 43 is electrically connected to the input control terminal IK1, the first node PU, the first second node PD1, the second second node PD2 and the second voltage line V2, respectively, and is used to control the connection between the first second node PD1 and the second voltage line V2, and the connection between the second second node PD2 and the second voltage line V2 under the control of the input control signal provided by the input control terminal IK1, and control the potential of the first second node PD1 and the potential of the second second node PD2 under the control of the potential of the first node PU;
所述储能电路40的第一端与第一节点PU电连接,所述储能电路40的第二端与驱动信号输出端GT电连接,所述储能电路40用于储存电能;The first end of the energy storage circuit 40 is electrically connected to the first node PU, the second end of the energy storage circuit 40 is electrically connected to the driving signal output terminal GT, and the energy storage circuit 40 is used to store electrical energy;
所述进位信号输出电路44分别与第一节点PU、第一个第二节点PD1、第二个第二节点PD2、进位信号输出端OC、时钟信号端CLK和第二电压线V2电连接,用于在所述第一节点PU的电位的控制下,控制所述进位信号输出端OC与所述时钟信号端CLK之间连通,在所述第一个第二节点PD1的电位的控制下,控制所述进位信号输出端OC与所述第二电压线V2之间连通,在所述第二个第二节点PD2的电位的控制下,控制所述进位信号输出端OC与所述第二电压线V2之间连通;The carry signal output circuit 44 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the carry signal output terminal OC, the clock signal terminal CLK and the second voltage line V2 respectively, and is used to control the communication between the carry signal output terminal OC and the clock signal terminal CLK under the control of the potential of the first node PU, control the communication between the carry signal output terminal OC and the second voltage line V2 under the control of the potential of the first second node PD1, and control the communication between the carry signal output terminal OC and the second voltage line V2 under the control of the potential of the second second node PD2;
所述驱动信号输出电路45分别与第一节点PU、第一个第二节点PD1、第二个第二节点PD2、驱动信号输出端GT、时钟信号端CLK和第四电压线V4电连接,用于在所述第一节点PU的电位的控制下,控制所述驱动信号输出端GT与所述时钟信号端CLK之间连通,在所述第一个第二节点PD1的电位的控制下,控制所述驱动信号输出端GT与所述第 四电压线V4之间连通,在所述第二个第二节点PD2的电位的控制下,控制所述驱动信号输出端GT与所述第四电压线V4之间连通。The drive signal output circuit 45 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the drive signal output terminal GT, the clock signal terminal CLK and the fourth voltage line V4, respectively, and is used to control the connection between the drive signal output terminal GT and the clock signal terminal CLK under the control of the potential of the first node PU, and to control the connection between the drive signal output terminal GT and the clock signal terminal CLK under the control of the potential of the first second node PD1. The four voltage lines V4 are connected to each other, and under the control of the potential of the second second node PD2, the driving signal output terminal GT is controlled to be connected to the fourth voltage line V4.
如图5所示,在图4所示的驱动电路的至少一实施例的基础上,As shown in FIG. 5 , based on at least one embodiment of the driving circuit shown in FIG. 4 ,
所述关机复位电路包括关机复位晶体管M14;The shutdown reset circuit includes a shutdown reset transistor M14;
所述关机复位晶体管M14的栅极和所述关机复位晶体管M14的源极与第一低电压线VGL电连接,所述关机复位晶体管M14的漏极与所述驱动信号输出端GT电连接;The gate of the shutdown reset transistor M14 and the source of the shutdown reset transistor M14 are electrically connected to the first low voltage line VGL, and the drain of the shutdown reset transistor M14 is electrically connected to the drive signal output terminal GT;
所述控制节点控制电路包括控制晶体管M0;The control node control circuit includes a control transistor M0;
所述控制晶体管M0的栅极与所述第一节点PU电连接,所述控制晶体管M0的源极与高电压线VGH电连接,所述控制晶体管M0的漏极与所述控制节点N0电连接;The gate of the control transistor M0 is electrically connected to the first node PU, the source of the control transistor M0 is electrically connected to the high voltage line VGH, and the drain of the control transistor M0 is electrically connected to the control node N0;
所述输入电路包括第一输入晶体管M1A和第二输入晶体管M1B;The input circuit includes a first input transistor M1A and a second input transistor M1B;
所述第一输入晶体管M1A的栅极与所述输入控制端IK1电连接,所述第一输入晶体管M1A的源极与所述输入端I0电连接,所述第一输入晶体管M1A的漏极与控制节点N0电连接;The gate of the first input transistor M1A is electrically connected to the input control terminal IK1, the source of the first input transistor M1A is electrically connected to the input terminal I0, and the drain of the first input transistor M1A is electrically connected to the control node N0;
所述第二输入晶体管M1B的栅极与所述输入控制端IK1电连接,所述第二输入晶体管M1B的源极与所述控制节点N0电连接,所述第二输入晶体管M1B的漏极与所述第一节点PU电连接;The gate of the second input transistor M1B is electrically connected to the input control terminal IK1, the source of the second input transistor M1B is electrically connected to the control node N0, and the drain of the second input transistor M1B is electrically connected to the first node PU;
所述复位电路包括第一复位晶体管M2A和第二复位晶体管M2B;The reset circuit includes a first reset transistor M2A and a second reset transistor M2B;
所述第一复位晶体管M2A的栅极与所述复位端R1电连接,所述第一复位晶体管M2A的源极与所述第一节点PU电连接,所述第一复位晶体管M2A的漏极与控制节点N0电连接;The gate of the first reset transistor M2A is electrically connected to the reset terminal R1, the source of the first reset transistor M2A is electrically connected to the first node PU, and the drain of the first reset transistor M2A is electrically connected to the control node N0;
所述第二复位晶体管M2B的栅极与所述复位端R1电连接,所述第二复位晶体管M2B的源极与所述控制节点N0电连接,所述第二复位晶体管M2B的漏极与所述第一低电压线VGL电连接;A gate of the second reset transistor M2B is electrically connected to the reset terminal R1, a source of the second reset transistor M2B is electrically connected to the control node N0, and a drain of the second reset transistor M2B is electrically connected to the first low voltage line VGL;
所述第一节点复位电路包括第一下拉晶体管M8A、第二下拉晶体管M8C、第三下拉晶体管M8B和第四下拉晶体管M8D;The first node reset circuit includes a first pull-down transistor M8A, a second pull-down transistor M8C, a third pull-down transistor M8B and a fourth pull-down transistor M8D;
所述第一下拉晶体管M8A的栅极与所述第一个第二节点PD1电连接,所述第一下拉晶体管M8A的源极与第一节点PU电连接,所述第一下拉晶体管M8A的漏极与控制节点N0电连接;The gate of the first pull-down transistor M8A is electrically connected to the first second node PD1, the source of the first pull-down transistor M8A is electrically connected to the first node PU, and the drain of the first pull-down transistor M8A is electrically connected to the control node N0;
所述第二下拉晶体管M8C的栅极与所述第一个第二节点PD1电连接,所述第二下拉晶体管M8C的源极与所述控制节点N0电连接,所述第二下拉晶体管M8C的漏极与所述第一低电压线VGL电连接;The gate of the second pull-down transistor M8C is electrically connected to the first second node PD1, the source of the second pull-down transistor M8C is electrically connected to the control node N0, and the drain of the second pull-down transistor M8C is electrically connected to the first low voltage line VGL;
所述第三下拉晶体管M8B的栅极与所述第二个第二节点PD2电连接,所述第三下拉晶体管M8B的源极与第一节点PU电连接,所述第三下拉晶体管M8B的漏极与控制节点N0电连接;The gate of the third pull-down transistor M8B is electrically connected to the second second node PD2, the source of the third pull-down transistor M8B is electrically connected to the first node PU, and the drain of the third pull-down transistor M8B is electrically connected to the control node N0;
所述第四下拉晶体管M8D的栅极与所述第二个第二节点PD2电连接,所述第四下拉 晶体管M8D的源极与所述控制节点N0电连接,所述第四下拉晶体管M8D的漏极与所述第一低电压线VGL电连接;The gate of the fourth pull-down transistor M8D is electrically connected to the second second node PD2. The source of the transistor M8D is electrically connected to the control node N0, and the drain of the fourth pull-down transistor M8D is electrically connected to the first low voltage line VGL;
所述帧复位电路包括第一帧复位晶体管M15A和第二帧复位晶体管M15B;The frame reset circuit includes a first frame reset transistor M15A and a second frame reset transistor M15B;
所述第一帧复位晶体管M15A的栅极与所述帧复位线STV0电连接,所述第一帧复位晶体管M15A的源极与所述第一节点PU电连接,所述第一帧复位晶体管M15A的漏极与控制节点N0电连接;The gate of the first frame reset transistor M15A is electrically connected to the frame reset line STV0, the source of the first frame reset transistor M15A is electrically connected to the first node PU, and the drain of the first frame reset transistor M15A is electrically connected to the control node N0;
所述第二帧复位晶体管M15B的栅极与所述帧复位线STV0电连接,所述第二帧复位晶体管M15B的源极与所述控制节点N0电连接,所述第二帧复位晶体管M15B的漏极与所述第二低电压线LVGL电连接;The gate of the second frame reset transistor M15B is electrically connected to the frame reset line STV0, the source of the second frame reset transistor M15B is electrically connected to the control node N0, and the drain of the second frame reset transistor M15B is electrically connected to the second low voltage line LVGL;
所述第二节点控制电路包括第一控制晶体管M5A、第二控制晶体管M6A、第三控制晶体管M16A、第四控制晶体管M5B、第五控制晶体管M6B和第六控制晶体管M16B;The second node control circuit includes a first control transistor M5A, a second control transistor M6A, a third control transistor M16A, a fourth control transistor M5B, a fifth control transistor M6B and a sixth control transistor M16B;
所述第一控制晶体管M5A的栅极和所述第一控制晶体管M5A的源极都与第一控制电压线VDDO电连接,所述第一控制晶体管M5A的漏极与第一个第二节点PD1电连接;The gate of the first control transistor M5A and the source of the first control transistor M5A are both electrically connected to the first control voltage line VDDO, and the drain of the first control transistor M5A is electrically connected to the first second node PD1;
所述第二控制晶体管M6A的栅极与所述第一节点PU电连接,所述第二控制晶体管M6A的源极与所述第一个第二节点PD1电连接,所述第二控制晶体管M6A的漏极与第二低电压线LVGL电连接;The gate of the second control transistor M6A is electrically connected to the first node PU, the source of the second control transistor M6A is electrically connected to the first second node PD1, and the drain of the second control transistor M6A is electrically connected to the second low voltage line LVGL;
所述第三控制晶体管M16A的栅极与所述输入控制端IK1电连接,所述第三控制晶体管M16A的源极与所述第一个第二节点PD1电连接,所述第三控制晶体管M16A的漏极与第二低电压线LVGL电连接;The gate of the third control transistor M16A is electrically connected to the input control terminal IK1, the source of the third control transistor M16A is electrically connected to the first second node PD1, and the drain of the third control transistor M16A is electrically connected to the second low voltage line LVGL;
所述第四控制晶体管M5B的栅极和所述第二控制晶体管M5B的源极都与第二控制电压线VDDE电连接,所述第二控制晶体管M5B的漏极与第二个第二节点PD2电连接;The gate of the fourth control transistor M5B and the source of the second control transistor M5B are both electrically connected to the second control voltage line VDDE, and the drain of the second control transistor M5B is electrically connected to the second second node PD2;
所述第五控制晶体管M6B的栅极与所述第一节点PU电连接,所述第五控制晶体管M6B的源极与所述第二个第二节点PD2电连接,所述第五控制晶体管M6B的漏极与第二低电压线LVGL电连接;The gate of the fifth control transistor M6B is electrically connected to the first node PU, the source of the fifth control transistor M6B is electrically connected to the second second node PD2, and the drain of the fifth control transistor M6B is electrically connected to the second low voltage line LVGL;
所述第六控制晶体管M16B的栅极与所述输入控制端IK1电连接,所述第六控制晶体管M16B的源极与所述第二个第二节点PD2电连接,所述第六控制晶体管M16B的漏极与第二低电压线LVGL电连接;The gate of the sixth control transistor M16B is electrically connected to the input control terminal IK1, the source of the sixth control transistor M16B is electrically connected to the second second node PD2, and the drain of the sixth control transistor M16B is electrically connected to the second low voltage line LVGL;
所述储能电路包括存储电容C0;The energy storage circuit includes a storage capacitor C0;
C0的第一极板与第一节点PU电连接,C0的第二极板与驱动信号输出端GT电连接;The first electrode plate of C0 is electrically connected to the first node PU, and the second electrode plate of C0 is electrically connected to the driving signal output terminal GT;
所述进位信号输出电路包括进位输出晶体管M11、第一进位复位晶体管M12A和第二进位复位晶体管M12B,所述驱动信号输出电路包括驱动输出晶体管M3、第一驱动复位晶体管M13A、第二驱动复位晶体管M13B和输出复位晶体管M4;The carry signal output circuit includes a carry output transistor M11, a first carry reset transistor M12A and a second carry reset transistor M12B, and the drive signal output circuit includes a drive output transistor M3, a first drive reset transistor M13A, a second drive reset transistor M13B and an output reset transistor M4;
所述进位输出晶体管M11的栅极与所述第一节点PU电连接,所述进位输出晶体管M11的源极与时钟信号端CLK电连接,所述进位输出晶体管M11的漏极与进位信号输出端OC电连接; The gate of the carry output transistor M11 is electrically connected to the first node PU, the source of the carry output transistor M11 is electrically connected to the clock signal terminal CLK, and the drain of the carry output transistor M11 is electrically connected to the carry signal output terminal OC;
所述第一进位复位晶体管M12A的栅极与第一个第二节点PD1电连接,所述第一进位复位晶体管M12A的源极与所述进位信号输出端OC电连接,所述第一进位复位晶体管M12A的漏极与第二低电压线LVGL电连接;The gate of the first carry reset transistor M12A is electrically connected to the first second node PD1, the source of the first carry reset transistor M12A is electrically connected to the carry signal output terminal OC, and the drain of the first carry reset transistor M12A is electrically connected to the second low voltage line LVGL;
所述第二进位复位晶体管M12B的栅极与第二个第二节点PD2电连接,所述第二进位复位晶体管M12B的源极与所述进位信号输出端OC电连接,所述第二进位复位晶体管M12B的漏极与第二低电压线LVGL电连接;The gate of the second carry reset transistor M12B is electrically connected to the second second node PD2, the source of the second carry reset transistor M12B is electrically connected to the carry signal output terminal OC, and the drain of the second carry reset transistor M12B is electrically connected to the second low voltage line LVGL;
所述驱动输出晶体管M3的栅极与第一节点PU电连接,所述驱动输出晶体管M3的源极与时钟信号端CLK电连接,所述驱动输出晶体管M3的漏极与驱动信号输出端GT电连接;The gate of the driving output transistor M3 is electrically connected to the first node PU, the source of the driving output transistor M3 is electrically connected to the clock signal terminal CLK, and the drain of the driving output transistor M3 is electrically connected to the driving signal output terminal GT;
所述第一驱动复位晶体管M13A的栅极与第一个第二节点PD1电连接,所述第一驱动复位晶体管M13A的源极与所述驱动信号输出端GT电连接,所述第一驱动复位晶体管M13A的漏极与第一低电压线VGL电连接;The gate of the first driving reset transistor M13A is electrically connected to the first second node PD1, the source of the first driving reset transistor M13A is electrically connected to the driving signal output terminal GT, and the drain of the first driving reset transistor M13A is electrically connected to the first low voltage line VGL;
所述第二驱动复位晶体管M13B的栅极与第二个第二节点PD2电连接,所述第二驱动复位晶体管M13B的源极与所述驱动信号输出端GT电连接,所述第二驱动复位晶体管M13B的漏极与第一低电压线VGL电连接;The gate of the second driving reset transistor M13B is electrically connected to the second second node PD2, the source of the second driving reset transistor M13B is electrically connected to the driving signal output terminal GT, and the drain of the second driving reset transistor M13B is electrically connected to the first low voltage line VGL;
所述输出复位晶体管M4的栅极与复位控制信号端R0电连接,所述输出复位晶体管M4的源极与所述驱动信号输出端GT电连接,所述输出复位晶体管M4的漏极与第一低电压线VGL电连接。The gate of the output reset transistor M4 is electrically connected to the reset control signal terminal R0, the source of the output reset transistor M4 is electrically connected to the drive signal output terminal GT, and the drain of the output reset transistor M4 is electrically connected to the first low voltage line VGL.
所述输入控制端IK1为相邻上一级驱动电路的进位信号输出端,所述输入端I0为相邻上一级驱动电路的驱动信号输出端;The input control terminal IK1 is a carry signal output terminal of the adjacent previous stage driving circuit, and the input terminal I0 is a drive signal output terminal of the adjacent previous stage driving circuit;
在图5所示的驱动电路的至少一实施例中,所有晶体管都为n型晶体管,但不以此为限。In at least one embodiment of the driving circuit shown in FIG. 5 , all transistors are n-type transistors, but the present invention is not limited thereto.
在图5所示的驱动电路的至少一实施例中,采用控制晶体管M0控制所述控制节点N0的电位,在第一节点PU的电位为高电压时,控制节点N0的电位被充电至高电压,此时第一节点PU的漏电途径为PU至N0,以有效防止第一节点PU漏电,提升显示产品的驱动能力;In at least one embodiment of the driving circuit shown in FIG5 , a control transistor M0 is used to control the potential of the control node N0. When the potential of the first node PU is a high voltage, the potential of the control node N0 is charged to a high voltage. At this time, the leakage path of the first node PU is from PU to N0, so as to effectively prevent the leakage of the first node PU and improve the driving capability of the display product.
所述第一输入晶体管M1A的漏极与控制节点N0电连接;所述第二输入晶体管M1B的源极与所述控制节点N0电连接;所述第一复位晶体管M2A的漏极与控制节点N0电连接;所述第二复位晶体管M2B的源极与所述控制节点N0电连接;所述第一下拉晶体管M8A的漏极与控制节点N0电连接;所述第二下拉晶体管M8C的源极与所述控制节点N0电连接;所述第三下拉晶体管M8B的漏极与控制节点N0电连接;所述第四下拉晶体管M8D的源极与所述控制节点N0电连接;所述第一帧复位晶体管M15A的漏极与控制节点N0电连接;所述第二帧复位晶体管M15B的源极与所述控制节点N0电连接;本公开至少一实施例将源极或漏极与第一节点PU电连接的晶体管设置为相互串联的两个晶体管,以减小第一节点PU的漏电流。 The drain of the first input transistor M1A is electrically connected to the control node N0; the source of the second input transistor M1B is electrically connected to the control node N0; the drain of the first reset transistor M2A is electrically connected to the control node N0; the source of the second reset transistor M2B is electrically connected to the control node N0; the drain of the first pull-down transistor M8A is electrically connected to the control node N0; the source of the second pull-down transistor M8C is electrically connected to the control node N0; the drain of the third pull-down transistor M8B is electrically connected to the control node N0; the source of the fourth pull-down transistor M8D is electrically connected to the control node N0; the drain of the first frame reset transistor M15A is electrically connected to the control node N0; the source of the second frame reset transistor M15B is electrically connected to the control node N0; at least one embodiment of the present disclosure sets the transistor whose source or drain is electrically connected to the first node PU to two transistors connected in series to reduce the leakage current of the first node PU.
在图5所示的驱动电路的至少一实施例中,M0、M2B、M8C、M8D、M15B、M16A和M16B共同构成PU电压确保单元;当I1提供高电压信号,对本级驱动电路的第一节点PU进行充电时,M16A和M16B打开,此时PD1的电位和PD2的电位被快速拉低,M8A、M8B、M8C和M8D关闭,同时PU的电位爬升,M0开启,N0的电位被充电至高电压,此时PU的漏电路径为PU-N0,M1A的漏源电压、M2A的漏源电压、M8A的漏源电压、M8B的漏源电压和M15A的漏源电压大幅降低,接近于0V或等于0V,有效防止第一节点PU的漏电,提升显示产品的驱动能力。同时,调整M0的沟道宽长比和M2B的沟道宽长比,在复位信号到来时,提升M2B的竞争力,使得N0的电位和第一节点PU的电压迅速被拉低,确保下拉节点的电位可以同步升高至高电压,开始对驱动信号和进位信号进行降噪。调整M0的沟道宽长比、M8C的沟道宽长比和M8D的沟道宽长比,使得M0的沟道宽长比与M8C的沟道宽长比的比值为1/12,M0的沟道宽长比与M8D的沟道宽长比的比值为1/12,调整M8A的沟道宽长比、M8B的沟道宽长比、M8C的沟道宽长比和M8D的沟道宽长比,将M8A的沟道宽长比和M8C的沟道宽长比之间的比值设置为1/2,将M8B的沟道宽长比和M8D的沟道宽长比的比值设置为1/2,防止控制节点N0的噪声通过漏电引入第一节点PU,提升驱动电路的稳定性,防止多输出。In at least one embodiment of the driving circuit shown in Figure 5, M0, M2B, M8C, M8D, M15B, M16A and M16B together constitute a PU voltage ensuring unit; when I1 provides a high voltage signal to charge the first node PU of the driving circuit at this level, M16A and M16B are turned on, at this time, the potential of PD1 and the potential of PD2 are quickly pulled down, M8A, M8B, M8C and M8D are turned off, and at the same time, the potential of PU rises, M0 is turned on, and the potential of N0 is charged to a high voltage. At this time, the leakage path of PU is PU-N0, and the drain-source voltage of M1A, the drain-source voltage of M2A, the drain-source voltage of M8A, the drain-source voltage of M8B and the drain-source voltage of M15A are greatly reduced, close to or equal to 0V, effectively preventing leakage of the first node PU and improving the driving capability of the display product. At the same time, the channel width-to-length ratio of M0 and the channel width-to-length ratio of M2B are adjusted. When the reset signal arrives, the competitiveness of M2B is improved, so that the potential of N0 and the voltage of the first node PU are quickly pulled down, ensuring that the potential of the pull-down node can be synchronously increased to a high voltage, and starting to reduce the noise of the drive signal and the carry signal. Adjust the channel width-to-length ratio of M0, the channel width-to-length ratio of M8C, and the channel width-to-length ratio of M8D, so that the ratio of the channel width-to-length ratio of M0 to the channel width-to-length ratio of M8C is 1/12, and the ratio of the channel width-to-length ratio of M0 to the channel width-to-length ratio of M8D is 1/12; adjust the channel width-to-length ratio of M8A, the channel width-to-length ratio of M8B, the channel width-to-length ratio of M8C, and the channel width-to-length ratio of M8D, and set the ratio between the channel width-to-length ratio of M8A and the channel width-to-length ratio of M8C to 1/2, and set the ratio between the channel width-to-length ratio of M8B and the channel width-to-length ratio of M8D to 1/2, so as to prevent the noise of the control node N0 from being introduced into the first node PU through leakage, thereby improving the stability of the driving circuit and preventing multiple outputs.
在图5所示的驱动电路的至少一实施例中,M0的沟道宽长比可以为5/12,M2B的沟道宽长比可以为5/6,M8C的沟道宽长比可以为30/6,M8D的沟道宽长比可以为30/6,M8A的沟道宽长比和M8B的沟道宽长比可以为15/6;In at least one embodiment of the driving circuit shown in FIG5 , the channel width-to-length ratio of M0 may be 5/12, the channel width-to-length ratio of M2B may be 5/6, the channel width-to-length ratio of M8C may be 30/6, the channel width-to-length ratio of M8D may be 30/6, the channel width-to-length ratio of M8A and the channel width-to-length ratio of M8B may be 15/6;
在图5所示的驱动电路的至少一实施例中,所述第一进位复位晶体管M12A的漏极与第二低电压线LVGL电连接;所述第二进位复位晶体管M12B的漏极与第二低电压线LVGL电连接;所述第一驱动复位晶体管M13A的漏极与第一低电压线VGL电连接;所述第二驱动复位晶体管M13B的漏极与第一低电压线VGL电连接;In at least one embodiment of the driving circuit shown in FIG5 , the drain of the first carry reset transistor M12A is electrically connected to the second low voltage line LVGL; the drain of the second carry reset transistor M12B is electrically connected to the second low voltage line LVGL; the drain of the first drive reset transistor M13A is electrically connected to the first low voltage line VGL; the drain of the second drive reset transistor M13B is electrically connected to the first low voltage line VGL;
所述第一低电压线VGL用于提供第一低电压信号,所述第二低电压线LVGL用于提供第二低电压信号;所述第二低电压信号的电压值可以小于所述第一低电压信号的电压值,当所述输入控制端为相邻上一级驱动电路的进位信号输出端,所述输入端为相邻上一级驱动电路的驱动信号输出端时,M1A的栅源电压和M1B的电压小于0V,M1A的工作状态和M1B的工作状态由亚阈值区变为关态,第一节点PU的电位二阶抬升时漏电减少。The first low voltage line VGL is used to provide a first low voltage signal, and the second low voltage line LVGL is used to provide a second low voltage signal; the voltage value of the second low voltage signal can be smaller than the voltage value of the first low voltage signal. When the input control terminal is the carry signal output terminal of the adjacent previous-level driving circuit and the input terminal is the driving signal output terminal of the adjacent previous-level driving circuit, the gate-source voltage of M1A and the voltage of M1B are smaller than 0V, the working state of M1A and the working state of M1B change from the subthreshold region to the off state, and the leakage current is reduced when the potential of the first node PU is raised in the second order.
在图5所示的驱动电路的至少一实施例中,M2B的漏极与第一低电压线VGL电连接,第二低电压线提供的第二低电压信号的电压值小于第一低电压线提供的第一低电压信号的电压值,M2B的栅源电压、M8C的栅源电压和M8D的栅源电压都小于0V,此时,M2B的工作状态、M8C的工作状态和M8D的工作状态由亚阈值区变为关态,漏电流大幅降低。In at least one embodiment of the driving circuit shown in Figure 5, the drain of M2B is electrically connected to the first low voltage line VGL, the voltage value of the second low voltage signal provided by the second low voltage line is less than the voltage value of the first low voltage signal provided by the first low voltage line, the gate-source voltage of M2B, the gate-source voltage of M8C and the gate-source voltage of M8D are all less than 0V. At this time, the working state of M2B, the working state of M8C and the working state of M8D change from the subthreshold region to the off state, and the leakage current is greatly reduced.
如图6所示,当图5所示的驱动电路的至少一实施例工作于触控扫描阶段SC时,由于第一节点PU的漏电流小,第一节点PU的电位能够维持为高电压。As shown in FIG. 6 , when at least one embodiment of the driving circuit shown in FIG. 5 operates in the touch scanning stage SC, since the leakage current of the first node PU is small, the potential of the first node PU can be maintained at a high voltage.
在图5所示的驱动电路的至少一实施例中,通过设置M14,In at least one embodiment of the driving circuit shown in FIG. 5 , by setting M14,
在显示面板正常显示时,第一低电压线VGL提供低电压信号,在显示面板准备关机 时,第一低电压线LVGL提供的电压信号的电位置高,M14打开,控制所述驱动信号输出端GT输出高电压信号,可以释放像素中的残留电荷,可以有效提升所述驱动信号输出端GT的开启能力,避免残像不良。When the display panel is displaying normally, the first low voltage line VGL provides a low voltage signal. When the voltage signal provided by the first low voltage line LVGL has a high voltage level, M14 is turned on, and the drive signal output terminal GT is controlled to output a high voltage signal, which can release the residual charge in the pixel, effectively improve the opening ability of the drive signal output terminal GT, and avoid poor afterimage.
图7是当处于正常显示状态时,图5所示的驱动电路的至少一实施例在工作时,第一节点PU的电位的仿真波形图;7 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG. 5 is in operation when in a normal display state;
图8是处于触控阶段时,图5所示的驱动电路的至少一实施例在工作时,第一节点PU的电位的仿真波形图;此时,PU的最高电位可以在16.95V左右。FIG8 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG5 is in operation during the touch stage; at this time, the highest potential of PU may be around 16.95V.
图9是图5所示的驱动电路的至少一实施例的工作时序图。FIG. 9 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 5 .
在图5所示的驱动电路的至少一实施例中,M14的沟道宽长比可以根据实际情况选定,M14的沟道宽长比通常与M4的沟道宽长比接近,确保在显示面板准备关机时,GT提供的驱动信号的电位能够充分快速拉高至高电平。In at least one embodiment of the driving circuit shown in FIG5 , the channel width-to-length ratio of M14 can be selected according to actual conditions. The channel width-to-length ratio of M14 is usually close to the channel width-to-length ratio of M4, ensuring that when the display panel is ready to shut down, the potential of the driving signal provided by GT can be sufficiently and quickly pulled up to a high level.
本公开图5所示的驱动电路的至少一实施例在工作时,VDDO提供的第一控制电压和VDDE提供的第二控制电压可以为方波信号,所述第一控制电压和所述第二控制电压相互反相,使得PD1和PD2交替工作。When at least one embodiment of the driving circuit shown in FIG. 5 of the present disclosure is working, the first control voltage provided by VDDO and the second control voltage provided by VDDE may be square wave signals, and the first control voltage and the second control voltage are inversely phased to each other, so that PD1 and PD2 work alternately.
图10是图5所示的驱动电路的至少一实施例的布局图,所述驱动电路设置于基底上。FIG. 10 is a layout diagram of at least one embodiment of the driving circuit shown in FIG. 5 , wherein the driving circuit is disposed on a substrate.
图11是图10中的栅金属层的布局图,图12是图10中的半导体层的布局图,图13是图10中的导电层的布局图,图14是图10中的源漏金属层的布局图。11 is a layout diagram of the gate metal layer in FIG. 10 , FIG. 12 is a layout diagram of the semiconductor layer in FIG. 10 , FIG. 13 is a layout diagram of the conductive layer in FIG. 10 , and FIG. 14 is a layout diagram of the source/drain metal layer in FIG. 10 .
如图10所示,标号为CLKA的为第一时钟信号线,标号为CLKB的为第二时钟信号线,标号为CLKC的为第三时钟信号线,标号为CLKD的为第四时钟信号线,标号为STV的为起始电压线,标号为VDDO的为第一控制电压线,标号为VDDE为第二控制电压线,标号为STV0的为帧复位线,标号为LVGL的为第二低电压线,标号为VGL1的为第一条第一低电压线,标号为VGL2的为第二条第一低电压线,标号为VGH的为高电压线;As shown in FIG10 , CLKA is the first clock signal line, CLKB is the second clock signal line, CLKC is the third clock signal line, CLKD is the fourth clock signal line, STV is the start voltage line, VDDO is the first control voltage line, VDDE is the second control voltage line, STV0 is the frame reset line, LVGL is the second low voltage line, VGL1 is the first low voltage line, VGL2 is the second low voltage line, and VGH is the high voltage line;
CLKA、CLKB、CLKC、CLKD、STV、VDDO、VDDE、STV0、LVGL和VGL1沿竖直方向延伸;CLKA, CLKB, CLKC, CLKD, STV, VDDO, VDDE, STV0, LVGL and VGL1 extend in a vertical direction;
CLKA、CLKB、CLKC、CLKD、STV、VDDO、VDDE、STV0、LVGL和VGL1设置于驱动电路远离显示区域的一侧;CLKA, CLKB, CLKC, CLKD, STV, VDDO, VDDE, STV0, LVGL and VGL1 are arranged on a side of the driving circuit away from the display area;
VGL2和VGH沿竖直方向延伸;VGL2 and VGH extend in the vertical direction;
VGL2和VGH设置于驱动电路靠近显示区域的一侧。VGL2 and VGH are arranged on a side of the driving circuit close to the display area.
如图10-图14所示,输入电路包括的晶体管、复位电路包括的晶体管和第一节点复位电路包括的晶体管沿着远离显示区域的方向依次排列;As shown in FIGS. 10 to 14 , the transistor included in the input circuit, the transistor included in the reset circuit, and the transistor included in the first node reset circuit are arranged in sequence along a direction away from the display area;
M14设置于M0远离显示区域的一侧,M0设置于M1A和M1B远离显示区域的一侧;M14 is arranged on a side of M0 away from the display area, and M0 is arranged on a side of M1A and M1B away from the display area;
M11的有源图形在基底上的正投影、C0的第一极板在基底上的正投影和M1A的有源图形在基底上的正投影沿着竖直方向依次排列;M11的有源图形在基底上的正投影、C0的第一极板在基底上的正投影和M1B的有源图形在基底上的正投影沿着竖直方向依次排列;以利用纵向空间布局M11、C0、M1A和M1B,利于实现窄边框; The orthographic projection of the active pattern of M11 on the substrate, the orthographic projection of the first electrode plate of C0 on the substrate, and the orthographic projection of the active pattern of M1A on the substrate are arranged in sequence along the vertical direction; the orthographic projection of the active pattern of M11 on the substrate, the orthographic projection of the first electrode plate of C0 on the substrate, and the orthographic projection of the active pattern of M1B on the substrate are arranged in sequence along the vertical direction; M11, C0, M1A and M1B are arranged in a longitudinal space to facilitate the realization of a narrow frame;
M1A和M1B并排设置,M1A和M1B沿着水平方向排列,M1B设置于M1A远离显示区域的一侧;M1A and M1B are arranged side by side, M1A and M1B are arranged in a horizontal direction, and M1B is arranged on a side of M1A away from the display area;
M14和M4沿着竖直方向依次排列,以利用纵向空间布局M14和M4,利于实现窄边框;M14 and M4 are arranged in sequence along the vertical direction to utilize the longitudinal space layout of M14 and M4, which is conducive to achieving a narrow frame;
M3和M0沿着竖直方向依次排列,以利用纵向空间布局M3和M0,利于实现窄边框;M3 and M0 are arranged in sequence along the vertical direction to utilize the longitudinal space to layout M3 and M0, which is conducive to achieving a narrow frame;
M3设置于M14和M11之间;M3 is set between M14 and M11;
M2A和M2B并排设置,M2B和M2A沿着水平方向排列;M2A and M2B are arranged side by side, and M2B and M2A are arranged in the horizontal direction;
M8D、M8B和M7A沿着竖直方向依次排列,M8D、M8B和M7B沿着竖直方向依次排列,以利用纵向空间布局M8D、M8B、M7A和M7B,利于实现窄边框;M8D, M8B and M7A are arranged in sequence along the vertical direction, and M8D, M8B and M7B are arranged in sequence along the vertical direction, so as to utilize the longitudinal space to arrange M8D, M8B, M7A and M7B, which is conducive to achieving a narrow frame;
M8C和M8A沿着竖直方向依次排列,以利用纵向空间布局M8C和M8A,利于窄边框;M8C and M8A are arranged in sequence along the vertical direction to utilize the vertical space to layout M8C and M8A, which is conducive to narrow bezels;
M8D和M8C并排设置,M8B和M8A并排设置,M8C和M8D沿着水平方向排列,M8A和M8B沿着水平方向排列,M8D设置于M8C远离显示区域的一侧,M8B设置于M8A远离显示区域的一侧;M8D and M8C are arranged side by side, M8B and M8A are arranged side by side, M8C and M8D are arranged in a horizontal direction, M8A and M8B are arranged in a horizontal direction, M8D is arranged on a side of M8C away from the display area, and M8B is arranged on a side of M8A away from the display area;
M12B、M13B、M13A和M12A沿着竖直方向依次排列,以利用竖向空间设置M12B、M13B、M13A和M12A,利于实现窄边框;M12B, M13B, M13A and M12A are arranged in sequence along the vertical direction, so as to utilize the vertical space to arrange M12B, M13B, M13A and M12A, which is conducive to achieving a narrow frame;
M13B设置于M8D远离显示区域的一侧;M13B is arranged on a side of M8D away from the display area;
M6B、M15A和M16A沿着竖直方向依次排列,M6B、M15B和M16A沿着竖直方向依次排列,以利用竖向空间设置M6B、M15A、M15B和M16A;M6B, M15A and M16A are arranged in sequence along the vertical direction, and M6B, M15B and M16A are arranged in sequence along the vertical direction to utilize the vertical space to set M6B, M15A, M15B and M16A;
M15A和M15B水平并排设置;The M15A and M15B are set side by side horizontally;
M6B设置于M12B远离显示区域的一侧;M6B is arranged on a side of M12B away from the display area;
M5B和M5A沿着竖直方向依次排列;M5A设置于M6A远离显示区域的一侧。M5B and M5A are arranged in sequence along the vertical direction; M5A is arranged on a side of M6A away from the display area.
在图11中,标号为CLKA1为CLKA包括的第一时钟信号线部,标号为CLKB1为CLKB包括的第一时钟信号线部,标号为CLKD1为CLKD包括的第一时钟信号线部,标号为CLKD1为CLKD包括的第一时钟信号线部。In FIG. 11 , CLKA1 is a first clock signal line portion included in CLKA, CLKB1 is a first clock signal line portion included in CLKB, CLKD1 is a first clock signal line portion included in CLKD, and CLKD1 is a first clock signal line portion included in CLKD.
在图12中,标号为A8D的为M8D的有源图形,标号为A8C的为M8C的有源图形,标号为A8B的为M8B的有源图形,标号为A8A的为M8A的有源图形。In FIG. 12 , A8D is an active pattern of M8D, A8C is an active pattern of M8C, A8B is an active pattern of M8B, and A8A is an active pattern of M8A.
在图14中,标号为CLKA2为CLKA包括的第二时钟信号线部,标号为CLKB2为CLKB包括的第二时钟信号线部,标号为CLKD2为CLKD包括的第二时钟信号线部,标号为CLKD2为CLKD包括的第二时钟信号线部;In FIG14 , CLKA2 is a second clock signal line portion included in CLKA, CLKB2 is a second clock signal line portion included in CLKB, CLKD2 is a second clock signal line portion included in CLKD, and CLKD2 is a second clock signal line portion included in CLKD;
CLKA2可以与CLKA1电连接,CLKB2可以与CLKB1电连接,CLKC2可以与CLKC1电连接,CLKD2可以与CLKD1电连接。CLKA2 may be electrically connected to CLKA1 , CLKB2 may be electrically connected to CLKB1 , CLKC2 may be electrically connected to CLKC1 , and CLKD2 may be electrically connected to CLKD1 .
图15所示的驱动电路的至少一实施例与图5所示的驱动电路的至少一实施例的区别在于:The difference between at least one embodiment of the driving circuit shown in FIG. 15 and at least one embodiment of the driving circuit shown in FIG. 5 is that:
不设置M0和控制节点N0; M0 and control node N0 are not set;
所述第一输入晶体管M1A的漏极与所述第二输入晶体管M1B的源极电连接;The drain of the first input transistor M1A is electrically connected to the source of the second input transistor M1B;
所述第一复位晶体管M2A的漏极与所述第二复位晶体管M2B的源极电连接;The drain of the first reset transistor M2A is electrically connected to the source of the second reset transistor M2B;
所述第一下拉晶体管M8A的漏极与所述第二下拉晶体管M8C的源极电连接;The drain of the first pull-down transistor M8A is electrically connected to the source of the second pull-down transistor M8C;
所述第三下拉晶体管M8B的漏极与所述第四下拉晶体管M8D的源极电连接;The drain of the third pull-down transistor M8B is electrically connected to the source of the fourth pull-down transistor M8D;
所述第一帧复位晶体管M15A的漏极与所述第二帧复位晶体管M15B的源极电连接。A drain of the first frame reset transistor M15A is electrically connected to a source of the second frame reset transistor M15B.
图16所示的驱动电路的至少一实施例与图15所示的驱动电路的至少一实施例的区别在于:The difference between at least one embodiment of the driving circuit shown in FIG. 16 and at least one embodiment of the driving circuit shown in FIG. 15 is that:
M1A的栅极和M1B的栅极都与I1电连接;The gate of M1A and the gate of M1B are both electrically connected to I1;
M2B的漏极与第二低电压线LVGL电连接,M8C的漏极与第二低电压线LVGL电连接,M8D的漏极与第二低电压线LVGL电连接。The drain of M2B is electrically connected to the second low voltage line LVGL, the drain of M8C is electrically connected to the second low voltage line LVGL, and the drain of M8D is electrically connected to the second low voltage line LVGL.
图17所示的驱动电路的至少一实施例与图16所示的驱动电路的至少一实施例的区别在于:The difference between at least one embodiment of the driving circuit shown in FIG. 17 and at least one embodiment of the driving circuit shown in FIG. 16 is that:
所述输入电路包括输入晶体管M1;The input circuit includes an input transistor M1;
所述输入晶体管M1的栅极和所述输入晶体管M1的源极都与所述输入端I0电连接,所述输入晶体管M1的漏极与所述第一节点PU电连接;The gate of the input transistor M1 and the source of the input transistor M1 are both electrically connected to the input terminal I0, and the drain of the input transistor M1 is electrically connected to the first node PU;
所述复位电路包括复位晶体管M2;The reset circuit includes a reset transistor M2;
所述复位晶体管M2的栅极与所述复位端R1电连接,所述复位晶体管M2的源极与所述第一节点PU电连接,所述复位晶体管M2的漏极与所述第一低电压线VGL电连接;The gate of the reset transistor M2 is electrically connected to the reset terminal R1, the source of the reset transistor M2 is electrically connected to the first node PU, and the drain of the reset transistor M2 is electrically connected to the first low voltage line VGL;
所述第一节点复位电路包括第一下拉晶体管M8A和第三下拉晶体管M8B;The first node reset circuit includes a first pull-down transistor M8A and a third pull-down transistor M8B;
所述第一下拉晶体管M8A的栅极与所述第一个第二节点PD1电连接,所述第一下拉晶体管M8A的源极与第一节点PU电连接,所述第一下拉晶体管M8A的漏极与所述第二低电压线LVGL电连接;The gate of the first pull-down transistor M8A is electrically connected to the first second node PD1, the source of the first pull-down transistor M8A is electrically connected to the first node PU, and the drain of the first pull-down transistor M8A is electrically connected to the second low voltage line LVGL;
所述第三下拉晶体管M8B的栅极与所述第二个第二节点PD2电连接,所述第三下拉晶体管M8B的源极与第一节点PU电连接,所述第三下拉晶体管M8B的漏极与所述第二低电压线LVGL电连接;The gate of the third pull-down transistor M8B is electrically connected to the second second node PD2, the source of the third pull-down transistor M8B is electrically connected to the first node PU, and the drain of the third pull-down transistor M8B is electrically connected to the second low voltage line LVGL;
所述帧复位电路包括帧复位晶体管M15;The frame reset circuit includes a frame reset transistor M15;
所述帧复位晶体管M15的栅极与所述帧复位线STV0电连接,所述帧复位晶体管M15的源极与所述第一节点PU电连接,所述帧复位晶体管M15的漏极与所述第二低电压线LVGL电连接。A gate of the frame reset transistor M15 is electrically connected to the frame reset line STV0 , a source of the frame reset transistor M15 is electrically connected to the first node PU, and a drain of the frame reset transistor M15 is electrically connected to the second low voltage line LVGL.
本公开实施例所述的显示基板包括基底和设置于所述基底上的上述的驱动电路。The display substrate described in the embodiment of the present disclosure includes a substrate and the above-mentioned driving circuit arranged on the substrate.
本公开至少一实施例所述的显示基板还包括设置于所述基底上的静电防护电路;The display substrate described in at least one embodiment of the present disclosure further includes an electrostatic protection circuit disposed on the substrate;
所述静电防护电路的第一端与驱动信号线电连接,所述静电防护电路的第二端通过短路线与公共电极电压端电连接,所述静电防护电路用于进行静电防护;The first end of the electrostatic protection circuit is electrically connected to the driving signal line, the second end of the electrostatic protection circuit is electrically connected to the common electrode voltage terminal through a short-circuit line, and the electrostatic protection circuit is used for electrostatic protection;
所述驱动信号线包括直流电压线、时钟信号线、控制电压线和帧复位线。The driving signal lines include a DC voltage line, a clock signal line, a control voltage line and a frame reset line.
在本公开至少一实施例中,驱动信号线为贯穿整个显示面板的金属线,且位于显示面 板边缘,在外界存在静电时极易受高压而导致烧毁,因此在信号线与shorting bar(短路线)之间设置静电防护电路,用于将瞬时电压分散,防止驱动信号线被烧毁。In at least one embodiment of the present disclosure, the driving signal line is a metal line that runs through the entire display panel and is located on the display surface. The edge of the board is very susceptible to high voltage and burnt when static electricity exists in the outside world. Therefore, an electrostatic protection circuit is set between the signal line and the shorting bar to disperse the instantaneous voltage and prevent the driving signal line from being burned.
本公开至少一实施例提供一种静电防护电路的具体结构,采用大小TFT(薄膜晶体管)混排设计,在保证静电释放性能的基础上,可以减少信号间的电流,减小串扰,同时因TFT的尺寸较小,从而布局空间较小。At least one embodiment of the present disclosure provides a specific structure of an electrostatic protection circuit, which adopts a mixed design of large and small TFTs (thin film transistors). On the basis of ensuring electrostatic release performance, it can reduce the current between signals and reduce crosstalk. At the same time, due to the small size of TFTs, the layout space is smaller.
可选的,所述静电防护电路包括第一防护晶体管、第二防护晶体管和第三防护晶体管;Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor and a third protection transistor;
所述第一防护晶体管的栅极和所述第一防护晶体管的第一极都与所述驱动信号线电连接,所述第一防护晶体管的第二极与所述第二防护晶体管的栅极电连接;The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;
所述第二防护晶体管的第一极与所述第一防护晶体管的栅极电连接,所述第二防护晶体管的的第二极与所述第三防护晶体管的栅极电连接;The first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor;
所述第三防护晶体管的栅极与所述第三防护晶体管的第一极都与所述短路线电连接,所述第三防护晶体管的第二极与所述第二防护晶体管的栅极电连接;The gate of the third protection transistor and the first electrode of the third protection transistor are both electrically connected to the short-circuit line, and the second electrode of the third protection transistor is electrically connected to the gate of the second protection transistor;
所述第一防护晶体管的沟道宽长比大于所述第二防护晶体管的沟道宽长比,所述第三防护晶体管的沟道宽长比大于所述防护第二晶体管的沟道宽长比。The channel width-to-length ratio of the first protection transistor is greater than that of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than that of the second protection transistor.
例如,所述第一防护晶体管的沟道宽长比和所述第三防护晶体管的沟道宽长比可以为3.5/8,第二防护晶体管的沟道宽长比可以为3.5/50,但不以此为限。For example, the channel width-to-length ratio of the first protection transistor and the channel width-to-length ratio of the third protection transistor may be 3.5/8, and the channel width-to-length ratio of the second protection transistor may be 3.5/50, but is not limited thereto.
在具体实施时,所述第一防护晶体管的沟道宽长比和所述第三防护晶体管的沟道宽长比可以大于或等于3.5/12而小于或等于3.5/6,所述第二防护晶体管的沟道宽长比可以大于或等于3.5/80而小于或等于3.5/30,但不以此为限。In a specific implementation, the channel width-to-length ratio of the first protection transistor and the channel width-to-length ratio of the third protection transistor may be greater than or equal to 3.5/12 and less than or equal to 3.5/6, and the channel width-to-length ratio of the second protection transistor may be greater than or equal to 3.5/80 and less than or equal to 3.5/30, but is not limited to this.
可选的,所述静电防护电路包括第一防护晶体管、第二防护晶体管、第三防护晶体管、第四防护晶体管和第五防护晶体管;Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor and a fifth protection transistor;
所述第一防护晶体管的栅极和所述第一防护晶体管的第一极都与所述驱动信号线电连接,所述第一防护晶体管的第二极与所述第二防护晶体管的栅极电连接;The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;
所述第二防护晶体管的第一极与所述第一防护晶体管的栅极电连接,所述第二防护晶体管的第二极与所述第三防护晶体管的栅极电连接;The first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor;
所述第三防护晶体管的第一极与所述第二防护晶体管的栅极电连接,所述第三防护晶体管的第二极与所述第四防护晶体管的栅极电连接;A first electrode of the third protection transistor is electrically connected to a gate of the second protection transistor, and a second electrode of the third protection transistor is electrically connected to a gate of the fourth protection transistor;
所述第四防护晶体管的第一极与所述第三防护晶体管的栅极电连接,所述第四防护晶体管的第二极与所述第五防护晶体管的栅极电连接;A first electrode of the fourth protection transistor is electrically connected to a gate of the third protection transistor, and a second electrode of the fourth protection transistor is electrically connected to a gate of the fifth protection transistor;
所述第五防护晶体管的栅极与所述第五防护晶体管的第一极都与所述短路线电连接,所述第五防护晶体管的第二极与所述第四防护晶体管的栅极电连接;The gate of the fifth protection transistor and the first electrode of the fifth protection transistor are both electrically connected to the short-circuit line, and the second electrode of the fifth protection transistor is electrically connected to the gate of the fourth protection transistor;
所述第一防护晶体管的沟道宽长比大于所述第二防护晶体管的沟道宽长比,所述第一防护晶体管的沟道宽长比大于所述第四防护晶体管的沟道宽长比;The channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;
所述第三防护晶体管的沟道宽长比大于所述第二防护晶体管的沟道宽长比,所述第三防护晶体管的沟道宽长比大于所述第四防护晶体管的沟道宽长比;The channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;
所述第五防护晶体管的沟道宽长比大于所述第二防护晶体管的沟道宽长比,所述第五防护晶体管的沟道宽长比大于所述第四防护晶体管的沟道宽长比。 The channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor.
例如,所述第一防护晶体管的沟道宽长比、所述第三防护晶体管的沟道宽长比和所述第五防护晶体管的沟道宽长比可以为3.5/8,第二防护晶体管的沟道宽长比和第四防护晶体管的沟道宽长比可以为3.5/50,但不以此为限。For example, the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor can be 3.5/8, and the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor can be 3.5/50, but are not limited to this.
在具体实施时,所述第一防护晶体管的沟道宽长比、所述第三防护晶体管的沟道宽长比和所述第五防护晶体管的沟道宽长比可以大于或等于3.5/12而小于或等于3.5/6,所述第二防护晶体管的沟道宽长比和第四防护晶体管的沟道宽长比可以大于或等于3.5/80而小于或等于3.5/30,但不以此为限。In a specific implementation, the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor may be greater than or equal to 3.5/12 and less than or equal to 3.5/6, and the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor may be greater than or equal to 3.5/80 and less than or equal to 3.5/30, but is not limited to this.
如图18所示,所述静电防护电路的至少一实施例可以包括第一防护晶体管T1、第二防护晶体管T2、第三防护晶体管T3、第四防护晶体管T4和第五防护晶体管T5;As shown in FIG. 18 , at least one embodiment of the electrostatic protection circuit may include a first protection transistor T1 , a second protection transistor T2 , a third protection transistor T3 , a fourth protection transistor T4 , and a fifth protection transistor T5 ;
所述第一防护晶体管T1的栅极和所述第一防护晶体管T1的源极都与驱动信号线QX电连接,所述第一防护晶体管T1的漏极与所述第二防护晶体管T2的栅极电连接;The gate of the first protection transistor T1 and the source of the first protection transistor T1 are both electrically connected to the driving signal line QX, and the drain of the first protection transistor T1 is electrically connected to the gate of the second protection transistor T2;
所述第二防护晶体管T2的源极与所述第一防护晶体管T1的栅极电连接,所述第二防护晶体管T2的漏极与所述第三防护晶体管T3的栅极电连接;The source of the second protection transistor T2 is electrically connected to the gate of the first protection transistor T1, and the drain of the second protection transistor T2 is electrically connected to the gate of the third protection transistor T3;
所述第三防护晶体管T3的源极与所述第二防护晶体管T2的栅极电连接,所述第三防护晶体管T3的漏极与所述第四防护晶体管T4的栅极电连接;The source of the third protection transistor T3 is electrically connected to the gate of the second protection transistor T2, and the drain of the third protection transistor T3 is electrically connected to the gate of the fourth protection transistor T4;
所述第四防护晶体管T4的源极与所述第三防护晶体管T3的栅极电连接,所述第四防护晶体管T4的漏极与所述第五防护晶体管T5的栅极电连接;The source of the fourth protection transistor T4 is electrically connected to the gate of the third protection transistor T3, and the drain of the fourth protection transistor T4 is electrically connected to the gate of the fifth protection transistor T5;
所述第五防护晶体管T5的栅极与所述第五防护晶体管T5的源极都与所述短路线SR电连接,所述第五防护晶体管T5的漏极与所述第四防护晶体管T4的栅极电连接;T5的栅极与公共电极电压端CM电连接;The gate of the fifth protection transistor T5 and the source of the fifth protection transistor T5 are both electrically connected to the short-circuit line SR, the drain of the fifth protection transistor T5 is electrically connected to the gate of the fourth protection transistor T4; the gate of T5 is electrically connected to the common electrode voltage terminal CM;
所述第一防护晶体管T1的沟道宽长比大于所述第二防护晶体管T2的沟道宽长比,所述第一防护晶体管T1的沟道宽长比大于所述第四防护晶体管T4的沟道宽长比;The channel width-to-length ratio of the first protection transistor T1 is greater than the channel width-to-length ratio of the second protection transistor T2, and the channel width-to-length ratio of the first protection transistor T1 is greater than the channel width-to-length ratio of the fourth protection transistor T4;
所述第三防护晶体管T3的沟道宽长比大于所述第二防护晶体管T2的沟道宽长比,所述第三防护晶体管T3的沟道宽长比大于所述第四防护晶体管T4的沟道宽长比;The channel width-to-length ratio of the third protection transistor T3 is greater than the channel width-to-length ratio of the second protection transistor T2, and the channel width-to-length ratio of the third protection transistor T3 is greater than the channel width-to-length ratio of the fourth protection transistor T4;
所述第五防护晶体管T5的沟道宽长比大于所述第二防护晶体管T2的沟道宽长比,所述第五防护晶体管T5的沟道宽长比大于所述第四防护晶体管T4的沟道宽长比。The channel width-to-length ratio of the fifth protection transistor T5 is greater than the channel width-to-length ratio of the second protection transistor T2 , and the channel width-to-length ratio of the fifth protection transistor T5 is greater than the channel width-to-length ratio of the fourth protection transistor T4 .
在图18所示的至少一实施例中,所述第一防护晶体管的沟道宽长比、所述第三防护晶体管的沟道宽长比和所述第五防护晶体管的沟道宽长比可以大于或等于3.5/12而小于或等于3.5/6,所述第二防护晶体管的沟道宽长比和第四防护晶体管的沟道宽长比可以大于或等于3.5/80而小于或等于3.5/30。In at least one embodiment shown in FIG. 18 , the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor may be greater than or equal to 3.5/12 and less than or equal to 3.5/6, and the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor may be greater than or equal to 3.5/80 and less than or equal to 3.5/30.
图19是静电防护电路的至少一实施例的布局图。FIG. 19 is a layout diagram of at least one embodiment of an electrostatic protection circuit.
在图19中,标号为CLKA的为第一时钟信号线,标号为CLKB的为第二时钟信号线,标号为CLKC的为第三时钟信号线,标号为CLKD的为第四时钟信号线;标号为STV的为起始电压线,标号为VDDO的为第一控制电压线,标号为VDDE的为第二控制电压线,标号为STV0的为帧复位线,标号为LVGL的为第二低电压线,标号为VGL的为第一低电压线;In FIG19 , CLKA is a first clock signal line, CLKB is a second clock signal line, CLKC is a third clock signal line, and CLKD is a fourth clock signal line; STV is a start voltage line, VDDO is a first control voltage line, VDDE is a second control voltage line, STV0 is a frame reset line, LVGL is a second low voltage line, and VGL is a first low voltage line;
标号为SR的为短路线; The one marked SR is a short route;
标号为E1的为第一静电防护电路,标号为E2的为第二静电防护电路,标号为E3的为第三静电防护电路,标号为E4的为第四静电防护电路,标号为E5的为第五静电防护电路,标号为E6的为第六静电防护电路,标号为E7的为第七静电防护电路,标号为E8的为第八静电防护电路,标号为E9的为第九静电防护电路,标号为E10的为第十静电防护电路。The one labeled E1 is the first electrostatic protection circuit, the one labeled E2 is the second electrostatic protection circuit, the one labeled E3 is the third electrostatic protection circuit, the one labeled E4 is the fourth electrostatic protection circuit, the one labeled E5 is the fifth electrostatic protection circuit, the one labeled E6 is the sixth electrostatic protection circuit, the one labeled E7 is the seventh electrostatic protection circuit, the one labeled E8 is the eighth electrostatic protection circuit, the one labeled E9 is the ninth electrostatic protection circuit, and the one labeled E10 is the tenth electrostatic protection circuit.
在图19中,标号为T1的为E5中的第一防护晶体管,标号为T2的为E5中的第二防护晶体管,标号为T3的为E5中的第三防护晶体管,标号为T4的为E5中的第四防护晶体管,标号为T5的为E5中的第五防护晶体管。In Figure 19, the first protection transistor in E5 is labeled T1, the second protection transistor in E5 is labeled T2, the third protection transistor in E5 is labeled T3, the fourth protection transistor in E5 is labeled T4, and the fifth protection transistor in E5 is labeled T5.
如图19所示,M2和M4沿着水平方向并排设置,M1、M3和M5沿着水平方向并排设置。As shown in FIG. 19 , M2 and M4 are arranged side by side in the horizontal direction, and M1 , M3 and M5 are arranged side by side in the horizontal direction.
在图19中,标号为CM的为公共电极电压端。In FIG. 19 , the terminal labeled CM is a common electrode voltage terminal.
如图20所示,所述静电防护电路的至少一实施例可以包括第一防护晶体管T1和第二防护晶体管T2;As shown in FIG. 20 , at least one embodiment of the electrostatic protection circuit may include a first protection transistor T1 and a second protection transistor T2 ;
T1的栅极和T1的源极都与驱动信号线QX电连接,T1的漏极与T2的栅极电连接;The gate of T1 and the source of T1 are both electrically connected to the driving signal line QX, and the drain of T1 is electrically connected to the gate of T2;
T2的源极与T1的栅极电连接,T1的栅极与公共电极电压端CM电连接。The source of T2 is electrically connected to the gate of T1 , and the gate of T1 is electrically connected to the common electrode voltage terminal CM.
T1的沟道宽长比和T2的沟道宽长比可以为3.5/180。The channel width-to-length ratio of T1 and the channel width-to-length ratio of T2 may be 3.5/180.
图21是静电防护电路的至少一实施例的布局图。FIG. 21 is a layout diagram of at least one embodiment of an electrostatic protection circuit.
在图21中,标号为CLKA的为第一时钟信号线,标号为CLKB的为第二时钟信号线,标号为CLKC的为第三时钟信号线,标号为CLKD的为第四时钟信号线;标号为STV的为起始电压线,标号为VDDO的为第一控制电压线,标号为VDDE的为第二控制电压线,标号为STV0的为帧复位线,标号为LVGL的为第二低电压线,标号为VGL的为第一低电压线;In FIG21 , CLKA is a first clock signal line, CLKB is a second clock signal line, CLKC is a third clock signal line, and CLKD is a fourth clock signal line; STV is a start voltage line, VDDO is a first control voltage line, VDDE is a second control voltage line, STV0 is a frame reset line, LVGL is a second low voltage line, and VGL is a first low voltage line;
标号为SR的为短路线;The one marked SR is a short route;
标号为E1的为第一静电防护电路,标号为E2的为第二静电防护电路,标号为E3的为第三静电防护电路,标号为E4的为第四静电防护电路,标号为E5的为第五静电防护电路,标号为E6的为第六静电防护电路,标号为E7的为第七静电防护电路,标号为E8的为第八静电防护电路,标号为E9的为第九静电防护电路,标号为E10的为第十静电防护电路。The one labeled E1 is the first electrostatic protection circuit, the one labeled E2 is the second electrostatic protection circuit, the one labeled E3 is the third electrostatic protection circuit, the one labeled E4 is the fourth electrostatic protection circuit, the one labeled E5 is the fifth electrostatic protection circuit, the one labeled E6 is the sixth electrostatic protection circuit, the one labeled E7 is the seventh electrostatic protection circuit, the one labeled E8 is the eighth electrostatic protection circuit, the one labeled E9 is the ninth electrostatic protection circuit, and the one labeled E10 is the tenth electrostatic protection circuit.
在图21中,标号为T1的为E5中的第一防护晶体管,标号为T2的为E5中的第二防护晶体管;In FIG21 , the first protection transistor in E5 is labeled T1, and the second protection transistor in E5 is labeled T2;
在图21中,标号为CM的为公共电极电压端。In FIG21 , the terminal labeled CM is a common electrode voltage terminal.
本公开实施例所述的显示装置包括上述的显示基板。The display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.
以上所述是本公开的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本公开所述原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本公开的保护范围。 The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.
Claims (29)
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CN107134258A (en) * | 2017-06-26 | 2017-09-05 | 京东方科技集团股份有限公司 | OLED compensation circuit and preparation method thereof, OLED compensation device and display device |
CN107578741A (en) * | 2017-09-28 | 2018-01-12 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
CN112838109A (en) * | 2020-08-28 | 2021-05-25 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof, and display device |
CN113920924A (en) * | 2021-10-19 | 2022-01-11 | 京东方科技集团股份有限公司 | Display substrate, driving method thereof and display device |
CN114038387A (en) * | 2021-12-07 | 2022-02-11 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
CN114822395A (en) * | 2022-05-07 | 2022-07-29 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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CN107134258A (en) * | 2017-06-26 | 2017-09-05 | 京东方科技集团股份有限公司 | OLED compensation circuit and preparation method thereof, OLED compensation device and display device |
CN107578741A (en) * | 2017-09-28 | 2018-01-12 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
CN112838109A (en) * | 2020-08-28 | 2021-05-25 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof, and display device |
CN113920924A (en) * | 2021-10-19 | 2022-01-11 | 京东方科技集团股份有限公司 | Display substrate, driving method thereof and display device |
CN114038387A (en) * | 2021-12-07 | 2022-02-11 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
CN114822395A (en) * | 2022-05-07 | 2022-07-29 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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