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WO2025046333A1 - Integrated circuit package and method of forming same - Google Patents

Integrated circuit package and method of forming same Download PDF

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Publication number
WO2025046333A1
WO2025046333A1 PCT/IB2024/056965 IB2024056965W WO2025046333A1 WO 2025046333 A1 WO2025046333 A1 WO 2025046333A1 IB 2024056965 W IB2024056965 W IB 2024056965W WO 2025046333 A1 WO2025046333 A1 WO 2025046333A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
package
major surface
voltage line
disposed
Prior art date
Application number
PCT/IB2024/056965
Other languages
French (fr)
Inventor
James R. Wasson
Mark E. Henschel
Songhua Shi
Christine M. DELEON
Jeff M. Wheeler
Matthew P. Hanly
Original Assignee
Medtronic, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Medtronic, Inc. filed Critical Medtronic, Inc.
Publication of WO2025046333A1 publication Critical patent/WO2025046333A1/en

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Classifications

    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/18—Applying electric currents by contact electrodes
    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/3605—Implantable neurostimulators for stimulating central or peripheral nerve system
    • A61N1/36125—Details of circuitry or electric components
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/18—Applying electric currents by contact electrodes
    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/372—Arrangements in connection with the implantation of stimulators
    • A61N1/375—Constructional arrangements, e.g. casings
    • A61N1/3758—Packaging of the components within the casing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads

Definitions

  • This disclosure generally relates to an integrated circuit package and, more particularly, to an integrated circuit package that includes a substrate contact electrically connected to a substrate of the package.
  • IMDs implantable medical devices
  • electronic circuitry e.g., for providing electrical stimulation of body tissue and/or monitoring a physiologic condition.
  • IMDs may deliver electrical therapy energy in the form of shocking energy and stimulating pulses to selected body tissue.
  • IMDs typically include output circuitry for generating the electrical energy under prescribed conditions and at least one lead bearing a stimulation electrode on the IMD or a lead connected to the IMD.
  • the stimulation electrode can be utilized to deliver the electrical energy to the selected tissue.
  • cardiac pacemakers and implantable cardioverter-defibrillators have been developed for maintaining a desired heart rate during episodes of bradycardia or for applying cardioversion or defibrillation therapies to the heart upon detection of serious arrhythmias.
  • Other nerve, brain, muscle, and organ tissue stimulating medical devices are also known for treating a variety of conditions.
  • IMDs including ICDs and implantable pulse generators (IPGs) typically include a metallic housing that is hermetically sealed and, therefore, is impervious to body fluids. Such devices also possess telemetry capabilities for communicating with external devices.
  • IMDs have evolved from relatively bulky devices to complex miniaturized devices that exhibit increasing functionality. For example, numerous improvements have been made in cardioversion/defibrillation leads and electrodes that have enabled the cardioversion/defibrillation energy to be precisely delivered to selected one or more portions of upper and lower heart chambers, thereby dramatically reducing the delivered shock energy required to cardiovert or defibrillate the heart chamber.
  • High voltage output circuitry has also been improved to provide monophasic, biphasic, or multi-phase cardioversion/defibrillation shock or pulse waveforms, sometimes with particular combinations of cardioversion/defibrillation electrodes, which are efficacious in lowering the required shock energy to cardiovert or defibrillate the heart.
  • IMDs The miniaturization of IMDs is driving size and cost reduction of all IMD components, including the electronic circuitry components, where it is desirable to increase the density and reduce the size of such components so that the overall circuitry can be more compact.
  • the electronic circuits of these IMDs are formed as integrated circuits to fit within a minimal space.
  • the present disclosure provides various embodiments of an integrated circuit package and a method of making such package.
  • the package can include a substrate contact that is configured to electrically connect a substrate of the package to one or more voltage lines.
  • Each voltage line can be a conductor, a voltage source, or a device.
  • the substrate contact can electrically connect the substrate to the largest positive or negative voltage of the package.
  • the substrate can be a part of an interposer of the package or the primary substrate for the package.
  • the substrate contact can be an Ohmic substrate contact or a Schottky substrate contact.
  • An integrated circuit package that includes a semiconductor substrate having a first major surface and a second major surface, a voltage line, and a substrate contact configured to electrically connect the substrate to the voltage line.
  • Clause 2 The package of Clause 1, further including a conductive via disposed into or through the substrate between the first major surface and the second major surface of the substrate.
  • Clause 3 The package of Clause 2, where the conductive via includes an opening that extends into or through the substrate, oxide material disposed within the opening on at least a portion of a sidewall of the opening, and conductive material disposed within the opening such that the oxide material is disposed between the conductive material and the at least a portion of the sidewall.
  • Clause 4 The package of any one of Clauses 2-3, where the semiconductor substrate, the conductive via, and the substrate contact define an interposer.
  • Clause 5 The package of any one of Clauses 2-4, where a portion of the substrate adjacent to the conductive via includes a depletion region, and where the substrate contact is configured to direct charge particles from the depletion region to the voltage line.
  • Clause 6 The package of any one of Clauses 2-5, further including a conductor electrically connected to the conductive via and the substrate contact.
  • Clause 7 The package of any one of Clauses 2-6, where the voltage line is electrically connected to the conductive via.
  • Clause 8 The package of any one of Clauses 1-7, where the substrate contact includes an Ohmic substrate contact.
  • Clause 9 The package of any one of Clauses 1-7, where the substrate contact includes a Schottky substrate contact.
  • Clause 10 The package of any one of Clauses 1-9, where the voltage line exhibits a largest absolute voltage of the integrated circuit package.
  • Clause 11 The package of any one of Clauses 1-10, further including an electronic device coupled to the substrate by a device interface.
  • Clause 12 The package of any one of Clauses 1-11, where the substrate includes silicon.
  • Clause 13 The package of any one of Clauses 1-12, where the substrate contact is disposed on either the first or second major surfaces of the substrate.
  • Clause 14 The package of any one of Clauses 1-12, where the substrate contact is disposed at least partially within the substrate.
  • Clause 15 A method of forming an integrated circuit package, including disposing a substrate contact on or at least partially within a semiconductor substrate, where the substrate includes a first major surface and second major surface; and electrically connecting the substrate to a voltage line of the package utilizing a substrate contact.
  • Clause 16 The method of Clause 15, further including disposing a conductive via into or through a semiconductor substrate between the first major surface and the second major surface of the substrate.
  • Clause 17 The method of Clause 16, further including disposing a conductive region or component adjacent to the second major surface of the substrate and electrically connecting the conductive region or component to the conductive via.
  • Clause 18 The method of any one of Clauses 16-17, where disposing the conductive via disposing an opening into or through the substrate, disposing an oxide material within the opening on at least a portion of a sidewall of the opening, and disposing conductive material within the opening such that the oxide material is disposed between the conductive material and the at least a portion of the sidewall.
  • Clause 19 The method of any one of Clauses 16-18, where the semiconductor substrate, the conductive via, and the substrate contact define an interposer.
  • Clause 20 The method of any one of Clauses 16-19, where a portion of the substrate adjacent to the conductive via includes a depletion region, where electrically connecting the substrate to the voltage line includes directing charge particles from the depletion region to the voltage line.
  • Clause 21 The method of any one of Clauses 16-20, where electrically connecting the substrate to the voltage line includes electrically connecting the substrate contact to the conductive via utilizing a conductor, and electrically connecting the voltage line to the conductive via.
  • Clause 22 The method of any one of Clauses 15-21, further including disposing a device interface on or in the first major surface of the substrate, and coupling an electronic device to the substrate at the device interface.
  • Clause 23 The method of Clause 22, where the device interface includes a cavity, where disposing the device interface includes disposing the cavity in the first major surface of the substrate.
  • Clause 24 The method of any one of Clauses 15-23, where the substrate includes silicon.
  • Clause 25 The method of any one of Clauses 15-24, where the substrate contact includes an Ohmic substrate contact.
  • Clause 26 The method of any one of Clauses 15-24, where the substrate contact includes a Schottky substrate contact.
  • Clause 27 The method of any one of Clauses 15-26, where the voltage line exhibits a largest absolute voltage of the integrated circuit package.
  • Clause 28 The method of any one of Clause 15-27, where disposing the substrate contact includes disposing the substrate contact on either the first or second major surfaces of the substrate.
  • Clause 29 The method of any one of Clauses 15-27, where disposing the substrate contact includes disposing the substrate contact at least partially within the substrate.
  • An implantable medical device including a housing and an integrated circuit package disposed within the housing, where the package a semiconductor substrate including a first major surface and a second major surface, a voltage line, and a substrate contact configured to electrically connect the substrate to the voltage line.
  • Clause 31 The device of Clause 30, further including a conductive via disposed into or through the substrate between the first major surface and the second major surface of the substrate;
  • Clause 32 The device of Clause 31, where the semiconductor substrate, the conductive via, and the substrate contact define an interposer.
  • Clause 33 The device of any one of Clauses 31-32, further including a conductor electrically connected to the conductive via and the substrate contact.
  • Clause 34 The device of any one of Clauses 31-33, where the voltage line is electrically connected to the conductive via.
  • Clause 35 The device of any one of Clauses 30-34, further including an electronic device coupled to the substrate by a device interface.
  • Clause 36 The device of any one of Clauses 30-35, where the voltage line is electrically connected to the housing.
  • Clause 37 The device of any one of Clauses 30-36, where the substrate contact includes an Ohmic substrate contact.
  • Clause 38 The device of any one of Clauses 30-36, where the substrate contact includes a Schottky substrate contact.
  • Clause 39 The device of any one of Clauses 30-38, where the voltage line includes a largest absolute voltage of the integrated circuit package.
  • Clause 40 The device of any one of Clauses 30-39, where the substrate includes silicon.
  • Clause 41 The device of any one of Clauses 30-40, where the substrate contact is disposed on either the first or second major surfaces of the substrate.
  • Clause 42 The device of any one of Clauses 30-40, where the substrate contact is disposed at least partially within the substrate.
  • Clause 43 A method including, in a semiconductor substrate having a first major surface and a second major surface, discharging the substrate with a voltage line electrically connected to the substrate with a substrate contact.
  • Clause 44 The method of Clause 43, where discharging the substrate includes directing charge particles from a depletion region of the substrate to the voltage line.
  • Clause 45 The method of any one of Clauses 43-44, where the substrate forms part of an integrated circuit package, where the method further includes reducing noise in a circuit or component of the package.
  • Clause 46 The method of any one of Clauses 43-45, further including a conductive via disposed in or through the substrate between the first major surface and the second major surface of the substrate.
  • Clause 47 The method of Clause 46, where the conductive via includes an opening that extends into or through the substrate, oxide material disposed within the opening on at least a portion of a sidewall of the opening, and conductive material disposed within the opening such that the oxide material is disposed between the conductive material and the at least a portion of the sidewall.
  • Clause 48 The method of any one of Clauses 46-47, where the semiconductor substrate, the conductive via, and the substrate contact define an interposer.
  • Clause 49 The method of any one of Clauses 46-48, further including a conductor electrically connected to the conductive via and the substrate contact.
  • Clause 50 The method of any one of Clauses 46-49, where the voltage line is electrically connected to the conductive via.
  • Clause 51 The method of any one of Clauses 43-50, where the substrate contact includes an Ohmic substrate contact.
  • Clause 52 The method of any one of Clauses 43-50, where the substrate contact includes a Schottky substrate contact.
  • Clause 53 The method of any one of Clauses 43-52, where the voltage line exhibits the largest absolute voltage of the integrated circuit package.
  • Clause 54 The method of any one of Clauses 43-53, further including an electronic device coupled to the substrate by a device interface.
  • phrases “at least one of’ and “comprises at least one of’ followed by a list refers to any one of the items in the list and any combination of two or more items in the list.
  • the term “about” refers to that variation in the measured quantity as would be expected by the skilled artisan making the measurement and exercising a level of care commensurate with the objective of the measurement and the precision of the measuring equipment used.
  • “up to” a number includes the number (e.g., 50).
  • FIG. 1 is a schematic cross-section view of one embodiment of an integrated circuit package.
  • FIG. 2 is a schematic cross-section view of a portion of the integrated circuit package of FIG. 1.
  • FIG. 3 is a schematic cross-section view of another embodiment of an integrated circuit package.
  • FIG. 4 is a diagrammatic view of one embodiment of an implantable medical device that includes the integrated circuit package of FIG. 1.
  • FIG. 5 is a flowchart of one embodiment of a method of forming the integrated circuit package of FIG. 1.
  • the present disclosure provides various embodiments of an integrated circuit package and a method of making such package.
  • the package can include a substrate contact that is configured to electrically connect a substrate of the package to one or more voltage lines.
  • Each voltage line can be a conductor, a voltage source, or a device.
  • the substrate contact can electrically connect the substrate to the largest positive or negative voltage of the package.
  • the substrate can be a part of an interposer of the package or the primary substrate for the package.
  • the substrate contact can be an Ohmic substrate contact or a Schottky substrate contact.
  • IMDs implantable medical devices
  • Such techniques can be used in high performance computing or high bandwidth memory chips, where integrated circuits are stacked vertically and disposed adjacent to CPU cores. These configurations can increase switching speeds and decrease power consumption because of the close proximity between the components.
  • Digital circuitry can benefit from this volumetric efficiency; however, analog circuitry may suffer from use of these techniques as the close proximity between components and leakage current that can be injected into silicon interposers or packaging material can increase noise in signals of one or more components of the circuitry.
  • a substrate of an interposer or device layer of the package can be connected to one or more voltage lines in the package or external to the package using a substrate contact that is disposed either on or at least partially within the substrate.
  • This electrical connection between the substrate and one or more of the voltage lines can drain stray charges from the substrate and prevent them from interfering with signals of highly sensitive analog circuitry of the package.
  • this substrate contact can form either an Ohmic or Schottky substrate contact with the substrate. Further, such substrate contact can electrically connect the substrate to either the most positive or most negative voltage in the circuitry, thereby providing an electrical path for stray charges that may reside in the substrate.
  • the substrate can be electrically connected to a voltage line that is electrically connected to ground.
  • FIGS. 1-2 are schematic cross-section views of one embodiment of an integrated circuit package 10.
  • the package 10 includes a substrate 12 having a first major surface 14 and a second major surface 16, a voltage line 18, and a substrate contact 20 configured to electrically connect the substrate to the voltage line.
  • the package 10 can further include one or more conductive vias 22, and one or more electronic devices 36 coupled to the substrate 12 by a device interface 38 as is further described herein.
  • the package 10 can include any suitable circuitry and components.
  • the substrate 12, the conductive via(s) 22, and the substrate contact 20 can define an interposer of the package 10.
  • the substrate 12, the conductive via(s) 22, and the substrate contact 20 can define a device layer of the package 10.
  • the package 10 can include any suitable substrate 12.
  • the substrate 12 can include any suitable material, e.g., metallic, polymeric, or non-metallic inorganic materials and combinations thereof.
  • the substrate 12 can be a nonconductive or dielectric substrate that provides electrical isolation between various conductors, vias, dies, etc.
  • the substrate 12 can be a semiconductor substate that includes one or more semiconductor materials, e.g., silicon. In one or more embodiments, such semiconductor substrate 12 can be doped using any suitable dopant.
  • FIG. 1 depicts the substrate 12 as a monolithic (i.e., single) layer.
  • the substrate 12 can include any suitable number of layers, where the layers can be formed from the same or different materials. Further, the substrate 12 can have any suitable dimensions. For example, the substrate 12 can have any suitable thickness as measured in a direction orthogonal to the first major surface 14 of the substrate. Further, the substrate 12 can be formed using any suitable technique.
  • the voltage line 18 can include any suitable conductor or voltage source that exhibits any suitable voltage. Further, the voltage line 18 can be an integrated circuit or packaged device that is disposed on or in the substate 12, a part of the package 10, or electrically connected to one or more components or devices of the package. In one or more embodiments, the voltage line 18 can be electrically connected to one or more conductive vias 22. As shown in FIGS. 1-2, a negative terminal 26 of the voltage line is electrically connected to a first conductive via 22-1 and a positive terminal 24 of the voltage line 18 is electrically connected to a second conductive via 22-2 (the first conductive via and the second conductive via are collectively referred to as conductive vias 22). The voltage line 18 can exhibit any suitable positive or negative voltage.
  • the voltage line 18 can be connected to ground using any suitable technique.
  • the voltage line 18 can be electrically connected to ground utilizing one or more conductive vias 22.
  • the voltage line 18 can exhibit a largest absolute voltage of the package 10, i.e., positive or negative voltage.
  • the package 10 further includes one or more substrate contacts 20. While the package 10 is illustrated as including one substrate contact 20, the package can include any suitable number of substrate contacts.
  • a second substate contact 54 can be disposed on the second major surface 16 of the substrate 12 and can be configured to electrically connect the substrate to the voltage line 18, e.g., via a conductor 56 that is electrically connected to the contact and the second conductive via 22-2, which is also electrically connected to the voltage line.
  • the substrate contact 20 can take any suitable shape, have any suitable dimensions, and include any suitable electrically conductive material. Further, the substrate contact 20 can be disposed in any suitable location relative to the substrate 12 using any suitable technique such that the contact is electrically connected to the substrate. In one or more embodiments, the substrate contact 20 is disposed on either the first major surface 14 or the second major surface 16. In one or more embodiments, the substrate contact 20 can be disposed at least partially within the substrate 12. In one or more embodiments, the substrate contact 20 can be disposed entirely within the substrate 12.
  • the substrate contact 20 can be configured to electrically connect the substrate 12 to the voltage line 18 using any suitable technique.
  • the substrate contact 20 is electrically connected to the first via 22-1 by a conductor 28.
  • Such conductor 28 can take any suitable shape and have any suitable dimensions.
  • the conductor 28 can include any suitable conductive material.
  • the conductor 28 can be a portion of a patterned conductive layer that is disposed adjacent to the first major surface 14 of the substrate 12.
  • the conductor 28 can be electrically isolated from the first major surface 14 of the substrate 12 by a nonconductive material 30 disposed between the substrate and the conductor.
  • the nonconductive material 30 can include any suitable material, e.g., polyimide, bismaleimide triazine, polybenzoxazole, photoresist, glass, quartz, sapphire, etc.
  • the nonconductive material 30 can include an electrically insulative material.
  • the nonconductive material 30 can include an oxide, e.g., silicon dioxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and other suitable metal or inorganic oxides.
  • the nonconductive material 30 can include a nitride, e.g., silicon nitride, silicon oxynitride, and other suitable metal or inorganic nitrides.
  • FIG. 3 is a schematic cross-section view of another embodiment of an integrated circuit package 100. All design considerations and possibilities described herein regarding integrated circuit package 10 of FIGS. 1-2 apply equally to integrated circuit package 100 of FIG. 3.
  • substrate contact 120 of package 100 is disposed within substrate 112.
  • the substrate contact 120 can be configured to electrically connect the substrate 112 to voltage line 118 using any suitable technique.
  • substrate contact 120 can be electrically connected to contact via 102 that is disposed at least partially within the substrate 112 and that extends between the substrate contact and a first major surface 114 of the substrate.
  • the contact via 102 can take any suitable shape and have any suitable dimensions. Further, the contact via 102 can include any suitable conductive material.
  • the contact via 102 can electrically connect the substrate contact 120 to a conductor 128 disposed adjacent to the first major surface 114 of the substrate 112 using any suitable technique.
  • the conductor 128 can electrically connect the substrate contact 120 and the contact via 102 to one or more conductive vias 122 using any suitable technique. As the substrate contact 120 and the voltage line 118 are each electrically connected to conductive via 122, the substrate contact electrically connects the substrate 112 to the voltage line.
  • the substrate contact 20 can include any suitable type of contact.
  • the substrate contact 20 can be an Ohmic substrate contact.
  • Ohmic substrate contact means a metal contact 20 that forms a non-rectifying electrical junction with the semiconductor substrate 12.
  • the substrate contact 20 can be a Schottky substrate contact.
  • Schottky substrate contact means a metal contact 20 that forms a rectifying electrical junction with the semiconductor substrate 12.
  • the substrate contact 20 can be electrically connected to the voltage line 18 using any suitable technique. As shown in FIG. 1, the substrate contact 20 is electrically connected to the voltage line 18 by the conductor 28 and the conductive via 22. In one or more embodiments, the substrate contact 20 can be electrically connected to the voltage line 18 directly by a conductor (not shown). Any suitable conductor or conductors can be utilized to directly connect the substrate contact 20 to the voltage line 18. In one or more embodiments, a patterned conductive layer can be disposed adjacent to the first major surface 14 of the substrate 12 upon which the substrate contact 20 is disposed, and the patterned conductive layer can electrically connect the contact directly to the voltage line 18.
  • the package 10 can also include the one or more conductive vias 22.
  • One or more of the conductive vias 22 can be disposed into or through the substrate 12 between the first major surface 14 and the second major surface 16 of the substrate.
  • the package 10 can include any suitable number of conductive vias 22.
  • Each conductive via 22 can include any suitable conductive material, can take any suitable shape, and can have any suitable dimensions. Further, each conductive via can be formed using any suitable technique.
  • the conductive vias 22 can electrically connect one or more conductive regions or components disposed adjacent to the first major surface 14 of the substrate 12 (e.g., the voltage line 18) with one or more conductive regions or components 32 disposed adjacent to the second major surface 16 of the substrate using any suitable technique.
  • any suitable conductive region or component 32 can be electrically connected by the conductive via 22 to one or more conductive regions or components disposed adjacent to the first major surface 14, e.g., at least one of a conductive pad, solder bump, ball grid array, landing pad, capacitor, resistor, passive integrated capacitor system, logic circuit, analog circuit, crystals, oscillator, accelerometer, and any suitable active or passive component, etc.
  • the conductive region or component 32 can include one or more solder bumps 34 as shown in FIG. 1.
  • Each conductive via 22 can include any suitable structure.
  • FIG. 2 which is a schematic cross-section view of a portion of the package 10 of FIG. 1 with the electronic component 36 and the device interface 38 removed for explanatory purposes
  • each via 22 includes an opening 40, oxide material 42 disposed within the opening on at least a portion of a sidewall 44 of the opening, and conductive material 46 disposed within the opening such that the oxide material is disposed between the conductive material and the at least a portion of the sidewall.
  • the oxide material is disposed over the entire sidewall 44 of the opening 40 such that the oxide material is disposed between the conductive material 46 and the sidewall.
  • the opening 40 extends into or through the substrate 12 and can be formed using any suitable technique, e.g., drilling, laser drilling, chemical etching, plasma etching, stamping, etc. Further, the oxide material 42 and conductive material 46 can be disposed in the opening using any suitable technique, e.g., vapor deposition, chemical vapor deposition, etc.
  • the oxide material 42 of the via 22 can allow charge particles (i.e., stray particles) 48 to leak from the conductive material 46 into the substrate 12 as current flows through the via.
  • charge particles 48 can form one or more depletion regions 50.
  • a width of a depletion region 50 as measured in a direction substantially parallel to the first major surface 14 of the substrate 12 can vary depending upon how much charge leaks into the substrate 12 through the oxide material 42.
  • the leaked charge particles 48 can produce noise variances in signals produced by integrated circuits or components of the package 10.
  • the one or more substrate contacts 20 can be configured to direct these charge particles 48 from the depletion regions 50 or other portions of the substrate 12 to the voltage line 18 such that they are at least substantially discharged from the substrate 12, thereby potentially reducing noise in one or more signals of the circuits or components of the package 10.
  • the substrate 12 can be discharged with the voltage line 18 that is electrically connected to the substrate 12 with the substrate contact 20.
  • Such discharging of the substrate 12 can include directing the charge particles 48 from the depletion regions 50 of the substrate to the voltage line 18.
  • the package 10 can include any suitable additional integrated circuits or components.
  • package 10 includes the electronic device 36 that is coupled to the substrate 12 by the device interface 38.
  • the package 10 can include any suitable number of devices 36 disposed in any suitable arrangement or array.
  • one or more electronic devices 36 can be disposed in a cavity 52 (serving as the device interface) of the substrate 12. Although depicted as including one device 36 per cavity 52, in one or more embodiments, two or more devices can be disposed within a single cavity. In one or more embodiments, one or more devices 36 can be disposed in the cavity 52 such that the device is completely within the cavity.
  • each device 36 can have a device height measured in a direction orthogonal to the first major surface 14 of the substrate 12 that is no greater than a height of the cavity 52 within which the device is disposed.
  • the device height of one or more devices 36 can be greater than the height of the cavity 52 within which the respective device is disposed.
  • the package 10 can include any suitable type of device 36.
  • the device 36 can include one or more high-voltage dies that can be utilized, e.g., in an implantable medical device (see, e.g., implantable medical device 200 of FIG. 4).
  • the term “high-voltage die” refers to an electronic component or device that is operable with a potential greater than about 50 V across any two electrical terminals or contacts of the component.
  • the package 10 can include one or more devices 36 that include low-voltage dies.
  • the one or more devices 36 can include one or more field effect transistors (FETs), metal oxide semiconductors (MOS), MOSFETs, insulated gate bipolar junction transistors (IGBT), thyristors, bipolar transistors, diodes, MOS -controlled thyristors, resistors, capacitors, etc.
  • FETs field effect transistors
  • MOS metal oxide semiconductors
  • IGBT insulated gate bipolar junction transistors
  • thyristors bipolar transistors
  • diodes MOS -controlled thyristors
  • resistors capacitors, etc.
  • two or more devices 36 can be arranged in a stacked relationship.
  • the package 10 can include any suitable device interface 38, e.g., a ball grid array, one or more conductive pads, a wire bond frame, etc. As shown in FIG. 1, the device interface 38 includes the cavity 52 that is disposed in the first major surface 14 of the substate 12.
  • the device interface 38 is configured to facilitate attachment of the electronic device 36 to any suitable additional components of the package or external to the package, e.g., an interposer, an interconnect region, a redistribution layer, one or more additional integrated circuits or components, etc., using any suitable technique.
  • FIG. 4 is a schematic plan view of one embodiment of an implantable medical device (IMD) 200.
  • the IMD 200 includes a housing 202 and electronic components 204 disposed within the housing.
  • the electronic components 204 can include any suitable electronic devices, e.g., at least one of a capacitor, resistor, passive integrated capacitor system, logic circuit, analog circuit, crystal, accelerometer, RF circuit, antenna, transformer, connector, etc.
  • the electronic components 204 include the integrated circuit package 10.
  • the integrated circuit package 10 can be electrically connected to other electronic components 204 using any suitable technique.
  • the voltage line 18 of the package 10 can be electrically connected to the housing 202 of the IMD 200 by one or more conductors 208 using any suitable technique.
  • the power source 206 can include any suitable power source or combination of power sources, e.g., one or more batteries, capacitors, inductive-coupled energy devices, photovoltaic devices, betavoltaic devices, alphavoltaic devices, and thermo-electric devices.
  • FIG. 5 is a flowchart of one embodiment of a method 300 of forming the integrated circuit package 10. Although described in reference to the integrated circuit package 10 of FIGS. 1-2, the method 300 can be utilized to form any suitable integrated circuit package. Further, the method 300 is illustrated as including one electronic device 36; however, the method can be utilized to form integrated circuit packages that include two or more devices.
  • the substrate contact 20 can be disposed on or at least partially within the substrate 12 using any suitable technique.
  • the substrate 12 can be electrically connected to the voltage line 18 at 304 via the substrate contract 20 using any suitable technique.
  • the substrate 12 can be electrically connected to the voltage line 18 by electrically connecting the substrate contact 20 to the conductive via 22 with the conductor 28, and electrically connecting the voltage line to the conductive via.
  • conductive via or vias Prior to electrically connecting the device contact 20 and the voltage line 18 to the conductive via 22, such conductive via or vias can be disposed through the substrate 12 between the first major surface 14 and the second major surface 16 at 306 using any suitable technique.
  • the opening 40 can be disposed into or through the substrate 12 using any suitable technique, e.g., by drilling, laser drilling, chemical etching, plasma etching, stamping, etc.
  • the oxide material 42 can be disposed within the opening on at least a portion of the sidewall 44 of the opening, and the conductive material 46 can be disposed within the opening such that the oxide material is disposed between the conductive material and the at least a portion of the sidewall using any suitable technique.
  • the conductive region or component 32 can optionally be disposed adjacent to the second major surface 16 of the substrate 12 and electrically connected to the conductive via 22 using any suitable technique.
  • the device interface 38 can optionally be disposed on or in the first major surface 14 of the substrate 12 at 310 using any suitable technique.
  • the device interface 38 includes or is included in the cavity 52
  • such cavity can be disposed in the first major surface 14 of the substrate 12 using any suitable technique, e.g., the same techniques described herein that are utilized to dispose the opening 40 of the via 22 in the substrate.
  • the electronic device 36 can optionally be coupled to the substrate 12 at the device interface 38 using any suitable technique.
  • the described techniques may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a computer-readable medium and executed by a hardware -based processing unit.
  • Computer-readable media may include computer-readable storage media, which corresponds to a tangible medium such as data storage media (e.g., RAM, ROM, EEPROM, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer).
  • processors such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry.
  • DSPs digital signal processors
  • ASICs application specific integrated circuits
  • FPGAs field programmable logic arrays
  • processors may refer to any of the foregoing structure or any other physical structure suitable for implementation of the described techniques. Also, the techniques could be fully implemented in one or more circuits or logic elements.

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Abstract

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a semiconductor substrate having a first major surface and a second major surface, a voltage line, and a substrate contact configured to electrically connect the substrate to the voltage line.

Description

INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME
[0001] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63/535,806, filed August 31, 2023, the entire content of which is incorporated herein by reference.
TECHNICAL FIELD
[0002] This disclosure generally relates to an integrated circuit package and, more particularly, to an integrated circuit package that includes a substrate contact electrically connected to a substrate of the package.
BACKGROUND
[0003] A wide variety of electronic assemblies such as those that are utilized with implantable medical devices (IMDs) employ electronic circuitry, e.g., for providing electrical stimulation of body tissue and/or monitoring a physiologic condition. Such IMDs may deliver electrical therapy energy in the form of shocking energy and stimulating pulses to selected body tissue. These IMDs typically include output circuitry for generating the electrical energy under prescribed conditions and at least one lead bearing a stimulation electrode on the IMD or a lead connected to the IMD. The stimulation electrode can be utilized to deliver the electrical energy to the selected tissue. For example, cardiac pacemakers and implantable cardioverter-defibrillators (ICDs) have been developed for maintaining a desired heart rate during episodes of bradycardia or for applying cardioversion or defibrillation therapies to the heart upon detection of serious arrhythmias. Other nerve, brain, muscle, and organ tissue stimulating medical devices are also known for treating a variety of conditions.
[0004] Currently available IMDs, including ICDs and implantable pulse generators (IPGs), typically include a metallic housing that is hermetically sealed and, therefore, is impervious to body fluids. Such devices also possess telemetry capabilities for communicating with external devices. Over the past several years, IMDs have evolved from relatively bulky devices to complex miniaturized devices that exhibit increasing functionality. For example, numerous improvements have been made in cardioversion/defibrillation leads and electrodes that have enabled the cardioversion/defibrillation energy to be precisely delivered to selected one or more portions of upper and lower heart chambers, thereby dramatically reducing the delivered shock energy required to cardiovert or defibrillate the heart chamber. High voltage output circuitry has also been improved to provide monophasic, biphasic, or multi-phase cardioversion/defibrillation shock or pulse waveforms, sometimes with particular combinations of cardioversion/defibrillation electrodes, which are efficacious in lowering the required shock energy to cardiovert or defibrillate the heart.
[0005] The miniaturization of IMDs is driving size and cost reduction of all IMD components, including the electronic circuitry components, where it is desirable to increase the density and reduce the size of such components so that the overall circuitry can be more compact. As the dimensions of IMDs decrease, the electronic circuits of these IMDs are formed as integrated circuits to fit within a minimal space. Furthermore, as the dimensions of the components are also decreased, it is desirable to improve the use of the dimensions within the IMD package.
SUMMARY
[0006] In general, the present disclosure provides various embodiments of an integrated circuit package and a method of making such package. The package can include a substrate contact that is configured to electrically connect a substrate of the package to one or more voltage lines. Each voltage line can be a conductor, a voltage source, or a device. In one or more embodiments, the substrate contact can electrically connect the substrate to the largest positive or negative voltage of the package. Further, the substrate can be a part of an interposer of the package or the primary substrate for the package. In one or more embodiments, the substrate contact can be an Ohmic substrate contact or a Schottky substrate contact.
[0007] This disclosure includes without limitation the following clauses:
[0008] Clause 1: An integrated circuit package that includes a semiconductor substrate having a first major surface and a second major surface, a voltage line, and a substrate contact configured to electrically connect the substrate to the voltage line.
[0009] Clause 2: The package of Clause 1, further including a conductive via disposed into or through the substrate between the first major surface and the second major surface of the substrate. [0010] Clause 3: The package of Clause 2, where the conductive via includes an opening that extends into or through the substrate, oxide material disposed within the opening on at least a portion of a sidewall of the opening, and conductive material disposed within the opening such that the oxide material is disposed between the conductive material and the at least a portion of the sidewall.
[0011] Clause 4: The package of any one of Clauses 2-3, where the semiconductor substrate, the conductive via, and the substrate contact define an interposer.
[0012] Clause 5: The package of any one of Clauses 2-4, where a portion of the substrate adjacent to the conductive via includes a depletion region, and where the substrate contact is configured to direct charge particles from the depletion region to the voltage line.
[0013] Clause 6: The package of any one of Clauses 2-5, further including a conductor electrically connected to the conductive via and the substrate contact.
[0014] Clause 7: The package of any one of Clauses 2-6, where the voltage line is electrically connected to the conductive via.
[0015] Clause 8: The package of any one of Clauses 1-7, where the substrate contact includes an Ohmic substrate contact.
[0016] Clause 9: The package of any one of Clauses 1-7, where the substrate contact includes a Schottky substrate contact.
[0017] Clause 10: The package of any one of Clauses 1-9, where the voltage line exhibits a largest absolute voltage of the integrated circuit package.
[0018] Clause 11: The package of any one of Clauses 1-10, further including an electronic device coupled to the substrate by a device interface.
[0019] Clause 12: The package of any one of Clauses 1-11, where the substrate includes silicon.
[0020] Clause 13: The package of any one of Clauses 1-12, where the substrate contact is disposed on either the first or second major surfaces of the substrate.
[0021] Clause 14: The package of any one of Clauses 1-12, where the substrate contact is disposed at least partially within the substrate.
[0022] Clause 15: A method of forming an integrated circuit package, including disposing a substrate contact on or at least partially within a semiconductor substrate, where the substrate includes a first major surface and second major surface; and electrically connecting the substrate to a voltage line of the package utilizing a substrate contact. [0023] Clause 16: The method of Clause 15, further including disposing a conductive via into or through a semiconductor substrate between the first major surface and the second major surface of the substrate.
[0024] Clause 17: The method of Clause 16, further including disposing a conductive region or component adjacent to the second major surface of the substrate and electrically connecting the conductive region or component to the conductive via.
[0025] Clause 18: The method of any one of Clauses 16-17, where disposing the conductive via disposing an opening into or through the substrate, disposing an oxide material within the opening on at least a portion of a sidewall of the opening, and disposing conductive material within the opening such that the oxide material is disposed between the conductive material and the at least a portion of the sidewall.
[0026] Clause 19: The method of any one of Clauses 16-18, where the semiconductor substrate, the conductive via, and the substrate contact define an interposer.
[0027] Clause 20: The method of any one of Clauses 16-19, where a portion of the substrate adjacent to the conductive via includes a depletion region, where electrically connecting the substrate to the voltage line includes directing charge particles from the depletion region to the voltage line.
[0028] Clause 21: The method of any one of Clauses 16-20, where electrically connecting the substrate to the voltage line includes electrically connecting the substrate contact to the conductive via utilizing a conductor, and electrically connecting the voltage line to the conductive via.
[0029] Clause 22: The method of any one of Clauses 15-21, further including disposing a device interface on or in the first major surface of the substrate, and coupling an electronic device to the substrate at the device interface.
[0030] Clause 23: The method of Clause 22, where the device interface includes a cavity, where disposing the device interface includes disposing the cavity in the first major surface of the substrate.
[0031] Clause 24: The method of any one of Clauses 15-23, where the substrate includes silicon.
[0032] Clause 25: The method of any one of Clauses 15-24, where the substrate contact includes an Ohmic substrate contact. [0033] Clause 26: The method of any one of Clauses 15-24, where the substrate contact includes a Schottky substrate contact.
[0034] Clause 27: The method of any one of Clauses 15-26, where the voltage line exhibits a largest absolute voltage of the integrated circuit package.
[0035] Clause 28: The method of any one of Clause 15-27, where disposing the substrate contact includes disposing the substrate contact on either the first or second major surfaces of the substrate.
[0036] Clause 29: The method of any one of Clauses 15-27, where disposing the substrate contact includes disposing the substrate contact at least partially within the substrate.
[0037] Clause 30: An implantable medical device including a housing and an integrated circuit package disposed within the housing, where the package a semiconductor substrate including a first major surface and a second major surface, a voltage line, and a substrate contact configured to electrically connect the substrate to the voltage line.
[0038] Clause 31: The device of Clause 30, further including a conductive via disposed into or through the substrate between the first major surface and the second major surface of the substrate;
[0039] Clause 32: The device of Clause 31, where the semiconductor substrate, the conductive via, and the substrate contact define an interposer.
[0040] Clause 33: The device of any one of Clauses 31-32, further including a conductor electrically connected to the conductive via and the substrate contact.
[0041] Clause 34: The device of any one of Clauses 31-33, where the voltage line is electrically connected to the conductive via.
[0042] Clause 35: The device of any one of Clauses 30-34, further including an electronic device coupled to the substrate by a device interface.
[0043] Clause 36: The device of any one of Clauses 30-35, where the voltage line is electrically connected to the housing.
[0044] Clause 37: The device of any one of Clauses 30-36, where the substrate contact includes an Ohmic substrate contact.
[0045] Clause 38: The device of any one of Clauses 30-36, where the substrate contact includes a Schottky substrate contact.
[0046] Clause 39: The device of any one of Clauses 30-38, where the voltage line includes a largest absolute voltage of the integrated circuit package. [0047] Clause 40: The device of any one of Clauses 30-39, where the substrate includes silicon.
[0048] Clause 41: The device of any one of Clauses 30-40, where the substrate contact is disposed on either the first or second major surfaces of the substrate.
[0049] Clause 42: The device of any one of Clauses 30-40, where the substrate contact is disposed at least partially within the substrate.
[0050] Clause 43: A method including, in a semiconductor substrate having a first major surface and a second major surface, discharging the substrate with a voltage line electrically connected to the substrate with a substrate contact.
[0051] Clause 44: The method of Clause 43, where discharging the substrate includes directing charge particles from a depletion region of the substrate to the voltage line. [0052] Clause 45: The method of any one of Clauses 43-44, where the substrate forms part of an integrated circuit package, where the method further includes reducing noise in a circuit or component of the package.
[0053] Clause 46: The method of any one of Clauses 43-45, further including a conductive via disposed in or through the substrate between the first major surface and the second major surface of the substrate.
[0054] Clause 47: The method of Clause 46, where the conductive via includes an opening that extends into or through the substrate, oxide material disposed within the opening on at least a portion of a sidewall of the opening, and conductive material disposed within the opening such that the oxide material is disposed between the conductive material and the at least a portion of the sidewall.
[0055] Clause 48: The method of any one of Clauses 46-47, where the semiconductor substrate, the conductive via, and the substrate contact define an interposer.
[0056] Clause 49: The method of any one of Clauses 46-48, further including a conductor electrically connected to the conductive via and the substrate contact.
[0057] Clause 50: The method of any one of Clauses 46-49, where the voltage line is electrically connected to the conductive via.
[0058] Clause 51: The method of any one of Clauses 43-50, where the substrate contact includes an Ohmic substrate contact.
[0059] Clause 52: The method of any one of Clauses 43-50, where the substrate contact includes a Schottky substrate contact. [0060] Clause 53: The method of any one of Clauses 43-52, where the voltage line exhibits the largest absolute voltage of the integrated circuit package.
[0061] Clause 54: The method of any one of Clauses 43-53, further including an electronic device coupled to the substrate by a device interface.
[0062] All headings provided herein are for the convenience of the reader and should not be used to limit the meaning of any text that follows the heading, unless so specified. [0063] The terms “comprises” and variations thereof do not have a limiting meaning where these terms appear in the description and claims. Such terms will be understood to imply the inclusion of a stated step or element or group of steps or elements but not the exclusion of any other step or element or group of steps or elements.
[0064] In this application, terms such as “a,” “an,” and “the” are not intended to refer to only a singular entity but include the general class of which a specific example may be used for illustration. The terms “a,” “an,” and “the” are used interchangeably with the term “at least one.” The phrases “at least one of’ and “comprises at least one of’ followed by a list refers to any one of the items in the list and any combination of two or more items in the list.
[0065] The phrases “at least one of’ and “comprises at least one of’ followed by a list refers to any one of the items in the list and any combination of two or more items in the list.
[0066] As used herein, the term “or” is generally employed in its usual sense including “and/or” unless the content clearly dictates otherwise.
[0067] The term “and/or” means one or all of the listed elements or a combination of any two or more of the listed elements.
[0068] As used herein in connection with a measured quantity, the term “about” refers to that variation in the measured quantity as would be expected by the skilled artisan making the measurement and exercising a level of care commensurate with the objective of the measurement and the precision of the measuring equipment used. Herein, “up to” a number (e.g., up to 50) includes the number (e.g., 50).
[0069] Also herein, the recitations of numerical ranges by endpoints include all numbers subsumed within that range as well as the endpoints (e.g., 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, 5, etc.). [0070] These and other aspects of the present disclosure will be apparent from the detailed description below. In no event, however, should the above summaries be construed as limitations on the claimed subject matter, which subject matter is defined solely by the attached claims, as may be amended during prosecution. The details of one or more aspects of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the techniques described in this disclosure will be apparent from the description and drawings, and from the claims.
BRIEF DESCRIPTION OF DRAWINGS
[0071] FIG. 1 is a schematic cross-section view of one embodiment of an integrated circuit package.
[0072] FIG. 2 is a schematic cross-section view of a portion of the integrated circuit package of FIG. 1.
[0073] FIG. 3 is a schematic cross-section view of another embodiment of an integrated circuit package.
[0074] FIG. 4 is a diagrammatic view of one embodiment of an implantable medical device that includes the integrated circuit package of FIG. 1.
[0075] FIG. 5 is a flowchart of one embodiment of a method of forming the integrated circuit package of FIG. 1.
DETAILED DESCRIPTION
[0076] In general, the present disclosure provides various embodiments of an integrated circuit package and a method of making such package. The package can include a substrate contact that is configured to electrically connect a substrate of the package to one or more voltage lines. Each voltage line can be a conductor, a voltage source, or a device. In one or more embodiments, the substrate contact can electrically connect the substrate to the largest positive or negative voltage of the package. Further, the substrate can be a part of an interposer of the package or the primary substrate for the package. In one or more embodiments, the substrate contact can be an Ohmic substrate contact or a Schottky substrate contact.
[0077] The use of currently-available silicon interposers and 3D stacking techniques can reduce the volume of electronic packaging, thereby providing volumetric efficiency to electronic devices such as implantable medical devices (IMDs). Such techniques can be used in high performance computing or high bandwidth memory chips, where integrated circuits are stacked vertically and disposed adjacent to CPU cores. These configurations can increase switching speeds and decrease power consumption because of the close proximity between the components. Digital circuitry can benefit from this volumetric efficiency; however, analog circuitry may suffer from use of these techniques as the close proximity between components and leakage current that can be injected into silicon interposers or packaging material can increase noise in signals of one or more components of the circuitry.
[0078] One or more of the embodiments of integrated circuit packages described herein can provide various advantages over currently available packages. For example, a substrate of an interposer or device layer of the package can be connected to one or more voltage lines in the package or external to the package using a substrate contact that is disposed either on or at least partially within the substrate. This electrical connection between the substrate and one or more of the voltage lines can drain stray charges from the substrate and prevent them from interfering with signals of highly sensitive analog circuitry of the package. In one or more embodiments, this substrate contact can form either an Ohmic or Schottky substrate contact with the substrate. Further, such substrate contact can electrically connect the substrate to either the most positive or most negative voltage in the circuitry, thereby providing an electrical path for stray charges that may reside in the substrate. In one or more embodiments, the substrate can be electrically connected to a voltage line that is electrically connected to ground.
[0079] FIGS. 1-2 are schematic cross-section views of one embodiment of an integrated circuit package 10. The package 10 includes a substrate 12 having a first major surface 14 and a second major surface 16, a voltage line 18, and a substrate contact 20 configured to electrically connect the substrate to the voltage line. In one or more embodiments, the package 10 can further include one or more conductive vias 22, and one or more electronic devices 36 coupled to the substrate 12 by a device interface 38 as is further described herein. The package 10 can include any suitable circuitry and components. In one or more embodiments, the substrate 12, the conductive via(s) 22, and the substrate contact 20 can define an interposer of the package 10. In one or more embodiments, the substrate 12, the conductive via(s) 22, and the substrate contact 20 can define a device layer of the package 10.
[0080] The package 10 can include any suitable substrate 12. Further, the substrate 12 can include any suitable material, e.g., metallic, polymeric, or non-metallic inorganic materials and combinations thereof. In one or more embodiments, the substrate 12 can be a nonconductive or dielectric substrate that provides electrical isolation between various conductors, vias, dies, etc. In one or more embodiments, the substrate 12 can be a semiconductor substate that includes one or more semiconductor materials, e.g., silicon. In one or more embodiments, such semiconductor substrate 12 can be doped using any suitable dopant.
[0081] For convenience and without intending to be limiting, FIG. 1 depicts the substrate 12 as a monolithic (i.e., single) layer. In one or more embodiments, the substrate 12 can include any suitable number of layers, where the layers can be formed from the same or different materials. Further, the substrate 12 can have any suitable dimensions. For example, the substrate 12 can have any suitable thickness as measured in a direction orthogonal to the first major surface 14 of the substrate. Further, the substrate 12 can be formed using any suitable technique.
[0082] The voltage line 18 can include any suitable conductor or voltage source that exhibits any suitable voltage. Further, the voltage line 18 can be an integrated circuit or packaged device that is disposed on or in the substate 12, a part of the package 10, or electrically connected to one or more components or devices of the package. In one or more embodiments, the voltage line 18 can be electrically connected to one or more conductive vias 22. As shown in FIGS. 1-2, a negative terminal 26 of the voltage line is electrically connected to a first conductive via 22-1 and a positive terminal 24 of the voltage line 18 is electrically connected to a second conductive via 22-2 (the first conductive via and the second conductive via are collectively referred to as conductive vias 22). The voltage line 18 can exhibit any suitable positive or negative voltage. In one or more embodiments, the voltage line 18 can be connected to ground using any suitable technique. For example, the voltage line 18 can be electrically connected to ground utilizing one or more conductive vias 22. As is further described herein, the voltage line 18 can exhibit a largest absolute voltage of the package 10, i.e., positive or negative voltage. [0083] The package 10 further includes one or more substrate contacts 20. While the package 10 is illustrated as including one substrate contact 20, the package can include any suitable number of substrate contacts. For example, a second substate contact 54 can be disposed on the second major surface 16 of the substrate 12 and can be configured to electrically connect the substrate to the voltage line 18, e.g., via a conductor 56 that is electrically connected to the contact and the second conductive via 22-2, which is also electrically connected to the voltage line.
[0084] The substrate contact 20 can take any suitable shape, have any suitable dimensions, and include any suitable electrically conductive material. Further, the substrate contact 20 can be disposed in any suitable location relative to the substrate 12 using any suitable technique such that the contact is electrically connected to the substrate. In one or more embodiments, the substrate contact 20 is disposed on either the first major surface 14 or the second major surface 16. In one or more embodiments, the substrate contact 20 can be disposed at least partially within the substrate 12. In one or more embodiments, the substrate contact 20 can be disposed entirely within the substrate 12.
[0085] As mentioned herein, the substrate contact 20 can be configured to electrically connect the substrate 12 to the voltage line 18 using any suitable technique. In the embodiment illustrated in FIGS. 1-2, the substrate contact 20 is electrically connected to the first via 22-1 by a conductor 28. Such conductor 28 can take any suitable shape and have any suitable dimensions. Further, the conductor 28 can include any suitable conductive material. In one or more embodiments, the conductor 28 can be a portion of a patterned conductive layer that is disposed adjacent to the first major surface 14 of the substrate 12.
[0086] The conductor 28 can be electrically isolated from the first major surface 14 of the substrate 12 by a nonconductive material 30 disposed between the substrate and the conductor. The nonconductive material 30 can include any suitable material, e.g., polyimide, bismaleimide triazine, polybenzoxazole, photoresist, glass, quartz, sapphire, etc. In one or more embodiments, the nonconductive material 30 can include an electrically insulative material. In one or more embodiments, the nonconductive material 30 can include an oxide, e.g., silicon dioxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and other suitable metal or inorganic oxides. In one or more embodiments, the nonconductive material 30 can include a nitride, e.g., silicon nitride, silicon oxynitride, and other suitable metal or inorganic nitrides.
[0087] As mentioned herein, the substrate contact 20 can be disposed at least partially within the substrate 12. For example, FIG. 3 is a schematic cross-section view of another embodiment of an integrated circuit package 100. All design considerations and possibilities described herein regarding integrated circuit package 10 of FIGS. 1-2 apply equally to integrated circuit package 100 of FIG. 3.
[0088] One difference between package 100 and package 10 is that substrate contact 120 of package 100 is disposed within substrate 112. The substrate contact 120 can be configured to electrically connect the substrate 112 to voltage line 118 using any suitable technique. For example, substrate contact 120 can be electrically connected to contact via 102 that is disposed at least partially within the substrate 112 and that extends between the substrate contact and a first major surface 114 of the substrate. The contact via 102 can take any suitable shape and have any suitable dimensions. Further, the contact via 102 can include any suitable conductive material. The contact via 102 can electrically connect the substrate contact 120 to a conductor 128 disposed adjacent to the first major surface 114 of the substrate 112 using any suitable technique. The conductor 128 can electrically connect the substrate contact 120 and the contact via 102 to one or more conductive vias 122 using any suitable technique. As the substrate contact 120 and the voltage line 118 are each electrically connected to conductive via 122, the substrate contact electrically connects the substrate 112 to the voltage line.
[0089] Returning to FIGS. 1-2, the substrate contact 20 can include any suitable type of contact. In one or more embodiments, the substrate contact 20 can be an Ohmic substrate contact. As used herein, the term “Ohmic substrate contact” means a metal contact 20 that forms a non-rectifying electrical junction with the semiconductor substrate 12. In one or more embodiments, the substrate contact 20 can be a Schottky substrate contact. As used herein, the term “Schottky substrate contact” means a metal contact 20 that forms a rectifying electrical junction with the semiconductor substrate 12.
[0090] The substrate contact 20 can be electrically connected to the voltage line 18 using any suitable technique. As shown in FIG. 1, the substrate contact 20 is electrically connected to the voltage line 18 by the conductor 28 and the conductive via 22. In one or more embodiments, the substrate contact 20 can be electrically connected to the voltage line 18 directly by a conductor (not shown). Any suitable conductor or conductors can be utilized to directly connect the substrate contact 20 to the voltage line 18. In one or more embodiments, a patterned conductive layer can be disposed adjacent to the first major surface 14 of the substrate 12 upon which the substrate contact 20 is disposed, and the patterned conductive layer can electrically connect the contact directly to the voltage line 18.
[0091] The package 10 can also include the one or more conductive vias 22. One or more of the conductive vias 22 can be disposed into or through the substrate 12 between the first major surface 14 and the second major surface 16 of the substrate. The package 10 can include any suitable number of conductive vias 22. Each conductive via 22 can include any suitable conductive material, can take any suitable shape, and can have any suitable dimensions. Further, each conductive via can be formed using any suitable technique. [0092] The conductive vias 22 can electrically connect one or more conductive regions or components disposed adjacent to the first major surface 14 of the substrate 12 (e.g., the voltage line 18) with one or more conductive regions or components 32 disposed adjacent to the second major surface 16 of the substrate using any suitable technique. Any suitable conductive region or component 32 can be electrically connected by the conductive via 22 to one or more conductive regions or components disposed adjacent to the first major surface 14, e.g., at least one of a conductive pad, solder bump, ball grid array, landing pad, capacitor, resistor, passive integrated capacitor system, logic circuit, analog circuit, crystals, oscillator, accelerometer, and any suitable active or passive component, etc. In one or more embodiments, the conductive region or component 32 can include one or more solder bumps 34 as shown in FIG. 1.
[0093] Each conductive via 22 can include any suitable structure. For example, as shown in FIG. 2, which is a schematic cross-section view of a portion of the package 10 of FIG. 1 with the electronic component 36 and the device interface 38 removed for explanatory purposes, each via 22 includes an opening 40, oxide material 42 disposed within the opening on at least a portion of a sidewall 44 of the opening, and conductive material 46 disposed within the opening such that the oxide material is disposed between the conductive material and the at least a portion of the sidewall. In one or more embodiments, the oxide material is disposed over the entire sidewall 44 of the opening 40 such that the oxide material is disposed between the conductive material 46 and the sidewall. [0094] The opening 40 extends into or through the substrate 12 and can be formed using any suitable technique, e.g., drilling, laser drilling, chemical etching, plasma etching, stamping, etc. Further, the oxide material 42 and conductive material 46 can be disposed in the opening using any suitable technique, e.g., vapor deposition, chemical vapor deposition, etc.
[0095] In one or more embodiments, the oxide material 42 of the via 22 can allow charge particles (i.e., stray particles) 48 to leak from the conductive material 46 into the substrate 12 as current flows through the via. Such charge particles 48 can form one or more depletion regions 50. A width of a depletion region 50 as measured in a direction substantially parallel to the first major surface 14 of the substrate 12 can vary depending upon how much charge leaks into the substrate 12 through the oxide material 42. The leaked charge particles 48 can produce noise variances in signals produced by integrated circuits or components of the package 10. The one or more substrate contacts 20 can be configured to direct these charge particles 48 from the depletion regions 50 or other portions of the substrate 12 to the voltage line 18 such that they are at least substantially discharged from the substrate 12, thereby potentially reducing noise in one or more signals of the circuits or components of the package 10. As a result, the substrate 12 can be discharged with the voltage line 18 that is electrically connected to the substrate 12 with the substrate contact 20. Such discharging of the substrate 12 can include directing the charge particles 48 from the depletion regions 50 of the substrate to the voltage line 18. [0096] The package 10 can include any suitable additional integrated circuits or components. For example, package 10 includes the electronic device 36 that is coupled to the substrate 12 by the device interface 38. The package 10 can include any suitable number of devices 36 disposed in any suitable arrangement or array. In one or more embodiments, one or more electronic devices 36 can be disposed in a cavity 52 (serving as the device interface) of the substrate 12. Although depicted as including one device 36 per cavity 52, in one or more embodiments, two or more devices can be disposed within a single cavity. In one or more embodiments, one or more devices 36 can be disposed in the cavity 52 such that the device is completely within the cavity. For example, each device 36 can have a device height measured in a direction orthogonal to the first major surface 14 of the substrate 12 that is no greater than a height of the cavity 52 within which the device is disposed. In one or more embodiments, the device height of one or more devices 36 can be greater than the height of the cavity 52 within which the respective device is disposed. [0097] The package 10 can include any suitable type of device 36. In one or more embodiments, the device 36 can include one or more high-voltage dies that can be utilized, e.g., in an implantable medical device (see, e.g., implantable medical device 200 of FIG. 4). As used herein, the term “high-voltage die” refers to an electronic component or device that is operable with a potential greater than about 50 V across any two electrical terminals or contacts of the component. Such high-voltage components may be further operable at DC voltages greater than about 100 V, and even further may be operable at DC voltages greater than about 500 V, 1000 V, 1600 V, 3000 V and even greater, perhaps in the tens of thousands or more volts. In one or more embodiments, the package 10 can include one or more devices 36 that include low-voltage dies. In one or more embodiments, the one or more devices 36 can include one or more field effect transistors (FETs), metal oxide semiconductors (MOS), MOSFETs, insulated gate bipolar junction transistors (IGBT), thyristors, bipolar transistors, diodes, MOS -controlled thyristors, resistors, capacitors, etc. In one or more embodiments, two or more devices 36 can be arranged in a stacked relationship.
[0098] Disposed on or in the first major surface 14 of the substrate 12 is the device interface 38. The package 10 can include any suitable device interface 38, e.g., a ball grid array, one or more conductive pads, a wire bond frame, etc. As shown in FIG. 1, the device interface 38 includes the cavity 52 that is disposed in the first major surface 14 of the substate 12. The device interface 38 is configured to facilitate attachment of the electronic device 36 to any suitable additional components of the package or external to the package, e.g., an interposer, an interconnect region, a redistribution layer, one or more additional integrated circuits or components, etc., using any suitable technique.
[0099] The various embodiments of integrated circuit packages described herein can be utilized in any suitable electronic system. For example, one or more embodiments of integrated circuit packages described herein can be utilized in an IMD, ICD, IPG (e.g., a pacemaker such as a leadless pacemaker), insertable cardiac monitor, implantable diagnostic monitor, deep brain stimulator, implantable neurostimulator, injectable neurostimulator, implantable ventricular assist device, etc. [0100] FIG. 4 is a schematic plan view of one embodiment of an implantable medical device (IMD) 200. The IMD 200 includes a housing 202 and electronic components 204 disposed within the housing. The electronic components 204 can include any suitable electronic devices, e.g., at least one of a capacitor, resistor, passive integrated capacitor system, logic circuit, analog circuit, crystal, accelerometer, RF circuit, antenna, transformer, connector, etc. In one or more embodiments, the electronic components 204 include the integrated circuit package 10. The integrated circuit package 10 can be electrically connected to other electronic components 204 using any suitable technique. In one or more embodiments, the voltage line 18 of the package 10 can be electrically connected to the housing 202 of the IMD 200 by one or more conductors 208 using any suitable technique.
[0101] Also disposed within the housing 202 of the IMD 200 is a power source 206 that is electrically connected to the electronic components 204 using any suitable technique. The power source 206 can include any suitable power source or combination of power sources, e.g., one or more batteries, capacitors, inductive-coupled energy devices, photovoltaic devices, betavoltaic devices, alphavoltaic devices, and thermo-electric devices.
[0102] Any suitable technique can be utilized to form the various embodiments of integrated circuit packages described herein. For example, FIG. 5 is a flowchart of one embodiment of a method 300 of forming the integrated circuit package 10. Although described in reference to the integrated circuit package 10 of FIGS. 1-2, the method 300 can be utilized to form any suitable integrated circuit package. Further, the method 300 is illustrated as including one electronic device 36; however, the method can be utilized to form integrated circuit packages that include two or more devices.
[0103] At 302, the substrate contact 20 can be disposed on or at least partially within the substrate 12 using any suitable technique. The substrate 12 can be electrically connected to the voltage line 18 at 304 via the substrate contract 20 using any suitable technique. In one or more embodiments, the substrate 12 can be electrically connected to the voltage line 18 by electrically connecting the substrate contact 20 to the conductive via 22 with the conductor 28, and electrically connecting the voltage line to the conductive via. Prior to electrically connecting the device contact 20 and the voltage line 18 to the conductive via 22, such conductive via or vias can be disposed through the substrate 12 between the first major surface 14 and the second major surface 16 at 306 using any suitable technique. For example, in one or more embodiments, the opening 40 can be disposed into or through the substrate 12 using any suitable technique, e.g., by drilling, laser drilling, chemical etching, plasma etching, stamping, etc. The oxide material 42 can be disposed within the opening on at least a portion of the sidewall 44 of the opening, and the conductive material 46 can be disposed within the opening such that the oxide material is disposed between the conductive material and the at least a portion of the sidewall using any suitable technique. [0104] At 308, the conductive region or component 32 can optionally be disposed adjacent to the second major surface 16 of the substrate 12 and electrically connected to the conductive via 22 using any suitable technique.
[0105] The device interface 38 can optionally be disposed on or in the first major surface 14 of the substrate 12 at 310 using any suitable technique. In one or more embodiments where the device interface 38 includes or is included in the cavity 52, such cavity can be disposed in the first major surface 14 of the substrate 12 using any suitable technique, e.g., the same techniques described herein that are utilized to dispose the opening 40 of the via 22 in the substrate. At 312 the electronic device 36 can optionally be coupled to the substrate 12 at the device interface 38 using any suitable technique.
[0106] It should be understood that various aspects disclosed herein may be combined in different combinations than the combinations specifically presented in the description and accompanying drawings. It should also be understood that, depending on the example, certain acts or events of any of the processes or methods described herein may be performed in a different sequence, may be added, merged, or left out altogether (e.g., all described acts or events may not be necessary to carry out the techniques). In addition, while certain aspects of this disclosure are described as being performed by a single module or unit for purposes of clarity, it should be understood that the techniques of this disclosure may be performed by a combination of units or modules associated with, for example, a medical device.
[0107] In one or more examples, the described techniques may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a computer-readable medium and executed by a hardware -based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to a tangible medium such as data storage media (e.g., RAM, ROM, EEPROM, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer).
[0108] Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor” as used herein may refer to any of the foregoing structure or any other physical structure suitable for implementation of the described techniques. Also, the techniques could be fully implemented in one or more circuits or logic elements.
[0109] All references and publications cited herein are expressly incorporated herein by reference in their entirety into this disclosure, except to the extent they may directly contradict this disclosure. Illustrative embodiments of this disclosure are discussed and reference has been made to possible variations within the scope of this disclosure. These and other variations and modifications in the disclosure will be apparent to those skilled in the art without departing from the scope of the disclosure, and it should be understood that this disclosure is not limited to the illustrative embodiments set forth herein. Accordingly, the disclosure is to be limited only by the claims provided below.

Claims

WHAT IS CLAIMED IS:
1. An integrated circuit package comprising: a semiconductor substrate comprising a first major surface and a second major surface; a voltage line; and a substrate contact configured to electrically connect the substrate to the voltage line.
2. The package of claim 1, further comprising a conductive via disposed into or through the substrate between the first major surface and the second major surface of the substrate.
3. The package of claim 2, wherein the conductive via comprises: an opening that extends into or through the substrate; oxide material disposed within the opening on at least a portion of a sidewall of the opening; and conductive material disposed within the opening such that the oxide material is disposed between the conductive material and the at least a portion of the sidewall.
4. The package of any one of claims 2-3, wherein the semiconductor substrate, the conductive via, and the substrate contact define an interposer.
5. The package of any one of claims 2-4, wherein a portion of the substrate adjacent to the conductive via comprises a depletion region, wherein the substrate contact is configured to direct charge particles from the depletion region to the voltage line.
6. The package of any one of claims 1-5, wherein the voltage line exhibits a largest absolute voltage of the integrated circuit package.
7. A method of forming an integrated circuit package, comprising: disposing a substrate contact on or at least partially within a semiconductor substrate, wherein the substrate comprises a first major surface and a second major surface; and electrically connecting the substrate to a voltage line of the package utilizing the substrate contact.
8. The method of claim 7, further comprising disposing a conductive via into or through a semiconductor substrate between the first major surface and the second major surface of the substrate.
9. The method of claim 8, further comprising disposing a conductive region or component adjacent to the second major surface of the substrate and electrically connecting the conductive region or component to the conductive via.
10. The method of any one of claims 7-9, wherein electrically connecting the substrate to the voltage line comprises: electrically connecting the substrate contact to the conductive via utilizing a conductor; and electrically connecting the voltage line to the conductive via.
11. An implantable medical device comprising a housing and an integrated circuit package disposed within the housing, wherein the package comprises: a semiconductor substrate comprising a first major surface and a second major surface; a voltage line; and a substrate contact configured to electrically connect the substrate to the voltage line.
12. The device of claim 11, further comprising a conductive via disposed into or through the substrate between the first major surface and the second major surface of the substrate.
13. The device of claim 12, wherein the voltage line is electrically connected to the conductive via.
14. A method comprising: in a semiconductor substrate comprising a first major surface and a second major surface, discharging the substrate with a voltage line electrically connected to the substrate with a substrate contact.
15. The method of claim 14, wherein discharging the substrate comprises directing charge particles from a depletion region of the substrate to the voltage line.
PCT/IB2024/056965 2023-08-31 2024-07-18 Integrated circuit package and method of forming same WO2025046333A1 (en)

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US63/535,806 2023-08-31

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895966A (en) * 1995-09-29 1999-04-20 Analog Devices, Inc. Integrated circuit and supply decoupling capacitor therefor
US6777802B1 (en) * 2002-06-06 2004-08-17 Lsi Logic Corporation Integrated circuit package substrate with multiple voltage supplies
US7795713B2 (en) * 2007-02-20 2010-09-14 Nec Electronics Corporation Semiconductor device and method for producing the same
US20220157676A1 (en) * 2018-08-14 2022-05-19 Medtronic, Inc. Integrated circuit package and method of forming same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895966A (en) * 1995-09-29 1999-04-20 Analog Devices, Inc. Integrated circuit and supply decoupling capacitor therefor
US6777802B1 (en) * 2002-06-06 2004-08-17 Lsi Logic Corporation Integrated circuit package substrate with multiple voltage supplies
US7795713B2 (en) * 2007-02-20 2010-09-14 Nec Electronics Corporation Semiconductor device and method for producing the same
US20220157676A1 (en) * 2018-08-14 2022-05-19 Medtronic, Inc. Integrated circuit package and method of forming same

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