WO2025030655A1 - Voltage selection circuit for power supply circuit - Google Patents

Abstract

Disclosed in the present invention is a voltage selection circuit for a power supply circuit. The voltage selection circuit comprises: a voltage comparison module, a first level shift module, and a second level shift module. The voltage comparison module comprises a high-voltage turn-on module, a low-voltage mirror module, and an inverter signal output module. The first level shift module comprises a first level shift branch and a second level shift branch. The second level shift module comprises a third level shift branch and a fourth level shift branch. A first supply voltage V₁ and a second supply voltage V₂ are inputted into the voltage comparison module, and the voltage comparison module outputs a first control signal V_1H and a second control signal V_2H; the first control signal V_1H is used for controlling the first level shift module so as to control the output of the first supply voltage V₁ to a voltage output end of the voltage selection circuit, and the second control signal V_2H is used for controlling the second level shift module so as to control the output of the second supply voltage V₂ to the voltage output end of the voltage selection circuit.

Description

Voltage selection circuit for power supply circuit Technical Field

The present invention relates to the technical field of power supply, and in particular to a voltage selection circuit for a power supply circuit.

Background Art

In the power supply circuit design in the prior art, there are often multiple power supply voltages supplying power to the power supply circuit. In order to ensure the reliable and stable operation of the power supply circuit, for example, when some power supply voltages have been powered on and some power supply voltages have not yet been established (for example, the power supply voltages are generated by the BOOST circuit), it is necessary to select a high voltage power supply voltage to power the power supply circuit.

However, the currently disclosed power supply circuits have the problem that the applicable range of the power supply voltage is small and cannot be applied to both high and low voltage domains; or when the power supply voltage is switched between different voltage domains, the power supply circuit has leakage.

In view of this, the technical purpose of the present invention is to design a new voltage selection circuit for a power supply circuit, which can operate in a high voltage domain (such as 40V) and can effectively avoid leakage through parasitic body diodes between different voltage domains.

Summary of the invention

The technical purpose to be achieved by the present invention is to provide a voltage selection circuit for a power supply circuit, so that it can automatically select and output a high power supply voltage under high voltage application conditions to power the entire circuit; and there is no leakage problem between different voltage domains, thereby improving circuit reliability.

The present invention provides a voltage selection circuit for a power supply circuit, the voltage selection circuit comprising: a voltage comparison module 1, a first level shift module 2 and a second level shift module 3; the voltage comparison module 1 comprises a high voltage conduction module 11, a low voltage mirror module 12 and an inverter signal output module 13; the first level shift module 2 comprises a first level shift branch 21 and a second level shift branch 22; the second level shift module 3 comprises a third level shift branch 31 and a fourth level shift branch 32;

The first supply voltage _V1 and the second supply voltage _V2 are input into the voltage comparison module 1, and the voltage comparison module 1 outputs a first control signal _V1H and a second control signal _V2H , wherein when the first control signal _V1H is at a high level, it indicates that the first supply voltage _V1 is higher than the second supply voltage _V2 , and when the second control signal _V2H is at a high level, it indicates that the first supply voltage _V1 is lower than the second supply voltage _V2 ;

The first control signal _V1H is used to control the first level shift module 2 to control the first supply voltage _V1 to be output to the voltage output end of the voltage selection circuit; the second control signal _V2H is used to control the second level shift module 3 to control the second supply voltage _V2 to be output to the voltage output end of the voltage selection circuit.

In one embodiment, the high-voltage conduction module 11 includes a first high-voltage PMOS transistor PH1, a second high-voltage PMOS transistor PH2, a first high-voltage NMOS transistor NH1 and a second high-voltage NMOS transistor NH2, wherein the source of the first high-voltage PMOS transistor PH1 is connected to a first power supply voltage V ₁ , the gate of the first high-voltage PMOS transistor PH1 is connected to its own drain, the source of the second high-voltage PMOS transistor PH2 is connected to a second power supply voltage V ₂ , and the gate of the second high-voltage PMOS transistor PH2 is connected to the gate of the first high-voltage PMOS transistor PH1; the drain of the first high-voltage NMOS transistor NH1 is connected to the drain of the first high-voltage PMOS transistor PH1, the gate of the first high-voltage NMOS transistor NH1 is connected to an external low-voltage power supply voltage V _L , the drain of the second high-voltage NMOS transistor NH2 is connected to the drain of the second high-voltage PMOS transistor PH2, and the gate of the second high-voltage NMOS transistor NH2 is also connected to the external low-voltage power supply voltage V _L .

In one embodiment, the low-voltage mirror module 12 includes a first low-voltage NMOS tube NM1, a second low-voltage NMOS tube NM2 and a third low-voltage NMOS tube NM3; the drain of the first low-voltage NMOS tube NM1 is connected to an external bias current I _B , the source of the first low-voltage NMOS tube NM1 is grounded, and the drain of the first low-voltage NMOS tube NM1 is connected to its own gate; the drain of the second low-voltage NMOS tube NM2 is connected to the source of the first high-voltage NMOS tube NH1, the source of the second low-voltage NMOS tube NM2 is grounded, and the gate of the second low-voltage NMOS tube NM2 is connected to the external bias current I _B ; the drain of the third low-voltage NMOS tube NM3 is connected to the source of the second high-voltage NMOS tube NH2, the source of the third low-voltage NMOS tube NM3 is grounded, and the gate of the third low-voltage NMOS tube NM3 is connected to the external bias current I _B.

In one embodiment, the inverter signal output module 13 includes a first inverter INV1, a second inverter INV2 and a third inverter INV3, the input end of the first inverter INV1 is connected to the source of the second high-voltage NMOS tube NH2, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3.

In one embodiment, the first level shift branch 21 includes a third high-voltage PMOS transistor PH3, a first resistor R1, a third high-voltage NMOS transistor NH3 and a fourth low-voltage NMOS transistor NM4; wherein, the source of the third high-voltage PMOS transistor PH3 is connected to the first power supply voltage V ₁ , and the first resistor R1 is connected between the source and the gate of the third high-voltage PMOS transistor PH3; the gate of the third high-voltage NMOS transistor NH3 is connected to the first control signal V _1H , and the drain of the third high-voltage NMOS transistor NH3 is connected to the gate of the third high-voltage PMOS transistor PH3; the drain of the fourth low-voltage NMOS transistor NM4 is connected to the source of the third high-voltage NMOS transistor NH3, the source of the fourth low-voltage NMOS transistor NM4 is grounded, and the gate of the fourth low-voltage NMOS transistor NM4 is connected to the external bias current I _B.

In one embodiment, the second level shift branch 22 includes a fourth high-voltage PMOS transistor PH4, a second resistor R2, a fourth high-voltage NMOS transistor NH4 and a fifth low-voltage NMOS transistor NM5; wherein, the drain of the fourth high-voltage PMOS transistor PH4 is connected to the drain of the third high-voltage PMOS transistor PH3, the source of the fourth high-voltage PMOS transistor PH4 is connected to one end of the second resistor R2, the gate of the fourth high-voltage PMOS transistor PH4 is connected to the other end of the second resistor R2, the drain of the fourth high-voltage NMOS transistor NH4 is connected to the other end of the second resistor R2, the gate of the fourth high-voltage NMOS transistor NH4 is connected to the first control signal V _1H , the drain of the fifth low-voltage NMOS transistor NM5 is connected to the source of the fourth high-voltage NMOS transistor NH4, the source of the fifth low-voltage NMOS transistor NM5 is grounded, and the gate of the fifth low-voltage NMOS transistor NM5 is connected to the external bias current I _B.

In one embodiment, the third level shift branch 31 includes a fifth high-voltage PMOS transistor PH5, a third resistor R3, a fifth high-voltage NMOS transistor NH5 and a sixth low-voltage NMOS transistor NM6; wherein, the source of the fifth high-voltage PMOS transistor PH5 is connected to the second power supply voltage _V2 , and the third resistor R3 is connected between the source and the gate of the fifth high-voltage PMOS transistor PH5; the gate of the fifth high-voltage NMOS transistor NH5 is connected to the second control signal _V2H , and the drain of the fifth high-voltage NMOS transistor NH5 is connected to the gate of the fifth high-voltage PMOS transistor PH5; the drain of the sixth low-voltage NMOS transistor NM6 is connected to the source of the fifth high-voltage NMOS transistor NH5, the source of the sixth low-voltage NMOS transistor NM6 is grounded, and the gate of the sixth low-voltage NMOS transistor NM6 is connected to the external bias current _IB .

In one embodiment, the fourth level shift branch 32 includes a sixth high-voltage PMOS transistor PH6, a fourth resistor R4, a sixth high-voltage NMOS transistor NH6 and a seventh low-voltage NMOS transistor NM7; wherein, the drain of the sixth high-voltage PMOS transistor PH6 is connected to the drain of the fifth high-voltage PMOS transistor PH5, the source of the sixth high-voltage PMOS transistor PH6 is connected to one end of the fourth resistor R4, the gate of the sixth high-voltage PMOS transistor PH6 is connected to the other end of the fourth resistor R4, the drain of the sixth high-voltage NMOS transistor NH6 is connected to the other end of the fourth resistor R4, the gate of the sixth high-voltage NMOS transistor NH6 is connected to the second control signal V _2H , the drain of the seventh low-voltage NMOS transistor NM7 is connected to the source of the sixth high-voltage NMOS transistor NH6, the source of the seventh low-voltage NMOS transistor NM7 is grounded, and the gate of the seventh low-voltage NMOS transistor NM7 is connected to the external bias current I _B.

Compared with the prior art, one or more embodiments of the present invention may have the following inventive features and advantages:

1. The present invention uses the isolation of the high-voltage NMOS tube and the level shift circuit to enable the overall circuit to work in the high-voltage domain, thereby realizing the judgment of the power supply voltage in the high-voltage domain;

2. The present invention can effectively cut off the leakage path between different voltage domains by adopting a high-voltage PMOS tube with a back-gate structure and its gate control circuit;

3. The grid of the high-voltage tube of the present invention will not bear high voltage, and has low requirements and dependence on the process.

Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

FIG1 is a schematic diagram of the structure of a voltage selection circuit for a power supply circuit of the present invention;

FIG2 is a circuit structure diagram of a voltage selection circuit for a power supply circuit of the present invention;

FIG. 3 is a circuit waveform diagram of a voltage selection circuit for a power supply circuit according to the present invention.

DETAILED DESCRIPTION

In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

Before proceeding to the following detailed description, it may be necessary to set forth the definitions of certain words and phrases used throughout the present invention. The terms "coupling", "connection" and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmission", "reception" and "communication" and their derivatives cover direct and indirect communication. The terms "include" and "comprising" and their derivatives refer to including but not limited to. The term "or" is inclusive, meaning and/or. The phrase "associated with..." and its derivatives refer to including, including within, interconnecting, containing, contained within, connecting or with...connecting, coupling or with...coupling, communicating with, cooperating, interweaving, parallel, approaching, binding or with...binding, having, having attributes, having a relationship or with...having a relationship, etc. The term "controller" refers to any device, system or part thereof that controls at least one operation. Such a controller can be implemented with hardware, or a combination of hardware and software and/or firmware. The functions associated with any particular controller can be centralized or distributed, whether local or remote. The phrase "at least one of", when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one of the items in the list may be required. For example, "at least one of A, B, C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

The description of the first end and the second end of a resistor, capacitor or inductor in the present invention is only to distinguish the two connection ends of the device, so as to facilitate the description of the connection relationship between the device and other devices, and does not specifically specify a certain end of the resistor, capacitor or inductor in actual situations. Those skilled in the art should know that when constructing an actual circuit, any end of the resistor, capacitor or inductor in an actual device can be defined as the first end, and when the first end is defined, the other end of the device is automatically defined as the second end.

When describing various components or elements in the present invention, the description methods of "first", "second", "third", etc. are used only to distinguish the various components and to express the different relationships between the various components. The description methods used above do not contain any implicit meaning of the relationship between the components. For example, when only the descriptions of "first" and "third" appear, it does not mean that there is a "second" between the two. The descriptions of "first" and "third" here only mean that there are two different independent components.

Definitions of other specific words and phrases are provided throughout this disclosure. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

In the present invention, the application combination of modules and the division level of sub-modules are only used for illustration, and the application combination of modules and the division level of sub-modules may have different modes without departing from the scope of the present disclosure.

Example 1

As shown in FIG1 , the voltage selection circuit for the power supply circuit of this embodiment includes a voltage comparison module 1, a first level shift module 2 and a second level shift module 3. The voltage comparison module 1 includes a high voltage conduction module 11, a low voltage mirror module 12 and an inverter signal output module 13. The first level shift module 2 includes a first level shift branch 21 and a second level shift branch 22. The second level shift module 3 includes a third level shift branch 31 and a fourth level shift branch 32.

In this embodiment, the first supply voltage _V1 and the second supply voltage _V2 are input into the voltage comparison module 1, and the voltage comparison module 1 outputs a first control signal _V1H and a second control signal _V2H . When the first control signal _V1H is at a high level, it indicates that the first supply voltage _V1 is higher than the second supply voltage _V2 , and when the second control signal _V2H is at a high level, it indicates that the first supply voltage _V1 is lower than the second supply voltage _V2 .

The first control signal _V1H is used to control the first level shift module 2 to control the first supply voltage _V1 to be output to the voltage output end of the voltage selection circuit; the second control signal _V2H is used to control the second level shift module 3 to control the second supply voltage _V2 to be output to the voltage output end of the voltage selection circuit.

As shown in FIG2 , in this embodiment, the high-voltage conduction module 11 includes a first high-voltage PMOS transistor PH1, a second high-voltage PMOS transistor PH2, a first high-voltage NMOS transistor NH1 and a second high-voltage NMOS transistor NH2, wherein the source of the first high-voltage PMOS transistor PH1 is connected to the first power supply voltage V ₁ , the gate of the first high-voltage PMOS transistor PH1 is connected to its own drain, the source of the second high-voltage PMOS transistor PH2 is connected to the second power supply voltage V ₂ , and the gate of the second high-voltage PMOS transistor PH2 is connected to the gate of the first high-voltage PMOS transistor PH1. The drain of the first high-voltage NMOS transistor NH1 is connected to the drain of the first high-voltage PMOS transistor PH1, the gate of the first high-voltage NMOS transistor NH1 is connected to the external low-voltage power supply voltage V _L , the drain of the second high-voltage NMOS transistor NH2 is connected to the drain of the second high-voltage PMOS transistor PH2, and the gate of the second high-voltage NMOS transistor NH2 is also connected to the external low-voltage power supply voltage V _L .

In this embodiment, the low-voltage mirror module 12 includes a first low-voltage NMOS tube NM1, a second low-voltage NMOS tube NM2, and a third low-voltage NMOS tube NM3. The drain of the first low-voltage NMOS tube NM1 is connected to the external bias current I _B , the source of the first low-voltage NMOS tube NM1 is grounded, and the drain of the first low-voltage NMOS tube NM1 is connected to its own gate. The drain of the second low-voltage NMOS tube NM2 is connected to the source of the first high-voltage NMOS tube NH1, the source of the second low-voltage NMOS tube NM2 is grounded, and the gate of the second low-voltage NMOS tube NM2 is connected to the external bias current I _B. The drain of the third low-voltage NMOS tube NM3 is connected to the source of the second high-voltage NMOS tube NH2, the source of the third low-voltage NMOS tube NM3 is grounded, and the gate of the third low-voltage NMOS tube NM3 is connected to the external bias current I _B.

In this embodiment, the inverter signal output module 13 includes a first inverter INV1, a second inverter INV2 and a third inverter INV3, the input end of the first inverter INV1 is connected to the source of the second high-voltage NMOS tube NH2, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3.

In this embodiment, in the low-voltage mirror circuit, the first low-voltage NMOS tube NM1, the second low-voltage NMOS tube NM2 and the third low-voltage NMOS tube NM3 form a current mirror, that is, when the second low-voltage NMOS tube NM2 and the third low-voltage NMOS tube NM3 are in the on state, the current flowing through the second low-voltage NMOS tube NM2 and the third low-voltage NMOS tube NM3 is the same. If the first power supply voltage _V1 is higher than the second power supply voltage _V2 , the gate-source voltage _VGS of the first high-voltage PMOS tube PH1 will be greater than the gate-source voltage _VGS of the second high-voltage PMOS tube PH2, thereby causing the source of the second high-voltage NMOS tube NH2 to output a low-level signal. Furthermore, the second control signal _V2H outputted from the output end of the second inverter INV2 is outputted as a low-level signal, and the first control signal _V1H outputted from the output end of the third inverter INV3 is outputted as a high-level signal. When the first power supply voltage _V1 is lower than the second power supply voltage _V2 , the first control signal _V1H is at a low level, and the second control signal _V2H is at a high level.

As shown in FIG2 , in this embodiment, the first level shift branch 21 includes a third high-voltage PMOS transistor PH3, a first resistor R1, a third high-voltage NMOS transistor NH3, and a fourth low-voltage NMOS transistor NM4. The source of the third high-voltage PMOS transistor PH3 is connected to the first power supply voltage V ₁ , and the first resistor R1 is connected between the source and the gate of the third high-voltage PMOS transistor PH3. The gate of the third high-voltage NMOS transistor NH3 is connected to the first control signal V _1H , and the drain of the third high-voltage NMOS transistor NH3 is connected to the gate of the third high-voltage PMOS transistor PH3. The drain of the fourth low-voltage NMOS transistor NM4 is connected to the source of the third high-voltage NMOS transistor NH3, the source of the fourth low-voltage NMOS transistor NM4 is grounded, and the gate of the fourth low-voltage NMOS transistor NM4 is connected to the external bias current I _B.

The second level shift branch 22 includes a fourth high-voltage PMOS transistor PH4, a second resistor R2, a fourth high-voltage NMOS transistor NH4, and a fifth low-voltage NMOS transistor NM5. The drain of the fourth high-voltage PMOS transistor PH4 is connected to the drain of the third high-voltage PMOS transistor PH3, the source of the fourth high-voltage PMOS transistor PH4 is connected to one end of the second resistor R2, the gate of the fourth high-voltage PMOS transistor PH4 is connected to the other end of the second resistor R2, the drain of the fourth high-voltage NMOS transistor NH4 is connected to the other end of the second resistor R2, the gate of the fourth high-voltage NMOS transistor NH4 is connected to the first control signal _V1H , the drain of the fifth low-voltage NMOS transistor NM5 is connected to the source of the fourth high-voltage NMOS transistor NH4, the source of the fifth low-voltage NMOS transistor NM5 is grounded, and the gate of the fifth low-voltage NMOS transistor NM5 is connected to the external bias current _IB .

The third level shift branch 31 includes a fifth high-voltage PMOS transistor PH5, a third resistor R3, a fifth high-voltage NMOS transistor NH5 and a sixth low-voltage NMOS transistor NM6. The source of the fifth high-voltage PMOS transistor PH5 is connected to the second power supply voltage _V2 , and the third resistor R3 is connected between the source and the gate of the fifth high-voltage PMOS transistor PH5. The gate of the fifth high-voltage NMOS transistor NH5 is connected to the second control signal _V2H , and the drain of the fifth high-voltage NMOS transistor NH5 is connected to the gate of the fifth high-voltage PMOS transistor PH5. The drain of the sixth low-voltage NMOS transistor NM6 is connected to the source of the fifth high-voltage NMOS transistor NH5, the source of the sixth low-voltage NMOS transistor NM6 is grounded, and the gate of the sixth low-voltage NMOS transistor NM6 is connected to the external bias current _IB .

The fourth level shift branch 32 includes a sixth high-voltage PMOS transistor PH6, a fourth resistor R4, a sixth high-voltage NMOS transistor NH6, and a seventh low-voltage NMOS transistor NM7. The drain of the sixth high-voltage PMOS transistor PH6 is connected to the drain of the fifth high-voltage PMOS transistor PH5, the source of the sixth high-voltage PMOS transistor PH6 is connected to one end of the fourth resistor R4, the gate of the sixth high-voltage PMOS transistor PH6 is connected to the other end of the fourth resistor R4, the drain of the sixth high-voltage NMOS transistor NH6 is connected to the other end of the fourth resistor R4, the gate of the sixth high-voltage NMOS transistor NH6 is connected to the second control signal _V2H , the drain of the seventh low-voltage NMOS transistor NM7 is connected to the source of the sixth high-voltage NMOS transistor NH6, the source of the seventh low-voltage NMOS transistor NM7 is grounded, and the gate of the seventh low-voltage NMOS transistor NM7 is connected to the external bias current _IB .

The source of the fourth high-voltage PMOS transistor PH4 is connected to the source of the sixth high-voltage PMOS transistor PH6 and serves as the voltage output terminal V _MAX of the voltage selection circuit.

In this embodiment, the first low-voltage NMOS tube NM1 to the seventh low-voltage NMOS tube NM7 are current mirror circuits composed of low-voltage NMOS tubes, and the first high-voltage NMOS tube NH1 to the sixth high-voltage NMOS tube NH6 are high-voltage NMOS tubes, which are used to isolate the high-voltage domain and the low-voltage domain so that the devices in the low-voltage domain will not be affected by the high voltage.

For the first level shift branch 21, when the first power supply voltage _V1 is higher than the second power supply voltage _V2 , the first control signal _V1H is at a high level, the gate of the third high-voltage NMOS transistor NH3 is opened, and the fourth high-voltage NMOS transistor NM4 generates a current _I1 flowing through the first resistor R1. By selecting appropriate _I1 and _R1, the value of _I1 * _R1 is greater than the conduction threshold of the third high-voltage PMOS transistor PH3 and less than the gate withstand voltage (for example, 5V) of the third high-voltage PMOS transistor PH3. At this time, the gate voltage _VG1 of the third high-voltage PMOS transistor PH3 is _V1 - _I1 * _R1 , so that the third high-voltage PMOS transistor PH3 is turned on; when the voltage _V1 is lower than _V2 , the first control signal _V1H is at a low level, the third high-voltage NMOS transistor NH3 is turned off, and no current flows through the first resistor _R1 . At this time, _VG1 = _V1 , and PH3 is turned off.

For the second level shift branch 22, NM5, NH4 and R2 form a level shift circuit for controlling the on or off of PH4, generating the gate voltage V _G2 of the fourth high-voltage PMOS tube PH4. If there is no fourth high-voltage PMOS tube PH4, when the output voltage V _MAX is greater than V ₁ by a diode conduction voltage, there will be a leakage current flowing from V _MAX to V ₁ through the parasitic body diode of PH3, and the existence of PH4 and its control circuit cuts off the leakage path, thereby improving the reliability of the circuit. When the voltage of _V1 is higher than _{that of V2} , _V1H is high, NH4 is turned on, and NM5 generates a current _I2 flowing through R2. By selecting appropriate _I2 and R2, the value of _I2 *R2 is greater than the turn-on threshold of PH4 but less than the gate withstand voltage of PH4 (for example, 5V). At this _time , _VG2 = _VMAX - _I2 *R2, and PH4 is turned on; when the voltage of _V1 is lower than that of V2, _V1H is low, NH4 is turned off, and no current flows through R2. At this time, _VG2 = _VMAX , and PH4 is turned off.

The first level shift branch 21 and the second level shift branch 22 are both controlled by _V1H , so the on and off of PH3 and PH4 are synchronous. When PH3 and PH4 are on, the voltage of _V1 is transmitted to _VMAX , otherwise _V1 and _VMAX are in an off state.

NM6, NH5 and R3 form a level shift circuit that controls the on or off of PH5, generating the gate voltage V _G3 of the fifth high-voltage PMOS tube PH5. When the voltage of V ₂ is higher than V ₁ , V _2H is high, NH5 is turned on, and NM6 generates a current I ₃ flowing through R3. By selecting appropriate I ₃ and R3, the value of I ₃ *R3 is greater than the on threshold of PH5 and less than the gate withstand voltage of PH5 (for example, 5V). At this time, V _G3 = V ₂ -I ₃ *R3, and PH5 is turned on; when the voltage of V ₂ is lower than V ₁ , V _2H is low, NH5 is turned off, and no current flows through R3. At this time, V _G3 = V ₂ , and PH5 is turned off.

NM7, NH6 and R4 form a level shift circuit that controls the on or off of PH6, generating the gate voltage V _G4 of the sixth high-voltage PMOS tube PH6. When the voltage of V ₂ is higher than V ₁ , V _2H is high, NH6 is turned on, and NM7 generates a current I ₄ flowing through R4. By selecting appropriate I ₄ and R4, the value of I ₄ *R4 is greater than the on threshold of PH6 and less than the gate withstand voltage of PH6 (for example, 5V). At this time, V _G4 =V _MAX -I ₄ *R4, PH6 is turned on; when the voltage of V ₂ is lower than V ₁ , V _2H is low, NH6 is turned off, and no current flows through R4. At this time, V _G4 =V _MAX , PH6 is turned off.

The third level shift branch 31 and the fourth level shift branch 32 are both controlled by _V2H , so the on and off of PH5 and PH6 are synchronous. When PH5 and PH6 are on, the voltage of _V2 is transmitted to _VMAX , otherwise _V2 and _VMAX are in an off state.

In summary, when the first power supply voltage _V1 is greater than the second power supply voltage _V2 , the third high-voltage PMOS tube PH3 and the fourth high-voltage PMOS tube PH4 are turned on, and the fifth high-voltage PMOS tube PH5 and the sixth high-voltage PMOS tube PH6 are turned off, and the voltage output by the voltage output terminal _VMAX is the first power supply voltage _V1 ; on the contrary, when the first power supply voltage _V1 is less than the second power supply voltage _V2 , the third high-voltage PMOS tube PH3 and the fourth high-voltage PMOS tube PH4 are turned off, and the fifth high-voltage PMOS tube PH5 and the sixth high-voltage PMOS tube PH6 are turned on, and the voltage output by the voltage output terminal _VMAX is the second power supply voltage _V2 . Thus, the function of the voltage output terminal _VMAX automatically selecting the high power supply voltage is realized.

As shown in FIG3 , the voltage waveform diagram of the voltage selection circuit for the power supply circuit of the present invention, when the first power supply voltage _V1 outputs 20V, the _second power supply voltage V2 gradually rises from 0V to 40V; the output voltage of the voltage output terminal V _MAX first outputs the first power supply voltage _V1 20V, and when the first power supply voltage _V1 is less than the second power supply voltage _V2 , the second power supply voltage _V2 starts to be output.

The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims (10)

A voltage selection circuit for a power supply circuit, characterized in that the voltage selection circuit comprises: a voltage comparison module, a first level shift module and a second level shift module; the voltage comparison module comprises a high voltage conduction module, a low voltage mirror module and an inverter signal output module; the first level shift module comprises a first level shift branch and a second level shift branch; the second level shift module comprises a third level shift branch and a fourth level shift branch; The first supply voltage _V1 and the second supply voltage _V2 are input into a voltage comparison module, and the voltage comparison module outputs a first control signal _V1H and a second control signal _V2H , wherein when the first control signal _V1H is at a high level, it indicates that the first supply voltage _V1 is higher than the second supply voltage _V2 , and when the second control signal _V2H is at a high level, it indicates that the first supply voltage _V1 is lower than the second supply voltage _V2 ; The first control signal _V1H is used to control the first level shift module to control the first supply voltage _V1 to be output to the voltage output end of the voltage selection circuit; the second control signal _V2H is used to control the second level shift module to control the second supply voltage _V2 to be output to the voltage output end of the voltage selection circuit. The voltage selection circuit for a power supply circuit according to claim 1 is characterized in that the high-voltage conduction module comprises a first high-voltage PMOS tube PH1, a second high-voltage PMOS tube PH2, a first high-voltage NMOS tube NH1 and a second high-voltage NMOS tube NH2, wherein the source of the first high-voltage PMOS tube PH1 is connected to the first power supply voltage _V1 , the gate of the first high-voltage PMOS tube PH1 is connected to its own drain, the source of the second high-voltage PMOS tube PH2 is connected to the second power supply voltage _V2 , and the gate of the second high-voltage PMOS tube PH2 is connected to the gate of the first high-voltage PMOS tube PH1; the drain of the first high-voltage NMOS tube NH1 is connected to the drain of the first high-voltage PMOS tube PH1, the gate of the first high-voltage NMOS tube NH1 is connected to the external low-voltage power supply voltage _VL , the drain of the second high-voltage NMOS tube NH2 is connected to the drain of the second high-voltage PMOS tube PH2, and the gate of the second high-voltage NMOS tube NH2 is also connected to the external low-voltage power supply voltage _VL . The voltage selection circuit for a power supply circuit according to claim 2 is characterized in that the low-voltage mirror module 12 includes a first low-voltage NMOS tube NM1, a second low-voltage NMOS tube NM2 and a third low-voltage NMOS tube NM3; the drain of the first low-voltage NMOS tube NM1 is connected to an external bias current I _B , the source of the first low-voltage NMOS tube NM1 is grounded, and the drain of the first low-voltage NMOS tube NM1 is connected to its own gate; the drain of the second low-voltage NMOS tube NM2 is connected to the source of the first high-voltage NMOS tube NH1, the source of the second low-voltage NMOS tube NM2 is grounded, and the gate of the second low-voltage NMOS tube NM2 is connected to the external bias current I _B ; the drain of the third low-voltage NMOS tube NM3 is connected to the source of the second high-voltage NMOS tube NH2, the source of the third low-voltage NMOS tube NM3 is grounded, and the gate of the third low-voltage NMOS tube NM3 is connected to the external bias current I _B. According to the voltage selection circuit for a power supply circuit according to claim 3, it is characterized in that the inverter signal output module includes a first inverter INV1, a second inverter INV2 and a third inverter INV3, the input end of the first inverter INV1 is connected to the source of the second high-voltage NMOS tube NH2, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3. The voltage selection circuit for a power supply circuit according to claim 4 is characterized in that the first level shift branch comprises a third high-voltage PMOS tube PH3, a first resistor R1, a third high-voltage NMOS tube NH3 and a fourth low-voltage NMOS tube NM4; wherein the source of the third high-voltage PMOS tube PH3 is connected to the first power supply voltage _V1 , and the first resistor R1 is connected between the source and the gate of the third high-voltage PMOS tube PH3; the gate of the third high-voltage NMOS tube NH3 is connected to the first control signal _V1H , and the drain of the third high-voltage NMOS tube NH3 is connected to the gate of the third high-voltage PMOS tube PH3; the drain of the fourth low-voltage NMOS tube NM4 is connected to the source of the third high-voltage NMOS tube NH3, the source of the fourth low-voltage NMOS tube NM4 is grounded, and the gate of the fourth low-voltage NMOS tube NM4 is connected to the external bias current _IB . The voltage selection circuit for a power supply circuit according to claim 5 is characterized in that the second level shift branch comprises a fourth high-voltage PMOS tube PH4, a second resistor R2, a fourth high-voltage NMOS tube NH4 and a fifth low-voltage NMOS tube NM5; wherein the drain of the fourth high-voltage PMOS tube PH4 is connected to the drain of the third high-voltage PMOS tube PH3, the source of the fourth high-voltage PMOS tube PH4 is connected to one end of the second resistor R2, the gate of the fourth high-voltage PMOS tube PH4 is connected to the other end of the second resistor R2, and the drain of the fourth high-voltage NMOS tube NH4 is connected to the other end of the second resistor R2, the gate of the fourth high-voltage NMOS tube NH4 is connected to the first control signal _V1H , the drain of the fifth low-voltage NMOS tube NM5 is connected to the source of the fourth high-voltage NMOS tube NH4, the source of the fifth low-voltage NMOS tube NM5 is grounded, and the gate of the fifth low-voltage NMOS tube NM5 is connected to the external bias current _IB . The voltage selection circuit for a power supply circuit according to claim 6 is characterized in that the third level shift branch comprises a fifth high-voltage PMOS tube PH5, a third resistor R3, a fifth high-voltage NMOS tube NH5 and a sixth low-voltage NMOS tube NM6; wherein the source of the fifth high-voltage PMOS tube PH5 is connected to the second power supply voltage _V2 , and the third resistor R3 is connected between the source and the gate of the fifth high-voltage PMOS tube PH5; the gate of the fifth high-voltage NMOS tube NH5 is connected to the second control signal _V2H , and the drain of the fifth high-voltage NMOS tube NH5 is connected to the gate of the fifth high-voltage PMOS tube PH5; the drain of the sixth low-voltage NMOS tube NM6 is connected to the source of the fifth high-voltage NMOS tube NH5, the source of the sixth low-voltage NMOS tube NM6 is grounded, and the gate of the sixth low-voltage NMOS tube NM6 is connected to the external bias current _IB . The voltage selection circuit for a power supply circuit according to claim 7 is characterized in that the fourth level shift branch comprises a sixth high-voltage PMOS tube PH6, a fourth resistor R4, a sixth high-voltage NMOS tube NH6 and a seventh low-voltage NMOS tube NM7; wherein the drain of the sixth high-voltage PMOS tube PH6 is connected to the drain of the fifth high-voltage PMOS tube PH5, the source of the sixth high-voltage PMOS tube PH6 is connected to one end of the fourth resistor R4, the gate of the sixth high-voltage PMOS tube PH6 is connected to the other end of the fourth resistor R4, and the drain of the sixth high-voltage NMOS tube NH6 is connected to the other end of the fourth resistor R4, the gate of the sixth high-voltage NMOS tube NH6 is connected to the second control signal _V2H , the drain of the seventh low-voltage NMOS tube NM7 is connected to the source of the sixth high-voltage NMOS tube NH6, the source of the seventh low-voltage NMOS tube NM7 is grounded, and the gate of the seventh low-voltage NMOS tube NM7 is connected to the external bias current _IB . The voltage selection circuit for a power supply circuit according to claim 8 is characterized in that the source of the fourth high-voltage PMOS tube PH4 is connected to the source of the sixth high-voltage PMOS tube PH6 and serves as a voltage output end of the voltage selection circuit. An integrated circuit chip, comprising the voltage selection circuit according to any one of claims 1 to 9.