WO2025018975A1

WO2025018975A1 - Apparatus and method for context memory synchronization for parallel processing

Info

Publication number: WO2025018975A1
Application number: PCT/US2023/027768
Authority: WO
Inventors: Sangwon Ki; Su-Lin Low
Original assignee: Greater Shine Ltd
Current assignee: Greater Shine Ltd
Priority date: 2023-07-14
Filing date: 2023-07-14
Publication date: 2025-01-23
Anticipated expiration: 2026-01-14

Abstract

According to one aspect of the present disclosure, a device is provided. The device may include a custom instruction (CX) synchronization component. The custom memory synchronization controller may include a synchronization component. The synchronization component may be configured to identify a first update to a first memory context entry at a first context memory associated with a first processing unit. The synchronization component may be configured to cause the first memory context entry at a second context memory associated with a second processing unit to be updated with the first update. The first processing unit and the second processing unit may perform parallel processing of an instructions set.

Description

APPARATUS AND METHOD FOR CONTEXT MEMORY SYNCHRONIZATION FOR PARALLEL PROCESSING

BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In cellular communication, such as the 4th-gen eration (4G) Long Term Evolution (LTE) and the 5th- generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various procedures for robust header compression (ROHC).

SUMMARY

[0003] According to one aspect of the present disclosure, a device is provided. The device may include a custom memory synchronization controller. The custom memory synchronization controller may include a synchronization component. The synchronization component may be configured to identify a first update to a first memory context entry at a first context memory associated with a first processing unit. The synchronization component may be configured to cause the first memory context entry at a second context memory associated with a second processing unit to be updated with the first update. The first processing unit and the second processing unit may perform parallel processing of an instructions set.

[0004] According to another aspect of the present disclosure, an apparatus for wireless communication is provided. The apparatus may include a first processing unit configured to perform first ROHC operations on a ROHC packet header. The apparatus may include a second processing unit configured to perform second ROHC operations on the ROHC packet header. The apparatus may include a custom instruction (CX) synchronization controller. The custom memory synchronization controller may include a synchronization component. The synchronization component may be configured to identify a first update to a first memory context entry at a first context memory associated with a first processing unit. The synchronization component may be configured to cause the first memory context entry at a second context memory associated with a second processing unit to be updated with the first update. The first processing unit and the second processing unit may perform parallel processing of an instructions set. [0005] According to a further aspect of the present disclosure a method of wireless communication of a user equipment is provided. The method may include identifying, by a synchronization component of a custom memory synchronization controller, a first update to a first memory context entry at a first context memory associated with a first processing unit. The method may include causing, by the synchronization component of the custom memory synchronization controller, the first memory context entry at a second context memory associated with a second processing unit to be updated with the first update. The first processing unit and the second processing unit may perform parallel processing of an instructions set.

[0006] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 illustrates example operations associated with a generic central processing unit (CPU) offloading some ROHC operations to a CX processing unit.

[0009] FIG. 2 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0010] FIG. 3 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0011] FIG. 4 illustrates a detailed block diagram of an exemplary wireless device, according to some embodiments of the present disclosure.

[0012] FIG. 5 illustrates a detailed block diagram of an exemplary system that includes a custom memory synchronization controller, according to some embodiments of the present disclosure.

[0013] FIG. 6 illustrates a flowchart for a first exemplary method of wireless communication, according to some embodiments of the present disclosure.

[0014] FIGs. 7A and 7B illustrate a flowchart for a second exemplary method of wireless communication, according to some embodiments of the present disclosure. [0015] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0016] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0017] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0018] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0019] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0020] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 1000, etc. A TDMA network may implement a RAT, such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as LTE or NR. A WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0021] Small-packet communication services, e.g., such as voice over internet protocol (VoIP), voice over NR (VoNR), intemet-of-things (loT), industrial loT (IIoT), interactive games, virtual reality (VR), augmented reality (AR), messaging, etc., in the 5G NR network may use ROHC to compress the headers of small packets such as Internet Protocol (IP) packets, user datagram protocol (UDP), real-time protocol (RTP), etc. ROHC may reduce header the overhead of voice packet transmissions, which lowers the block error rate (BER), reduces latency, and limits resource block (RB) consumption.

[0022] In the context of VoIP communications, ROHC may be useful since the header of the VoIP packets is much larger than the payload data it carries. For example, the payload of a VoIP packet may include around 32 bytes of payload voice data and 60 bytes of header. Thus, VoIP is a good candidate for ROHC to reduce the size of the header that is transmitted over the air. Moreover, while voice traffic tends to be very small in terms of data size, it has very frequent transmission. So, ROHC provides an efficient solution to reduce the number of transmitted resource blocks (RBs).

[0023] In the ROHC compression procedure, the ROHC protocol analyzes the incoming IP/UDP/RTP headers for compression. These headers include static and semi-static fields, which never or seldom change or can be inferred, and hence there is no need to send these fields every time to the decompressor. On the other hand, there are 3 main dynamic changing fields, which are the main targets for compression by the ROHC protocol, e.g., namely, the RTP Sequence Number (SN), RTP TimeStamp (TS), and IP Identification (IP ID) fields.

[0024] FIG. 1 illustrates example operations 100 associated with a generic CPU offloading some ROHC operations to a CX processing unit. Referring to FIG. 1, an ROHC packet may be input (at 101) into flow classification component 106, which is operated by the generic CPU. Flow classification component 106 may update (at 103) the “A” address in CPU context memory 102. Before invoking the analysis pattern component 110 in the CX, the generic CPU may compare/update (at 105) the “A” address in both CPU context memory 102 and CX context memory 104. Then, flow classification component 106 may invoke (at 107) pattern analysis component 110, which refers (at 109) to “A” address of CX context memory 104 as its input parameter. Pattern analysis component 110 updates (at 111) the “B” address in the CX context memory as a result of its operation. Before invoking the packet-type selection component 108, the generic CPU may compare/update (at 113) the “B” address in both the CPU context memory 102 and the CX context memory 104. Once the “B” addresses the same, flow classification component 106 activates (at 115) packet-type selection component 108. Packet-type selection component 108 may refer (at 117) to the “B” address of CPU context memory 102 as an input.

[0025] Still referring to FIG. 1, before invoking the CX, the generic CPU ensures the corresponding memory context entries in CPU context memory 102 and CX context memory 104 are the same. In the event that the corresponding context memory entries are not the same, the generic CPU copies the data from CPU context memory 102 to CX context memory 104. In the other direction, after the CX performs an operation, the generic CPU compares the corresponding content entries of CPU context memory 102 and CX context memory 104. This happens before the generic CPU performs the subsequent operation.

[0026] Unfortunately, the comparing and copying of the CPU context memory 102 and the

CX context memory 104 for concurrent (also referred to herein as “parallel”) CPU and CX operations suffers from various drawbacks. For example, these drawbacks include, e.g. 1) a wastage of CPU cycles by comparing and copying data between CPU context memory 102 and CX context memory 104, 2) a complicated software structure that is difficult to maintain, 3) difficulty in designing and implementing offloading to the CX, 4) a large number of million- instructions-per-second (MIPS) cycles, and 5) undesirable power consumption. [0027] To overcome these and other challenges, the present disclosure provides a custom memory synchronization controller coupled between a first context memory component (e.g., a CPU) and a second context memory associated with a second processing unit (e.g., a CX processing component). The custom memory synchronization controller may synchronize corresponding context memory entries in the first context memory component and the second context memory component without comparing and updating by the CPU.

[0028] In some embodiments, the exemplary custom memory synchronization controller may be used to synchronize context memory entries for parallel processing of a ROHC packet. In ROHC processing, both CPU and CX processing units may be used to enhance the ROHC procedure, but it is difficult and inefficient to synchronize two memory blocks between CPU and CX frequently, causing unnecessary MIPS cycles. The exemplary custom memory synchronization controller may enable a seamless operation between the CPU and CX processing unit for their respective memories without waiting by either the CPU and/or CX processing unit. Using the present techniques, the CX processing unit may offload the CPU function at any anytime because the CX context memory is synchronized with CPU context memory in the program flow. This allows a streamlined programming flow without waiting on either side, and eliminates the processing overhead of copying the contexts information, thereby reducing power consumption and processing latency. For example, using the exemplary custom memory synchronization controller, the comparing and copying of context information of the CPU context memory and the CX context memory to maintain the context between CPU and CX processing unit may be eliminated. By simplifying the system structure and reducing the number of CPU cycles, the present device is provided with a flexible and robust design. Additional details of the exemplary custom memory synchronization controller and its operations are provided below in connection with FIGs. 2-6.

[0029] Although the exemplary context memory synchronization procedure is described below in connection with a wireless device, it is not limited thereto. Instead, the exemplary context memory synchronization procedure may be applied to any computing device or system in which two processing units perform parallel processing of different instructions of an instruction set.

[0030] FIG. 2 illustrates an exemplary wireless network 200, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 2, wireless network 200 may include a network of nodes, such as user equipment 202, an access node 204, and a core network element 206. User equipment 202 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (loT) node. It is understood that user equipment 202 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0031] Access node 204 may be a device that communicates with user equipment 202, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 204 may have a wired connection to user equipment 202, a wireless connection to user equipment 202, or any combination thereof. Access node 204 may be connected to user equipment 202 by multiple connections, and user equipment 202 may be connected to other access nodes in addition to access node 204. Access node 204 may also be connected to other user equipments. When configured as a gNB, access node 204 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 202. When access node 204 operates in mmW or near mmW frequencies, the access node 204 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the radio frequency (RF) in the electromagnetic spectrum. EHF has a range of 30 GHz to 200 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 200 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 202 to compensate for the extremely high path loss and short range. It is understood that access node 204 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0032] Access nodes 204, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as NG-RAN in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., SI interface). In addition to other functions, access node 204 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 204 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless.

[0033] Core network element 206 may serve access node 204 and user equipment 202 to provide core network services. Examples of core network element 206 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 206 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 202 and the 5GC. Generally, the AMF provides QoS flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides user equipment (UE) IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 206 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0034] Core network element 206 may connect with a large network, such as the Internet 208, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 202 may be communicated to other user equipments connected to other access points, including, for example, a computer 210 connected to Internet 208, for example, using a wired connection or a wireless connection, or to a tablet 212 wirelessly connected to Internet 208 via a router 214. Thus, computer 210 and tablet 212 provide additional examples of possible user equipments, and router 214 provides an example of another possible access node. [0035] A generic example of a rack-mounted server is provided as an illustration of core network element 206. However, there may be multiple elements in the core network including database servers, such as a database 216, and security and authentication servers, such as an authentication server 218. Database 216 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 218 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 206, authentication server 218, and database 216, may be local connections within a single rack.

[0036] Each element in FIG. 2 may be considered a node of wireless network 200. More detail regarding the possible implementation of a node is provided by way of an example in the description of a node 300 in FIG. 3. Node 300 may be configured as user equipment 202, access node 204, or core network element 206 in FIG. 2. Similarly, node 300 may also be configured as computer 210, router 214, tablet 212, database 216, or authentication server 218 in FIG. 2. As shown in FIG. 3, node 300 may include a processor 302, a memory 304, and a transceiver 306. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 300 is user equipment 202, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 300 may be implemented as a blade in a server system when node 300 is configured as core network element 206. Other implementations are also possible.

[0037] Transceiver 306 may include any suitable device for sending and/or receiving data. Node 300 may include one or more transceivers, although only one transceiver 306 is shown for simplicity of illustration. An antenna 308 is shown as a possible communication mechanism for node 300. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 300 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 204 may communicate wirelessly to user equipment 202 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 206. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0038] As shown in FIG. 3, node 300 may include processor 302. Although only one processor is shown, it is understood that multiple processors can be included. Processor 302 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 302 may be a hardware device having one or more processing cores. Processor 302 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0039] As shown in FIG. 3, node 300 may also include memory 304. Although only one memory is shown, it is understood that multiple memories can be included. Memory 304 can broadly include both memory and storage. For example, memory 304 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc readonly memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 302. Broadly, memory 304 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0040] Processor 302, memory 304, and transceiver 306 may be implemented in various forms in node 300 for performing wireless communication functions. In some embodiments, at least two of processor 302, memory 304, and transceiver 306 are integrated into a single system- on-chip (SoC) or a single system-in-package (SiP). In some embodiments, processor 302, memory 304, and transceiver 306 of node 300 are implemented (e.g., integrated) on one or more SoCs. In one example, processor 302 and memory 304 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 302 and memory 304 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 302 and transceiver 306 (and memory 304 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 308. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication.

[0041] Referring back to FIG. 2, in some embodiments, user equipment 202 may include the exemplary custom memory synchronization controller described herein, which may be used to synchronize context memory entries for parallel processing of a ROHC packet by a CPU and a CX processing unit, for example.

[0042] FIG. 4 illustrates a detailed block diagram of an exemplary wireless device 400, according to some embodiments of the present disclosure. FIG. 5 illustrates a detailed block diagram of an exemplary system 500 that includes a custom memory synchronization controller, according to some embodiments of the present disclosure. FIGs. 4 and 5 will be described together. [0043] Referring to FIG. 4, exemplary wireless device 400 (referred to hereinafter as “wireless device 400”) may include, e.g., a host chip and a baseband chip, among others. The host chip may include, e.g., an application processor (AP)/host 414, and external connectivity/ network applications 416. AP/host 414 may host multiple IMS applications, e.g., such as Voice coderdecoder (codec) over the RTP/UDP/IP stack, and may also include other audio, video, or IIoT applications (not shown) whose sources may be from external connect! vity/network applications 416 (e.g., an external IMS source) connected to AP/host 414. External connect! vity/network applications 416 may have payloads encapsulated in IP/UDP/RTP layers. When these RTP packets arrive at the modem from the AP, the arrival times at the ROHC compressor 410a residing at the ROHC uC 408a, may contain jitter delays associated with unpredictable link connection and network delays.

[0044] The baseband chip may include, e.g., a downlink (DL) physical layer (PHY) subsystem 402a, an uplink (UL) PHY subsystem 402b, a dataplane (DP) subsystem 404, and a control plane subsystem 412. The DP subsystem 404 may include a DL dataplane (DP) subsystem 406a, which includes a ROHC microcontroller (uC) 408a with a ROHC compressor 410a and a ROHC decompressor 410b. The DP subsystem 404 may also include a UL DP subsystem 406b with a logical channel prioritization (LCP) uC 408b. Although ROHC compressor 410a is located on the DL DP subsystem 406a, it may be part of the UL datapath. Other configurations of the ROHC uC 408a are possible such that a DL ROHC uC is located on the DL DP subsystem 406a and a UL DP subsystem 406b is located on the UL DP subsystem, for example.

[0045] ROHC compressor 410a may communicate with the IMS applications (e.g., voice application) on AP/host 414, the Layer 2 layers, and the PHY layers. The connection between the host chip and the baseband chip may be achieved through various communication link protocols such as universal serial bus (USB), peripheral component interconnect express (PCIe) or proprietary connections, where uncertainties in the link delays are unavoidable and unpredictable. [0046] Once the RTP packets for a QoS flow arrive at the baseband chip’s data stack, the ROHC protocol compresses the RTP packet’s IP/UDP/RTP header for this QoS flow via an associated ROHC context flow. Then, ROHC compressor 410a sends out the replaced compressed ROHC header and payload to the DP UL hardware layers (e.g., cipher layer, packet data convergence protocol (PDCP) layer, radio link control (RLC) layer, medium access control (MAC) layer, etc.) and PHY layers to the network. On the network side, the peer ROHC decompressor for this ROHC context flow will decode the corresponding ROHC headers and decompress them back to the full IP header.

[0047] In the ROHC compression procedure, the ROHC protocol analyzes the incoming fP/UDP/RTP headers for compression. These headers comprise static and semi-static fields, which never or seldom change or can be inferred, and hence, there may be no need to send these fields every time to the network-side ROHC decompressor. On the other hand, there are three main dynamic changing fields, which are the main targets for compression by the ROHC protocol; namely, these fields include, e.g., the RTP Sequence Number (SN), RTP TimeStamp (TS), and IP Identification (IP ID) fields. Based on these analyses, the ROHC compressor 410a may compress the IP/UDP/R.TP header into a small ROHC header-compressed packet type. To maximize ROHC packet-processing performance, ROHC uC 408a or ROHC compressor 410a may include a CX processing unit that performs parallel processing of data (e.g., ROHC packets) with a CPU.

The number of CPU-processing cycles may be reduced using a custom memory synchronization controller. The custom memory synchronization controller may use a background synchronization component that updates corresponding context entries in a CPU context memory and a CX context memory so that the CPU can focus on performing operations on a ROHC instruction set, for example. Additional details of the custom memory synchronization controller and its exemplary operations are provided below in connection with FIG. 5.

[0048] Referring to FIG. 5, system 500 may include a CPU 502, CX processing unit 504, CPU context memory 506a, CX context memory 506b, and a custom memory synchronization controller. The custom memory synchronization controller may include, e.g., a synchronization component 508 (e.g., synchronization hardware or firmware), a first update detector 510a, a second update detector 510b, and a bit table 512 (e.g., a bitmap). First update detector 510a may identify an update to CPU context memory 506a, and cause a corresponding bit in bit table 512 to be updated, accordingly. Second update detector may identify an update to CX context memory 506b, and cause a corresponding bit in bit table 512 to be updated, accordingly. Bit table 512 may indicate the states of changes between CPU context memory 506a and CX context memory 506b. For example, a bit table entry of 00 indicates no changes to a corresponding memory location in either CPU context memory 506a or CX context memory 506b. A bit table entry of 01 indicates a change to corresponding context data in CX context memory 506b, while an entry of 10 indicates a change to corresponding context data in CPU context memory 506a. A change to corresponding context data in CPU context memory 506a and CX context memory 506b is indicated with a bit table entry of 11 which indicates a collision since both CPU 502 and CX processing unit 504 are not supposed to operate on the same instruction in the instruction set. Synchronization component 508 decides the data copy direction between CPU context memory 506a and the CX context memory 506b through bit table 512. Moreover, synchronization component 508 sends a collision interrupt signal to CPU 502 when a collision state is identified in bit table 512.

[0049] Still referring to FIG. 5, CPU 502 and CX processing unit 504 may perform operations on an instruction set in parallel. In some embodiments, the instruction set may be associated with ROHC packet processing. For example, if the instruction set includes ten instructions, CPU 502 may perform operations on a first subset of the instructions, while CX processing unit 504 concurrently performs operations on a second subset of the instructions.

[0050] In either embodiment, each time CPU 502 completes an operation on one of its instructions, it sends a context signal to CPU context memory 506a to update (at 501) a memory entry or location (e.g., address) with the context information that corresponds to that instruction. CPU context memory 506a may send a signal to first update detector 510a when CPU 502 causes an update to a context memory location at CPU context memory 506a. First update detector 510a updates (at 503) a corresponding entry at bit table 512 to indicate the change to memory entry of CPU context memory 506a. Synchronization component 508 may identify (at 505) when an entry to CPU context memory 506a is updated. When this happens, synchronization component 508 may cause a corresponding memory location in CX context memory 506b to be updated with the information in the CPU context memory 506a. [0051] Similarly, CX processing unit 504 may send a context signal to CX context memory 506b each time it performs an operation on an instruction in the instruction set to update (at 507) a memory entry or location (e.g., address) with the context information that corresponds to that instruction. CX context memory 506b may send a signal to second update detector 510b when CX processing unit 504 causes an update to a context memory location at CX context memory 506b. Second update detector 510b updates (at 509) a corresponding entry at bit table 512 to indicate the change to memory entry of CX context memory 506b. Synchronization component 508 may identify (at 511) when an entry to CX context memory 506b is updated. When this happens, synchronization component 508 may cause a corresponding memory location in CPU context memory 506a to be updated with the information in the CX context memory 506b.

[0052] In some circumstances, both CPU 502 and CX processing unit 504 may perform operations on the same instruction in the instructions set. When this happens, both first update detector 510a and second update detector 510b may update (at 515) bit table 512 to indicate these changes. When a bit table value of 11 is identified (at 513), synchronization component 508 may send (at 517) a collision interrupt signal to CPU 502. CPU 502 may then perform interrupt handling to resolve the issue.

[0053] FIG. 6 is a flowchart of a first exemplary method 600 (referred to hereinafter as “first method 600”) of wireless communication, according to some aspects of the present disclosure. First method 600 may be performed by a wireless device, e.g., such as user equipment 202, node 300, wireless device 400, DP subsystem 404, ROHC uC 408a, ROHC compressor 410a, CPU 502, CX processing unit 504 (e.g., a processor, a uC, a digital signal processor (DSP), etc.), CPU context memory 506a, CX context memory 506b, synchronization component 508, first update detector 510a, second update detector 510b, etc. First method 600 may include steps 602- 610, as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIG. 6.

[0054] Referring to FIG. 6, at 602, the wireless device may identify a first update to a first memory context entry at a first context memory associated with a first processing unit. For example, referring to FIG. 5, synchronization component 508 may identify (at 505) when an entry to CPU context memory 506a is updated.

[0055] At 604, the wireless device may cause the first memory context entry at a second context memory associated with a second processing unit to be updated with the first update. For example, referring to FIG. 5, synchronization component 508 may cause a corresponding memory location in CX context memory 506b to be updated with the information in the CPU context memory 506a.

[0056] At 606, the wireless device may update a first bitmap value corresponding to the first update to the first memory context entry at the first context memory associated with the first processing unit. For example, referring to FIG. 5, first update detector 510a updates (at 503) a corresponding entry at bit table 512 to indicate the change to memory entry of CPU context memory 506a.

[0057] At 608, the wireless device may identify when bitmap values indicate a context collision associated with a same location in the first context memory and the second context memory. For example, referring to FIG. 5, in some circumstances, both CPU 502 and CX processing unit 504 may perform operations on the same instruction in the instructions set. When this happens, both first update detector 510a and second update detector 510b may update (at 515) bit table 512 to indicate these changes. Synchronization component 508 may identify (at 513) when a bit table value of 11 for corresponding entries of CPU context memory 506a and CX context memory 506b occurs.

[0058] At 610, the wireless device may send an interrupt signal indicating the context collision associated with a same location in the first context memory and the second context memory to the first processing unit. For example, referring to FIG. 5, when a collision is identified, synchronization component 508 may send (at 517) a collision interrupt signal to CPU 502. CPU 502 may then perform interrupt handling to resolve the issue.

[0059] FIGs. 7A and 7B illustrate a flowchart for a second exemplary method 700 (referred to hereinafter as “second method 700”) of wireless communication, according to some embodiments of the present disclosure. Second method 700 may be performed by a wireless device, e.g., such as user equipment 202, node 300, wireless device 400, DP subsystem 404, ROHC uC 408a, ROHC compressor 410a, CPU 502, CX processing unit 504 (e.g., a processor, a uC, a digital signal processor (DSP), etc.), CPU context memory 506a, CX context memory 506b, synchronization component 508, first update detector 510a, second update detector 510b, etc. Second method 700 may include steps 702-732, as described below. It is to be appreciated that some of the steps may be optional, and some of the steps may be performed simultaneously, or in a different order than shown in FIGs. 7A and 7B.

[0060] Referring to FIG. 7A, at 702, the wireless device may initiate context memory update sensing. At 704, the wireless device may determine whether a CPU context memory address or a CX context memory address is updated. If “Yes” at 704, the operations may move to 706; otherwise, if “No” at 706, the operations may return to 702. At 706, the wireless device may determine whether the context memory address that was updated is located at the CPU context memory. If “Yes” at 706, the operations may move to 708; otherwise, if “No” at 706, the operations may move to 718.

[0061] Still referring to FIG. 7A, at 708, the wireless device may determine the bit table row index corresponding to the updated CPU context memory address as the CPU context memory base minus the CPU memory address that was updated divided by four. At 710, the wireless device may update the bit table row index to a bit value of 10, indicating the update to the CPU context memory address. At 712, the wireless device may determine the bit information associated with the bit table row index as 10. At 714, the wireless device may determine the corresponding CPU memory address that was changed in the CPU context memory as the CPU memory base plus the bit table row index multiplied by four. At 716, the wireless device may determine the corresponding CX context memory address as the CX context memory base plus the bit table row index multiplied by four.

[0062] Referring again to FIG. 7 A, at 718, the wireless device may determine the bit table row index associated with the updated CX context memory address as the CX context memory base minus the CX memory address that was updated divided by four. At 720, the wireless device may update the bit table row index to a bit value of 01.

[0063] Referring to FIG. 7B, at 722, the wireless device may determine whether the bit information of the updated bit table row index is 10. If “Yes” at 722, the operations may move to 724; otherwise, if “No” at 722, the operations may move to 728. At 724, the wireless device may copy the updated CPU context memory address to the corresponding CX context memory address. At 726, the wireless device may cause the corresponding bit table row index to be updated to a bit value of 00, at which time the operations may return to 702.

[0064] Still referring to FIG. 7B, at 728, the wireless device may determine whether the bit information in the updated bit table row index is 01. If “Yes” at 728, the operations may move to 730; otherwise, if “No” at 728, the operations may move to 732. At 730, the wireless device may copy the updated CX context memory address to the corresponding CPU context memory address. If “No” at 728, the wireless device may determine the updated bit table row index is 11. Thus, at 732, the wireless device may send an interrupt signal to the CPU with the colliding CPU context memory and CX memory addresses. [0065] Referring again to FIGs. 7A and 7B, the operations from 706 onward are described in connection to a change in the CPU context memory address rather than a change in CX context memory address. However, when a change in CX context memory address is determined/identified at 706, the same or similar operations may be performed to update the CPU context memory address. For instance, referring to FIG. 5, these operations may include one or more of operations 507, 509, 511, etc.

[0066] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 300 in FIG. 3. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital video disc (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. [0067] According to one aspect of the present disclosure, a device is provided. The device may include a custom memory synchronization controller. The custom memory synchronization controller may include a synchronization component. The synchronization component may be configured to identify a first update to a first memory context entry at a first context memory associated with a first processing unit. The synchronization component may be configured to cause the first memory context entry at a second context memory associated with a second processing unit to be updated with the first update. The first processing unit and the second processing unit may perform parallel processing of an instructions set.

[0068] In some embodiments, the custom memory synchronization controller may further include a first update detector. In some embodiments, the first update detector may be configured to update a first bitmap value corresponding to the first update to the first memory context entry at the first context memory associated with the first processing unit. In some embodiments, the first update detector may be coupled to the first context memory. [0069] In some embodiments, the custom memory synchronization controller may further include a second update detector. In some embodiments, the second update detector may be configured to identify a second update to a second memory context entry at a second context memory associated with a second processing unit. In some embodiments, the second update detector may be configured to cause the second memory context entry at the first context memory associated with a first processing unit to be updated with the second update.

[0070] In some embodiments, the second update detector may be further configured to update a second bitmap value corresponding to the second update to the second memory context entry at the second context memory associated with the second processing unit. In some embodiments, the second update detector is coupled to the second context memory.

[0071] In some embodiments, the synchronization component may be further configured to identify when bitmap values indicate a context collision associated with a same location in the first context memory and the second context memory.

[0072] In some embodiments, the synchronization component may be further configured to send an interrupt signal indicating the context collision associated with a same location in the first context memory and the second context memory to the first processing unit.

[0073] In some embodiments, the context collision may indicate both the first processing unit and the second processing unit perform operations on a same instruction of the instruction set. [0074] According to another aspect of the present disclosure, an apparatus for wireless communication is provided. The apparatus may include a first processing unit configured to perform first ROHC operations on a ROHC packet header. The apparatus may include a second processing unit configured to perform second ROHC operations on the ROHC packet header. The apparatus may include a CX synchronization controller. The custom memory synchronization controller may include a synchronization component. The synchronization component may be configured to identify a first update to a first memory context entry at a first context memory associated with a first processing unit. The synchronization component may be configured to cause the first memory context entry at a second context memory associated with a second processing unit to be updated with the first update. The first processing unit and the second processing unit may perform parallel processing of an instructions set.

[0075] In some embodiments, the custom memory synchronization controller may further include a first update detector. In some embodiments, the first update detector may be configured to update a first bitmap value corresponding to the first update to the first memory context entry at the first context memory associated with the first processing unit. In some embodiments, the first update detector may be coupled to the first context memory.

[0076] In some embodiments, the custom memory synchronization controller may further include a second update detector. In some embodiments, the second update detector may be configured to identify a second update to a second memory context entry at a second context memory associated with a second processing unit. In some embodiments, the second update detector may be configured to cause the second memory context entry at the first context memory associated with a first processing unit to be updated with the second update.

[0077] In some embodiments, the second update detector may be further configured to update a second bitmap value corresponding to the second update to the second memory context entry at the second context memory associated with the second processing unit. In some embodiments, the second update detector is coupled to the second context memory.

[0078] In some embodiments, the synchronization component may be further configured to identify when bitmap values indicate a context collision associated with a same location in the first context memory and the second context memory.

[0079] In some embodiments, the synchronization component may be further configured to send an interrupt signal indicating the context collision associated with a same location in the first context memory and the second context memory to the first processing unit.

[0080] According to a further aspect of the present disclosure a method of wireless communication of a user equipment is provided. The method may include identifying, by a synchronization component of a custom memory synchronization controller, a first update to a first memory context entry at a first context memory associated with a first processing unit. The method may include causing, by the synchronization component of the custom memory synchronization controller, the first memory context entry at a second context memory associated with a second processing unit to be updated with the first update. The first processing unit and the second processing unit may perform parallel processing of an instructions set.

[0081] In some embodiments, the method may further include updating, by a first update detector of the custom memory synchronization controller, a first bitmap value corresponding to the first update to the first memory context entry at the first context memory associated with the first processing unit. In some embodiments, the first update detector may be coupled to the first context memory.

[0082] In some embodiments, the method may further include identifying, by a second update detector of the custom memory synchronization controller, a second update to a second memory context entry at a second context memory associated with a second processing unit. In some embodiments, the method may further include causing, by the second update detector of the custom memory synchronization controller, the second memory context entry at the first context memory associated with a first processing unit to be updated with the second update.

[0083] In some embodiments, the method may further include updating, by the second update detector of the custom memory synchronization controller, a second bitmap value corresponding to the second update to the second memory context entry at the second context memory associated with the second processing unit. In some embodiments, the second update detector may be coupled to the second context memory.

[0084] In some embodiments, the method may further include identifying, by the synchronization component of the custom memory synchronization controller, when bitmap values indicate a context collision associated with a same location in the first context memory and the second context memory. In some embodiments, the method may further include sending, by the synchronization component of the custom memory synchronization controller, an interrupt signal indicating the context collision associated with a same location in the first context memory and the second context memory to the first processing unit.

[0085] In some embodiments, the context collision indicates both the first processing unit, and the second processing unit may perform operations on a same instruction of the instruction set. [0086] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0087] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0088] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way. [0089] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A device, comprising: a custom memory synchronization controller, comprising: a synchronization component configured to: identify a first update to a first memory context entry at a first context memory associated with a first processing unit; and cause the first memory context entry at a second context memory associated with a second processing unit to be updated with the first update, wherein the first processing unit and the second processing unit perform parallel processing of an instructions set.

2. The device of claim 1, wherein the custom memory synchronization controller further comprises: a first update detector configured to: update a first bitmap value corresponding to the first update to the first memory context entry at the first context memory associated with the first processing unit, wherein the first update detector is coupled to the first context memory.

3. The device of claim 1, wherein the custom memory synchronization controller further comprises: a second update detector configured to: identify a second update to a second memory context entry at a second context memory associated with the second processing unit; and cause the second memory context entry at the first context memory associated with the first processing unit to be updated with the second update.

4. The device of claim 3, wherein second update detector is further configured to: update a second bitmap value corresponding to the second update to the second memory context entry at the second context memory associated with the second processing unit, wherein the second update detector is coupled to the second context memory.

5. The device of claim 4, wherein the synchronization component is further configured to: identify when bitmap values indicate a context collision associated with a same location in the first context memory and the second context memory.

6. The device of claim 5, wherein the synchronization component is further configured to: send an interrupt signal indicating the context collision associated with the same location in the first context memory and the second context memory to the first processing unit.

7. The device of claim 5, wherein the context collision indicates both the first processing unit and the second processing unit perform operations on a same instruction of the instruction set.

8. An apparatus for wireless communication, comprising: a first processing unit configured to: perform first robust header compression (ROHC) operations on a ROHC packet header; and a second processing unit configured to: perform second ROHC operations on the ROHC packet header; a custom memory synchronization controller, comprising: a synchronization component configured to: identify a first update to a first memory context entry at a first context memory associated with a first processing unit; and cause the first memory context entry at a second context memory associated with the second processing unit to be updated with the first update, wherein the first processing unit and the second processing unit perform parallel processing of an instruction set.

9. The apparatus of claim 8, wherein the custom memory synchronization controller further comprises: a first update detector configured to: update a first bitmap value corresponding to the first update to the first memory context entry at the first context memory associated with the first processing unit, wherein the first update detector is coupled to the first context memory.

10. The apparatus of claim 8, wherein the custom memory synchronization controller further comprises: a second update detector configured to: identify a second update to a second memory context entry at a second context memory associated with the second processing unit; and cause the second memory context entry at the first context memory associated with the first processing unit to be updated with the second update.

11. The apparatus of claim 10, wherein the second update detector is further configured to: update a second bitmap value corresponding to the second update to the second memory context entry at the second context memory associated with the second processing unit, wherein the second update detector is coupled to the second context memory.

12. The apparatus of claim 11, wherein the synchronization component is further configured to: identify when bitmap values indicate a context collision associated with a same location in the first context memory and the second context memory.

13. The apparatus of claim 12, wherein the synchronization component is further configured to: send an interrupt signal indicating the context collision associated with the same location in the first context memory and the second context memory to the first processing unit.

14. The apparatus of claim 12, wherein the context collision indicates both the first processing unit and the second processing unit perform operations on a same instruction of the instruction set.

15. A method of wireless communication of a user equipment, comprising: identifying, by a synchronization component of a custom memory synchronization controller, a first update to a first memory context entry at a first context memory associated with a first processing unit; and causing, by the synchronization component of the custom memory synchronization controller, the first memory context entry at a second context memory associated with a second processing unit to be updated with the first update, wherein the first processing unit and the second processing unit perform parallel processing of an instructions set.

16. The method of claim 15, further comprising: updating, by a first update detector of the custom memory synchronization controller, a first bitmap value corresponding to the first update to the first memory context entry at the first context memory associated with the first processing unit, wherein the first update detector is coupled to the first context memory.

17. The method of claim 15, further comprising: identifying, by a second update detector of the custom memory synchronization controller, a second update to a second memory context entry at a second context memory associated with the second processing unit; and causing, by the second update detector of the custom memory synchronization controller, the second memory context entry at the first context memory associated with the first processing unit to be updated with the second update.

18. The method of claim 17, further comprising updating, by the second update detector of the custom memory synchronization controller, a second bitmap value corresponding to the second update to the second memory context entry at the second context memory associated with the second processing unit, wherein the second update detector is coupled to the second context memory.

19. The method of claim 18, further comprising: identifying, by the synchronization component of the custom memory synchronization controller, when bitmap values indicate a context collision associated with a same location in the first context memory and the second context memory; and sending, by the synchronization component of the custom memory synchronization controller, an interrupt signal indicating the context collision associated with a same location in the first context memory and the second context memory to the first processing unit.

20. The method of claim 19, wherein the context collision indicates both the first processing unit and the second processing unit perform operations on a same instruction of the instruction set.