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WO2025008545A1 - Photonic chip having a heterogeneous iii-v semiconductor structure on a second semiconductor - Google Patents

Photonic chip having a heterogeneous iii-v semiconductor structure on a second semiconductor Download PDF

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Publication number
WO2025008545A1
WO2025008545A1 PCT/EP2024/069135 EP2024069135W WO2025008545A1 WO 2025008545 A1 WO2025008545 A1 WO 2025008545A1 EP 2024069135 W EP2024069135 W EP 2024069135W WO 2025008545 A1 WO2025008545 A1 WO 2025008545A1
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Prior art keywords
waveguide
layer
iii
confinement layer
photonic chip
Prior art date
Application number
PCT/EP2024/069135
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French (fr)
Inventor
Joan RAMIREZ
Claire BESANCON
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Thales
Commissariat à l'Energie Atomique et aux Energies Alternatives
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Publication of WO2025008545A1 publication Critical patent/WO2025008545A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/021—Silicon based substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
    • H01S5/04257—Electrodes, e.g. characterised by the structure characterised by the configuration having positive and negative electrodes on the same side of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/1028—Coupling to elements in the cavity, e.g. coupling to waveguides adjacent the active region, e.g. forward coupled [DFC] structures
    • H01S5/1032—Coupling to elements comprising an optical axis that is not aligned with the optical axis of the active region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2004—Confining in the direction perpendicular to the layer structure
    • H01S5/2018—Optical confinement, e.g. absorbing-, reflecting- or waveguide-layers
    • H01S5/2031—Optical confinement, e.g. absorbing-, reflecting- or waveguide-layers characterized by special waveguide layers, e.g. asymmetric waveguide layers or defined bandgap discontinuities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/2202—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure by making a groove in the upper laser structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/2203—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure with a transverse junction stripe [TJS] structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227—Buried mesa structure ; Striped active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/3211—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures characterised by special cladding layers, e.g. details on band-discontinuities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/3211—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures characterised by special cladding layers, e.g. details on band-discontinuities
    • H01S5/3213—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures characterised by special cladding layers, e.g. details on band-discontinuities asymmetric clading layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2301/00—Functional characteristics
    • H01S2301/17—Semiconductor lasers comprising special layers
    • H01S2301/176—Specific passivation layers on surfaces other than the emission facet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/2205—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers
    • H01S5/2214—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers based on oxides or nitrides

Definitions

  • the invention relates to a photonic chip with a heterogeneous structure of III-V semiconductor on a second semiconductor allowing efficient transmission, in particular adiabatic, without loss, of an optical mode between a waveguide made of a first III-V semiconductor material and a waveguide made of a second semiconductor material.
  • III-V semiconductor structures are known for the production of efficient optical sources. Heterogeneous structures are therefore developed which integrate III-V type semiconductors on silicon wafers. These heterogeneous structures therefore combine the versatility, high density, and scalability of CMOS technology with the optical gain of III-V semiconductor materials.
  • FIG. 1 illustrates an example of a heterogeneous structure 50 according to the prior art.
  • the structure 50 comprises a first waveguide 51 made of III-V semiconductor material coupled to a second waveguide 52 made of silicon material.
  • the III-V waveguide 51 comprises a first p-doped confinement layer 510 and a second n-doped confinement layer 512, on either side of an active layer 511 containing multiple quantum wells (or MQWs for “Multi Quantum Wells” in English).
  • the first p-doped confinement layer 510 comprises on its external face a highly p-doped layer 508 so as to improve electrical contact with an electrode layer 506.
  • Electrodes 534, 536 allow an electrical connection of the second n-doped confinement layer 512, in particular at a highly n-doped zone of the second n-doped confinement layer.
  • the second optical guide 52 comprises a silicon layer 520.
  • the guides 51, 52 are separated by a material 55 made of silicon oxide SiO2 and are sufficiently close to allow optical coupling between them.
  • III-V quantum well structures are susceptible to the phenomenon of interval band absorption (or IVBA) in which the light signal interacts with the p-doping of the first p-doped confinement layer.
  • IVBA interval band absorption
  • the first p-doped confinement layer 510 is relatively thicker than the second n-doped confinement layer 512 in order to distance the heavily p-doped layer 508 from the active layer 511.
  • the first confinement layer 510 may further have a doping gradient from the heavily doped layer 508 to the active layer 511 to further attenuate the IVBA phenomenon.
  • the optical signal produced by the quantum wells of the active layer 511 then interacts mainly with the lightly p-doped areas of the first confinement layer 510, which allows for low or moderate absorption.
  • the III-V waveguide 51 and the silicon waveguide 52 must have equal effective propagation indices in the area, called the transition area, where the optical mode transfer must occur.
  • the effective propagation index n e ff is also known as the "mode phase constant”. It is defined by the following relationship:
  • n g is the group index and A is the wavelength of the optical signal guided by the waveguide.
  • the effective propagation index of a waveguide depends on the dimensions of the core of this waveguide and the indices of the materials forming the core and the cladding of this waveguide. It can be determined experimentally or by numerical simulation.
  • Photonic chips can be fabricated from a silicon-on-oxide (SOI) substrate.
  • the thickness of the layer in monocrystalline silicon of such an SOI substrate is typically between 220 and 300 nm.
  • the III-V waveguide 51 generally has a thickness between 2 and 3 pm.
  • Such a thickness of the III-V waveguide 51 does not allow a phase matching condition to be obtained with a silicon waveguide with a thickness between 220 and 300 nm.
  • the optical mode transmission between the III-V waveguide and the silicon waveguide could then not be done without losses.
  • the thickness of the silicon layer of the silicon guide 52 is increased compared to the conventional thickness, to reach an E2 value between 400 and 500 nm.
  • the silicon layer has in particular a thickness E2 of 500 nm which makes it possible to obtain a phase matching condition between the guides 51 , 52.
  • E2 thickness of 500 nm which makes it possible to obtain a phase matching condition between the guides 51 , 52.
  • having a thicker silicon layer than in conventional silicon photonic chips makes the manufacturing process of the heterogeneous structure 50 more complex, because it is not compatible with standard manufacturing processes which define silicon layers with a thickness of between 220 and 300 nm.
  • a photonic chip comprising a III-V/silicon heterogeneous structure is known from the publication “Membrane buried-heterostructure DFB laser with an optically coupled lll-V/Si waveguide,” T. Aihara et al. Optics Express, vol. 27, no. 25, p. 36438, Dec. 2019, doi: 10.1364/oe.27.036438.
  • This publication describes a heterogeneous structure that does not require the addition of an excess silicon thickness in the silicon waveguide at the transition zone. However, for this, the injection of current into the active layer is no longer done in a vertical direction, as is the case in the example in Figure 1, but in a horizontal direction.
  • the structure of the photonic chip in this publication is not conventional in the field of photonic components, particularly those intended for optical telecommunications.
  • the electric current flowing between the electrode of the second n-doped confinement layer and the electrode of the first p-doped confinement layer sees a greater electrical resistance than in a vertical structure, such as in the structure of Figure 1 for example.
  • a photonic chip comprising a heterogeneous III-V/silicon structure whose architecture remains compatible with the processes of industrial manufacturing of silicon photonic circuits, while limiting optical losses in the III-V structure and losses in the transmission of an optical mode between the III-V waveguide and the silicon waveguide.
  • the invention proposes a photonic chip with a heterogeneous structure of a III-V semiconductor on a second semiconductor comprising, in a stacking direction: i. a waveguide made of a first III-V semiconductor material, called a III-V waveguide, comprising a first confinement layer, an active layer and a second confinement layer, ii.
  • a waveguide made of a second semiconductor material comprising a layer of the second semiconductor material
  • the III-V waveguide further comprising a first electrode and a second electrode configured to respectively ensure electrical contact with one of said confinement layers, such that the active layer emits a light wave when an electric current flows between said electrodes through the active layer and the confinement layers
  • the first confinement layer comprising a first portion superimposed on the active layer and at least one extension, extending laterally beyond said active layer, said extension having a thickness in the stacking direction which is greater than that of the first portion, so as to define an electrical contact face located before the first portion in the stacking direction, said first electrode comprising a first contact layer coming against said electrical contact face.
  • the photonic chip according to the invention maintains a vertical injection which makes it more compatible with the industrial manufacturing processes of CMOS technologies, in particular SOI technology.
  • the thickness of the extension defines at least one staircase-shaped portion comprising a low landing separated from a high landing by a step height, the low landing comprising an external face of the first portion of the first confinement layer, the high landing comprising the contact face of the first confinement layer, the distance between the foot of the step height and the first portion being between 0 and 2 ⁇ m.
  • the distance between the foot of the step height and the first portion of the first confinement layer is equal to zero.
  • the thickness of the extension is configured to avoid an intervalence band absorption phenomenon in the III-V waveguide; and the first portion has a thickness configured for a phase matching condition between the III-V waveguide and the SC waveguide.
  • the extension has a doping profile decreasing from the contact face along said stacking direction; and the first portion of the first confinement layer has substantially constant doping.
  • the waveguides extend in a longitudinal direction, said chip comprising a transition zone in which the III-V waveguide and/or the SC waveguide have a profiling along said longitudinal direction making it possible to transmit an optical mode between the III-V waveguide and the SC waveguide.
  • said extension is at least included in said transition zone.
  • the first confinement layer consists of the first portion and has a thickness configured to avoid an intervalence band absorption phenomenon in the III-V waveguide.
  • the second confinement layer extends at least partly laterally beyond the active layer and the first confinement layer. confinement; and the second electrode comprises at least one via extending in the stacking direction, in particular on the side of the first confinement layer and the active layer.
  • said first confinement layer comprises two extensions each extending from opposite edges of said first portion of the first confinement layer.
  • FIG 1 Figure 1, already described, represents an example of a photonic chip of the prior art
  • Figure 2 represents an example of a photonic chip according to the invention
  • Figure 3 shows top views and cross-sectional views of the chip of Figure 2;
  • Figure 4 is an explanatory diagram of an electric current flowing in the chip illustrated in Figure 2;
  • FIG 5 illustrates a variant of the photonic chip of Figure 2;
  • FIG 6 Figure 6 illustrates another variation of the photonic chip of Figure 2;
  • Figure 7 is a schematic bottom view of the photonic chip illustrated in Figure 2;
  • Figure 8a shows successive views of an optical mode propagating in the photonic chip illustrated in Figure 2;
  • Figure 8b shows other successive views of an optical mode propagating in the photonic chip illustrated in Figure 2;
  • Figure 9 represents successive steps of an example of a manufacturing process for the photonic chip of Figure 2.
  • FIG. 2 shows an example of a photonic chip 10 according to an example of the invention.
  • the photonic chip 10 comprises a heterogeneous structure of III-V semiconductor on a second semiconductor.
  • the photonic chip 10 comprises a waveguide made of III-V semiconductor material, designated herein waveguide 11, and a waveguide made of a second semiconductor material.
  • the second semiconductor material is silicon.
  • the waveguide made of a second semiconductor material is designated in the following as a waveguide SC 12.
  • the waveguides 11, 12 comprise layers forming a stack.
  • the III-V waveguide 11 comprises a first confinement layer 110, an active layer 111, a second confinement layer 112.
  • the active layer 111 comprises in particular quantum wells, in particular multiple quantum wells, which make it possible to obtain an optical gain from an electric current flowing between the confinement layers 110, 112. In a manner known per se, the quantum wells then produce a light wave which will be confined in the active part 111.
  • the confinement layers 110, 112 are located respectively on either side of the active layer 111.
  • the first confinement layer 110 is located on one side of the active layer 111; the second confinement layer 112 is located on the opposite side of the active layer 111.
  • the confinement layers 110, 112 have in particular refractive indices lower than that of the active layer 111, thus making it possible to confine the light wave in the active layer 111 and to guide it.
  • the confinement layers 110, 112 have dopings of opposite types.
  • the first confinement layer 110 has a p-type doping; and the second confinement layer 112 has an n-type doping.
  • the first confinement layer 110, the active layer 111, and the second confinement layer 112 form a PIN junction.
  • the III-V material is for example indium phosphide InP.
  • the waveguide SC 12 is located after the waveguide III-V 11 in the stacking direction A.
  • the waveguide SC 12 comprises a silicon layer 120.
  • the silicon layer 120 serves in particular as a propagation medium for the light wave in the silicon photonic circuit.
  • the silicon layer 120 is located opposite the second confinement layer 112 in the stacking direction A.
  • the silicon layer 120 is in particular included in a layer of dielectric material 14 serving as a sheath for the waveguide SC 12.
  • the dielectric material is in particular silicon oxide SiO2.
  • a thin layer of dielectric material 14 separates the second confinement layer 112 of the III-V waveguide 11 from the silicon layer 120 of the SC waveguide 12, so as to allow optical coupling between the III-V waveguide 11 and the SC waveguide 12.
  • the thickness of dielectric material 14 separating the second confinement layer 112 and the silicon layer 120 may be between 5 nm and 200 nm, or even equal to 50 nm.
  • the thickness of dielectric material 14 may be greater by extending the length of an optical transition zone described later.
  • the first confinement layer 110, the active layer 111, the second confinement layer 112 of the III-V waveguide 11, the silicon layer 120 of the SC waveguide 12 form at least in part a stack of layers.
  • the layers extend in particular along parallel planes, which are in particular perpendicular to the stacking direction A.
  • III-V waveguide 11 and the SC waveguide 12 are therefore in particular located opposite each other in the stacking direction A of the layers so as to allow optical coupling between the two waveguides.
  • the photonic chip 10 comprises in particular a substrate 16 serving as a support for the photonic chip 10.
  • This substrate 16 is in particular made of silicon.
  • the substrate 16 can serve as a support for other III-V structures or other silicon photonic components, such as for example a phase modulator or a Mach-Zehnder interferometer.
  • the III-V waveguide 11 further comprises a first electrode B1 which ensures electrical contact with the first confinement layer 110; and a second electrode B2 which ensures electrical contact with the second confinement layer 112.
  • the active layer 11 can emit a light wave when a current flows between the electrodes B1, B2 through the confinement layers 110, 112.
  • the photonic chip 10 is particular in that, due to the shape of the first confinement layer 110, it does not require an excess thickness of the silicon layer for efficient optical mode transfer between the III-V waveguide 11 and the SC waveguide 12.
  • the first confinement layer 110 comprises a first portion 110a superimposed on the active layer 111, and an extension 110b which extends laterally beyond the active layer 111.
  • the extension 110b forms a second portion of the first confinement layer 110, and extends from one side of the first portion 110a of the first confinement layer 110.
  • the extension 110b extends from the first portion 110a in a transverse direction, in particular perpendicular, to the stacking direction A.
  • the extension 110b has a thickness Eb in the stacking direction A which is greater than the thickness Ea of the first portion 110a.
  • the extension 110b thus defines an electrical contact face 116 located before the first portion 110a along the stacking direction A.
  • the following faces or interfaces are located one after the other along the stacking direction A: the contact face 116 of the first stacking layer 110, an upper face 117 of the first portion 110a of the first confinement layer, the interface between the first confinement layer 110 and the active layer 111, the interface between the active layer 111 and the second confinement layer 112, the interface between the III-V waveguide 11 and the SC waveguide 12.
  • the first electrode B1 comprises a first contact layer B10 which comes against the contact face 116 of the first confinement layer 110 for an electrical connection thereof.
  • the effective propagation index of the optical mode is sensitive only to the first portion 110a. Unlike the prior art illustrated in FIG. 1, it is therefore not necessary to add an excess thickness to the silicon layer 120 compared to a conventional silicon photonic chip.
  • the thickness Ea of the first portion 110a may be adapted to ensure a phase matching condition between the III-V waveguide 11 and the SC waveguide 12. In particular, the thickness of the first portion 110a may be sufficiently small to allow a phase matching condition between the III-V waveguide 11 and the SC waveguide 12.
  • the thickness Ea of the first portion 110a of the first confinement layer 110 may be between 200 and 500 nm.
  • the extension 110b makes it possible to move a heavily doped layer of the first confinement layer 110 away from the active layer 111.
  • the extension 110b can then have a thickness Eb which makes it possible to avoid or greatly limit the phenomenon of intervalence band absorption.
  • the thickness of the protrusion 110b is sufficiently large to avoid the phenomenon of intervalence band absorption.
  • the thickness Eb of the extension 110b can be between 1 and 3 pm.
  • the thicknesses Ea, Eb are in particular defined according to the stacking direction A.
  • the photonic chip 10 is more compatible with CMOS manufacturing technologies than the chip of the prior art which comprises a III-V structure in which the injection is horizontal.
  • the extension 110b extends from an edge of the first portion 110a which is in the extension of an edge of the active layer 111. In other words, seen in the stacking direction A, the extension 110b does not cover the active layer 111, which limits the phenomenon of intervalence band absorption.
  • a staircase-shaped part is defined by the thickness Eb of the extension 110b, in particular by the first portion 110a and the second portion 110b.
  • a low landing of the stepped shape comprises the outer face 117 of the first portion 110a of the first confinement layer 110.
  • the outer face 117 of the first portion 110a is its opposite face relative to its interface with the active layer 111.
  • a high landing of the stepped shape comprises the contact face 116.
  • the high landing and the low landing are separated by a step height, which is in particular equal to the difference between the thicknesses Ea, Eb of the first portion 110a and the second portion 110b.
  • the distance between the foot of the step height and the first portion 110a is equal to zero, apart from positioning uncertainties.
  • the step height extends in particular from an edge of the first portion 110a which is in the extension of an edge of the active layer 111.
  • the distance between the foot of the step height and the first portion 110a may be greater than or equal to zero, from the edge of the first portion 110a moving away from the active layer 111.
  • the distance between the foot of the step height and the first portion 110a may be between 0 and 2 pm, depending on the size of the photonic chip 10.
  • the extension 110b of the first confinement layer 110 may have a doping profile which decreases from the contact face 116 along the stacking direction A.
  • the extension 110b is heavily doped at the contact face 116 to allow good electrical contact with the first contact layer B 10.
  • the doping of the extension 110b may range from 1x10 20 /cm 3 near the contact face 116 to 7x10 17 /cm 3 near the active layer 111.
  • the first portion 110a of the first confinement layer 110 may have a substantially constant doping, in particular substantially equal to the smallest doping value in the extension 110b.
  • the first portion 110a has a doping of 7x10 17 /cm 3 .
  • the active layer 111 may be delimited on the sides by a layer of insulating material 118.
  • the layer of insulating material 118 makes it possible to confine the light wave coming from the active layer 111 on the sides.
  • the layer of insulating material 118 extends in particular laterally from an edge of the active layer 111.
  • the extension 110b of the first confinement layer 110 comes against the layer of insulating material 118.
  • the layer of insulating material 118 extends in particular between the extension 110b of the first confinement layer 110 and the layer of dielectric material 14.
  • the layer of insulating material 118 may be made of polymer, such as benzocyclobutene (or BCB) for example, or silica SiO2 or even aluminum nitride AIN.
  • the layer of insulating material 118 may be made of a material forming a semi-insulating buried heterostructure (or SIBH for “semi insulating buried heterostructure”), such as semi-insulating indium phosphide, in particular an lnP:Fe material.
  • SIBH semi-insulating buried heterostructure
  • the second confinement layer 112 may extend laterally beyond the active layer 111 and the first confinement layer 110 for an electrical contact.
  • the second electrode B2 of the III-V waveguide comprises a via which extends in the stacking direction A, in particular on the side of the first confinement layer 110.
  • An electrical contact layer B20 is in particular deposited at the bottom of the via on the second confinement layer 112 for an electrical contact thereof.
  • a passivation layer 113 may cover the III-V/silicon heterogeneous structure.
  • the passivation layer 113 may be made of polymer, such as benzocyclobutene (or BCB) for example, or silica SiO2 or even aluminum nitride AIN.
  • Figure 3 shows a partial top view 1 of the photonic chip 10. To make the representation readable, in view 1, the passivation layer 113, the electrodes B1, B2, the first portion 110a of the first confinement layer 110 and the second confinement layer 112 are not shown.
  • the other views a, b, c, d of Figure 3 show sectional views of the photonic chip 10 taken along the corresponding lines of view 1.
  • the III-V waveguide 11 and the SC waveguide 12 extend in particular in a longitudinal direction corresponding to a direction of propagation of the light waves.
  • the longitudinal direction is perpendicular to the stacking direction A.
  • the photonic chip 10 comprises an optical transition zone 17 in which the SC waveguide 12 or the III-V waveguide 11 have a profile along the longitudinal direction allowing a transfer or coupling of optical mode from one guide to the other.
  • the cross-section of the SC waveguide 12, in particular of the silicon layer 120 gradually decreases while the cross-section of the III-V waveguide 11, in particular of the active layer 111, gradually increases.
  • the insulating layer 118 of the III-V waveguide forms a semi-insulating heterostructure, it itself has a cross-section which gradually increases, as for example shown in views a, b. Then, the cross-section of the active layer 11 gradually increases as for example shown in views c, d.
  • the first confinement layer 110 comprises the extension 110b at least in the transition zone 17, in order to improve the optical mode transfer.
  • the III-V waveguide 11 and the SC waveguide 12 have in particular constant cross-sections.
  • the optical mode is then confined in the III-V waveguide 11.
  • the III-V waveguide 11 may have a semiconductor optical amplifier function.
  • An electric current then flows between the electrodes B1, B2 of the III-V waveguide 11 to amplify the III-V light wave propagating in the III-V waveguide 11.
  • the first confinement layer 110 may also comprise the extension 110b beyond the transition zone 17.
  • the path of the electric current i flowing in the III-V structure is for example illustrated in FIG. 4.
  • the electrical resistance R1 across the first confinement layer may be about 6 Q.
  • the current injection is vertical; but the electric current also flows laterally through the section S at the interface of the first portion 110a and the second portion 110b, which notably limits the current compared to the prior art.
  • the resistance Rs of the section S can be about 5.8 ⁇ .
  • the total resistance across the first confinement layer 110 can then be 11.8 ⁇ .
  • the photonic chip 10 remains more advantageous than the prior art chip because the silicon layer can have a thickness E of 220 nm.
  • the photonic chip 10 remains more advantageous than a prior art photonic chip described above in which the current injection into the III-V structure is in a horizontal direction. For a III-V waveguide of length 500 pm, the latter has a resistance of about 25 ⁇ .
  • the photonic chip 20 has a conventional architecture of III-V/silicon heterogeneous structure.
  • the first confinement layer 110 comprises only the first portion and is devoid of the extension 110b.
  • the first confinement layer 110 can then have a thickness and a doping gradient configured to avoid the phenomenon of intervalence band absorption in the III-V waveguide 11.
  • the photonic chip 20 of FIG. 5 is also identical to the photonic chip 10 described previously. This variant has an electrical resistance similar to that of the prior art chip described in the previous paragraph, because the electric current flows mainly through the part of the III-V waveguide which is of constant section.
  • Figure 6 illustrates an example of a photonic chip 30 according to a variant in which the first confinement layer 310 comprises two extensions 310b.
  • the photonic chip 30 is otherwise identical to the photonic chip 10 described in relation to the preceding figures.
  • Each of the extensions 310b is similar to the extension 110b of the photonic chip 10 described in relation to the preceding figures.
  • the presence of two extensions 310b makes it possible to reduce by a factor of 2 the contribution of the p-doped part in the total electrical resistance seen by the current injected into the III-V structure.
  • Figure 7 shows a partial bottom view of the photonic chip 10, in which only the silicon layer 120 of the waveguide SC 12 and the edges of the assembly formed by the active layer 111 and the layer of insulating material 118 are shown.
  • the photonic chip 10 extends along a plane (X, Z) perpendicular to the stacking direction A.
  • the direction Z corresponds to the longitudinal direction of the photonic chip 10;
  • the direction X corresponds to a transverse direction of the photonic chip 10.
  • Each axis X, Z bears a scale in pm.
  • the silicon layer 120 is profiled so that its section decreases; over a second length L2, the assembly formed by the active layer 111 and the layer of insulating material 118 is profiled.
  • Figures 8a, 8b represent the spatial distribution of the optical mode in cross sections taken at successive Z positions of Figure 7, during a transmission of an optical mode from the SC waveguide 12 to the III-V waveguide 11.
  • the origin of the X axis corresponds to the point with coordinate 4.5 on the X axis of Figure 7.
  • a progressive transmission of the optical mode is observed from the SC waveguide 12 to the III-V waveguide 11.
  • the photonic chip 10 notably allows an efficient optical mode transfer between the III-V waveguide and the SC waveguide, notably a 97% transmission.
  • a III-V structure formed from a p-doped layer 4, an intermediate layer 3 and an n-doped layer 2 is first formed by growth on a III-V substrate, in particular indium phosphide InP. The assembly is then fixed by bonding to a silicon photonic chip. The III-V substrate is then removed. Alternatively, a thin layer of III-V substrate can be bonded to the silicon photonic chip. Growth is then carried out from this thin layer of III-V substrate directly onto the silicon substrate (view a). Then, a dielectric mask M is deposited on the p-doped layer 4 (view b).
  • This mask M makes it possible to define by etching, the active layer 111 in the intermediate layer 3.
  • the n-doped layer then forms the second confinement layer 112.
  • An insulating material is epitaxially grown around the active layer 111 to form the insulating material layer 118 (view c).
  • the mask M is removed.
  • an additional p-doped layer of the layer 4 is grown (view d).
  • an optional layer of quaternary material 5 can be deposited to cover the initial p-doped layer 4.
  • This layer of quaternary material 5 is in particular made of a GalnAsP alloy. It forms a sacrificial layer which facilitates the manufacturing process.
  • the first confinement layer 110 is then defined by etching (view e). A portion of the insulating material 118 is then removed to define locations where the contact layer B20 is deposited on the second confinement layer 112; and the contact layer B10 is deposited on the contact face 116 of the first confinement layer 110.
  • the second semiconductor material is for example silicon, germanium, silicon nitride or lithium niobate or an alloy thereof.
  • the second semiconductor material may be any semiconductor material suitable for the confinement and propagation of an optical mode in the waveguide SC.
  • such a material has a refractive index sufficiently high to confine an optical mode, in particular a refractive index greater than or equal to 2.
  • the second material is an indirect gap semiconductor, which makes it unfavorable for the production of laser components or optical amplification.
  • the second material may be a direct gap material, but whose physical characteristics are unfavorable for the generation of a laser or optical amplification.
  • the III-V structure overcomes the inadequacies of the second semiconductor material.

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Abstract

The invention relates to a photonic chip (10) having a heterogeneous III-V semiconductor structure on a second semiconductor comprising, in a stacking direction (Δ): a waveguide (11) made of a first III-V semiconductor material, referred to as the lll-V waveguide, comprising a first confinement layer (110), an active layer (111) and a second confinement layer (112), a waveguide (12) made of a second semiconductor material, referred to as the SC waveguide, comprising a layer (120) of the second semiconductor material. The first confinement layer (110) comprising a first portion (110a) on top of the active layer (111) and at least one extension (110b) extending laterally beyond the active layer (111), the extension (110b) having a thickness (Eb) in the stacking direction that is greater than that (Ea) of the first portion (110a) so as to define an electrical contact face (116) located before the first portion (110a) in the stacking direction (Δ).

Description

DESCRIPTION DESCRIPTION

Titre de l’invention : Puce photonique à structure hétérogène de semi- conducteur lll-V sur un deuxième semi-conducteur Title of the invention: Photonic chip with heterogeneous structure of III-V semiconductor on a second semiconductor

[0001] L’invention concerne une puce photonique à structure hétérogène de semi- conducteur lll-V sur un deuxième semi-conducteur permettant une transmission efficace, notamment adiabatique, sans perte, d’un mode optique entre un guide d’onde en un premier matériau semi-conducteur lll-V et un guide d’onde en un deuxième matériau semi-conducteur. [0001] The invention relates to a photonic chip with a heterogeneous structure of III-V semiconductor on a second semiconductor allowing efficient transmission, in particular adiabatic, without loss, of an optical mode between a waveguide made of a first III-V semiconductor material and a waveguide made of a second semiconductor material.

[0002] Il existe un intérêt pour des circuits photoniques intégrés sur des puces en silicium utilisant des guides optiques en silicium. De tels circuits photoniques ont pour avantage d’être réalisables avec les lignes de fabrication à grande échelle des technologies CMOS bien connues. Cependant, le silicium est un semi-conducteur qui se prête mal à une utilisation comme source laser ou amplificateur optique, du fait de certains de ses paramètres physiques, notamment son gap indirect. [0002] There is interest in photonic circuits integrated on silicon chips using silicon optical guides. Such photonic circuits have the advantage of being achievable with the large-scale manufacturing lines of well-known CMOS technologies. However, silicon is a semiconductor that is poorly suited for use as a laser source or optical amplifier, due to some of its physical parameters, in particular its indirect gap.

[0003] Or, les structures en semi-conducteurs lll-V sont connues pour la réalisation de sources optiques efficaces. Des structures hétérogènes sont donc développées qui intègrent des semi-conducteurs de type lll-V sur des plaques de silicium. Ces structures hétérogènes combinent donc la versatilité, la haute densité, et la scalabilité de la technologie CMOS avec le gain optique des matériaux semi- conducteurs lll-V. [0003] However, III-V semiconductor structures are known for the production of efficient optical sources. Heterogeneous structures are therefore developed which integrate III-V type semiconductors on silicon wafers. These heterogeneous structures therefore combine the versatility, high density, and scalability of CMOS technology with the optical gain of III-V semiconductor materials.

[0004] La figure 1 illustre un exemple de structure hétérogène 50 selon l’art antérieur. La structure 50 comprend un premier guide d’onde 51 en matériau semi-conducteur lll-V couplé à un deuxième guide d’onde 52 en matériau silicium. Le guide d’onde III- V 51 comprend une première couche de confinement 510 dopée p et une deuxième couche de confinement 512 dopée n, de part et d’autre d’une couche active 511 contenant des puits quantiques multiples (ou MQWs pour « Multi Quantum Wells » en anglais). La première couche de confinement dopée p 510 comprend sur sa face externe une couche de fort dopage p 508 de manière à améliorer un contact électrique avec une couche d’électrode 506. Des électrodes 534, 536 permettent une connexion électrique de la deuxième couche de confinement dopée n 512, notamment au niveau d’une zone fortement dopée n de la deuxième couche de confinement n. Le deuxième guide optique 52 comprend une couche de silicium 520. Les guides 51 , 52 sont séparés par un matériau 55 en oxyde de silicium SiO2 et sont suffisamment proches pour permettre un couplage optique entre eux. [0004] Figure 1 illustrates an example of a heterogeneous structure 50 according to the prior art. The structure 50 comprises a first waveguide 51 made of III-V semiconductor material coupled to a second waveguide 52 made of silicon material. The III-V waveguide 51 comprises a first p-doped confinement layer 510 and a second n-doped confinement layer 512, on either side of an active layer 511 containing multiple quantum wells (or MQWs for “Multi Quantum Wells” in English). The first p-doped confinement layer 510 comprises on its external face a highly p-doped layer 508 so as to improve electrical contact with an electrode layer 506. Electrodes 534, 536 allow an electrical connection of the second n-doped confinement layer 512, in particular at a highly n-doped zone of the second n-doped confinement layer. The second optical guide 52 comprises a silicon layer 520. The guides 51, 52 are separated by a material 55 made of silicon oxide SiO2 and are sufficiently close to allow optical coupling between them.

[0005] Typiquement, les structures lll-V à puits quantiques sont sensibles au phénomène d’absorption de bande d’intervalence (ou IVBA pour « intervalence band absorption » en anglais) dans lequel le signal lumineux interagit avec le dopage p de la première couche de confinement dopée p. Cela entraine des pertes optiques qui dégradent les performances du laser. Pour minimiser cet effet, la première couche de confinement dopée p 510 est relativement plus épaisse que la deuxième couche de confinement dopée n 512 afin d’éloigner de la couche active 511 la couche fortement dopée p 508. La première couche de confinement 510 peut en outre présenter un gradient de dopage de la couche fortement dopée 508 vers la couche active 511 pour atténuer encore le phénomène IVBA. Le signal optique produit par les puits quantiques de la couche active 511 interagit alors principalement avec les zones faiblement dopées p de la première couche de confinement 510, ce qui permet une absorption faible ou modérée. [0005] Typically, III-V quantum well structures are susceptible to the phenomenon of interval band absorption (or IVBA) in which the light signal interacts with the p-doping of the first p-doped confinement layer. This results in optical losses that degrade laser performance. To minimize this effect, the first p-doped confinement layer 510 is relatively thicker than the second n-doped confinement layer 512 in order to distance the heavily p-doped layer 508 from the active layer 511. The first confinement layer 510 may further have a doping gradient from the heavily doped layer 508 to the active layer 511 to further attenuate the IVBA phenomenon. The optical signal produced by the quantum wells of the active layer 511 then interacts mainly with the lightly p-doped areas of the first confinement layer 510, which allows for low or moderate absorption.

[0006] Or, pour un transfert de mode optique efficace entre le guide d’onde lll-V 51 et le guide d’onde silicium 52, une condition d’accord de phase doit être respectée. A cet effet, le guide d’onde lll-V 51 et le guide d’onde silicium 52 doivent présenter des indices effectifs de propagation égaux dans la zone, dite zone de transition, où le transfert de mode optique doit se produire. L'indice effectif de propagation neff est aussi connu sous le nom de « constante de phase du mode ». Il est défini par la relation suivante : [0006] Now, for an efficient optical mode transfer between the III-V waveguide 51 and the silicon waveguide 52, a phase matching condition must be respected. For this purpose, the III-V waveguide 51 and the silicon waveguide 52 must have equal effective propagation indices in the area, called the transition area, where the optical mode transfer must occur. The effective propagation index n e ff is also known as the "mode phase constant". It is defined by the following relationship:

[Math 1]

Figure imgf000004_0001
où ng est l'indice de groupe et A est la longueur d'onde du signal optique guidé par le guide d’onde. L'indice effectif de propagation d'un guide d'onde dépend des dimensions du cœur de ce guide d'onde et des indices des matériaux formant le cœur et la gaine de ce guide d'onde. Il peut être déterminé expérimentalement ou par simulation numérique. [Math 1]
Figure imgf000004_0001
where n g is the group index and A is the wavelength of the optical signal guided by the waveguide. The effective propagation index of a waveguide depends on the dimensions of the core of this waveguide and the indices of the materials forming the core and the cladding of this waveguide. It can be determined experimentally or by numerical simulation.

[0007] Les puces photoniques peuvent être fabriquées à partir d'un substrat silicium sur oxyde (ou SOI pour « Silicon On Insulator » en anglais). L'épaisseur de la couche en silicium monocristallin d'un tel substrat SOI est typiquement compris entre 220 et 300 nm. Dans la structure de la figure 1 , le guide d’onde lll-V 51 a généralement une épaisseur entre 2 et 3 pm. Une telle épaisseur de guide d’onde lll-V 51 ne permet pas d’obtenir une condition d’accord de phase avec un guide d’onde silicium d’épaisseur entre 220 et 300 nm. La transmission de mode optique entre le guide d’onde lll-V et le guide d’onde silicium ne pourrait alors pas se faire sans pertes. Pour pallier cela, dans la figure 1 , l’épaisseur de la couche silicium du guide silicium 52 est augmentée par rapport à l’épaisseur classique, pour atteindre une valeur E2 comprise entre 400 et 500 nm. Dans la structure hétérogène 50 illustrée en figure 1 , la couche de silicium a en particulier une épaisseur E2 de 500 nm qui permet d’obtenir une condition d’accord de phase entre les guides 51 , 52. Cependant, le fait d’avoir une couche de silicium plus épaisse que dans les puces photoniques en silicium classiques rend plus complexe le procédé de fabrication de la structure hétérogène 50, car il n’est pas compatible avec les procédés de fabrication standards qui définissent des couches de silicium d’épaisseur comprise entre 220 et 300 nm. [0007] Photonic chips can be fabricated from a silicon-on-oxide (SOI) substrate. The thickness of the layer in monocrystalline silicon of such an SOI substrate is typically between 220 and 300 nm. In the structure of FIG. 1 , the III-V waveguide 51 generally has a thickness between 2 and 3 pm. Such a thickness of the III-V waveguide 51 does not allow a phase matching condition to be obtained with a silicon waveguide with a thickness between 220 and 300 nm. The optical mode transmission between the III-V waveguide and the silicon waveguide could then not be done without losses. To overcome this, in FIG. 1 , the thickness of the silicon layer of the silicon guide 52 is increased compared to the conventional thickness, to reach an E2 value between 400 and 500 nm. In the heterogeneous structure 50 illustrated in FIG. 1 , the silicon layer has in particular a thickness E2 of 500 nm which makes it possible to obtain a phase matching condition between the guides 51 , 52. However, having a thicker silicon layer than in conventional silicon photonic chips makes the manufacturing process of the heterogeneous structure 50 more complex, because it is not compatible with standard manufacturing processes which define silicon layers with a thickness of between 220 and 300 nm.

[0008] On connait une puce photonique comprenant une structure hétérogène III- V/silicium à partir de la publication “Membrane buried-heterostructure DFB laser with an optically coupled lll-V/Si waveguide,” T. Aihara et al. Optics Express, vol. 27, no. 25, p. 36438, Dec. 2019, doi: 10.1364/oe.27.036438. Cette publication décrit une structure hétérogène qui ne nécessite pas l’ajout d’une surépaisseur de silicium dans le guide d’onde silicium au niveau de la zone de transition. Cependant, pour cela, l’injection de courant dans la couche active ne se fait plus suivant une direction verticale, comme c’est le cas dans l’exemple de la figure 1 , mais suivant une direction horizontale. La structure de la puce photonique de cette publication n’est pas classique dans le domaine des composants photoniques, notamment ceux destinés aux télécommunications optiques. Le courant électrique circulant entre l’électrode de la deuxième couche de confinement dopée n et l’électrode de la première couche de confinement dopée p voit une résistance électrique plus grande que dans une structure verticale, telle que dans la structure de la figure 1 par exemple. [0008] A photonic chip comprising a III-V/silicon heterogeneous structure is known from the publication “Membrane buried-heterostructure DFB laser with an optically coupled lll-V/Si waveguide,” T. Aihara et al. Optics Express, vol. 27, no. 25, p. 36438, Dec. 2019, doi: 10.1364/oe.27.036438. This publication describes a heterogeneous structure that does not require the addition of an excess silicon thickness in the silicon waveguide at the transition zone. However, for this, the injection of current into the active layer is no longer done in a vertical direction, as is the case in the example in Figure 1, but in a horizontal direction. The structure of the photonic chip in this publication is not conventional in the field of photonic components, particularly those intended for optical telecommunications. The electric current flowing between the electrode of the second n-doped confinement layer and the electrode of the first p-doped confinement layer sees a greater electrical resistance than in a vertical structure, such as in the structure of Figure 1 for example.

[0009] Il est donc recherché une puce photonique comprenant une structure hétérogène lll-V/ silicium dont l’architecture reste compatible avec les procédés de fabrication industrielle des circuits photoniques en silicium, tout en limitant les pertes optiques dans la structure lll-V et les pertes dans la transmission d’un mode optique entre le guide d’onde lll-V et le guide d’onde silicium. [0009] A photonic chip is therefore sought comprising a heterogeneous III-V/silicon structure whose architecture remains compatible with the processes of industrial manufacturing of silicon photonic circuits, while limiting optical losses in the III-V structure and losses in the transmission of an optical mode between the III-V waveguide and the silicon waveguide.

[0010] A cet effet, l’invention propose une puce photonique à structure hétérogène de semi-conducteur lll-V sur un deuxième semi-conducteur comprenant, suivant une direction d’empilement : i. un guide d’onde en un premier matériau semi-conducteur lll-V, dit guide d’onde lll-V, comportant une première couche de confinement, une couche active et une deuxième couche de confinement, ii. un guide d’onde en un deuxième matériau semi-conducteur, dit guide d’onde SC, comportant une couche du deuxième matériau semi-conducteur, le guide d’onde lll-V comprenant en outre une première électrode et une deuxième électrode configurées pour respectivement assurer un contact électrique avec une desdites couches de confinement, de sorte que la couche active émette une onde lumineuse lorsqu’un courant électrique circule entre lesdites électrodes à travers la couche active et les couches de confinement, la première couche de confinement comprenant une première portion superposée à la couche active et au moins une extension, s’étendant latéralement au-delà de ladite couche active, ladite extension ayant une épaisseur suivant la direction d’empilement qui est supérieure à celle de la première portion, de manière à définir une face de contact électrique située avant la première portion suivant la direction d’empilement, ladite première électrode comprenant une première couche de contact venant contre ladite face de contact électrique. [0010] For this purpose, the invention proposes a photonic chip with a heterogeneous structure of a III-V semiconductor on a second semiconductor comprising, in a stacking direction: i. a waveguide made of a first III-V semiconductor material, called a III-V waveguide, comprising a first confinement layer, an active layer and a second confinement layer, ii. a waveguide made of a second semiconductor material, called an SC waveguide, comprising a layer of the second semiconductor material, the III-V waveguide further comprising a first electrode and a second electrode configured to respectively ensure electrical contact with one of said confinement layers, such that the active layer emits a light wave when an electric current flows between said electrodes through the active layer and the confinement layers, the first confinement layer comprising a first portion superimposed on the active layer and at least one extension, extending laterally beyond said active layer, said extension having a thickness in the stacking direction which is greater than that of the first portion, so as to define an electrical contact face located before the first portion in the stacking direction, said first electrode comprising a first contact layer coming against said electrical contact face.

[0011] En décalant une partie de l’épaisseur de la première couche de confinement sur le côté par rapport à la couche active, on limite l’influence de cette partie sur l’indice effectif de propagation du guide d’onde lll-V. L’indice effectif de propagation du guide d’onde lll-V peut alors être inférieur à l’indice effectif de propagation du guide d’onde lll-V 51 de la structure hétérogène lll-V / silicium de l’art antérieur illustrée en figure 1 . Ainsi, il n’est plus nécessaire de rajouter une surcouche sur la couche de silicium du guide d’onde SC pour équilibrer les indices effectifs de propagation entre le guide d’onde lll-V et le guide d’onde SC. En outre, par rapport à la structure lll-V de l’art antérieur dans laquelle l’injection de courant dans la couche active est horizontale, la puce photonique selon l’invention garde une injection verticale qui la rend plus compatible avec les processus de fabrication industrielle des technologies CMOS, en particulier la technologie SOI. [0011] By offsetting a portion of the thickness of the first confinement layer to the side relative to the active layer, the influence of this portion on the effective propagation index of the III-V waveguide is limited. The effective propagation index of the III-V waveguide can then be lower than the effective propagation index of the III-V waveguide 51 of the prior art III-V/silicon heterogeneous structure illustrated in FIG. 1 . Thus, it is no longer necessary to add an overlayer on the silicon layer of the SC waveguide to balance the effective propagation indices between the III-V waveguide and the SC waveguide. Furthermore, compared to the prior art III-V structure in which the injection of current into the layer active is horizontal, the photonic chip according to the invention maintains a vertical injection which makes it more compatible with the industrial manufacturing processes of CMOS technologies, in particular SOI technology.

[0012] Selon un mode de réalisation, l’épaisseur de l’extension définit au moins une partie en forme d’escalier comprenant un palier bas séparé d’un palier haut par une hauteur de marche, le palier bas comprenant une face externe de la première portion de la première couche de confinement, le palier haut comprenant la face de contact de la première couche de confinement, la distance entre le pied de la hauteur de marche et la première portion étant comprise entre 0 et 2 pm. [0012] According to one embodiment, the thickness of the extension defines at least one staircase-shaped portion comprising a low landing separated from a high landing by a step height, the low landing comprising an external face of the first portion of the first confinement layer, the high landing comprising the contact face of the first confinement layer, the distance between the foot of the step height and the first portion being between 0 and 2 μm.

[0013] Selon une variante, la distance entre le pied de la hauteur de marche et la première portion de la première couche de confinement est égale à zéro. [0013] According to a variant, the distance between the foot of the step height and the first portion of the first confinement layer is equal to zero.

[0014] Selon un mode de réalisation, l’épaisseur de l’extension est configurée pour éviter un phénomène d’absorption de bande d’intervalence dans le guide d’onde III- V ; et la première portion a une épaisseur configurée pour une condition d'accord de phase entre le guide d’onde lll-V et le guide d’onde SC. [0014] According to one embodiment, the thickness of the extension is configured to avoid an intervalence band absorption phenomenon in the III-V waveguide; and the first portion has a thickness configured for a phase matching condition between the III-V waveguide and the SC waveguide.

[0015] Selon un mode de réalisation, l’extension présente un profil de dopage diminuant depuis la face de contact suivant ladite direction d’empilement ; et la première portion de la première couche de confinement présente un dopage sensiblement constant. [0015] According to one embodiment, the extension has a doping profile decreasing from the contact face along said stacking direction; and the first portion of the first confinement layer has substantially constant doping.

[0016] Selon un mode de réalisation, les guides d’onde s’étendent suivant une direction longitudinale, ladite puce comprenant une zone de transition dans laquelle le guide d’onde lll-V et/ou le guide d’onde SC présentent un profilage le long de ladite direction longitudinale permettant de transmettre un mode optique entre le guide d’onde lll-V et le guide d’onde SC. [0016] According to one embodiment, the waveguides extend in a longitudinal direction, said chip comprising a transition zone in which the III-V waveguide and/or the SC waveguide have a profiling along said longitudinal direction making it possible to transmit an optical mode between the III-V waveguide and the SC waveguide.

[0017] Selon une variante, la dite extension est au moins comprise dans ladite zone de transition. [0017] According to a variant, said extension is at least included in said transition zone.

[0018] Selon une variante, hors de ladite zone de transition, la première couche de confinement consiste en la première portion et a une épaisseur configurée pour éviter un phénomène d’absorption de bande d’intervalence dans le guide d’onde lll-V. [0018] According to a variant, outside said transition zone, the first confinement layer consists of the first portion and has a thickness configured to avoid an intervalence band absorption phenomenon in the III-V waveguide.

[0019] Selon un mode de réalisation, la deuxième couche de confinement s’étend au moins en partie latéralement au-delà de la couche active et de la première couche de confinement ; et la deuxième électrode comprend au moins un via s’étendant suivant la direction d’empilement, notamment du côté de la première couche de confinement et de la couche active. [0019] According to one embodiment, the second confinement layer extends at least partly laterally beyond the active layer and the first confinement layer. confinement; and the second electrode comprises at least one via extending in the stacking direction, in particular on the side of the first confinement layer and the active layer.

[0020] Selon un mode de réalisation, la dite première couche de confinement comprend deux extensions s’étendant chacune depuis des bords opposés de ladite première portion de la première couche de confinement. [0020] According to one embodiment, said first confinement layer comprises two extensions each extending from opposite edges of said first portion of the first confinement layer.

[0021] D’autres caractéristiques et avantages de la présente invention apparaîtront mieux à la lecture de la description qui suit en relation aux figures annexées suivantes : [0021] Other features and advantages of the present invention will become more apparent upon reading the description which follows in relation to the following appended figures:

[Fig 1] : la figure 1 , déjà décrite, représente un exemple de puce photonique de l’art antérieur ; [Fig 1]: Figure 1, already described, represents an example of a photonic chip of the prior art;

[Fig 2] : la figure 2 représente un exemple de puce photonique selon l’invention ;[Fig 2]: Figure 2 represents an example of a photonic chip according to the invention;

[Fig 3] : la figure 3 représente des vues de dessus et des vues de coupe de la puce de la figure 2 ; [Fig 3]: Figure 3 shows top views and cross-sectional views of the chip of Figure 2;

[Fig 4] : la figure 4 est un schéma explicatif d’un courant électrique circulant dans la puce illustrée en figure 2 ; [Fig 4]: Figure 4 is an explanatory diagram of an electric current flowing in the chip illustrated in Figure 2;

[Fig 5] : la figure 5 illustre une variante de la puce photonique de la figure 2 ; [Fig 5]: Figure 5 illustrates a variant of the photonic chip of Figure 2;

[Fig 6] : la figure 6 illustre une autre variante de la puce photonique de la figure 2 ;[Fig 6]: Figure 6 illustrates another variation of the photonic chip of Figure 2;

[Fig 7] : la figure 7 est une vue de dessous schématique de la puce photonique illustrée en figure 2 ; [Fig 7]: Figure 7 is a schematic bottom view of the photonic chip illustrated in Figure 2;

[Fig 8a] : la figure 8a présente des vues successives d’un mode optique se propageant dans la puce photonique illustrée en figure 2 ; [Fig 8a]: Figure 8a shows successive views of an optical mode propagating in the photonic chip illustrated in Figure 2;

[Fig 8b] : la figure 8b présente d’autres vues successives d’un mode optique se propageant dans la puce photonique illustrée en figure 2 ; [Fig 8b]: Figure 8b shows other successive views of an optical mode propagating in the photonic chip illustrated in Figure 2;

[Fig 9] : la figure 9 représente des étapes successives d’un exemple de procédé de fabrication de la puce photonique de la figure 2. [Fig 9]: Figure 9 represents successive steps of an example of a manufacturing process for the photonic chip of Figure 2.

[0022] La figure 2 représente un exemple de puce photonique 10 selon un exemple de l’invention. La puce photonique 10 comprend une structure hétérogène de semi- conducteur lll-V sur un deuxième semi-conducteur. Ainsi, la puce photonique 10 comprend un guide d’onde en matériau semi-conducteur lll-V, désigné dans ce qui suit guide d’onde lll-V 11 , et un guide d’onde en un deuxième matériau semi- conducteur. En particulier, le deuxième matériau semi-conducteur est du silicium. Le guide d’onde en deuxième matériau semi-conducteur est désigné dans ce qui suit guide d’onde SC 12. Les guides d’ondes 11 , 12 comprennent des couches formant un empilement. [0022] Figure 2 shows an example of a photonic chip 10 according to an example of the invention. The photonic chip 10 comprises a heterogeneous structure of III-V semiconductor on a second semiconductor. Thus, the photonic chip 10 comprises a waveguide made of III-V semiconductor material, designated herein waveguide 11, and a waveguide made of a second semiconductor material. In particular, the second semiconductor material is silicon. The waveguide made of a second semiconductor material is designated in the following as a waveguide SC 12. The waveguides 11, 12 comprise layers forming a stack.

[0023] Suivant une direction d’empilement A, le guide d’onde lll-V 11 comprend une première couche de confinement 110, une couche active 111 , une deuxième couche de confinement 112. La couche active 111 comprend notamment des puits quantiques, en particulier des puits quantiques multiples, qui permettent d’obtenir un gain optique à partir d’un courant électrique circulant entre les couches de confinement 110, 112. De manière connue en soi, les puits quantiques produisent alors une onde lumineuse qui va être confinée dans la partie active 111. Les couches de confinement 110, 112 sont situées respectivement de part et d’autre de la couche active 111. Notamment, la première couche de confinement 110 est située d’un côté de la couche active 111 ; la deuxième couche de confinement 112 est située du côté opposé de la couche active 111. Les couches de confinement 110, 112 ont en particulier des indices de réfraction inférieurs à celui de la couche active 111 , permettant ainsi de confiner l’onde lumineuse dans la couche active 111 et de la guider. En particulier, les couches de confinement 110, 112 présentent des dopages de types opposés. Par exemple, la première couche de confinement 110 a un dopage de type p ; et la deuxième couche de confinement 112 a un dopage de type n. En particulier, la première couche de confinement 110, la couche active 111 , et la deuxième couche de confinement 112 forment une jonction PIN. Le matériau lll-V est par exemple du phosphure d’indium InP. [0023] In a stacking direction A, the III-V waveguide 11 comprises a first confinement layer 110, an active layer 111, a second confinement layer 112. The active layer 111 comprises in particular quantum wells, in particular multiple quantum wells, which make it possible to obtain an optical gain from an electric current flowing between the confinement layers 110, 112. In a manner known per se, the quantum wells then produce a light wave which will be confined in the active part 111. The confinement layers 110, 112 are located respectively on either side of the active layer 111. In particular, the first confinement layer 110 is located on one side of the active layer 111; the second confinement layer 112 is located on the opposite side of the active layer 111. The confinement layers 110, 112 have in particular refractive indices lower than that of the active layer 111, thus making it possible to confine the light wave in the active layer 111 and to guide it. In particular, the confinement layers 110, 112 have dopings of opposite types. For example, the first confinement layer 110 has a p-type doping; and the second confinement layer 112 has an n-type doping. In particular, the first confinement layer 110, the active layer 111, and the second confinement layer 112 form a PIN junction. The III-V material is for example indium phosphide InP.

[0024] Le guide d’onde SC 12 se trouve après le guide d’onde lll-V 11 suivant la direction d’empilement A. Le guide d’onde SC 12 comprend une couche en silicium 120. La couche de silicium 120 sert notamment de milieu de propagation de l’onde lumineuse dans le circuit photonique en silicium. En particulier, la couche de silicium 120 est située en vis-à-vis de la deuxième couche de confinement 112 suivant la direction d’empilement A. [0024] The waveguide SC 12 is located after the waveguide III-V 11 in the stacking direction A. The waveguide SC 12 comprises a silicon layer 120. The silicon layer 120 serves in particular as a propagation medium for the light wave in the silicon photonic circuit. In particular, the silicon layer 120 is located opposite the second confinement layer 112 in the stacking direction A.

[0025] La couche de silicium 120 est notamment comprise dans une couche de matériau diélectrique 14 servant de gaine pour le guide d’onde SC 12. Le matériau diélectrique est notamment de l’oxyde de silicium SiO2. En particulier, une mince couche du matériau diélectrique 14 sépare la deuxième couche de confinement 112 du guide d’onde lll-V 11 de la couche de silicium 120 du guide d’onde SC 12, de façon à permettre un couplage optique entre le guide d’onde lll-V 11 et le guide d’onde SC 12. L’épaisseur de matériau diélectrique 14 séparant la deuxième couche de confinement 112 et la couche de silicium 120 peut être comprise entre 5 nm et 200 nm, voire est égale à 50 nm. L’épaisseur de matériau diélectrique 14 peut être plus grande en allongeant la longueur d’une zone de transition optique décrite plus loin. [0025] The silicon layer 120 is in particular included in a layer of dielectric material 14 serving as a sheath for the waveguide SC 12. The dielectric material is in particular silicon oxide SiO2. In particular, a thin layer of dielectric material 14 separates the second confinement layer 112 of the III-V waveguide 11 from the silicon layer 120 of the SC waveguide 12, so as to allow optical coupling between the III-V waveguide 11 and the SC waveguide 12. The thickness of dielectric material 14 separating the second confinement layer 112 and the silicon layer 120 may be between 5 nm and 200 nm, or even equal to 50 nm. The thickness of dielectric material 14 may be greater by extending the length of an optical transition zone described later.

[0026] Ainsi, la première couche de confinement 110, la couche active 111 , la deuxième couche de confinement 112 du guide d’onde lll-V 11 , la couche de silicium 120 du guide d’onde SC 12 forment au moins en partie un empilement de couches. Au sein de cet empilement, les couches s’étendent notamment suivant des plans parallèles, qui sont en particulier perpendiculaires à la direction d’empilement A. [0026] Thus, the first confinement layer 110, the active layer 111, the second confinement layer 112 of the III-V waveguide 11, the silicon layer 120 of the SC waveguide 12 form at least in part a stack of layers. Within this stack, the layers extend in particular along parallel planes, which are in particular perpendicular to the stacking direction A.

[0027] Le guide d’onde lll-V 11 et le guide d’onde SC 12 sont donc en particulier situés en vis-à-vis l’un de l’autre suivant la direction d’empilement A des couches de sorte à permettre un couplage optique entre les deux guides d’ondes. [0027] The III-V waveguide 11 and the SC waveguide 12 are therefore in particular located opposite each other in the stacking direction A of the layers so as to allow optical coupling between the two waveguides.

[0028] Toujours suivant la direction d’empilement A, la puce photonique 10 comprend notamment un substrat 16 servant de support à la puce photonique 10. Ce substrat 16 est en particulier en silicium. Le substrat 16 peut servir de support à d’autres structures lll-V ou d’autres composants photoniques en silicium, tels que par exemple un modulateur de phase ou un interféromètre de Mach-Zehnder. [0028] Still following the stacking direction A, the photonic chip 10 comprises in particular a substrate 16 serving as a support for the photonic chip 10. This substrate 16 is in particular made of silicon. The substrate 16 can serve as a support for other III-V structures or other silicon photonic components, such as for example a phase modulator or a Mach-Zehnder interferometer.

[0029] Le guide d’onde lll-V 11 comprend en outre une première électrode B1 qui assure un contact électrique avec la première couche de confinement 110 ; et une deuxième électrode B2 qui assure un contact électrique avec la deuxième couche de confinement 112. Ainsi, la couche active 11 peut émettre une onde lumineuse lorsqu’un courant circule entre les électrodes B1 , B2 à travers les couches de confinement 110, 112. [0029] The III-V waveguide 11 further comprises a first electrode B1 which ensures electrical contact with the first confinement layer 110; and a second electrode B2 which ensures electrical contact with the second confinement layer 112. Thus, the active layer 11 can emit a light wave when a current flows between the electrodes B1, B2 through the confinement layers 110, 112.

[0030] La puce photonique 10 est particulière en ce que, de par la forme de la première couche de confinement 110, elle ne nécessite pas une surépaisseur de la couche de silicium pour un transfert de mode optique efficace entre le guide d’onde lll-V 11 et le guide d’onde SC 12. [0031] En effet, la première couche de confinement 110 comprend une première portion 110a superposée à la couche active 111 , et une extension 110b qui s’étend latéralement au-delà de la couche active 111. Autrement dit, l’extension 110b forme une deuxième portion de la première couche de confinement 110, et s’étend depuis un côté de la première portion 110a de la première couche de confinement 110. En particulier, l’extension 110b s’étend depuis la première portion 110a suivant une direction transversale, notamment perpendiculaire, à la direction d’empilement A. L’extension 110b a une épaisseur Eb suivant la direction d’empilement A qui est supérieure à l’épaisseur Ea de la première portion 110a. L’extension 110b définit ainsi une face de contact électrique 116 située avant la première portion 110a suivant la direction d’empilement A. Ainsi, notamment, les faces ou interfaces suivantes sont situées l’une après l’autre suivant la direction d’empilement A : la face de contact 116 de la première couche d’empilement 110, une face supérieure 117 de la première portion 110a de la première couche de confinement, l’interface entre la première couche de confinement 110 et la couche active 111 , l’interface entre la couche active 111 et la deuxième couche de confinement 112, l’interface entre le guide d’onde lll-V 11 et le guide d’onde SC 12. La première électrode B1 comprend une première couche de contact B10 qui vient contre la face de contact 116 de la première couche de confinement 110 pour une connexion électrique de celle-ci. [0030] The photonic chip 10 is particular in that, due to the shape of the first confinement layer 110, it does not require an excess thickness of the silicon layer for efficient optical mode transfer between the III-V waveguide 11 and the SC waveguide 12. [0031] Indeed, the first confinement layer 110 comprises a first portion 110a superimposed on the active layer 111, and an extension 110b which extends laterally beyond the active layer 111. In other words, the extension 110b forms a second portion of the first confinement layer 110, and extends from one side of the first portion 110a of the first confinement layer 110. In particular, the extension 110b extends from the first portion 110a in a transverse direction, in particular perpendicular, to the stacking direction A. The extension 110b has a thickness Eb in the stacking direction A which is greater than the thickness Ea of the first portion 110a. The extension 110b thus defines an electrical contact face 116 located before the first portion 110a along the stacking direction A. Thus, in particular, the following faces or interfaces are located one after the other along the stacking direction A: the contact face 116 of the first stacking layer 110, an upper face 117 of the first portion 110a of the first confinement layer, the interface between the first confinement layer 110 and the active layer 111, the interface between the active layer 111 and the second confinement layer 112, the interface between the III-V waveguide 11 and the SC waveguide 12. The first electrode B1 comprises a first contact layer B10 which comes against the contact face 116 of the first confinement layer 110 for an electrical connection thereof.

[0032] Grâce à la première couche de confinement 110 en deux parties 110a, 110b, lors d’une transmission de mode optique entre le guide d’onde lll-V 11 et le guide d’onde SC 12, l’indice effectif de propagation du mode optique n’est sensible qu’à la première portion 110a. Contrairement à l’art antérieur illustré en figure 1 , il n’est donc pas nécessaire de rajouter une surépaisseur à la couche de silicium 120 par rapport à une puce photonique en silicium classique. L’épaisseur Ea de la première portion 110a peut être adaptée pour assurer une condition d’accord de phase entre le guide d’onde lll-V 11 et le guide d’onde SC 12. En particulier, l’épaisseur de la première portion 110a peut être suffisamment petite pour permettre une condition d’accord de phase entre le guide lll-V 11 et le guide d’onde SC 12. Par exemple, pour une épaisseur de couche de silicium 120 d’environ 220 nm, l’épaisseur Ea de la première portion 110a de la première couche de confinement 110 peut être comprise entre 200 et 500 nm. D’autre part, l’extension 110b permet d’éloigner de la couche active 111 une couche fortement dopée de la première couche de confinement 110. L’extension 110b peut alors avoir une épaisseur Eb qui permet d’éviter ou de fortement limiter le phénomène d’absorption de bande d’intervalence. Notamment, l’épaisseur de l’excroissance 110b est suffisamment grande pour éviter le phénomène d’absorption de bande d’intervalence. Par exemple, l’épaisseur Eb de l’extension 110b peut être comprise entre 1 et 3 pm. Les épaisseurs Ea, Eb sont notamment définies suivant la direction d’empilement A. En outre, du fait de sa structure lll-V qui permet une injection de courant verticale dans la couche active, la puce photonique 10 est plus compatible avec les technologies de fabrication CMOS que la puce de l’art antérieur qui comprend une structure lll-V dans laquelle l’injection est horizontale. [0032] Thanks to the first confinement layer 110 in two parts 110a, 110b, during an optical mode transmission between the III-V waveguide 11 and the SC waveguide 12, the effective propagation index of the optical mode is sensitive only to the first portion 110a. Unlike the prior art illustrated in FIG. 1, it is therefore not necessary to add an excess thickness to the silicon layer 120 compared to a conventional silicon photonic chip. The thickness Ea of the first portion 110a may be adapted to ensure a phase matching condition between the III-V waveguide 11 and the SC waveguide 12. In particular, the thickness of the first portion 110a may be sufficiently small to allow a phase matching condition between the III-V waveguide 11 and the SC waveguide 12. For example, for a silicon layer thickness 120 of approximately 220 nm, the thickness Ea of the first portion 110a of the first confinement layer 110 may be between 200 and 500 nm. Furthermore, the extension 110b makes it possible to move a heavily doped layer of the first confinement layer 110 away from the active layer 111. The extension 110b can then have a thickness Eb which makes it possible to avoid or greatly limit the phenomenon of intervalence band absorption. In particular, the thickness of the protrusion 110b is sufficiently large to avoid the phenomenon of intervalence band absorption. For example, the thickness Eb of the extension 110b can be between 1 and 3 pm. The thicknesses Ea, Eb are in particular defined according to the stacking direction A. Furthermore, due to its III-V structure which allows vertical current injection into the active layer, the photonic chip 10 is more compatible with CMOS manufacturing technologies than the chip of the prior art which comprises a III-V structure in which the injection is horizontal.

[0033] Notamment, l’extension 110b s’étend depuis un bord de la première portion 110a qui est dans le prolongement d’un bord de la couche active 111. Autrement dit, vu selon la direction d’empilement A, l’extension 110b ne recouvre pas la couche active 111 , ce qui limite le phénomène d’absorption de bande d’intervalence. En particulier, une partie en forme d’escalier est définie par l’épaisseur Eb de l’extension 110b, notamment par la première portion 110a et la deuxième portion 110b. Un palier bas de la forme en escalier comprend la face externe 117 de la première portion 110a de la première couche de confinement 110. Notamment, la face externe 117 de la première portion 110a est sa face opposée par rapport à son interface avec la couche active 111. Un palier haut de la forme en escalier comprend la face de contact 116. Le palier haut et le palier bas sont séparés par une hauteur de marche, qui est notamment égale à la différence entre les épaisseurs Ea, Eb de la première portion 110a et de la deuxième portion 110b. De préférence, la distance entre le pied de la hauteur de marche et la première portion 110a est égale à zéro, aux incertitudes de positionnement près. Autrement dit, la hauteur de marche s’étend notamment depuis un bord de la première portion 110a qui est dans le prolongement d’un bord de la couche active 111. Cependant, la distance entre le pied de la hauteur de marche et la première portion 110a peut être supérieure ou égale à zéro, depuis le bord de la première portion 110a en s’éloignant de la couche active 111. La distance entre le pied de la hauteur de marche et la première portion 110a peut être comprise entre 0 et 2 pm, en fonction de l’encombrement de la puce photonique 10. [0033] In particular, the extension 110b extends from an edge of the first portion 110a which is in the extension of an edge of the active layer 111. In other words, seen in the stacking direction A, the extension 110b does not cover the active layer 111, which limits the phenomenon of intervalence band absorption. In particular, a staircase-shaped part is defined by the thickness Eb of the extension 110b, in particular by the first portion 110a and the second portion 110b. A low landing of the stepped shape comprises the outer face 117 of the first portion 110a of the first confinement layer 110. In particular, the outer face 117 of the first portion 110a is its opposite face relative to its interface with the active layer 111. A high landing of the stepped shape comprises the contact face 116. The high landing and the low landing are separated by a step height, which is in particular equal to the difference between the thicknesses Ea, Eb of the first portion 110a and the second portion 110b. Preferably, the distance between the foot of the step height and the first portion 110a is equal to zero, apart from positioning uncertainties. In other words, the step height extends in particular from an edge of the first portion 110a which is in the extension of an edge of the active layer 111. However, the distance between the foot of the step height and the first portion 110a may be greater than or equal to zero, from the edge of the first portion 110a moving away from the active layer 111. The distance between the foot of the step height and the first portion 110a may be between 0 and 2 pm, depending on the size of the photonic chip 10.

[0034] Afin de limiter le phénomène d’absorption de bande d’intervalence, l’extension 110b de la première couche de confinement 110 peut présenter un profil de dopage qui diminue depuis la face de contact 116 suivant la direction d’empilement A. Notamment, l’extension 110b est fortement dopée au niveau de la face de contact 116 pour permettre un bon contact électrique avec la première couche de contact B 10. Le dopage de l’extension 110b peut aller de 1x1020/cm3 à proximité de la face de contact 116 à 7x1017/cm3 à proximité de la couche active 111. La première portion 110a de la première couche de confinement 110 peut présenter un dopage sensiblement constant, notamment sensiblement égal à la plus petite valeur de dopage dans l’extension 110b. Par exemple, la première portion 110a présente un dopage de 7x1017/cm3. [0034] In order to limit the phenomenon of intervalence band absorption, the extension 110b of the first confinement layer 110 may have a doping profile which decreases from the contact face 116 along the stacking direction A. In particular, the extension 110b is heavily doped at the contact face 116 to allow good electrical contact with the first contact layer B 10. The doping of the extension 110b may range from 1x10 20 /cm 3 near the contact face 116 to 7x10 17 /cm 3 near the active layer 111. The first portion 110a of the first confinement layer 110 may have a substantially constant doping, in particular substantially equal to the smallest doping value in the extension 110b. For example, the first portion 110a has a doping of 7x10 17 /cm 3 .

[0035] La couche active 111 peut être délimitée sur les côtés par une couche de matériau isolant 118. La couche de matériau isolant 118 permet de confiner sur les côtés l’onde lumineuse issue de la couche active 111. La couche de matériau isolant 118 s’étend notamment latéralement depuis un bord de la couche active 111. En particulier, l’extension 110b de la première couche de confinement 110 vient contre la couche de matériau isolant 118. La couche de matériau isolant 118 s’étend en particulier entre l’extension 110b de la première couche de confinement 110 et la couche en matériau diélectrique 14. La couche de matériau isolant 118 peut être en polymère, tel que le benzocyclobutène (ou BCB) par exemple, ou de la silice SiO2 ou encore du nitrure d’aluminium AIN. La couche de matériau isolant 118 peut être en un matériau formant une hétérostructure semi-isolante enterrée (ou SIBH pour « semi insulating buried heterostructure »), tel que le phosphure d’indium semi- isolant, notamment un matériau lnP:Fe. [0035] The active layer 111 may be delimited on the sides by a layer of insulating material 118. The layer of insulating material 118 makes it possible to confine the light wave coming from the active layer 111 on the sides. The layer of insulating material 118 extends in particular laterally from an edge of the active layer 111. In particular, the extension 110b of the first confinement layer 110 comes against the layer of insulating material 118. The layer of insulating material 118 extends in particular between the extension 110b of the first confinement layer 110 and the layer of dielectric material 14. The layer of insulating material 118 may be made of polymer, such as benzocyclobutene (or BCB) for example, or silica SiO2 or even aluminum nitride AIN. The layer of insulating material 118 may be made of a material forming a semi-insulating buried heterostructure (or SIBH for “semi insulating buried heterostructure”), such as semi-insulating indium phosphide, in particular an lnP:Fe material.

[0036] La deuxième couche de confinement 112 peut s’étendre latéralement au-delà de la couche active 111 et de la première couche de confinement 110 pour un contact électrique. Notamment, la deuxième électrode B2 du guide d’onde lll-V comprend un via qui s’étend suivant la direction d’empilement A, en particulier du côté de la première couche de confinement 110. Une couche de contact électrique B20 est en particulier déposée au fond du via sur la deuxième couche de confinement 112 pour un contact électrique de celle-ci. [0036] The second confinement layer 112 may extend laterally beyond the active layer 111 and the first confinement layer 110 for an electrical contact. In particular, the second electrode B2 of the III-V waveguide comprises a via which extends in the stacking direction A, in particular on the side of the first confinement layer 110. An electrical contact layer B20 is in particular deposited at the bottom of the via on the second confinement layer 112 for an electrical contact thereof.

[0037] Une couche de passivation 113 peut recouvrir la structure hétérogène III- V/silicium. La couche de passivation 113 peut être en polymère, tel que le benzocyclobutène (ou BCB) par exemple, ou de la silice SiO2 ou encore du nitrure d’aluminium AIN. [0038] La figure 3 présente une vue de dessus partielle 1 de la puce photonique 10. Pour rendre la représentation lisible, dans la vue 1 , la couche de passivation 113, les électrodes B1 , B2, la première portion 110a de la première couche de confinement 110 et la deuxième couche de confinement 112 ne sont pas représentées. Les autres vues a, b, c, d de la figure 3 présentent des vues de coupe de la puce photonique 10 prises le long des droites correspondantes de la vue 1 . [0037] A passivation layer 113 may cover the III-V/silicon heterogeneous structure. The passivation layer 113 may be made of polymer, such as benzocyclobutene (or BCB) for example, or silica SiO2 or even aluminum nitride AIN. [0038] Figure 3 shows a partial top view 1 of the photonic chip 10. To make the representation readable, in view 1, the passivation layer 113, the electrodes B1, B2, the first portion 110a of the first confinement layer 110 and the second confinement layer 112 are not shown. The other views a, b, c, d of Figure 3 show sectional views of the photonic chip 10 taken along the corresponding lines of view 1.

[0039] Le guide d’onde lll-V 11 et le guide d’onde SC 12 s’étendent notamment suivant une direction longitudinale correspondant à une direction de propagation des ondes lumineuses. Notamment, la direction longitudinale est perpendiculaire à la direction d’empilement A. De manière connue en soi, la puce photonique 10 comprend une zone de transition optique 17 dans laquelle le guide d’onde SC 12 ou le guide d’onde lll-V 11 présentent un profil le long de la direction longitudinale permettant un transfert ou couplage de mode optique d’un guide à l’autre. Par exemple, la section transversale du guide d’onde SC 12, notamment de la couche de silicium 120, diminue progressivement alors que la section transversale du guide d’onde lll-V 11 , notamment de la couche active 111 , augmente progressivement. En particulier lorsque la couche isolante 118 du guide d’onde lll-V forme une hétérostructure semi-isolante, elle présente elle-même une section transversale qui augmente progressivement, comme par exemple représenté dans les vues a, b. Ensuite, la section de la couche active 11 augmente progressivement comme par exemple représenté dans les vues c, d. La première couche de confinement 110 comprend l’extension 110b au moins dans la zone de transition 17, afin d’améliorer le transfert de mode optique. [0039] The III-V waveguide 11 and the SC waveguide 12 extend in particular in a longitudinal direction corresponding to a direction of propagation of the light waves. In particular, the longitudinal direction is perpendicular to the stacking direction A. In a manner known per se, the photonic chip 10 comprises an optical transition zone 17 in which the SC waveguide 12 or the III-V waveguide 11 have a profile along the longitudinal direction allowing a transfer or coupling of optical mode from one guide to the other. For example, the cross-section of the SC waveguide 12, in particular of the silicon layer 120, gradually decreases while the cross-section of the III-V waveguide 11, in particular of the active layer 111, gradually increases. In particular when the insulating layer 118 of the III-V waveguide forms a semi-insulating heterostructure, it itself has a cross-section which gradually increases, as for example shown in views a, b. Then, the cross-section of the active layer 11 gradually increases as for example shown in views c, d. The first confinement layer 110 comprises the extension 110b at least in the transition zone 17, in order to improve the optical mode transfer.

[0040] Au-delà de la zone de transition 17, notamment en allant vers la droite dans la vue 1 de la figure 3, le guide d’onde lll-V 11 et le guide d’onde SC 12 présentent notamment des sections transversales constantes. En particulier, le mode optique est alors confiné dans le guide d’onde lll-V 11. Le guide d’onde lll-V 11 peut avoir une fonction d’amplificateur optique semi-conducteur. Un courant électrique circule alors entre les électrodes B1 , B2 du guide d’onde lll-V 11 pour amplifier l’onde lumineuse lll-V se propageant dans le guide d’onde lll-V 11 . La première couche de confinement 110 peut encore comprendre l’extension 110b au-delà de la zone de transition 17. Le chemin du courant électrique i circulant dans la structure lll-V est par exemple illustré en figure 4. [0041] Pour une puce photonique de l’art antérieur ayant une injection de courant verticale, dans laquelle le guide d’onde lll-V a une longueur de 600 pm, et la première couche de confinement est intégralement superposée à la couche active, avec une épaisseur de 2 pm et une largeur de 2,4 pm, la résistance électrique R1 à travers la première couche de confinement peut être d’environ 6 Q. Dans la puce photonique 10, l’injection de courant est verticale ; mais le courant électrique circule aussi latéralement à travers la section S à l’interface de la première portion 110a et de la deuxième portion 110b, ce qui limite notamment le courant par rapport à l’art antérieur. Par exemple, lorsque le guide d’onde lll-V 11 a une longueur de 600 pm, une épaisseur Ea de la première portion 110a de 500 nm et une épaisseur Eb de l’extension 110b de 2 pm, la résistance Rs de la section S peut être d’environ 5,8 Q. La résistance totale à travers la première couche de confinement 110 peut être alors de 11 ,8 Q. Cependant, la puce photonique 10 reste plus avantageuse que la puce de l’art antérieur car la couche de silicium peut avoir une épaisseur E de 220 nm. En outre, la puce photonique 10 reste plus avantageuse qu’une puce photonique de l’art antérieur décrite précédemment dans laquelle l’injection de courant dans la structure lll-V est suivant une direction horizontale. Pour un guide d’onde lll-V de longueur 500 pm, celle-ci a une résistance d’environ 25 Q. [0040] Beyond the transition zone 17, in particular going to the right in view 1 of FIG. 3, the III-V waveguide 11 and the SC waveguide 12 have in particular constant cross-sections. In particular, the optical mode is then confined in the III-V waveguide 11. The III-V waveguide 11 may have a semiconductor optical amplifier function. An electric current then flows between the electrodes B1, B2 of the III-V waveguide 11 to amplify the III-V light wave propagating in the III-V waveguide 11. The first confinement layer 110 may also comprise the extension 110b beyond the transition zone 17. The path of the electric current i flowing in the III-V structure is for example illustrated in FIG. 4. [0041] For a prior art photonic chip having vertical current injection, in which the III-V waveguide has a length of 600 pm, and the first confinement layer is fully superimposed on the active layer, with a thickness of 2 pm and a width of 2.4 pm, the electrical resistance R1 across the first confinement layer may be about 6 Q. In the photonic chip 10, the current injection is vertical; but the electric current also flows laterally through the section S at the interface of the first portion 110a and the second portion 110b, which notably limits the current compared to the prior art. For example, when the III-V waveguide 11 has a length of 600 pm, a thickness Ea of the first portion 110a of 500 nm and a thickness Eb of the extension 110b of 2 pm, the resistance Rs of the section S can be about 5.8 Ω. The total resistance across the first confinement layer 110 can then be 11.8 Ω. However, the photonic chip 10 remains more advantageous than the prior art chip because the silicon layer can have a thickness E of 220 nm. Furthermore, the photonic chip 10 remains more advantageous than a prior art photonic chip described above in which the current injection into the III-V structure is in a horizontal direction. For a III-V waveguide of length 500 pm, the latter has a resistance of about 25 Ω.

[0042] Dans une variante illustrée en figure 5, hors de la zone de transition optique 17, la puce photonique 20 a une architecture classique de structure hétérogène III- V/silicium. La première couche de confinement 110 ne comprend que la première portion et est dépourvue de l’extension 110b. La première couche de confinement 110 peut alors avoir une épaisseur et un gradient de dopage configurés pour éviter le phénomène d’absorption de bande d’intervalence dans le guide d’onde lll-V 11 . La puce photonique 20 de la figure 5 est par ailleurs identique à la puce photonique 10 décrite précédemment. Cette variante a une résistance électrique similaire à celle de la puce de l’art antérieur décrite dans le paragraphe précédent, car le courant électrique circule en grande majorité à travers la partie du guide d’onde lll-V qui est de section constante. [0042] In a variant illustrated in FIG. 5, outside the optical transition zone 17, the photonic chip 20 has a conventional architecture of III-V/silicon heterogeneous structure. The first confinement layer 110 comprises only the first portion and is devoid of the extension 110b. The first confinement layer 110 can then have a thickness and a doping gradient configured to avoid the phenomenon of intervalence band absorption in the III-V waveguide 11. The photonic chip 20 of FIG. 5 is also identical to the photonic chip 10 described previously. This variant has an electrical resistance similar to that of the prior art chip described in the previous paragraph, because the electric current flows mainly through the part of the III-V waveguide which is of constant section.

[0043] La figure 6 illustre un exemple de puce photonique 30 selon une variante dans laquelle la première couche de confinement 310 comprend deux extensions 310b. La puce photonique 30 est par ailleurs identique à la puce photonique 10 décrite en relation avec les figures précédentes. Chacune des extensions 310b est similaire à l’extension 110b de la puce photonique 10 décrite en relation avec les figures précédentes. Dans cette variante, la présence de deux extensions 310b permet de diminuer d’un facteur 2 la contribution de la partie dopée p dans la résistance électrique totale vue par le courant injecté dans la structure lll-V. [0043] Figure 6 illustrates an example of a photonic chip 30 according to a variant in which the first confinement layer 310 comprises two extensions 310b. The photonic chip 30 is otherwise identical to the photonic chip 10 described in relation to the preceding figures. Each of the extensions 310b is similar to the extension 110b of the photonic chip 10 described in relation to the preceding figures. In this variant, the presence of two extensions 310b makes it possible to reduce by a factor of 2 the contribution of the p-doped part in the total electrical resistance seen by the current injected into the III-V structure.

[0044] La figure 7 présente une vue de dessous partielle de la puce photonique 10, dans laquelle seule la couche de silicium 120 du guide d’onde SC 12 et les bords de l’ensemble formé par la couche active 111 et la couche de matériau isolant 118 sont représentés. La puce photonique 10 s’étend suivant un plan (X, Z) perpendiculaire à la direction d’empilement A. La direction Z correspond à la direction longitudinale de puce photonique 10 ; la direction X correspond à une direction transversale de la puce photonique 10. Chaque axe X, Z porte une échelle en pm. De manière similaire à la figure 3, dans la zone de transition, sur une première longueur L1 la couche de silicium 120 est profilée de sorte que sa section diminue ; sur une deuxième longueur L2, l’ensemble formé par la couche active 111 et la couche de matériau isolant 118 est profilé. [0044] Figure 7 shows a partial bottom view of the photonic chip 10, in which only the silicon layer 120 of the waveguide SC 12 and the edges of the assembly formed by the active layer 111 and the layer of insulating material 118 are shown. The photonic chip 10 extends along a plane (X, Z) perpendicular to the stacking direction A. The direction Z corresponds to the longitudinal direction of the photonic chip 10; the direction X corresponds to a transverse direction of the photonic chip 10. Each axis X, Z bears a scale in pm. Similarly to Figure 3, in the transition zone, over a first length L1 the silicon layer 120 is profiled so that its section decreases; over a second length L2, the assembly formed by the active layer 111 and the layer of insulating material 118 is profiled.

[0045] Les figures 8a, 8b représentent la répartition spatiale du mode optique dans des sections transversales prises à des positions Z successives de la figure 7, lors d’une transmission d’un mode optique du guide d’onde SC 12 vers le guide d’onde lll-V 11 . Dans ces vues transversales, l’origine de l’axe X correspond au point de coordonnée 4,5 sur l’axe X de la figure 7. Le long de l’axe longitudinal Z, on observe une transmission progressive du mode optique depuis le guide d’onde SC 12 vers le guide d’onde lll-V 11 . La puce photonique 10 permet notamment un transfert de mode optique efficace entre le guide d’onde lll-V et le guide d’onde SC, notamment une transmission à 97%. [0045] Figures 8a, 8b represent the spatial distribution of the optical mode in cross sections taken at successive Z positions of Figure 7, during a transmission of an optical mode from the SC waveguide 12 to the III-V waveguide 11. In these cross-sectional views, the origin of the X axis corresponds to the point with coordinate 4.5 on the X axis of Figure 7. Along the longitudinal Z axis, a progressive transmission of the optical mode is observed from the SC waveguide 12 to the III-V waveguide 11. The photonic chip 10 notably allows an efficient optical mode transfer between the III-V waveguide and the SC waveguide, notably a 97% transmission.

[0046] Un exemple de procédé de fabrication de la puce photonique 10 va être décrit en relation avec la figure 9. Une structure lll-V formée d’une couche dopée p 4, une couche intermédiaire 3 et une couche dopée n 2 est d’abord formée par croissance sur un substrat lll-V, notamment de phosphure d’indium InP. L’ensemble est alors fixé par collage sur une puce photonique en silicium. Le substrat lll-V est ensuite enlevé. Alternativement, une fine couche de substrat lll-V peut être collée sur la puce photonique en silicium. La croissance se fait alors depuis cette fine couche de substrat lll-V directement sur le substrat en silicium (vue a). Puis, un masque diélectrique M est déposé sur la couche dopée p 4 (vue b). Ce masque M permet de définir par gravure, la couche active 111 dans la couche intermédiaire 3. La couche dopée n forme alors la deuxième couche de confinement 112. Un matériau isolant, est épitaxié autour de la couche active 111 pour former la couche de matériau isolant 118 (vue c). Le masque M est retiré. Puis, on procède à la croissance d’une couche dopée p additionnelle de la couche 4 (vue d). Préalablement à la croissance, une couche facultative de matériau quaternaire 5 peut être déposée pour recouvrir la couche dopée p 4 initiale. Cette couche de matériau quaternaire 5 est notamment en un alliage GalnAsP. Elle forme une couche sacrificielle qui facilite le procédé de fabrication. Elle sert notamment de couche d’arrêt pour la gravure ultérieure de la couche dopée p 4. La première couche de confinement 110 est alors définie par gravure (vue e). Une partie du matériau isolant 118 est alors enlevée pour définir des emplacements où la couche de contact B20 est déposée sur la deuxième couche de confinement 112 ; et la couche de contact B10 est déposée sur la face de contact 116 de la première couche de confinement 110. [0046] An example of a method for manufacturing the photonic chip 10 will be described in relation to FIG. 9. A III-V structure formed from a p-doped layer 4, an intermediate layer 3 and an n-doped layer 2 is first formed by growth on a III-V substrate, in particular indium phosphide InP. The assembly is then fixed by bonding to a silicon photonic chip. The III-V substrate is then removed. Alternatively, a thin layer of III-V substrate can be bonded to the silicon photonic chip. Growth is then carried out from this thin layer of III-V substrate directly onto the silicon substrate (view a). Then, a dielectric mask M is deposited on the p-doped layer 4 (view b). This mask M makes it possible to define by etching, the active layer 111 in the intermediate layer 3. The n-doped layer then forms the second confinement layer 112. An insulating material is epitaxially grown around the active layer 111 to form the insulating material layer 118 (view c). The mask M is removed. Then, an additional p-doped layer of the layer 4 is grown (view d). Prior to the growth, an optional layer of quaternary material 5 can be deposited to cover the initial p-doped layer 4. This layer of quaternary material 5 is in particular made of a GalnAsP alloy. It forms a sacrificial layer which facilitates the manufacturing process. It serves in particular as a stop layer for the subsequent etching of the p-doped layer 4. The first confinement layer 110 is then defined by etching (view e). A portion of the insulating material 118 is then removed to define locations where the contact layer B20 is deposited on the second confinement layer 112; and the contact layer B10 is deposited on the contact face 116 of the first confinement layer 110.

[0047] Dans le guide d’onde décrit en relation avec les figures, le deuxième matériau semi-conducteur est par exemple du silicium, du germanium, du nitrure de silicium ou du niobate de lithium ou un alliage de ceux-ci. Le deuxième matériau semi- conducteur peut être tout matériau semi-conducteur adapté pour le confinement et la propagation d’un mode optique dans le guide d’onde SC. Notamment, un tel matériau présente un indice de réfraction suffisamment élevé pour confiner un mode optique, en particulier un indice de réfraction supérieur ou égal à 2. [0047] In the waveguide described in relation to the figures, the second semiconductor material is for example silicon, germanium, silicon nitride or lithium niobate or an alloy thereof. The second semiconductor material may be any semiconductor material suitable for the confinement and propagation of an optical mode in the waveguide SC. In particular, such a material has a refractive index sufficiently high to confine an optical mode, in particular a refractive index greater than or equal to 2.

[0048] Par exemple, le deuxième matériau est un semi-conducteur à gap indirect, ce qui le rend défavorable pour la réalisation de composants laser ou d’une amplification optique. Le deuxième matériau peut-être un matériau à gap direct, mais dont les caractéristiques physiques sont défavorables à la génération d’un laser ou à une amplification optique. Dans ces deux cas, la structure lll-V pallie les insuffisances du deuxième matériau semi-conducteur. [0048] For example, the second material is an indirect gap semiconductor, which makes it unfavorable for the production of laser components or optical amplification. The second material may be a direct gap material, but whose physical characteristics are unfavorable for the generation of a laser or optical amplification. In these two cases, the III-V structure overcomes the inadequacies of the second semiconductor material.

Claims

REVENDICATIONS 1 . Puce photonique (10,20,30) à structure hétérogène de semi-conducteur lll-V sur un deuxième semi-conducteur comprenant, suivant une direction d’empilement (A) : i. un guide d’onde (11 ) en un premier matériau semi-conducteur lll-V, dit guide d’onde lll-V, comportant une première couche de confinement (110), une couche active (111 ) et une deuxième couche de confinement (112), ii. un guide d’onde (12) en un deuxième matériau semi-conducteur, dit guide d’onde SC, comportant une couche (120) du deuxième matériau semi- conducteur, le guide d’onde lll-V (11 ) comprenant en outre une première électrode (B1 ) et une deuxième électrode (B2) configurées pour respectivement assurer un contact électrique avec une desdites couches de confinement, de sorte que la couche active (111 ) émette une onde lumineuse lorsqu’un courant électrique (i) circule entre lesdites électrodes à travers la couche active (111 ) et les couches de confinement, la première couche de confinement (110) comprenant une première portion (110a) superposée à la couche active (111 ) et au moins une extension (110b), s’étendant latéralement au-delà de ladite couche active (111 ), ladite extension (110b) ayant une épaisseur (Eb) suivant la direction d’empilement (A) qui est supérieure à celle (Ea) de la première portion (110a), de manière à définir une face de contact électrique (116) située avant la première portion (110a) suivant la direction d’empilement (A), ladite première électrode (B1) comprenant une première couche de contact (B10) venant contre ladite face de contact électrique (116). 1. Photonic chip (10,20,30) with a heterogeneous structure of III-V semiconductor on a second semiconductor comprising, in a stacking direction (A): i. a waveguide (11) made of a first III-V semiconductor material, called III-V waveguide, comprising a first confinement layer (110), an active layer (111) and a second confinement layer (112), ii. a waveguide (12) made of a second semiconductor material, called an SC waveguide, comprising a layer (120) of the second semiconductor material, the III-V waveguide (11) further comprising a first electrode (B1) and a second electrode (B2) configured to respectively ensure electrical contact with one of said confinement layers, such that the active layer (111) emits a light wave when an electric current (i) flows between said electrodes through the active layer (111) and the confinement layers, the first confinement layer (110) comprising a first portion (110a) superimposed on the active layer (111) and at least one extension (110b), extending laterally beyond said active layer (111), said extension (110b) having a thickness (Eb) in the stacking direction (A) which is greater than that (Ea) of the first portion (110a), so as to define an electrical contact face (116) located before the first portion (110a) along the stacking direction (A), said first electrode (B1) comprising a first contact layer (B10) coming against said electrical contact face (116). 2. Puce photonique (10, 20, 30) selon la revendication 1 , dans laquelle l’épaisseur (Eb) de l’extension (110b) définit au moins une partie en forme d’escalier comprenant un palier bas séparé d’un palier haut par une hauteur de marche, le palier bas comprenant une face externe (117) de la première portion (110a) de la première couche de confinement (110), le palier haut comprenant la face de contact (116) de la première couche de confinement (110), la distance entre le pied de la hauteur de marche et la première portion (110a) étant comprise entre 0 et 2 pm.2. Photonic chip (10, 20, 30) according to claim 1, in which the thickness (Eb) of the extension (110b) defines at least one staircase-shaped portion comprising a low landing separated from a high landing by a step height, the low landing comprising an external face (117) of the first portion (110a) of the first confinement layer (110), the high landing comprising the contact face (116) of the first confinement layer (110), the distance between the foot of the step height and the first portion (110a) being between 0 and 2 pm. 3. Puce photonique (10, 20, 30) selon la revendication précédente, dans laquelle la distance entre le pied de la hauteur de marche et la première portion (110a) de la première couche de confinement (110) est égale à zéro. 3. Photonic chip (10, 20, 30) according to the preceding claim, in which the distance between the foot of the step height and the first portion (110a) of the first confinement layer (110) is equal to zero. 4. Puce photonique (10, 20, 30) selon l’une des revendications précédentes, dans laquelle l’épaisseur (Eb) de l’extension (110b) est configurée pour éviter un phénomène d’absorption de bande d’intervalence dans le guide d’onde lll-V (11 ) ; et la première portion (110a) a une épaisseur (Ea) configurée pour une condition d'accord de phase entre le guide d’onde lll-V (11 ) et le guide d’onde SC (12). 4. Photonic chip (10, 20, 30) according to one of the preceding claims, wherein the thickness (Eb) of the extension (110b) is configured to avoid an intervalence band absorption phenomenon in the III-V waveguide (11); and the first portion (110a) has a thickness (Ea) configured for a phase matching condition between the III-V waveguide (11) and the SC waveguide (12). 5. Puce photonique (10, 20, 30) selon l’une des revendications précédentes, dans laquelle l’extension (110b) présente un profil de dopage diminuant depuis la face de contact (116) suivant ladite direction d’empilement (A) ; et la première portion (110a) de la première couche de confinement (110) présente un dopage sensiblement constant. 5. Photonic chip (10, 20, 30) according to one of the preceding claims, in which the extension (110b) has a doping profile decreasing from the contact face (116) along said stacking direction (A); and the first portion (110a) of the first confinement layer (110) has a substantially constant doping. 6. Puce photonique (10, 20, 30) selon l’une des revendications précédentes, dans laquelle les guides d’onde (11 , 12) s’étendent suivant une direction longitudinale, ladite puce comprenant une zone de transition (17) dans laquelle le guide d’onde lll-V (11) et/ou le guide d’onde SC (12) présentent un profilage le long de ladite direction longitudinale permettant de transmettre un mode optique entre le guide d’onde lll-V (11) et le guide d’onde SC (12). 6. Photonic chip (10, 20, 30) according to one of the preceding claims, in which the waveguides (11, 12) extend in a longitudinal direction, said chip comprising a transition zone (17) in which the III-V waveguide (11) and/or the SC waveguide (12) have a profiling along said longitudinal direction making it possible to transmit an optical mode between the III-V waveguide (11) and the SC waveguide (12). 7. Puce photonique (10, 20, 30) selon la revendication précédente, dans laquelle la dite extension (110b) est au moins comprise dans ladite zone de transition (17). 7. Photonic chip (10, 20, 30) according to the preceding claim, in which said extension (110b) is at least included in said transition zone (17). 8. Puce photonique (20) selon la revendication 6 ou 7, dans laquelle, hors de ladite zone de transition (17), la première couche de confinement (110) consiste en la première portion (110a) et a une épaisseur (Ea) configurée pour éviter un phénomène d’absorption de bande d’intervalence dans le guide d’onde lll-V (11 ).8. Photonic chip (20) according to claim 6 or 7, wherein, outside said transition zone (17), the first confinement layer (110) consists of the first portion (110a) and has a thickness (Ea) configured to avoid an intervalence band absorption phenomenon in the III-V waveguide (11). 9. Puce photonique (10, 20, 30) selon l’une des revendications précédentes, dans laquelle la deuxième couche de confinement (112) s’étend au moins en partie latéralement au-delà de la couche active (111 ) et de la première couche de confinement (110) ; et la deuxième électrode (B2) comprend au moins un via s’étendant suivant la direction d’empilement (A), notamment du côté de la première couche de confinement (110) et de la couche active (111 ). 9. Photonic chip (10, 20, 30) according to one of the preceding claims, in which the second confinement layer (112) extends at least partly laterally beyond the active layer (111) and the first confinement layer (110); and the second electrode (B2) comprises at least one via extending along the stacking direction (A), in particular on the side of the first confinement layer (110) and the active layer (111). 10. Puce photonique (30) selon l’une des revendications précédentes, dans laquelle la dite première couche de confinement (110) comprend deux extensions (310b) s’étendant chacune depuis des bords opposés de ladite première portion (110a) de la première couche de confinement (110). 10. Photonic chip (30) according to one of the preceding claims, in which said first confinement layer (110) comprises two extensions (310b) each extending from opposite edges of said first portion (110a) of the first confinement layer (110).
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