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WO2024261277A1 - Tantalum-oxide-based transistor gate - Google Patents

Tantalum-oxide-based transistor gate Download PDF

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Publication number
WO2024261277A1
WO2024261277A1 PCT/EP2024/067497 EP2024067497W WO2024261277A1 WO 2024261277 A1 WO2024261277 A1 WO 2024261277A1 EP 2024067497 W EP2024067497 W EP 2024067497W WO 2024261277 A1 WO2024261277 A1 WO 2024261277A1
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WO
WIPO (PCT)
Prior art keywords
layer
barrier layer
tantalum
gate
effect transistor
Prior art date
Application number
PCT/EP2024/067497
Other languages
French (fr)
Inventor
Jorge Pereira
Nicolas Michel
Sébastien AROULANDA
Original Assignee
Thales
Commissariat à l'Energie Atomique et aux Energies Alternatives
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Filing date
Publication date
Application filed by Thales, Commissariat à l'Energie Atomique et aux Energies Alternatives filed Critical Thales
Publication of WO2024261277A1 publication Critical patent/WO2024261277A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28581—Deposition of Schottky electrodes
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H01L21/28593—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T asymmetrical sectional shape
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes

Definitions

  • the invention relates to the field of transistor manufacturing, more particularly the manufacturing of transistor gates subjected to high thermal stresses.
  • the manufacture of transistors includes a crucial step: the manufacture of the control gate. Indeed, the gate is subjected to high thermal stresses, both during manufacture and during use.
  • the transistor gates produced tend not to sufficiently prevent the diffusion of the conductive metal of said gate into the body of the transistor, which is generally made of a semiconductor material.
  • the term "transistor body" refers to the structure in at least one semiconductor layer in which the conduction channel between the source and the drain is formed when the transistor is in an on state. This diffusion leads to a reduction in the performance of the transistor, with an increase in leakage currents.
  • the diffusion of the metal constituting the gate contact into the body of the transistor induces a degradation of the rectifier contact between the gate and the upper semiconductor layer of the transistor body.
  • the technical robustness and reliability of transistors depend on the electrical, thermal and mechanical properties of the control gate.
  • CMOS complementary metal-oxide-semiconductor
  • SOI an enzyme-oxide-semiconductor
  • HEMT an enzyme-catalyzed metal-oxide-semiconductor
  • FinFET an enzyme-driven Fin field-effect transistor
  • HEMTs high electron mobility transistors
  • HEMT transistors are intended for microwave power applications.
  • HEMT transistors are subjected to significant thermal stresses.
  • the high temperatures to which the transistors are exposed cause failures due to the diffusion of the conductive material from the gate to the surface of the semiconductor constituting the transistor body. Diffusion leads to increased leakage currents which degrade the transistor's performance and reduce its lifetime.
  • the invention proposes a control gate structure of a transistor comprising a barrier layer made of an alloy of tantalum and tantalum oxide.
  • the barrier layer CB separates the electrical contact structure of the gate from the body of the transistor to block the diffusion of metal into the body of the transistor.
  • the gate structure according to the invention makes it possible to eliminate the phenomenon of metal diffusion and thus improve the reliability and robustness of the transistor.
  • the invention allows the improvement of the electrical characteristics of the transistor. Indeed, the stack of layers constituting the gate according to the invention makes it possible to obtain a rectifier contact with a high barrier height with or without thermal annealing.
  • the invention further proposes an “in-situ” method for manufacturing the control grid according to the invention.
  • the stacking of layers forming the grid according to the invention can be carried out in the same environment without the need to unload the sample from the deposition equipment. This makes it possible to simplify the grid manufacturing process and thus save production time and yield.
  • the invention relates to a field effect transistor comprising a drain, a source and a gate arranged on an upper layer made of a first semiconductor material of a stack of layers arranged on a substrate and forming a base structure; the gate comprising:
  • barrier layer made of an alloy of tantalum and tantalum oxide; the barrier layer separating said upper layer from the contact structure to block the diffusion of the first electrically conductive material into the base structure; the barrier layer having a tantalum oxide concentration gradient, the tantalum oxide being in the majority compared to the tantalum in a first part of the barrier layer located at a first interface between the barrier layer and the upper layer.
  • the barrier layer comprises a second part made of tantalum located at a second interface opposite the first interface.
  • the first electrically conductive material is gold or aluminum or copper.
  • the grid further comprises an intermediate layer confined between the contact structure and the barrier layer; said intermediate layer being made of a platinoid or of nickel or of molybdenum.
  • the first semiconductor material has an output work lower than that of tantalum to produce a rectifier contact.
  • the barrier layer has a thickness of between 5 nm and 30 nm.
  • the field effect transistor further comprises an encapsulation layer made of diamond or boron nitride; the gate being covered by said encapsulation layer.
  • the contact structure comprises a pillar and an upper contact layer resting on said pillar and having a width greater than that of the pillar.
  • - providing a stack of layers forming a basic structure comprising an upper layer made of a first semiconductor material; - depositing a resin with a chemical composition comprising free oxygen functions on the upper layer and manufacturing a pattern corresponding to a predetermined shape of the grid in the resin by lithography; depositing a barrier layer made of an alloy of tantalum and tantalum oxide on the internal walls of said pattern in the enclosure of deposition equipment having a temperature greater than 1900°C; the deposition being carried out from a tantalum source placed at a separation distance from the base structure chosen so as to obtain a barrier layer having a tantalum oxide concentration gradient;
  • Figure 2b shows a sectional view of the grid according to the second embodiment of the invention.
  • FIG. 4 the figure represents a sectional view of a transistor having a gate according to a fourth embodiment of the invention.
  • FIG. 5 Figure 5 illustrates a flowchart of the method of manufacturing the grid according to any of the embodiments of the invention.
  • Figure 6a Figure 6a illustrates the first step of the method of manufacturing the grid according to the invention.
  • Figure 6b illustrates the second step of the method of manufacturing the grid according to the invention.
  • Figure 6c illustrates the third step of the method of manufacturing the grid according to the invention.
  • Figure 6d illustrates the third optional step of the method of manufacturing the grid according to the invention.
  • Figure 6e illustrates the fourth step of the method of manufacturing the grid according to the invention.
  • Figure 6f illustrates the fifth step of the method of manufacturing the grid according to the invention.
  • Figure 6g illustrates the seventh step of the method of manufacturing the grid according to the invention.
  • Figure 7 illustrates an example of execution of the third step of the method of manufacturing the grid according to the invention.
  • FIG. 1 shows a cross-sectional view of a transistor T1 having a gate G1 according to a first embodiment of the invention.
  • the transistor T1 is a high electron mobility transistor.
  • the transistor T1 comprises a drain D1, a source S1, a gate G1 and a base structure B1 corresponding to the body of the transistor T1.
  • the base structure B1 is formed by a stack of thin layers deposited on a substrate SUB forming a hetero-structure.
  • the base structure B1 may be a bulk layer made of a semiconductor material.
  • the base structure comprises an upper semiconductor layer C1 starting from the substrate SUB.
  • the drain D1, the source S1 and the gate G1 are arranged on said upper semiconductor layer C1.
  • the base structure B1 is intended to contain the conduction channel between the source S1 and the drain D1.
  • the basic structure B1 comprises the following stack of layers starting from the substrate SUB: - a C3 buffer layer to adjust the crystal structure during epitaxial growth.
  • the C3 buffer layer is made of gallium nitride alloy with aluminum GaN/AIGaN.
  • the C2 channel layer corresponding to the transistor channel is made of a semiconductor material with high electron mobility, such as gallium nitride GaN.
  • the confinement layer C1 to generate the charge carriers in the channel layer.
  • the confinement layer C1 is made of a semiconductor material having an energy gap greater than that of the semiconductor material of the channel layer C2.
  • the confinement layer C1 is made of a quaternary alloy of type III-V semiconductor.
  • the basic structure B1 comprises isolation trenches TR produced by etching or ion implantation to laterally delimit the transistor T1 and thus reduce leakage currents.
  • the drain D1 and the source S1 are each made of a layer of an electrically conductive material making an ohmic contact with the upper layer C1.
  • the drain D1 and the source S1 are made of copper or aluminum or gold preferably, because gold has better resistance to chemical attack.
  • the barrier layer is made of an alloy of tantalum and tantalum oxide.
  • the barrier layer CB has a concentration gradient of tantalum oxide.
  • the barrier layer based on tantalum and tantalum oxide makes it possible to prevent the diffusion of the atoms of the first electrically conductive material in all of the semiconductor layers C1, C2, C3 forming the basic structure B1, and corresponding to the body of the transistor T1. The elimination of the diffusion phenomenon makes it possible to improve the reliability and technological robustness of the transistor.
  • the barrier layer CB has a thickness of between 5nm and 30nm, preferably between 10nm and 20nm. A thickness of the barrier layer CB of less than 20nm makes it possible to minimize the leakage currents of the transistor T1.
  • Tantalum oxide is predominant compared to tantalum in a first part P1 of the barrier layer CB.
  • the first part P1 is located at the interface between the barrier layer CB and the upper layer C1 of the base structure B1.
  • the concentration of tantalum oxide is thus maximum at a first interface between the barrier layer CB and the upper layer C1 and gradually decreases as it moves away from said interface.
  • the first part P1 of the barrier layer CB is comparable to a tantalum oxide layer having a thickness of between 5 nm and 10 nm.
  • the first part P1 plays the electrical role of an oxide layer in the gate of a field effect transistor at said interface.
  • tantalum is in the majority compared to tantalum oxide in a second part P2 of the barrier layer CB.
  • the second part P2 is located at the interface opposite the first interface between the barrier layer CB and the upper layer C1 of the basic structure B1.
  • the tantalum concentration is thus at a maximum at the interface between the barrier layer CB and the layer intermediate Cl and gradually decreases as it moves away from said interface.
  • the second part P2 in tantalum makes it possible to improve the mechanical robustness of the grid by supporting at least the electrical contact structure SC.
  • the total thickness of the barrier layer CB is less than 5 nm.
  • the entire barrier layer CB is mainly made of tantalum oxide.
  • the intermediate layer Cl is optional.
  • the intermediate layer Cl is made of a platinoid or of nickel or of molybdenum.
  • a platinoid is a material chosen from platinum, rhodium, palladium, ruthenium, iridium and osmium.
  • the intermediate layer Cl is confined between the barrier layer CB and the electrical contact structure SC. This makes it possible to improve the adhesion of the electrical contact structure SC, more particularly in the case of gold, and thus improve the mechanical robustness of the gate G1.
  • the introduction of the intermediate layer Cl makes it possible to add an additional barrier to the diffusion of the atoms of the first electrically conductive material in all of the semiconductor layers C1, C2, C3 forming the basic structure B1.
  • the structure of the gate G1 comprising a barrier layer made of a tantalum alloy and tantalum oxide as described above makes it possible to produce a rectifier contact. This makes it possible to obtain a considerable reduction in the leakage currents of the transistor T1 over time.
  • a rectifier electronic contact is designed to allow the flow of electric current in a single direction from the gate G1 to the upper layer C1, by blocking the flow of current in the opposite direction. Consequently, a rectifier electronic contact offers a high resistance in the reverse direction of the flow of current, and a low resistance in the forward direction.
  • FIG. 1 shows a sectional view of a transistor T1 having a gate G1 according to a second embodiment of the invention.
  • Figure 2b shows an enlarged sectional view of the gate G1 according to the second embodiment of the invention.
  • the second embodiment of the invention differs from the first embodiment by the shape of the gate G1.
  • the gate G1 comprises an electrical contact structure SC consisting of a pillar PG and an upper contact layer CH.
  • the upper contact layer CH rests on the pillar PG.
  • the pillar PG has a first width L1 in a parallel direction X orthogonal to the direction of the stack Z.
  • the upper contact layer CH has a second width L2 in a parallel direction X orthogonal to the direction of the stack Z.
  • the second width L2 of the upper contact layer CH is greater than the first width L1 of the pillar PG. Reducing the first width L1 makes it possible to reduce the parasitic capacitance of the gate G1 and increasing the maximum operating frequency of the transistor T1. Widening the second width L2 makes it possible to reduce the resistance of the gate G1.
  • the thickness e1 of the PG pillar is between 20nm and 500nm.
  • a thickness e1 less than 20nm can cause an increase in the parasitic capacitances of the gate G1.
  • a thickness e1 greater than 500nm can mechanically weaken the gate G1.
  • the stack formed by the barrier layer CB and the intermediate layer C1 is arranged between, on the one hand, the pillar PG of the electrical contact structure SC and, on the other hand, the upper layer C1.
  • the barrier layer CB is deposited on the external walls of the pillar PG, with direct or indirect contact through the intermediate layer C1.
  • the barrier layer CB is further deposited on the lower external wall of the upper contact layer CH, with direct or indirect contact through the intermediate layer C1.
  • the second width L2 is greater than or equal to six times the first width L1. This makes it possible to optimize the resistance of the grid G1 and the reduction of parasitic capacitances on the one hand, and the mechanical robustness of the G1 grid structure on the other hand.
  • FIG. 3 shows a cross-sectional view of a transistor T1 having a gate G1 according to a third embodiment of the invention.
  • the technical characteristics and advantages described for the first and second embodiments remain valid for the third embodiment.
  • the third embodiment of the invention differs from the second embodiment by a progressive variation in the width of the electrical contact structure SC so as to obtain a “tulip” type structure.
  • the electrical contact structure SC gradually widens as it moves away from the base structure B1. This makes it possible to reduce the resistance of the gate G1 while reducing the parasitic capacitance of the gate G1.
  • a progressive increase in the width of the electrical contact structure SC makes it possible to obtain a mechanically more robust gate without degrading the electrical performance of the transistor T1.
  • the barrier layer CB is deposited on the external walls of the electrical contact structure SC, with direct or indirect contact through the intermediate layer Cl so as to confine the first electrically conductive material.
  • Figure 4 shows a cross-sectional view of a transistor T1 having a gate G1 according to a fourth embodiment of the invention.
  • the characteristics and technical advantages described for the first and second embodiments remain valid for the fourth embodiment.
  • This is a variant of the shape of the gate G1 in the form of Gamma.
  • the transistor T1 comprises a diamond or boron nitride encapsulation layer which encapsulates at least the gate G1.
  • This variant is compatible with all the embodiments previously described.
  • the deposition of a diamond or boron nitride layer requires the application of a high thermal stress on the transistor T1.
  • the structure of the gate G1 according to the invention makes it possible to carry out this step of deposition of a diamond or boron nitride encapsulation layer without degradation of the robustness of the transistor by diffusion thanks to the barrier layer made of tantalum alloy and tantalum oxide.
  • Figure 5 illustrates a flowchart of the method P1 for manufacturing the grid G1 according to any one of the embodiments of the invention.
  • Figures 6a to 6g illustrate the steps of the method P1 according to the invention.
  • the first step i) consists in providing a stack of layers forming a base structure B1 comprising the upper layer C1 in a first semiconductor material.
  • the base structure B1 is produced on a substrate SUB.
  • the base structure B1 is intended to form the body of the transistor T1 during manufacture.
  • FIG. 6a illustrates by way of non-limiting example and without loss of generality the base structure B1 described above for the production of a high electron speed transistor HEMT.
  • the first step i) can be carried out by the growth of thin layers by epitaxy.
  • the second step ii) consists in depositing an electro-sensitive resin RES on the entire upper surface of the base structure B1 and in manufacturing a pattern 11 corresponding to a predetermined shape of the grid G1 in said resin.
  • the manufacturing of the pattern 11 is carried out by electron beam lithography:
  • the resin RES is exposed to an electron beam.
  • the beam defines the pattern 11 according to a predetermined program.
  • the pattern 11 corresponds to an empty volume manufactured in a portion of the resin.
  • the parts of the resin RES exposed to the electron beam are weakened and then removed by a suitable solvent.
  • the resin RES must have a chemical composition comprising free oxygen functions.
  • the resin RES is made of Poly-methyl-methacrylate (P MM A).
  • P MM A Poly-methyl-methacrylate
  • the method P1 is illustrated with a grid shape G1 according to the second embodiment for information purposes and without limitation.
  • the method P1 is compatible with the other embodiments of the grid G1 according to the invention by adapting the shape of the pattern 11.
  • the third step iii) consists in depositing a barrier layer CB made of an alloy of tantalum and tantalum oxide on the internal walls of said pattern 11 as illustrated in FIG. 6c.
  • the deposition can be carried out by evaporation or by sputtering.
  • FIG. 7 illustrates the performance of this step in an evaporation deposition equipment as an example. Indeed, the sample is loaded into the enclosure E0 (also called a frame or chamber) of a deposition equipment.
  • the enclosure E0 comprises a tantalum source SoM1 heated to a temperature T o higher than at 1900°C.
  • the pressure P o in the enclosure is less than 5.10' 5 Pa.
  • the tantalum source SoM1 is bombarded by an electron beam, which causes tantalum atoms to be torn off from the tantalum source SoM1 and to move them towards the upper surface of the sample (target formed by the base structure B1 on which the pattern 11 was fabricated).
  • the tantalum source SoM1 is placed at a separation distance d1 from the base structure B1 chosen so as to obtain an oxidation reaction between the deposited tantalum atoms and the free oxygen atoms provided by the resin RES.
  • the separation distance d1 is between 30 cm and 70 cm and preferably between 45 cm and 55 cm. The intensity of the oxidation reactions gradually decreases with the growth of the deposited layer.
  • the barrier layer CB made of an alloy of tantalum and tantalum oxide with a concentration gradient of tantalum oxide decreasing with the increase in the thickness of the barrier layer CB, and conversely a concentration gradient of tantalum increasing with the increase in the thickness of the barrier layer CB.
  • the barrier layer CB is deposited on internal walls of the pattern 11 formed by the resin RES and on the visible upper surface of the upper layer C1 of the base structure B1.
  • Step iv) consists in depositing a layer of a first electrically conductive material to fill the pattern 11 in order to obtain a contact structure SC as illustrated in FIG. 6e.
  • the deposition is carried out in the enclosure E0 of the same deposition equipment without discharging the base structure B1 and while maintaining the same pressure P o .
  • the deposit is made from a source of gold metal for example bombarded by an electron beam.
  • Step v) consists of destroying the remaining RES resin structure to keep only the grid G1 from the pattern 11.
  • the destruction of the RES resin can be carried out chemically using specific solvents.
  • the method P1 further comprises a step vi) of thermal annealing of the transistor T1 at a temperature between 400°C and 600°C for a duration of between 1 and 2 minutes in a nitrogen atmosphere or under vacuum.
  • the annealing step makes it possible to obtain a significant reduction in the leakage current density to values below 200 nA/mm. This reduction in leakage currents is also accompanied by an increase in the output current density, for example from 0.77 A/mm (before annealing) to 1.4 A/mm (after annealing).
  • the structure of the gate G1 according to the invention makes it possible to carry out this thermal annealing step without degrading the robustness of the transistor by diffusion thanks to the barrier layer made of tantalum alloy and tantalum oxide.
  • the method P1 further comprises a step vii) of depositing a diamond or boron nitride encapsulation layer by the chemical vapor deposition technique (CVD) at a temperature above 600°C as illustrated in FIG. 6g.
  • CVD chemical vapor deposition technique
  • the structure of the gate G1 according to the invention makes it possible to carry out this encapsulation layer deposition step without degrading the robustness of the transistor by diffusion thanks to the barrier layer made of tantalum alloy and tantalum oxide.
  • the barrier layer CB gives the gate G1 excellent temperature resistance, preventing the latter from deforming under the effect of heat.

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Abstract

Disclosed is a field-effect transistor comprising a drain (D1), source (S1) and gate (G1) deposited on a top layer (C1), made of a first semiconductor material, of a stack of layers that is deposited on a substrate (SUB) and forms a base structure (B1), the gate comprising: • - an electrical contact structure (SC) made of a first electrically conductive material; • - a barrier layer (CB) made of an alloy of tantalum and tantalum oxide, the barrier layer separating said top layer from the contact structure in order to block diffusion of the first electrically conductive material into the base structure, and the barrier layer having a tantalum-oxide concentration gradient, tantalum oxide being present in greater amount than tantalum in a first portion (P1) of the barrier layer located at a first interface between the barrier layer and the top layer.

Description

DESCRIPTION DESCRIPTION

Titre de l’invention : Grille de transistor à base d’oxyde de tantale Title of the invention: Tantalum oxide-based transistor gate

[0001] L’invention concerne le domaine de la fabrication des transistors, plus particulièrement la fabrication des grilles de transistors soumis à des fortes contraintes thermiques. [0001] The invention relates to the field of transistor manufacturing, more particularly the manufacturing of transistor gates subjected to high thermal stresses.

[0002] La fabrication des transistors comprend une étape cruciale : la fabrication de la grille de commande. En effet, la grille est soumise à de fortes contraintes thermiques, tant pendant la fabrication que lors de l'utilisation. Les grilles de transistors produites ont tendance à ne pas suffisamment empêcher la diffusion du métal conducteur de ladite grille dans le corps du transistor, qui est constitué généralement d'un matériau semi-conducteur. On entend par le corps du transistor la structure en au moins une couche en semi-conducteur dans laquelle se forme le canal de conduction entre la source et le drain lorsque le transistor est dans un état passant. Cette diffusion entraîne une diminution des performances du transistor, avec une augmentation des courants de fuite. De plus, la diffusion du métal constituant le contact de la grille dans le corps du transistor induit une dégradation du contact redresseur entre la grille et la couche supérieure semi-conductrice du corps du transistor. En d'autres termes, la robustesse technique et la fiabilité des transistors dépendent des propriétés électriques, thermiques et mécaniques de la grille de commande. [0002] The manufacture of transistors includes a crucial step: the manufacture of the control gate. Indeed, the gate is subjected to high thermal stresses, both during manufacture and during use. The transistor gates produced tend not to sufficiently prevent the diffusion of the conductive metal of said gate into the body of the transistor, which is generally made of a semiconductor material. The term "transistor body" refers to the structure in at least one semiconductor layer in which the conduction channel between the source and the drain is formed when the transistor is in an on state. This diffusion leads to a reduction in the performance of the transistor, with an increase in leakage currents. In addition, the diffusion of the metal constituting the gate contact into the body of the transistor induces a degradation of the rectifier contact between the gate and the upper semiconductor layer of the transistor body. In other words, the technical robustness and reliability of transistors depend on the electrical, thermal and mechanical properties of the control gate.

[0003] Le problème technique identifié est rencontré dans les différentes structures de transistors couvrant à titre d’exemple illustratif non limitatif les technologies CMOS (acronyme de l’expression en anglais Complementary metal-oxide-semiconductor) SOI (acronyme de l’expression en anglais Silicon-on-lnsulator), HEMT (acronyme de l’expression en anglais High Electron Mobility Transistor) et FinFET (acronyme de l’expression en anglais fin field-effect transistor). [0003] The identified technical problem is encountered in the various transistor structures covering, by way of non-limiting illustrative example, CMOS (acronym for the expression in English Complementary metal-oxide-semiconductor), SOI (acronym for the expression in English Silicon-on-lnsulator), HEMT (acronym for the expression in English High Electron Mobility Transistor) and FinFET (acronym for the expression in English Fin field-effect transistor) technologies.

[0004] De manière plus particulière, les transistors à haute mobilité électronique (High Electron Mobility Transistors - HEMT) sont destinés à des applications de puissance hyperfréquence. Ainsi, lors de leurs utilisations, les transistors HEMT sont soumis à d’importantes contraintes thermiques. Les hautes températures auxquelles les transistors sont exposés sont à l’origine de défaillances dues à la diffusion du matériau conducteur de la grille jusqu’à la surface du semi-conducteur constituant le corps du transistor. La diffusion entraine l’augmentation des courants de fuite qui dégradent les performances du transistor et réduisent sa durée de vie. [0004] More specifically, high electron mobility transistors (HEMTs) are intended for microwave power applications. Thus, during their use, HEMT transistors are subjected to significant thermal stresses. The high temperatures to which the transistors are exposed cause failures due to the diffusion of the conductive material from the gate to the surface of the semiconductor constituting the transistor body. Diffusion leads to increased leakage currents which degrade the transistor's performance and reduce its lifetime.

[0005] De plus, le phénomène de diffusion peut présenter des limitations par rapport à l’exécution d’autres étapes du procédé de fabrication du transistor nécessitant l’application d’un fort budget thermique. Par exemple, la réalisation d’une couche d’encapsulation en diamant à haute température provoque le phénomène de diffusion préalablement décrit. Cela limite le choix des matériaux de la couche d’encapsulation et empêche le dépôt de couches d’encapsulation présentant une protection améliorée tel que le diamant. [0005] In addition, the diffusion phenomenon may present limitations with respect to the execution of other steps of the transistor manufacturing process requiring the application of a high thermal budget. For example, the production of a diamond encapsulation layer at high temperature causes the diffusion phenomenon previously described. This limits the choice of materials for the encapsulation layer and prevents the deposition of encapsulation layers having improved protection such as diamond.

[0006] En ce sens, il est donc important de développer une architecture de grille et un procédé de fabrication de ladite grille permettant d’éliminer le phénomène de diffusion métallique de la grille de commande dans le corps du transistor soumis à de fortes contraintes thermiques et/ou électriques. [0006] In this sense, it is therefore important to develop a gate architecture and a method of manufacturing said gate making it possible to eliminate the phenomenon of metallic diffusion of the control gate in the body of the transistor subjected to high thermal and/or electrical constraints.

[0007] Nous allons commencer par introduire les solutions connues par l’Homme de l’art présentant des matériaux utilisés pour réaliser une grille de commande d’un transistor soumis à de fortes contraintes thermiques ou électriques. [0007] We will begin by introducing the solutions known to those skilled in the art presenting materials used to produce a control grid for a transistor subjected to high thermal or electrical constraints.

[0008] Différents empilements métalliques constituant une grille de commande d’un transistor, tels que le Ni/Au, le Mo/Au, le Pt/Au et le Ni/Pt/Au, ont été étudiés, mais cela n'a pas conduit à une amélioration significative de la robustesse des grilles. [0008] Various metal stacks constituting a control gate of a transistor, such as Ni/Au, Mo/Au, Pt/Au and Ni/Pt/Au, have been studied, but this has not led to a significant improvement in the robustness of the gates.

[0009] Le brevet américain US7411226B2 concerne une structure de transistor à haute mobilité électronique en InP dans laquelle un empilement de métaux de grille comprend une fine couche supplémentaire d'un métal réfractaire, tel que le molybdène Mo ou le platine Pt. La couche de métal réfractaire réduit ou élimine la dégradation à long terme de la jonction Schottky entre le métal de grille et la couche barrière. [0009] US patent US7411226B2 relates to a high electron mobility transistor structure made of InP in which a gate metal stack includes an additional thin layer of a refractory metal, such as molybdenum Mo or platinum Pt. The refractory metal layer reduces or eliminates long-term degradation of the Schottky junction between the gate metal and the barrier layer.

[0010] Pour pallier les limitations des solutions existantes, l’invention propose une structure de grille de commande d’un transistor comprenant une couche barrière réalisée en un alliage de tantale et d’oxyde de tantale. La couche barrière CB sépare la structure de contact électrique de la grille, du corps du transistor pour bloquer la diffusion du métal dans le corps du transistor. Principalement, la structure de grille selon l’invention permet d’éliminer le phénomène de diffusion métallique et ainsi améliorer la fiabilité et la robustesse du transistor. [0011] De plus, l’invention permet l’amélioration des caractéristiques électriques du transistor. En effet, l’empilement de couches constituant la grille selon l’invention permet d’obtenir un contact redresseur à hauteur de barrière élevée avec ou sans recuit thermique. [0010] To overcome the limitations of existing solutions, the invention proposes a control gate structure of a transistor comprising a barrier layer made of an alloy of tantalum and tantalum oxide. The barrier layer CB separates the electrical contact structure of the gate from the body of the transistor to block the diffusion of metal into the body of the transistor. Mainly, the gate structure according to the invention makes it possible to eliminate the phenomenon of metal diffusion and thus improve the reliability and robustness of the transistor. [0011] Furthermore, the invention allows the improvement of the electrical characteristics of the transistor. Indeed, the stack of layers constituting the gate according to the invention makes it possible to obtain a rectifier contact with a high barrier height with or without thermal annealing.

[0012] De plus, la structure de la grille de commande selon l’invention est compatible avec un fonctionnement des applications dans des environnements agressifs. En effet, la grille présente une résistance améliorée à la corrosion et aux agressions chimiques. [0012] Furthermore, the structure of the control grid according to the invention is compatible with operation of the applications in aggressive environments. Indeed, the grid has improved resistance to corrosion and chemical attacks.

[0013] L’invention propose en outre un procédé « in-situ » de fabrication de la grille de commande selon l’invention. En effet, l’empilement de couches formant la grille selon l’invention est réalisable dans le même environnement sans besoin de décharger l’échantillon de l’équipement du dépôt. Cela permet de simplifier le procédé de fabrication de la grille et ainsi gagner en temps de production et en rendement (du terme « yield » en anglais). [0013] The invention further proposes an “in-situ” method for manufacturing the control grid according to the invention. Indeed, the stacking of layers forming the grid according to the invention can be carried out in the same environment without the need to unload the sample from the deposition equipment. This makes it possible to simplify the grid manufacturing process and thus save production time and yield.

[0014] Nous allons décrire l’invention dans le contexte d’un transistor à haute mobilité électronique à titre illustratif, non limitatif et sans perte de généralité. La grille selon l’invention et son procédé de fabrication restent compatibles avec tout type de transistor à effet de champ, indépendamment de la nature de l’empilement de couches constituant le corps du transistor. [0014] We will describe the invention in the context of a high electron mobility transistor for illustrative purposes, without limitation and without loss of generality. The gate according to the invention and its manufacturing method remain compatible with any type of field effect transistor, regardless of the nature of the stack of layers constituting the body of the transistor.

[0015] L’invention a pour objet un transistor à effet de champ comprenant un drain , une source et une grille disposés sur une couche supérieure en un premier matériau semi-conducteur d’un empilement de couches disposé sur un substrat et formant une structure de base ; la grille comprenant : [0015] The invention relates to a field effect transistor comprising a drain, a source and a gate arranged on an upper layer made of a first semiconductor material of a stack of layers arranged on a substrate and forming a base structure; the gate comprising:

- une structure de contact électrique réalisée en un premier matériau électriquement conducteur ; - an electrical contact structure made of a first electrically conductive material;

- une couche barrière réalisée en un alliage de tantale et d’oxyde de tantale ; la couche barrière séparant ladite couche supérieure de la structure de contact pour bloquer la diffusion du premier matériau électriquement conducteur dans la structure de base; la couche barrière présentant un gradient de concentration en oxyde de tantale, l’oxyde de tantale étant majoritaire par rapport au tantale dans une première partie de la couche barrière située à une première interface entre la couche barrière et la couche supérieure . - a barrier layer made of an alloy of tantalum and tantalum oxide; the barrier layer separating said upper layer from the contact structure to block the diffusion of the first electrically conductive material into the base structure; the barrier layer having a tantalum oxide concentration gradient, the tantalum oxide being in the majority compared to the tantalum in a first part of the barrier layer located at a first interface between the barrier layer and the upper layer.

[0016] Selon un aspect particulier de l’invention, la couche barrière comprend une seconde partie constituée de tantale située à une seconde interface opposée à la première interface. [0016] According to a particular aspect of the invention, the barrier layer comprises a second part made of tantalum located at a second interface opposite the first interface.

[0017] Selon un aspect particulier de l’invention, le premier matériau électriquement conducteur est l’or ou l’aluminium ou le cuivre. [0017] According to a particular aspect of the invention, the first electrically conductive material is gold or aluminum or copper.

[0018] Selon un aspect particulier de l’invention, la grille comprend en outre une couche intermédiaire confinée entre la structure de contact et la couche barrière ; ladite couche intermédiaire étant réalisée en un platinoïde ou en nickel ou en molybdène. [0018] According to a particular aspect of the invention, the grid further comprises an intermediate layer confined between the contact structure and the barrier layer; said intermediate layer being made of a platinoid or of nickel or of molybdenum.

[0019] Selon un aspect particulier de l’invention, le premier matériau semi- conducteur présente un travail de sortie inférieur à celui du tantale pour réaliser un contact redresseur. [0019] According to a particular aspect of the invention, the first semiconductor material has an output work lower than that of tantalum to produce a rectifier contact.

[0020] Selon un aspect particulier de l’invention, la couche barrière présente une épaisseur comprise entre 5nm et 30nm. [0020] According to a particular aspect of the invention, the barrier layer has a thickness of between 5 nm and 30 nm.

[0021 ] Selon un aspect particulier de l’invention, la première partie de la couche barrière présente une épaisseur comprise entre 5nm et 10nm. [0021] According to a particular aspect of the invention, the first part of the barrier layer has a thickness of between 5 nm and 10 nm.

[0022] Selon un aspect particulier de l’invention, le transistor à effet de champ comprend en outre une couche d’encapsulation en diamant ou en nitrure de bore ; la grille étant couverte par ladite couche d’encapsulation. [0022] According to a particular aspect of the invention, the field effect transistor further comprises an encapsulation layer made of diamond or boron nitride; the gate being covered by said encapsulation layer.

[0023] Selon un aspect particulier de l’invention, la structure de contact comprend un pilier et une couche supérieure de contact reposant sur ledit pilier et ayant une largeur supérieure à celle du pilier. [0023] According to a particular aspect of the invention, the contact structure comprises a pillar and an upper contact layer resting on said pillar and having a width greater than that of the pillar.

[0024] L’invention a également pour objet un procédé de fabrication d’une grille d’un transistor à effet de champ comprenant les étapes suivantes: [0024] The invention also relates to a method of manufacturing a gate of a field effect transistor comprising the following steps:

- fournir un empilement de couches formant une structure de base comprenant une couche supérieure en un premier matériau semi-conducteur ; - déposer une résine avec une composition chimique comprenant des fonctions oxygène libres sur la couche supérieure et fabriquer un motif correspondant à une forme prédéterminée de la grille dans la résine par lithographie; déposer une couche barrière réalisée en un alliage de tantale et d’oxyde de tantale sur les parois internes dudit motif dans l’enceinte d’un équipement de dépôt ayant une température supérieure à 1900°C; le dépôt étant réalisé à partir d’une source de tantale placée à une distance de séparation de la structure de base choisie de manière à obtenir une couche barrière présentant un gradient de concentration en oxyde de tantale ; - providing a stack of layers forming a basic structure comprising an upper layer made of a first semiconductor material; - depositing a resin with a chemical composition comprising free oxygen functions on the upper layer and manufacturing a pattern corresponding to a predetermined shape of the grid in the resin by lithography; depositing a barrier layer made of an alloy of tantalum and tantalum oxide on the internal walls of said pattern in the enclosure of deposition equipment having a temperature greater than 1900°C; the deposition being carried out from a tantalum source placed at a separation distance from the base structure chosen so as to obtain a barrier layer having a tantalum oxide concentration gradient;

- déposer une couche en un premier matériau électriquement conducteur pour remplir le motif afin d’obtenir une structure de contact ; le dépôt étant réalisé dans l’enceinte dudit équipement de dépôt sans décharger la structure de base ; le dépôt étant réalisé à partir d’une source du premier matériau électriquement conducteur ; - depositing a layer of a first electrically conductive material to fill the pattern in order to obtain a contact structure; the deposition being carried out in the enclosure of said deposition equipment without discharging the base structure; the deposition being carried out from a source of the first electrically conductive material;

- détruire la résine. - destroy the resin.

[0025] D’autres caractéristiques et avantages de la présente invention apparaîtront mieux à la lecture de la description qui suit en relation aux dessins annexés suivants. [0025] Other features and advantages of the present invention will become more apparent upon reading the following description in relation to the following appended drawings.

[0026] [Fig. 1] la figure 1 représente une vue en coupe d’un transistor ayant une grille selon un premier mode de réalisation de l’invention. [0026] [Fig. 1] Figure 1 shows a sectional view of a transistor having a gate according to a first embodiment of the invention.

[0027] [Fig. 2a] la figure 2a représente une vue en coupe d’un transistor ayant une grille selon un deuxième mode de réalisation de l’invention. [0027] [Fig. 2a] Figure 2a shows a sectional view of a transistor having a gate according to a second embodiment of the invention.

[0028] [Fig. 2b] la figure 2b représente une vue en coupe de la grille selon le deuxième mode de réalisation de l’invention. [0028] [Fig. 2b] Figure 2b shows a sectional view of the grid according to the second embodiment of the invention.

[0029] [Fig. 3] la figure représente une vue en coupe d’un transistor ayant une grille selon un troisième mode de réalisation de l’invention. [0029] [Fig. 3] the figure represents a sectional view of a transistor having a gate according to a third embodiment of the invention.

[0030] [Fig. 4] la figure représente une vue en coupe d’un transistor ayant une grille selon un quatrième mode de réalisation de l’invention. [0030] [Fig. 4] the figure represents a sectional view of a transistor having a gate according to a fourth embodiment of the invention.

[0031] [Fig. 5] la figure 5 illustre un organigramme du procédé de fabrication de la grille selon l’un quelconque des modes de réalisation de l’invention. [0032] [Fig. 6a] la figure 6a illustre la première étape du procédé de fabrication de la grille selon l’invention. [0031] [Fig. 5] Figure 5 illustrates a flowchart of the method of manufacturing the grid according to any of the embodiments of the invention. [0032] [Fig. 6a] Figure 6a illustrates the first step of the method of manufacturing the grid according to the invention.

[0033] [Fig. 6b] la figure 6b illustre la deuxième étape du procédé de fabrication de la grille selon l’invention. [0033] [Fig. 6b] Figure 6b illustrates the second step of the method of manufacturing the grid according to the invention.

[0034] [Fig. 6c] la figure 6c illustre la troisième étape du procédé de fabrication de la grille selon l’invention. [0034] [Fig. 6c] Figure 6c illustrates the third step of the method of manufacturing the grid according to the invention.

[0035] [Fig. 6d] la figure 6d illustre la troisième étape optionnelle du procédé de fabrication de la grille selon l’invention. [0035] [Fig. 6d] Figure 6d illustrates the third optional step of the method of manufacturing the grid according to the invention.

[0036] [Fig. 6e] la figure 6e illustre la quatrième étape du procédé de fabrication de la grille selon l’invention. [0036] [Fig. 6e] Figure 6e illustrates the fourth step of the method of manufacturing the grid according to the invention.

[0037] [Fig. 6f] la figure 6f illustre la cinquième étape du procédé de fabrication de la grille selon l’invention. [0037] [Fig. 6f] Figure 6f illustrates the fifth step of the method of manufacturing the grid according to the invention.

[0038] [Fig. 6g] la figure 6g illustre la septième étape du procédé de fabrication de la grille selon l’invention. [0038] [Fig. 6g] Figure 6g illustrates the seventh step of the method of manufacturing the grid according to the invention.

[0039] [Fig. 7] la figure 7 illustre un exemple d’exécution de la troisième étape du procédé de fabrication de la grille selon l’invention. [0039] [Fig. 7] Figure 7 illustrates an example of execution of the third step of the method of manufacturing the grid according to the invention.

[0040] La figure 1 représente une vue en coupe d’un transistor T1 ayant une grille G1 selon un premier mode de réalisation de l’invention. À titre illustratif et sans perte de généralité, le transistor T1 est un transistor à haute mobilité électronique. Le transistor T1 comprend un drain D1 , une source S1 , une grille G1 et une structure de base B1 correspondant au corps du transistor T1. La structure de base B1 est formée par un empilement de couches minces déposées sur un substrat SUB formant une hétéro-structure. Alternativement, la structure de base B1 peut être une couche massive en un matériau semi-conducteur. De manière générale, la structure de base comprend une couche supérieure semi-conductrice C1 en partant de substrat SUB. Le drain D1 , la source S1 et la grille G1 sont disposés sur ladite couche supérieure semi-conductrice C1. La structure de base B1 est destinée à contenir le canal de conduction entre la source S1 et le drain D1 . [0040] Figure 1 shows a cross-sectional view of a transistor T1 having a gate G1 according to a first embodiment of the invention. By way of illustration and without loss of generality, the transistor T1 is a high electron mobility transistor. The transistor T1 comprises a drain D1, a source S1, a gate G1 and a base structure B1 corresponding to the body of the transistor T1. The base structure B1 is formed by a stack of thin layers deposited on a substrate SUB forming a hetero-structure. Alternatively, the base structure B1 may be a bulk layer made of a semiconductor material. Generally, the base structure comprises an upper semiconductor layer C1 starting from the substrate SUB. The drain D1, the source S1 and the gate G1 are arranged on said upper semiconductor layer C1. The base structure B1 is intended to contain the conduction channel between the source S1 and the drain D1.

[0041] Dans l’exemple illustré d’un transistor T1 à haute mobilité électronique (HEMT), la structure de base B1 comprend l’empilement de couches suivant en partant du substrat SUB : - une couche tampon C3 pour ajuster la structure cristalline lors de la croissance par épitaxie. Par exemple, la couche tampon C3 est réalisée en alliage de nitrure de gallium avec de l’aluminium GaN/AIGaN. [0041] In the illustrated example of a high electron mobility transistor (HEMT) T1, the basic structure B1 comprises the following stack of layers starting from the substrate SUB: - a C3 buffer layer to adjust the crystal structure during epitaxial growth. For example, the C3 buffer layer is made of gallium nitride alloy with aluminum GaN/AIGaN.

- La couche de canal C2 correspondant au canal du transistor. Elle est constituée d'un matériau semi-conducteur à haute mobilité électronique, comme le nitrure de gallium GaN. - The C2 channel layer corresponding to the transistor channel. It is made of a semiconductor material with high electron mobility, such as gallium nitride GaN.

- La couche de confinement C1 pour générer les porteurs de charges dans la couche de canal. La couche de confinement C1 est réalisée par un matériau semi-conducteur ayant un gap d’énergie supérieur à celui du matériau semi- conducteur de la couche de canal C2. Par exemple, la couche confinement C1 est réalisée en alliage quaternaire de semi-conducteur de type lll-V. - The confinement layer C1 to generate the charge carriers in the channel layer. The confinement layer C1 is made of a semiconductor material having an energy gap greater than that of the semiconductor material of the channel layer C2. For example, the confinement layer C1 is made of a quaternary alloy of type III-V semiconductor.

[0042] Avantageusement, la structure de base B1 comprend des tranchées d’isolation TR réalisées par gravure ou implantation ionique pour délimiter latéralement le transistor T1 et ainsi réduire les courants de fuite. [0042] Advantageously, the basic structure B1 comprises isolation trenches TR produced by etching or ion implantation to laterally delimit the transistor T1 and thus reduce leakage currents.

[0043] Dans l’exemple illustré, la couche supérieure de la structure de base B1 est la couche de confinement C1 . Ladite couche supérieure C1 présente une interface de contact avec la grille G1 , le drain D1 et la source S1 . [0043] In the illustrated example, the upper layer of the base structure B1 is the confinement layer C1. Said upper layer C1 has a contact interface with the gate G1, the drain D1 and the source S1.

[0044] Le drain D1 et la source S1 sont réalisés chacun par une couche en un matériau électriquement conducteur réalisant un contact ohmique avec la couche supérieure C1. À titre d’exemple, le drain D1 et la source S1 sont réalisés par du cuivre ou de l’aluminium ou de l’or de manière préférentielle, car l’or présente une meilleure résistance aux agressions chimiques. Alternativement, il est possible de réaliser le drain D1 et la source S1 par croissance par épitaxie de GaN. [0044] The drain D1 and the source S1 are each made of a layer of an electrically conductive material making an ohmic contact with the upper layer C1. For example, the drain D1 and the source S1 are made of copper or aluminum or gold preferably, because gold has better resistance to chemical attack. Alternatively, it is possible to make the drain D1 and the source S1 by epitaxial growth of GaN.

[0045] La grille G1 selon le premier mode de réalisation de l’invention comprend une structure de contact électrique SC formée par une couche en un premier matériau électriquement conducteur, une couche intermédiaire Cl et une couche barrière CB. On obtient ainsi une grille sous forme de pilier formé par l’empilement des couches planaires CB, Cl, SC. Le pilier est réalisé selon cet ordre en partant de la couche supérieure C1 de la structure de base B1 : la couche barrière CB puis la couche intermédiaire Cl puis la structure de contact électrique SC. La couche barrière CB sépare la couche supérieure C1 semi-conductrice de la structure de contact électrique SC. [0046] La structure de contact SC électrique est destinée à recevoir un signal de commande appliqué à la grille de commande G1 du transistor T1 pour le configurer selon un état passant ou un état bloquant. À titre d’exemple, le premier matériau électriquement conducteur est l’or ou l’aluminium ou le cuivre. Préférentiellement, le premier matériau électriquement conducteur est l’or qui présente des caractéristiques électriques compatibles avec un fonctionnement hyperfréquence et une bonne résistance aux corrosions chimiques. [0045] The gate G1 according to the first embodiment of the invention comprises an electrical contact structure SC formed by a layer of a first electrically conductive material, an intermediate layer Cl and a barrier layer CB. A gate is thus obtained in the form of a pillar formed by stacking the planar layers CB, Cl, SC. The pillar is produced in this order starting from the upper layer C1 of the base structure B1: the barrier layer CB then the intermediate layer Cl then the electrical contact structure SC. The barrier layer CB separates the upper semiconducting layer C1 from the electrical contact structure SC. [0046] The electrical contact structure SC is intended to receive a control signal applied to the control gate G1 of the transistor T1 to configure it according to an on state or a blocking state. For example, the first electrically conductive material is gold or aluminum or copper. Preferably, the first electrically conductive material is gold which has electrical characteristics compatible with microwave operation and good resistance to chemical corrosion.

[0047] La couche barrière est réalisée en un alliage de tantale et d’oxyde de tantale. La couche barrière CB présente un gradient de concentration en oxyde de tantale. La couche barrière à base de tantale et d’oxyde de tantale permet d’empêcher la diffusion des atomes du premier matériau électriquement conducteur dans l’ensemble des couches semi-conductrices C1 , C2, C3 formant la structure de base B1 , et correspondant au corps du transistor T1. L’élimination du phénomène de diffusion permet d’améliorer la fiabilité et la robustesse technologique du transistor. [0047] The barrier layer is made of an alloy of tantalum and tantalum oxide. The barrier layer CB has a concentration gradient of tantalum oxide. The barrier layer based on tantalum and tantalum oxide makes it possible to prevent the diffusion of the atoms of the first electrically conductive material in all of the semiconductor layers C1, C2, C3 forming the basic structure B1, and corresponding to the body of the transistor T1. The elimination of the diffusion phenomenon makes it possible to improve the reliability and technological robustness of the transistor.

[0048] La couche barrière CB présente une épaisseur comprise entre 5nm et 30nm, de préférence comprise entre 10nm et 20nm. Une épaisseur de la couche barrière CB inférieure à 20nm permet de minimiser les courants de fuites du transistor T1 . [0048] The barrier layer CB has a thickness of between 5nm and 30nm, preferably between 10nm and 20nm. A thickness of the barrier layer CB of less than 20nm makes it possible to minimize the leakage currents of the transistor T1.

[0049] L’oxyde de tantale est majoritaire par rapport au tantale dans une première partie P1 de la couche barrière CB. La première partie P1 est située au niveau de l’interface entre la couche barrière CB et la couche supérieure C1 de la structure de base B1 . La concentration en oxyde de tantale est ainsi maximale au niveau d’une première interface entre la couche barrière CB et la couche supérieure C1 et diminue progressivement en s’éloignant de ladite interface. La première partie P1 de la couche barrière CB est assimilable à une couche en oxyde de tantale présentant une épaisseur comprise entre 5nm et 10nm. La première partie P1 joue le rôle électrique d’une couche d’oxyde dans la grille d’un transistor à effet de champ au niveau de ladite interface. [0049] Tantalum oxide is predominant compared to tantalum in a first part P1 of the barrier layer CB. The first part P1 is located at the interface between the barrier layer CB and the upper layer C1 of the base structure B1. The concentration of tantalum oxide is thus maximum at a first interface between the barrier layer CB and the upper layer C1 and gradually decreases as it moves away from said interface. The first part P1 of the barrier layer CB is comparable to a tantalum oxide layer having a thickness of between 5 nm and 10 nm. The first part P1 plays the electrical role of an oxide layer in the gate of a field effect transistor at said interface.

[0050] Inversement, le tantale est majoritaire par rapport à l’oxyde de tantale dans une seconde partie P2 de la couche barrière CB. La seconde partie P2 est située au niveau de l’interface opposée à la première interface entre la couche barrière CB et la couche supérieure C1 de la structure de base B1 . La concentration en tantale est ainsi maximale au niveau de l’interface entre la couche barrière CB et la couche intermédiaire Cl et diminue progressivement en s’éloignant de ladite interface. La seconde partie P2 en tantale permet d’améliorer la robustesse mécanique de la grille en supportant au moins la structure de contact électrique SC. [0050] Conversely, tantalum is in the majority compared to tantalum oxide in a second part P2 of the barrier layer CB. The second part P2 is located at the interface opposite the first interface between the barrier layer CB and the upper layer C1 of the basic structure B1. The tantalum concentration is thus at a maximum at the interface between the barrier layer CB and the layer intermediate Cl and gradually decreases as it moves away from said interface. The second part P2 in tantalum makes it possible to improve the mechanical robustness of the grid by supporting at least the electrical contact structure SC.

[0051] Selon un aspect particulier de l’invention, l’épaisseur totale de la couche barrière CB est inférieure à 5nm. Dans ce cas, l’ensemble de la couche barrière CB est majoritairement en oxyde de tantale. [0051] According to a particular aspect of the invention, the total thickness of the barrier layer CB is less than 5 nm. In this case, the entire barrier layer CB is mainly made of tantalum oxide.

[0052] Dans le contexte de l’invention, la couche intermédiaire Cl est optionnelle. La couche intermédiaire Cl est réalisée en un platinoïde ou en nickel ou en molybdène. Un platinoïde est un matériau choisi parmi le platine, le rhodium, le palladium, le ruthénium, l'iridium et l'osmium. La couche intermédiaire Cl est confinée entre la couche barrière CB et la structure de contact électrique SC. Cela permet d’améliorer l’adhérence de la structure de contact électrique SC, plus particulièrement dans le cas de l’or, et ainsi améliorer la robustesse mécanique de la grille G1. De plus, l’introduction de la couche intermédiaire Cl permet de rajouter une barrière supplémentaire à la diffusion des atomes du premier matériau électriquement conducteur dans l’ensemble des couches semi-conductrices C1 , C2, C3 formant la structure de base B1 . [0052] In the context of the invention, the intermediate layer Cl is optional. The intermediate layer Cl is made of a platinoid or of nickel or of molybdenum. A platinoid is a material chosen from platinum, rhodium, palladium, ruthenium, iridium and osmium. The intermediate layer Cl is confined between the barrier layer CB and the electrical contact structure SC. This makes it possible to improve the adhesion of the electrical contact structure SC, more particularly in the case of gold, and thus improve the mechanical robustness of the gate G1. In addition, the introduction of the intermediate layer Cl makes it possible to add an additional barrier to the diffusion of the atoms of the first electrically conductive material in all of the semiconductor layers C1, C2, C3 forming the basic structure B1.

[0053] La structure de la grille G1 comprenant une couche barrière en un alliage de tantale et oxyde de tantale tel que décrit précédemment permet de réaliser un contact redresseur. Cela permet d’obtenir une réduction considérable des courants de fuite du transistor T1 dans le temps. Un contact électronique redresseur est conçu pour permettre la circulation du courant électrique dans un seul sens partant de la grille G1 vers la couche supérieure C1 , en bloquant la circulation du courant dans le sens opposé. Par conséquent, un contact électronique redresseur offre une résistance élevée dans le sens inverse de la circulation du courant, et une résistance faible dans le sens direct. [0053] The structure of the gate G1 comprising a barrier layer made of a tantalum alloy and tantalum oxide as described above makes it possible to produce a rectifier contact. This makes it possible to obtain a considerable reduction in the leakage currents of the transistor T1 over time. A rectifier electronic contact is designed to allow the flow of electric current in a single direction from the gate G1 to the upper layer C1, by blocking the flow of current in the opposite direction. Consequently, a rectifier electronic contact offers a high resistance in the reverse direction of the flow of current, and a low resistance in the forward direction.

[0054] De plus, le tantale et l’oxyde de tantale sont des matériaux réfractaires qui peuvent résister à des températures élevées (généralement supérieures à 1000°C) sans se déformer, fondre ou se dégrader. Ainsi, la couche barrière CB permet d’offrir à la grille G1 une robustesse thermique élevée, et ainsi protéger le corps du transistor T1 . [0055] La figure 2a représente une vue en coupe d’un transistor T1 ayant une grille G1 selon un deuxième mode de réalisation de l’invention. La figure 2b représente une vue en coupe agrandie de la grille G1 selon le deuxième mode de réalisation de l’invention. [0054] In addition, tantalum and tantalum oxide are refractory materials that can withstand high temperatures (generally above 1000°C) without deforming, melting or degrading. Thus, the barrier layer CB makes it possible to provide the gate G1 with high thermal robustness, and thus protect the body of the transistor T1. [0055] Figure 2a shows a sectional view of a transistor T1 having a gate G1 according to a second embodiment of the invention. Figure 2b shows an enlarged sectional view of the gate G1 according to the second embodiment of the invention.

[0056] Les caractéristiques et les avantages techniques décrits pour le premier mode de réalisation restent valables pour le deuxième mode de réalisation. Le deuxième mode de réalisation de l’invention diffère du premier mode de réalisation par la forme de la grille G1. La grille G1 comprend une structure de contact électrique SC constituée d’un pilier PG et une couche supérieure de contact CH. La couche supérieure de contact CH se repose le pilier PG. Le pilier PG présente une première largeur L1 selon une direction parallèle X orthogonale à la direction de l’empilement Z. La couche supérieure de contact CH présente une seconde largeur L2 selon une direction parallèle X orthogonale à la direction de l’empilement Z. La seconde largeur L2 de couche supérieure de contact CH est supérieure à la première largeur L1 du pilier PG. La réduction de la première largeur L1 permet de réduire la capacité parasite de la grille G1 et l’augmentation de la fréquence de fonctionnement maximale du transistor T1. L’élargissement de la seconde largeur L2 permet de réduire la résistance de la grille G1 . [0056] The technical features and advantages described for the first embodiment remain valid for the second embodiment. The second embodiment of the invention differs from the first embodiment by the shape of the gate G1. The gate G1 comprises an electrical contact structure SC consisting of a pillar PG and an upper contact layer CH. The upper contact layer CH rests on the pillar PG. The pillar PG has a first width L1 in a parallel direction X orthogonal to the direction of the stack Z. The upper contact layer CH has a second width L2 in a parallel direction X orthogonal to the direction of the stack Z. The second width L2 of the upper contact layer CH is greater than the first width L1 of the pillar PG. Reducing the first width L1 makes it possible to reduce the parasitic capacitance of the gate G1 and increasing the maximum operating frequency of the transistor T1. Widening the second width L2 makes it possible to reduce the resistance of the gate G1.

[0057] L’épaisseur e1 du pilier PG est comprise entre 20nm et 500nm. Une épaisseur e1 inférieure à 20nm peut engendrer une augmentation des capacités parasites de la grille G1. Une épaisseur e1 supérieure à 500nm peut fragiliser mécaniquement la grille G1 . [0057] The thickness e1 of the PG pillar is between 20nm and 500nm. A thickness e1 less than 20nm can cause an increase in the parasitic capacitances of the gate G1. A thickness e1 greater than 500nm can mechanically weaken the gate G1.

[0058] L’empilement formé par la couche barrière CB et la couche intermédiaire Cl est disposé entre d’une part le pilier PG de la structure de contact électrique SC et d’autre part la couche supérieure C1 . Avantageusement, la couche barrière CB est déposée sur les parois externes du pilier PG, avec un contact direct ou indirect à travers la couche intermédiaire Cl. Avantageusement, la couche barrière CB est déposée, en outre, sur la paroi externe inférieure de la couche supérieure de contact CH, avec un contact direct ou indirect à travers la couche intermédiaire Cl. [0058] The stack formed by the barrier layer CB and the intermediate layer C1 is arranged between, on the one hand, the pillar PG of the electrical contact structure SC and, on the other hand, the upper layer C1. Advantageously, the barrier layer CB is deposited on the external walls of the pillar PG, with direct or indirect contact through the intermediate layer C1. Advantageously, the barrier layer CB is further deposited on the lower external wall of the upper contact layer CH, with direct or indirect contact through the intermediate layer C1.

[0059] Avantageusement, la seconde largeur L2 est supérieure ou égale à six fois la première largeur L1. Cela permet d’optimiser la résistance de la grille G1 et la réduction des capacités parasites d’un côté, et la robustesse mécanique de la structure de la grille G1 d’un autre côté. [0059] Advantageously, the second width L2 is greater than or equal to six times the first width L1. This makes it possible to optimize the resistance of the grid G1 and the reduction of parasitic capacitances on the one hand, and the mechanical robustness of the G1 grid structure on the other hand.

[0060] La figure 3 représente une vue en coupe d’un transistor T1 ayant une grille G1 selon un troisième mode de réalisation de l’invention. Les caractéristiques et les avantages techniques décrits pour le premier et le deuxième mode de réalisation restent valables pour le troisième mode de réalisation. Le troisième mode de réalisation de l’invention diffère du deuxième mode de réalisation par une variation progressive de la largeur de la structure de contact électrique SC de manière à obtenir une structure de type « tulipe ». La structure de contact électrique SC s’élargit progressivement en s’éloignant de la structure de base B1 . Cela permet de diminuer la résistance de la grille G1 tout en réduisant la capacité parasite de la grille G1 . Une augmentation progressive de la largeur de la structure de contact électrique SC permet d’obtenir une grille plus robuste mécaniquement sans dégrader les performances électriques du transistor T1. La couche barrière CB est déposée sur les parois externes de la structure de contact électrique SC, avec un contact direct ou indirect à travers la couche intermédiaire Cl de manière à confiner le premier matériau électriquement conducteur. [0060] Figure 3 shows a cross-sectional view of a transistor T1 having a gate G1 according to a third embodiment of the invention. The technical characteristics and advantages described for the first and second embodiments remain valid for the third embodiment. The third embodiment of the invention differs from the second embodiment by a progressive variation in the width of the electrical contact structure SC so as to obtain a “tulip” type structure. The electrical contact structure SC gradually widens as it moves away from the base structure B1. This makes it possible to reduce the resistance of the gate G1 while reducing the parasitic capacitance of the gate G1. A progressive increase in the width of the electrical contact structure SC makes it possible to obtain a mechanically more robust gate without degrading the electrical performance of the transistor T1. The barrier layer CB is deposited on the external walls of the electrical contact structure SC, with direct or indirect contact through the intermediate layer Cl so as to confine the first electrically conductive material.

[0061] La figure 4 représente une vue en coupe d’un transistor T1 ayant une grille G1 selon un quatrième mode de réalisation de l’invention. Les caractéristiques et les avantages techniques décrits pour le premier et le deuxième mode de réalisation restent valables pour le quatrième mode de réalisation. Il s’agit d’une variante de la forme de la grille G1 sous forme de Gamma. [0061] Figure 4 shows a cross-sectional view of a transistor T1 having a gate G1 according to a fourth embodiment of the invention. The characteristics and technical advantages described for the first and second embodiments remain valid for the fourth embodiment. This is a variant of the shape of the gate G1 in the form of Gamma.

[0062] Selon un aspect particulier de l’invention, le transistor T1 comprend une couche d’encapsulation en diamant ou en nitrure de bore qui encapsule au moins la grille G1. Cette variante est compatible avec tous les modes de réalisation préalablement décrits. Le dépôt d’une couche en diamant ou en nitrure de bore nécessite l’application d’une forte contrainte thermique sur le transistor T1. La structure de la grille G1 selon l’invention permet de réaliser cette étape de dépôt de couche d’encapsulation en diamant ou en nitrure de bore sans dégradation de la robustesse du transistor par diffusion grâce à la couche barrière en alliage de tantale et oxyde de tantale. [0063] La figure 5 illustre un organigramme du procédé P1 de fabrication de la grille G1 selon l’un quelconque des modes de réalisation de l’invention. Les figures 6a à 6g illustrent les étapes du procédé P1 selon l’invention. [0062] According to a particular aspect of the invention, the transistor T1 comprises a diamond or boron nitride encapsulation layer which encapsulates at least the gate G1. This variant is compatible with all the embodiments previously described. The deposition of a diamond or boron nitride layer requires the application of a high thermal stress on the transistor T1. The structure of the gate G1 according to the invention makes it possible to carry out this step of deposition of a diamond or boron nitride encapsulation layer without degradation of the robustness of the transistor by diffusion thanks to the barrier layer made of tantalum alloy and tantalum oxide. [0063] Figure 5 illustrates a flowchart of the method P1 for manufacturing the grid G1 according to any one of the embodiments of the invention. Figures 6a to 6g illustrate the steps of the method P1 according to the invention.

[0064] La première étape i) consiste à fournir un empilement de couches formant une structure de base B1 comprenant la couche supérieure C1 en un premier matériau semi-conducteur. La structure de base B1 est réalisée sur un substrat SUB. La structure de base B1 est destinée à former le corps du transistor T1 en cours de fabrication. La figure 6a illustre à titre d’exemple non limitatif et sans perte de généralité la structure de base B1 décrite précédemment pour la réalisation d’un transistor à haute vitesse d’électron HEMT. La première étape i) est réalisable par la croissance de couches minces par épitaxie. [0064] The first step i) consists in providing a stack of layers forming a base structure B1 comprising the upper layer C1 in a first semiconductor material. The base structure B1 is produced on a substrate SUB. The base structure B1 is intended to form the body of the transistor T1 during manufacture. FIG. 6a illustrates by way of non-limiting example and without loss of generality the base structure B1 described above for the production of a high electron speed transistor HEMT. The first step i) can be carried out by the growth of thin layers by epitaxy.

[0065] La deuxième étape ii) consiste à déposer une résine électro-sensible RES sur toute la surface supérieure de la structure de base B1 et à fabriquer un motif 11 correspondant à une forme prédéterminée de la grille G1 dans ladite résine. À titre d’exemple d’illustration non limitatif, la fabrication du motif 11 est réalisée par lithographie à faisceau d’électrons : La résine RES est exposée à un faisceau d’électrons. Le faisceau définit le motif 11 selon une programmation prédéterminée. Dans l’exemple illustré sur la figure 6b, le motif 11 correspond à un volume vide fabriqué dans une portion de la résine. Les parties de la résine RES exposées au faisceau d’électrons sont fragilisées et ensuite retirées par un solvant adapté. La résine RES doit avoir une composition chimique comprenant des fonctions oxygène libres. À titre d’exemple, la résine RES est en Poly-méthyl-méthacrylate (P MM A). Le procédé P1 est illustré avec une forme de grille G1 selon le deuxième mode de réalisation à titre indicatif et non limitatif. Le procédé P1 est compatible avec les autres modes de réalisation de la grille G1 selon l’invention en adaptant la forme du motif 11 . [0065] The second step ii) consists in depositing an electro-sensitive resin RES on the entire upper surface of the base structure B1 and in manufacturing a pattern 11 corresponding to a predetermined shape of the grid G1 in said resin. As a non-limiting illustrative example, the manufacturing of the pattern 11 is carried out by electron beam lithography: The resin RES is exposed to an electron beam. The beam defines the pattern 11 according to a predetermined program. In the example illustrated in FIG. 6b, the pattern 11 corresponds to an empty volume manufactured in a portion of the resin. The parts of the resin RES exposed to the electron beam are weakened and then removed by a suitable solvent. The resin RES must have a chemical composition comprising free oxygen functions. As an example, the resin RES is made of Poly-methyl-methacrylate (P MM A). The method P1 is illustrated with a grid shape G1 according to the second embodiment for information purposes and without limitation. The method P1 is compatible with the other embodiments of the grid G1 according to the invention by adapting the shape of the pattern 11.

[0066] La troisième étape iii) consiste à déposer une couche barrière CB réalisée en un alliage de tantale et d’oxyde de tantale sur les parois internes dudit motif 11 comme illustré sur la figure 6c. Le dépôt peut être réalisé par évaporation ou par pulvérisation. La figure 7 illustre la réalisation de cette étape dans un équipement de dépôt par évaporation à titre d’exemple. En effet, l’échantillon est chargé dans l’enceinte E0 (appelée aussi bâti ou chambre) d’un équipement de dépôt. L’enceinte E0 comprend une source de tantale SoM1 chauffée à une température To supérieure à 1900°C. La pression Po dans l’enceinte est inférieure à 5.10’5 Pa. La source de tantale SoM1 est bombardée par un faisceau d’électrons, ce qui provoque l’arrachement d’atomes de tantale de la source de tantale SoM1 et leur déplacement vers la surface supérieure de l’échantillon (cible formée par la structure de base B1 sur laquelle le motif 11 a été fabriqué). La source de tantale SoM1 placée à une distance de séparation d1 par rapport la structure de base B1 choisie de manière à obtenir une réaction d’oxydation entre les atomes de tantale déposés et les atomes oxygène libres fournis par la résine RES. À titre d’exemple non limitatif, la distance de séparation d1 est comprise entre 30 cm et 70 cm et préférentiellement entre 45 cm et 55 cm. L’intensité des réactions d’oxydation diminue progressivement avec la croissance de la couche déposée. On obtient ainsi, la couche barrière CB réalisée en un alliage de tantale et d’oxyde de tantale avec un gradient de concentration en oxyde de tantale décroissant avec l’augmentation de l’épaisseur de la couche barrière CB, et inversement un gradient de concentration en tantale croissant avec l’augmentation de l’épaisseur de la couche barrière CB. La couche barrière CB est déposée sur des parois internes du motif 11 formé par la résine RES et sur la surface supérieure apparente de la couche supérieure C1 de la structure de base B1. [0066] The third step iii) consists in depositing a barrier layer CB made of an alloy of tantalum and tantalum oxide on the internal walls of said pattern 11 as illustrated in FIG. 6c. The deposition can be carried out by evaporation or by sputtering. FIG. 7 illustrates the performance of this step in an evaporation deposition equipment as an example. Indeed, the sample is loaded into the enclosure E0 (also called a frame or chamber) of a deposition equipment. The enclosure E0 comprises a tantalum source SoM1 heated to a temperature T o higher than at 1900°C. The pressure P o in the enclosure is less than 5.10' 5 Pa. The tantalum source SoM1 is bombarded by an electron beam, which causes tantalum atoms to be torn off from the tantalum source SoM1 and to move them towards the upper surface of the sample (target formed by the base structure B1 on which the pattern 11 was fabricated). The tantalum source SoM1 is placed at a separation distance d1 from the base structure B1 chosen so as to obtain an oxidation reaction between the deposited tantalum atoms and the free oxygen atoms provided by the resin RES. As a non-limiting example, the separation distance d1 is between 30 cm and 70 cm and preferably between 45 cm and 55 cm. The intensity of the oxidation reactions gradually decreases with the growth of the deposited layer. We thus obtain the barrier layer CB made of an alloy of tantalum and tantalum oxide with a concentration gradient of tantalum oxide decreasing with the increase in the thickness of the barrier layer CB, and conversely a concentration gradient of tantalum increasing with the increase in the thickness of the barrier layer CB. The barrier layer CB is deposited on internal walls of the pattern 11 formed by the resin RES and on the visible upper surface of the upper layer C1 of the base structure B1.

[0067] 0ptionnellement, l’étape suivante iiï) consiste à déposer une couche intermédiaire Cl sur la couche barrière CB déposée préalablement à l’intérieur du motif 11 comme illustré sur la figure 6d. La couche intermédiaire Cl est réalisée à partir d’une source d’un platinoïde ou de nickel ou de molybdène dans le même équipement de dépôt sans décharger l’échantillon de l’enceinte E0 et en gardant la même pression Po. On parle dans ce cas d’un dépôt « in-situ » car il ne nécessite pas la décharge de la structure de base B1 du bâti. Cela permet de réduire le nombre d’étapes du procédé de fabrication de la grille G1 par rapport à un procédé de fabrication selon l’état de l’art. [0067] Optionally, the next step ii) consists in depositing an intermediate layer C1 on the barrier layer CB previously deposited inside the pattern 11 as illustrated in FIG. 6d. The intermediate layer C1 is produced from a source of a platinoid or nickel or molybdenum in the same deposition equipment without unloading the sample from the enclosure E0 and while maintaining the same pressure P o . In this case, we speak of an “in-situ” deposition because it does not require the unloading of the base structure B1 of the frame. This makes it possible to reduce the number of steps in the manufacturing process for the grid G1 compared with a manufacturing process according to the state of the art.

[0068] L’étape iv) consiste à déposer une couche en un premier matériau électriquement conducteur pour remplir le motif 11 afin d’obtenir une structure de contact SC comme illustré sur la figure 6e. Le dépôt est réalisé dans l’enceinte E0 du même équipement de dépôt sans décharger la structure de base B1 et en gardant la même pression Po. On parle dans ce cas d’un dépôt « in-situ » car il ne nécessite pas la décharge de la structure de base B1 du bâti. Le dépôt est réalisé à partir d’une source de métal en or par exemple bombardée par un faisceau d’électrons. [0068] Step iv) consists in depositing a layer of a first electrically conductive material to fill the pattern 11 in order to obtain a contact structure SC as illustrated in FIG. 6e. The deposition is carried out in the enclosure E0 of the same deposition equipment without discharging the base structure B1 and while maintaining the same pressure P o . In this case, we speak of an “in-situ” deposition because it does not require not the discharge of the basic structure B1 of the frame. The deposit is made from a source of gold metal for example bombarded by an electron beam.

[0069] L’étape v) consiste à détruire la structure de résine RES restante pour garder uniquement la grille G1 à partir du motif 11. La destruction de la résine RES est réalisable par voie chimique par des solvants spécifiques. [0069] Step v) consists of destroying the remaining RES resin structure to keep only the grid G1 from the pattern 11. The destruction of the RES resin can be carried out chemically using specific solvents.

[0070] 0ptionnellement, le procédé P1 comprend en outre une étape vi) de recuit thermique du transistor T1 à une température comprise entre 400°C et 600°C pendant une durée comprise entre 1 et 2 minutes dans une atmosphère d’azote ou sous vide. L’étape de recuit permet d’obtenir une forte réduction de la densité de courant de fuite à des valeurs inférieures à 200nA/mm. Cette réduction des courants de fuite s’accompagne également d’une augmentation de la densité de courant de sortie, passant par exemple de 0,77 A/mm (avant recuit) à 1 ,4 A/mm (après recuit). La structure de la grille G1 selon l’invention permet de réaliser cette étape de recuit thermique sans dégradation de la robustesse du transistor par diffusion grâce à la couche barrière en alliage de tantale et oxyde de tantale. [0070] Optionally, the method P1 further comprises a step vi) of thermal annealing of the transistor T1 at a temperature between 400°C and 600°C for a duration of between 1 and 2 minutes in a nitrogen atmosphere or under vacuum. The annealing step makes it possible to obtain a significant reduction in the leakage current density to values below 200 nA/mm. This reduction in leakage currents is also accompanied by an increase in the output current density, for example from 0.77 A/mm (before annealing) to 1.4 A/mm (after annealing). The structure of the gate G1 according to the invention makes it possible to carry out this thermal annealing step without degrading the robustness of the transistor by diffusion thanks to the barrier layer made of tantalum alloy and tantalum oxide.

[0071] Optionnellement, le procédé P1 comprend en outre une étape vii) de dépôt d’une couche d’encapsulation en diamant ou en nitrure de bore par la technique de dépôt chimique en phase vapeur (CVD acronyme de l’expression anglaise Chemical Vapor Deposition) à une température supérieure à 600°C comme illustré sur la figure 6g. La structure de la grille G1 selon l’invention permet de réaliser cette étape de dépôt de couche d’encapsulation sans dégradation de la robustesse du transistor par diffusion grâce à la couche barrière en alliage de tantale et oxyde de tantale. De plus, la couche barrière CB confère à la grille G1 une excellente tenue en température, empêchant cette dernière de se déformer sous l’effet de la chaleur. [0071] Optionally, the method P1 further comprises a step vii) of depositing a diamond or boron nitride encapsulation layer by the chemical vapor deposition technique (CVD) at a temperature above 600°C as illustrated in FIG. 6g. The structure of the gate G1 according to the invention makes it possible to carry out this encapsulation layer deposition step without degrading the robustness of the transistor by diffusion thanks to the barrier layer made of tantalum alloy and tantalum oxide. In addition, the barrier layer CB gives the gate G1 excellent temperature resistance, preventing the latter from deforming under the effect of heat.

Claims

REVENDICATIONS 1. Transistor à effet de champ (T1 ) comprenant un drain (D1 ), une source (S1) et une grille (G1 ) disposés sur une couche supérieure (C1) en un premier matériau semi- conducteur d’un empilement de couches disposé sur un substrat (SUB) et formant une structure de base (B1 ) ; la grille (G1 ) comprenant : 1. Field effect transistor (T1) comprising a drain (D1), a source (S1) and a gate (G1) arranged on an upper layer (C1) made of a first semiconductor material of a stack of layers arranged on a substrate (SUB) and forming a base structure (B1); the gate (G1) comprising: - une structure de contact (SC) électrique réalisée en un premier matériau électriquement conducteur ; - an electrical contact structure (SC) made of a first electrically conductive material; - une couche barrière (CB) réalisée en un alliage de tantale et d’oxyde de tantale ; la couche barrière (CB) séparant ladite couche supérieure (C1 ) de la structure de contact pour bloquer la diffusion du premier matériau électriquement conducteur dans la structure de base (B1 ) ; la couche barrière (CB) présentant un gradient de concentration en oxyde de tantale, l’oxyde de tantale étant majoritaire par rapport au tantale dans une première partie (P1) de la couche barrière (CB) située à une première interface entre la couche barrière (CB) et la couche supérieure (C1 ). - a barrier layer (CB) made of an alloy of tantalum and tantalum oxide; the barrier layer (CB) separating said upper layer (C1) from the contact structure to block the diffusion of the first electrically conductive material into the base structure (B1); the barrier layer (CB) having a tantalum oxide concentration gradient, the tantalum oxide being in the majority compared to the tantalum in a first part (P1) of the barrier layer (CB) located at a first interface between the barrier layer (CB) and the upper layer (C1). 2. Transistor à effet de champ (T1 ) selon la revendication 1 dans lequel la couche barrière (CB) comprend une seconde partie (P2) constituée de tantale située à une seconde interface opposée à la première interface. 2. Field effect transistor (T1) according to claim 1 in which the barrier layer (CB) comprises a second part (P2) made of tantalum located at a second interface opposite the first interface. 3. Transistor à effet de champ (T1 ) selon l’une quelconque des revendications 1 ou 2 dans lequel le premier matériau électriquement conducteur est l’or ou l’aluminium ou le cuivre. 3. Field effect transistor (T1) according to any one of claims 1 or 2 in which the first electrically conductive material is gold or aluminum or copper. 4. Transistor à effet de champ (T1 ) selon l’une quelconque des revendications 1 à 3 dans lequel la grille (G1 ) comprend en outre une couche intermédiaire (Cl) confinée entre la structure de contact (SC) et la couche barrière (CB) ; ladite couche intermédiaire (Cl) étant réalisée en un platinoïde ou en nickel ou en molybdène. 4. Field effect transistor (T1) according to any one of claims 1 to 3, in which the gate (G1) further comprises an intermediate layer (Cl) confined between the contact structure (SC) and the barrier layer (CB); said intermediate layer (Cl) being made of a platinoid or of nickel or of molybdenum. 5. Transistor à effet de champ (T 1 ) selon l’une quelconque des revendications 1 à 4 dans lequel le premier matériau semi-conducteur présente un travail de sortie inférieur à celui du tantale pour réaliser un contact redresseur. 5. Field effect transistor (T 1 ) according to any one of claims 1 to 4 in which the first semiconductor material has an output work lower than that of tantalum to produce a rectifier contact. 6. Transistor à effet de champ (T1 ) selon l’une quelconque des revendications 1 à 5 dans lequel la couche barrière (CB) présente une épaisseur comprise entre 5nm et 30nm. 6. Field effect transistor (T1) according to any one of claims 1 to 5 in which the barrier layer (CB) has a thickness of between 5nm and 30nm. 7. Transistor à effet de champ (T1 ) selon l’une quelconque des revendications 1 à 6 dans lequel la première partie (P1) de la couche barrière (CB) présente une épaisseur comprise entre 5nm et 10nm. 7. Field effect transistor (T1) according to any one of claims 1 to 6 in which the first part (P1) of the barrier layer (CB) has a thickness of between 5nm and 10nm. 8. Transistor à effet de champ (T1 ) selon l’une quelconque des revendications 1 à 7 comprenant en outre une couche d’encapsulation (CE) en diamant ou en nitrure de bore ; la grille (G1 ) étant couverte par ladite couche d’encapsulation (CE). 8. Field effect transistor (T1) according to any one of claims 1 to 7 further comprising an encapsulation layer (CE) made of diamond or boron nitride; the gate (G1) being covered by said encapsulation layer (CE). 9. Transistor à effet de champ (T1 ) selon l’une quelconque des revendications 1 à 8 dans lequel la structure de contact (SC) comprend un pilier (PG) et une couche supérieure de contact (CH) reposant sur ledit pilier et ayant une largeur (L2) supérieure à celle du pilier (L1 ). 9. Field effect transistor (T1) according to any one of claims 1 to 8 in which the contact structure (SC) comprises a pillar (PG) and an upper contact layer (CH) resting on said pillar and having a width (L2) greater than that of the pillar (L1). 10. Procédé (P1 ) de fabrication d’une grille (G1 ) d’un transistor à effet de champ (T1 ) comprenant les étapes suivantes: i) fournir un empilement de couches formant une structure de base (B1 ) comprenant une couche supérieure (C1 ) en un premier matériau semi- conducteur ; ii) déposer une résine avec une composition chimique comprenant des fonctions oxygène libres sur la couche supérieure (C1 ) et fabriquer un motif (11 ) correspondant à une forme prédéterminée de la grille (G1 ) dans la résine par lithographie; iii) déposer une couche barrière (CB) réalisée en un alliage de tantale et d’oxyde de tantale sur les parois internes dudit motif (11 ) dans l’enceinte d’un équipement de dépôt ayant une température supérieure à 1900°C; le dépôt étant réalisé à partir d’une source de tantale placée à une distance de séparation (d1 ) de la structure de base (B1 ) choisie de manière à obtenir une couche barrière (CB) présentant un gradient de concentration en oxyde de tantale ; iv) déposer une couche en un premier matériau électriquement conducteur pour remplir le motif (11 ) afin d’obtenir une structure de contact (SC) ; le dépôt étant réalisé dans l’enceinte dudit équipement de dépôt sans décharger la structure de base (B1 ) ; le dépôt étant réalisé à partir d’une source du premier matériau électriquement conducteur ; v) détruire la résine (RES). 10. Method (P1) for manufacturing a gate (G1) of a field effect transistor (T1) comprising the following steps: i) providing a stack of layers forming a base structure (B1) comprising an upper layer (C1) made of a first semiconductor material; ii) depositing a resin with a chemical composition comprising free oxygen functions on the upper layer (C1) and manufacturing a pattern (11) corresponding to a predetermined shape of the gate (G1) in the resin by lithography; iii) depositing a barrier layer (CB) made of an alloy of tantalum and tantalum oxide on the internal walls of said pattern (11) in the enclosure of deposition equipment having a temperature greater than 1900°C; the deposition being carried out from a tantalum source placed at a separation distance (d1) from the base structure (B1) chosen so as to obtain a barrier layer (CB) having a tantalum oxide concentration gradient; iv) depositing a layer of a first electrically conductive material to fill the pattern (11) in order to obtain a contact structure (SC); the deposition being carried out in the enclosure of said deposition equipment without discharging the base structure (B1); the deposition being carried out from a source of the first electrically conductive material; v) destroying the resin (RES).
PCT/EP2024/067497 2023-06-22 2024-06-21 Tantalum-oxide-based transistor gate WO2024261277A1 (en)

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US9780181B1 (en) * 2016-12-07 2017-10-03 Mitsubishi Electric Research Laboratories, Inc. Semiconductor device with multi-function P-type diamond gate

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US20060197107A1 (en) * 2005-03-03 2006-09-07 Fujitsu Limited Semiconductor device and production method thereof
US7411226B2 (en) 2005-04-27 2008-08-12 Northrop Grumman Corporation High electron mobility transistor (HEMT) structure with refractory gate metal
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