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WO2024250591A1 - 封装结构及其形成方法 - Google Patents

封装结构及其形成方法 Download PDF

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Publication number
WO2024250591A1
WO2024250591A1 PCT/CN2023/134258 CN2023134258W WO2024250591A1 WO 2024250591 A1 WO2024250591 A1 WO 2024250591A1 CN 2023134258 W CN2023134258 W CN 2023134258W WO 2024250591 A1 WO2024250591 A1 WO 2024250591A1
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WO
WIPO (PCT)
Prior art keywords
conductive pad
substrate
redistribution layer
electrically connected
conductive
Prior art date
Application number
PCT/CN2023/134258
Other languages
English (en)
French (fr)
Inventor
陈海杰
谢皆雷
吴靖宇
Original Assignee
江阴长电先进封装有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江阴长电先进封装有限公司 filed Critical 江阴长电先进封装有限公司
Publication of WO2024250591A1 publication Critical patent/WO2024250591A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements

Definitions

  • the present invention relates to the field of packaging, and in particular to a packaging structure and a forming method thereof.
  • Chiplet technology refers to pre-manufactured, functional, and combinable chips (Die).
  • SiP System-in-Package
  • SiP is used to package chips with different functions and different process nodes together through effective inter-chip interconnection and packaging architecture to form a system chip.
  • adapter board connection is one of the effective ways to achieve electrical interconnection between chips and between chips and substrates.
  • the existing adapter board does not integrate passive devices (such as capacitors), and passive devices need to be connected to the adapter board through additional surface mounting (Surface Mounted Technology, SMT) and other processes, which does not match the flip-chip process between chips and between chips and substrates.
  • SMT Surface Mounted Technology
  • the size of passive devices is large, resulting in a waste of adapter board area, which is not conducive to the miniaturization of the packaging structure.
  • the technical problem to be solved by the present invention is to provide a packaging structure and a method for forming the same, which can improve the compatibility of the packaging process and facilitate the miniaturization of the packaging structure.
  • the present invention provides a method for forming a packaging structure, comprising: providing a transfer substrate, the transfer substrate comprising a first conductive pad, and the first conductive pad is exposed on a first surface of the transfer substrate; providing a device substrate, the device substrate comprising a passive device layer and a first redistribution layer covering the passive device layer, the passive device layer comprising a passive device, the first redistribution layer comprising a second conductive pad, the second conductive pad is electrically connected to the passive device, and the second conductive pad is exposed on a first surface of the first redistribution layer; using the first surface of the transfer substrate and the first surface of the first redistribution layer as bonding surfaces, and using a hybrid bonding process to bond the transfer substrate to the device substrate, wherein the first conductive pad is electrically connected to the second conductive pad; removing a portion of the device substrate from a surface of the device substrate facing away from the transfer substrate to form a groove, the groove exposing the transfer substrate or the
  • the transfer substrate also includes a fourth conductive pad, and the fourth conductive pad is exposed to the first surface of the transfer substrate;
  • the device substrate also includes a first conductive column, the first conductive column is arranged in the device substrate and one surface of which is exposed to the first surface of the first redistribution layer; in the step of bonding the transfer substrate to the device substrate using a hybrid bonding process, the fourth conductive pad is electrically connected to the first conductive column.
  • the method further includes: plastic packaging to form a plastic packaging body, wherein the plastic packaging body fills the groove, and the third conductive pad is exposed to the plastic packaging body.
  • the step of molding to form a molding body includes: filling the molding compound, wherein the molding compound fills the groove and also covers the surface of the device substrate facing away from the transfer substrate; thinning the molding compound to remove the molding compound on the surface of the device substrate facing away from the transfer substrate and expose the third conductive pad, and the remaining molding compound serves as the molding body.
  • the step further includes: thinning the device substrate from a surface of the device substrate facing away from the transfer substrate to expose the surface of the first conductive pillar.
  • the step further includes: planarizing the surface of the device substrate away from the transfer substrate, the surface of the plastic package and the surface of the silicon bridge.
  • the step further includes: forming a second redistribution layer, the second redistribution layer covers the surface of the device substrate facing away from the adapter substrate and the surface of the silicon bridge, the second redistribution layer includes a fifth conductive pad, the fifth conductive pad is electrically connected to the third conductive pad, and the fifth conductive pad is exposed to the surface of the second redistribution layer; in the step of mounting a functional chip on the side of the device substrate facing away from the adapter substrate, the functional chip is electrically connected to the fifth conductive pad.
  • the second redistribution layer also includes a seventh conductive pad, which is electrically connected to the first conductive column and exposed to the surface of the second redistribution layer; in the step of mounting a functional chip on the side of the device substrate facing away from the transfer substrate, the functional chip is also electrically connected to the seventh conductive pad.
  • the embodiment of the present invention further provides a packaging structure, comprising: a transfer substrate, comprising a first conductive pad; a device substrate, comprising a passive device layer and a first redistribution layer covering the passive device layer, wherein the passive device layer comprises passive devices, and the first redistribution layer is bonded to the transfer substrate, wherein the first redistribution layer comprises a second conductive pad, One end of the second conductive pad is electrically connected to the passive device, and the other end is electrically connected to the first conductive pad, the device substrate has a groove, the groove exposes the transfer substrate or the first redistribution layer; a silicon bridge is arranged in the groove, and the silicon bridge includes a third conductive pad; a functional chip is arranged on a side of the device substrate away from the transfer substrate, and the functional chip is electrically connected to the third conductive pad.
  • the transfer substrate further includes a fourth conductive pad
  • the device substrate further includes a first conductive column
  • the first conductive column penetrates the device substrate
  • the fourth conductive pad is electrically connected to the first conductive column
  • it also includes a second redistribution layer, which covers the surface of the device substrate facing away from the adapter substrate and the surface of the silicon bridge.
  • the functional chip is arranged on the second redistribution layer.
  • the second redistribution layer includes a fifth conductive pad, one end of the fifth conductive pad is electrically connected to the third conductive pad, and the other end is electrically connected to the functional chip.
  • the second redistribution layer further includes a seventh conductive pad, one end of the seventh conductive pad is electrically connected to the first conductive column, and the other end of the seventh conductive pad is electrically connected to the functional chip.
  • a plastic packaging body is further included, and the plastic packaging body fills the groove.
  • the passive devices are directly integrated inside the adapter substrate by using the wafer-level packaging process before the functional chip is set, and the silicon bridge is formed after the passive devices are integrated, and then the adapter board composed of the adapter substrate and the silicon bridge is formed, and then the functional chip is electrically connected to the adapter board to form the packaging structure.
  • the formation method of the present invention does not need to use an additional surface mounting process to connect the passive device to the adapter board, which greatly improves the compatibility of the process; and this formation method greatly saves the area of the adapter substrate, which is conducive to the miniaturization of the packaging structure; the functional chip and the passive device are arranged on the same side of the adapter substrate, so that the distance between the passive device and the functional chip is relatively close, which improves the performance of the packaging structure.
  • the parameters of the passive device (such as the capacitance value) can be adjusted during the manufacturing process of the passive device in the device substrate to achieve accurate matching between the passive device and the functional chip.
  • FIG1 is a schematic diagram of steps of a method for forming a packaging structure provided by an embodiment of the present invention.
  • FIGS. 2A to 2J are schematic diagrams of structures formed by main steps of a forming method provided in one embodiment of the present invention.
  • FIG1 is a schematic diagram of the steps of a method for forming a packaging structure provided by an embodiment of the present invention.
  • the forming method comprises: step S10, providing a transfer substrate, wherein the transfer substrate comprises a first conductive pad, and the first conductive pad is exposed on a first surface of the transfer substrate; step S11, providing a device substrate, wherein the device substrate comprises a passive device layer and a first redistribution layer covering the passive device layer, wherein the passive device layer comprises a passive device, and the first redistribution layer comprises a second conductive pad, wherein the second conductive pad is electrically connected to the passive device, and the second conductive pad is exposed on a first surface of the first redistribution layer; step S12, providing a device substrate, wherein the device substrate comprises a passive device layer and a first redistribution layer covering the passive device layer, wherein the passive device layer comprises a passive device, and the first redistribution layer comprises a second conductive pad, wherein the second conductive pad, where
  • step S13 removing a portion of the device substrate from the surface of the device substrate facing away from the transfer substrate to form a groove, wherein the groove exposes the transfer substrate or the first redistribution layer, and the area of the passive device layer having the passive device is retained; step S14, forming a silicon bridge in the groove, wherein the silicon bridge includes a third conductive pad; step S15, mounting a functional chip on the side of the device substrate facing away from the transfer substrate, wherein the functional chip is electrically connected to the third conductive pad.
  • the passive device before setting the functional chip, the passive device is directly integrated inside the adapter substrate using a wafer-level packaging process, and after integrating the passive device, the silicon bridge is formed, and then an adapter board consisting of the adapter substrate and the silicon bridge is formed, and then the functional chip is electrically connected to the adapter board to form the packaging structure.
  • the formation method of the present invention does not need to use an additional surface mounting process to connect the passive device to the adapter board, which greatly improves the process compatibility; and this formation method greatly saves the area of the adapter substrate, which is conducive to the miniaturization of the packaging structure; the functional chip and the passive device are arranged on the same side of the adapter substrate, so that the distance between the passive device and the functional chip is relatively close, which improves the performance of the packaging structure.
  • the parameters of the passive device (such as the capacitance value) can be adjusted during the manufacturing process of the passive device in the device substrate to achieve accurate matching between the passive device and the functional chip.
  • FIGS. 2A to 2J are schematic diagrams of structures formed by main steps of a forming method provided in one embodiment of the present invention.
  • a transfer substrate 200 is provided.
  • the transfer substrate 200 includes a first conductive pad 201 , and the first conductive pad 201 is exposed on a first surface 200A of the transfer substrate 200 .
  • the transfer substrate 200 further includes a first dielectric layer 202, the first conductive pad 201 is formed in the first dielectric layer 202 and exposed on the top surface of the first dielectric layer 202, and the top surface serves as the first surface 200A of the transfer substrate 200.
  • the first dielectric layer 202 includes but is not limited to an organic dielectric layer.
  • the material of the substrate layer may be an organic resin, which includes but is not limited to epoxy resin (FR4), BT resin (bismaleimide triazine resin), PPE resin (polyphenylene ether resin), and PI resin (polyimide resin).
  • the first conductive pad 201 may be a metal pad.
  • the first conductive pad 201 is a copper pad.
  • the first conductive pad 201 may penetrate the first dielectric layer 202, that is, the upper surface and the lower surface of the first conductive pad 201 are exposed to the top surface and the bottom surface of the first dielectric layer 202, respectively.
  • the transfer substrate 200 further includes a conductive interconnection line and at least one bottom conductive pad.
  • the conductive interconnection line is arranged in the first dielectric layer 202, and the first conductive pad 201 is electrically connected to the conductive interconnection line.
  • the bottom conductive pad is arranged at the bottom of the first dielectric layer 202, and the bottom conductive pad is electrically connected to the conductive interconnection line, that is, the first conductive pad 201 is electrically connected to the bottom conductive pad through the conductive interconnection line.
  • the surface of the bottom conductive pad is exposed to the bottom surface of the first dielectric layer 202, and is used as an external connection area at the bottom of the transfer substrate 200.
  • the transfer substrate 200 further includes a fourth conductive pad 203, and the fourth conductive pad 203 is exposed to the first surface 200A of the transfer substrate 200.
  • the fourth conductive pad 203 is formed in the first dielectric layer 202 and penetrates the first dielectric layer 202, and its upper surface and lower surface are respectively exposed to the top surface and bottom surface of the first dielectric layer 202.
  • the upper surface of the fourth conductive pad 203 is exposed to the top surface of the first dielectric layer 202, and its lower surface can also be electrically connected to the bottom conductive pad through the conductive interconnect line.
  • the present invention provides a method for forming the transfer substrate 200.
  • the method includes: providing a carrier substrate 210; forming a sacrificial layer 211 on the carrier substrate 210; forming a first dielectric layer 202 on the sacrificial layer 211, wherein the first dielectric layer 202 includes a via hole; and filling the via hole with a conductive material to form the first conductive pad 201 and the fourth conductive pad 203.
  • the first conductive pad 201 and the fourth conductive pad 203 are made of the same material structure and are formed in the same step.
  • the formation method further includes the step of flattening the transfer substrate 200. That is, before performing the hybrid bonding process, the first surface 200A of the transfer substrate 200 is flattened to improve the bonding firmness of the package structure formed by subsequent hybrid bonding.
  • the flattening process includes but is not limited to chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the conductive material when forming the transfer substrate 200, the conductive material not only fills the via hole but also covers part of the surface of the first dielectric layer 202. When performing the flattening process, the conductive material on the surface of the first dielectric layer 202 can be removed at the same time.
  • step S11 providing a device substrate 220, the device substrate 220 includes a passive device layer 230 and a first redistribution layer 240 covering the passive device layer 230, the passive device layer 230 includes a passive device 231, the first redistribution layer 240 includes a second conductive pad 241, the second conductive pad 241 is electrically connected to the passive device 231, and the second conductive pad 241 is exposed to the first surface 240A of the first redistribution layer 240.
  • the passive device 231 includes but is not limited to resistors, capacitors, and inductors.
  • the passive device 231 is a capacitor
  • the passive device layer 230 is a capacitor device layer, which can be obtained by preparing a capacitor on a wafer using a semiconductor process.
  • the capacitor includes but is not limited to a deep trench capacitor.
  • the second conductive pad 241 is electrically connected to the passive device 231 and serves as a pin of the passive device 231.
  • the passive device 231 is a capacitor
  • the second conductive pad 241 is electrically connected to the positive electrode or the negative electrode of the capacitor and serves as a pin of the positive electrode or the negative electrode of the capacitor.
  • the first redistribution layer 240 includes a second dielectric layer 242, the second dielectric layer 242 covers the passive device layer 230, and the second conductive pad 241 penetrates the second dielectric layer 242, one surface of the second conductive pad 241 is electrically connected to the passive device 231, and the other surface is exposed to the top surface of the second dielectric layer 242, and the top surface serves as the first surface 240A of the first redistribution layer 240.
  • the second dielectric layer 242 is an organic dielectric layer, and the material of the organic dielectric layer can be an organic resin, and the organic resin includes but is not limited to: epoxy resin (FR4), BT resin (bismaleimide triazine resin), PPE resin (polyphenylene ether resin), PI resin (polyimide resin).
  • the first dielectric layer 202 and the second dielectric layer 242 are made of the same material layer, so in the subsequent bonding process, the first dielectric layer 202 and the second dielectric layer 242 have a higher bonding strength.
  • the first conductive pad 201 and the second conductive pad 241 may both be metal pads, and the materials thereof may be the same or different.
  • the first conductive pad 201 and the second conductive pad 241 are made of the same material and are both copper pads, so that in the subsequent bonding process, the bonding strength of the first conductive pad 201 and the second conductive pad 241 is higher.
  • the second conductive pad 241 penetrates the second dielectric layer 242, while in other embodiments, the second conductive pad 241 is only disposed in a partial area below the top surface of the second dielectric layer 242, and is electrically led out on the bottom surface of the second dielectric layer 242 through a conductive interconnection line disposed in the second dielectric layer 242, that is, the second conductive pad 241 is electrically connected to the passive device 231 through the conductive interconnection line.
  • the parameters of the passive device 231 can be adjusted during the manufacturing process of the passive device 231 in the device substrate 220, for example, by changing the processing technology or adjusting the area of the capacitor matrix to adjust the capacitance.
  • the capacitance value makes the parameters of the passive components approach the calculated values in the simulation design, thereby achieving accurate matching between the passive component 231 and the functional chip 290 to be subsequently arranged.
  • the device substrate 220 further includes a first conductive column 250, which is disposed in the device substrate 220 and has one surface exposed to the first surface 240A of the first redistribution layer 240, and the other surface is not exposed.
  • the first conductive column 250 extends from the second dielectric layer 242 to the device substrate 220 in a direction perpendicular to the second dielectric layer 242, and has one surface exposed to the top surface of the second dielectric layer 242, and the other surface is located in the device substrate 220 and is not exposed.
  • the embodiment of the present disclosure provides a method for forming the device substrate 220.
  • the method includes: providing a wafer, the wafer including a passive device layer 230; forming the first redistribution layer 240 on the surface of the passive device layer 230; forming a first conductive column 250, the first conductive column 250 extending from the first surface 240A of the first redistribution layer 240 to the inside of the passive device layer 230.
  • the method for forming the first conductive column 250 includes but is not limited to through silicon via (TSV) technology.
  • the formation method further includes the step of planarizing the device substrate 220. That is, the first surface 240A of the first redistribution layer 240 is planarized before the hybrid bonding process is performed to improve the bonding firmness of the package structure formed by the subsequent hybrid bonding.
  • the planarization process includes but is not limited to chemical mechanical polishing (CMP).
  • step S12 using the first surface 200A of the transfer substrate 200 and the first surface 240A of the first redistribution layer 240 as bonding surfaces, the transfer substrate 200 is bonded to the device substrate 220 using a hybrid bonding process, wherein the first conductive pad 201 is electrically connected to the second conductive pad 241.
  • the structure formed by the hybrid bonding process has a higher current load capacity and better thermal performance.
  • the top surface of the first dielectric layer 202 is also bonded to the top surface of the second dielectric layer 242.
  • the fourth conductive pad 203 is electrically connected to the first conductive column 250.
  • the hybrid bonding process includes: bonding the first surface 200A of the transfer substrate 200 to the first surface 240A of the first redistribution layer 240, wherein the first dielectric layer 202 is bonded to the second dielectric layer 242; performing annealing treatment, bonding the first conductive pad 201 to the second conductive pad 241 to form a bonding structure.
  • the method before performing the hybrid bonding process, further includes: performing an activation treatment on the first surface 200A of the transfer substrate 200 and/or the first surface 240A of the first redistribution layer 240 to form activation points on the first surface 200A of the transfer substrate 200 and/or the first surface 240A of the first redistribution layer 240, which can improve the hybrid bonding process.
  • the activation treatment includes but is not limited to plasma activation treatment.
  • the first surface 200A of the transfer substrate 200 and/or the first surface 240A of the first redistribution layer 240 are activated to form activation points on the surface of the first dielectric layer 202 and/or the second dielectric layer 242, thereby improving the bonding strength of the first dielectric layer 202 and the second dielectric layer 242.
  • the first surface 200A of the transfer substrate 200 and the first surface 240A of the first redistribution layer 240 are both activated before performing the hybrid bonding process; in another embodiment, one of the first surface 200A of the transfer substrate 200 or the first surface 240A of the first redistribution layer 240 is activated before performing the bonding process.
  • step S13 a portion of the device substrate 220 is removed from the surface of the device substrate 220 away from the transfer substrate 200 to form a groove 260 , wherein the groove 260 exposes the transfer substrate 200 or the first redistribution layer 240 , and the area of the passive device layer 230 having the passive device 231 is retained.
  • the area of the passive device layer 230 where the passive device 231 is arranged is retained, and the area where the passive device 231 is not arranged is removed.
  • the first redistribution layer 240 corresponding to the removed passive device layer 230 is also removed, thereby exposing the transfer substrate 200.
  • the groove 260 uses the device substrate 220 as a side wall and the transfer substrate 200 as a bottom surface. In other embodiments, only part of the passive device layer 230 may be removed, and the first redistribution layer 240 is not removed, or the first redistribution layer 240 is only partially removed.
  • the method of removing part of the passive device layer 230 includes but is not limited to an etching process.
  • the method of removing part of the passive device layer 230 includes: forming a patterned mask layer on the surface of the device substrate 220 away from the transfer substrate 200, the mask layer shielding the area of the passive device layer 230 where the passive device 231 is disposed, and exposing the area of the passive device layer 230 where the passive device 231 is not disposed; using the mask layer as a mask, etching the passive device layer 230 and the first redistribution layer 240 until the transfer substrate 200 is exposed; and removing the mask layer.
  • a silicon bridge (si bridge) 270 is formed in the groove 260, and the silicon bridge 270 includes a third conductive pad 271.
  • the silicon bridge 270 has interconnection lines inside, so that in the packaging structure formed subsequently, the functional chip 290 can realize electrical connection between chips or the chip itself through the third conductive pad 271 and the interconnection structure.
  • the silicon bridge 270 can be attached to the surface of the transfer substrate 200 by a mounting method.
  • the third conductive pad 271 includes but is not limited to a copper pad.
  • the groove 260 can play a role in limiting and aligning, so that there is no need to form an additional groove for mounting the silicon bridge 270 in the transfer substrate 200, and there is no need to perform a precise alignment process, thereby reducing the process difficulty.
  • the body of the silicon bridge 270 is attached to the surface of the transfer substrate 200, and the top surface of the third conductive pad 271 protrudes from the body of the silicon bridge 270 and the surface of the device substrate 220. In other embodiments, the body of the silicon bridge 270 is attached to the surface of the transfer substrate 200, and the top surface of the third conductive pad 271 protrudes from the body of the silicon bridge 270 and is lower than the surface of the device substrate 220, or is flush with the surface of the device substrate 220.
  • plastic encapsulation is performed to form a plastic encapsulation body 272, wherein the plastic encapsulation body 272 fills the groove 260, and the third conductive pad 271 is exposed to the plastic encapsulation body 272.
  • the plastic encapsulation body 272 can protect and seal the silicon bridge 270.
  • the step of molding to form the molding body 272 includes: referring to FIG. 2F , filling the molding compound 300, wherein the molding compound 300 fills the groove 260, and the molding compound 300 also covers the surface of the device substrate 220 away from the transfer substrate 200. In this step, the molding compound 300 also covers the top surface of the third conductive pad 271. Referring to FIG. 2G , thinning the molding compound 300 to remove the molding compound 300 on the surface of the device substrate 220 away from the transfer substrate 200, and expose the third conductive pad 271, and the remaining molding compound 300 serves as the molding body 272. In this step, if the top surface of the third conductive pad 271 protrudes from the surface of the device substrate 220, when the molding compound 300 is thinned, the third conductive pad 271 is thinned at the same time.
  • the step further includes: thinning the device substrate 220 from the surface of the device substrate 220 away from the transfer substrate 200 to expose the surface of the first conductive pillar 250.
  • the device substrate 220 may be thinned by a chemical mechanical polishing (CMP) process or a mechanical polishing process.
  • CMP chemical mechanical polishing
  • the process further includes: flattening the surface of the device substrate 220 away from the transfer substrate 200, the surface of the plastic package 272, and the surface of the silicon bridge 270 to provide a flat surface for subsequent formation of other structures.
  • the flattening process includes but is not limited to a chemical mechanical polishing process.
  • the step further includes: forming a second redistribution layer 280, the second redistribution layer 280 covers the surface of the device substrate 220 away from the transfer substrate 200 and the surface of the silicon bridge 270, the second redistribution layer 280 includes a fifth conductive pad 281, the fifth conductive pad 281 is electrically connected to the third conductive pad 271, and the fifth conductive pad 281 is exposed to the The first surface 280A of the second redistribution layer 280.
  • the plastic package 272 covers the surface of the silicon bridge 270, and the second redistribution layer 280 also covers the surface of the plastic package 272.
  • the fifth conductive pad 281 can be a metal pad, such as a copper pad.
  • the second redistribution layer 280 includes a third dielectric layer 282, the fifth conductive pad 281 is formed in the third dielectric layer 282, and is exposed to the top surface of the third dielectric layer 282, and the top surface serves as the first surface 280A of the second redistribution layer 280.
  • the third dielectric layer 282 includes but is not limited to an organic dielectric layer.
  • the material of the organic dielectric layer may be an organic resin, and the organic resin includes but is not limited to: epoxy resin (FR4), BT resin (bismaleimide triazine resin), PPE resin (polyphenylene ether resin), PI resin (polyimide resin).
  • the fifth conductive pad 281 may penetrate the third dielectric layer 282, that is, the upper surface and the lower surface of the fifth conductive pad 281 are respectively exposed to the top surface and the bottom surface of the third dielectric layer 282.
  • the second redistribution layer 280 further includes a conductive interconnection line 283.
  • the conductive interconnection line 283 is disposed in the third dielectric layer 282, and the fifth conductive pad 281 is electrically connected to one end of the conductive interconnection line 283, and the other end of the conductive interconnection line 283 is electrically connected to the third conductive pad 271, that is, the fifth conductive pad 281 is electrically connected to the third conductive pad 271 through the conductive interconnection line 283.
  • the second redistribution layer 280 further includes a seventh conductive pad 284, the seventh conductive pad 284 is electrically connected to the first conductive column 250, and the seventh conductive pad 284 is exposed on the surface of the second redistribution layer 280.
  • the seventh conductive pad 284 may be a metal pad, such as a copper pad.
  • the seventh conductive pad 284 may penetrate the third dielectric layer 282, that is, the upper surface and the lower surface of the seventh conductive pad 284 are exposed to the top surface and the bottom surface of the third dielectric layer 282, respectively.
  • the seventh conductive pad 284 is electrically connected to one end of the conductive interconnect line 283, and the other end of the conductive interconnect line 283 is electrically connected to the first conductive column 250, that is, the seventh conductive pad 284 is electrically connected to the first conductive column 250 through the conductive interconnect line 283.
  • multiple redistribution processes may be performed to form the conductive interconnection line 283 , the fifth conductive pad 281 , and the seventh conductive pad 284 .
  • step S15 a functional chip 290 is mounted on a side of the device substrate 220 away from the transfer substrate 200 , and the functional chip 290 is electrically connected to the third conductive pad 271 , thereby forming the packaging structure.
  • the functional chip 290 and the passive device 231 are arranged on the same side of the transfer substrate 200, so that the passive device 231 is close to the functional chip 290, thereby improving the performance of the packaging structure.
  • the function chip 290 is disposed on the first surface 280A of the second redistribution layer 280, and is electrically connected to the fifth conductive pad 281, and is electrically connected to the third conductive pad 271 through the fifth conductive pad 281. Further, the function chip 290 is also electrically connected to the seventh conductive pad 284, and is electrically connected to the first conductive column 250 through the seventh conductive pad 284.
  • the function chip 290 may be one or more, all of which are arranged on the first surface of the second redistribution layer 280, and the conductive pads of the function chip 290 facing the device substrate 220 are electrically connected to the fifth conductive pad 281 and the seventh conductive pad 284.
  • the function chip 290 may be electrically connected to the fifth conductive pad 281 and the seventh conductive pad 284 by a flip-chip process. It is understandable that the conductive pads of different function chips 290 may be electrically connected through the silicon bridge 270, and the conductive pads of the function chip 290 may be electrically connected to the transfer substrate 200 through the first conductive column 250.
  • a step of forming a plastic encapsulation structure 291 is also included, wherein the plastic encapsulation structure 291 covers the functional chip 290 and fills the gap between the functional chip 290 and the second redistribution layer 280 to seal and support the functional chip 290 .
  • the method for forming the packaging structure provided by the embodiment of the present invention does not need to use an additional surface mounting process to connect the passive device 231 to the adapter board, which greatly improves the process compatibility; and this formation method greatly saves the area of the adapter substrate 200, which is conducive to the miniaturization of the packaging structure.
  • the parameters of the passive device 231 can be adjusted during the manufacturing process of the passive device 231 in the device substrate 220 to achieve accurate matching between the passive device 231 and the functional chip 290.
  • the present invention also provides a packaging structure formed by adopting the above forming method.
  • the package structure includes: a transfer substrate 200 including a first conductive pad 201; a device substrate 220 including a passive device layer 230 and a first redistribution layer 240 covering the passive device layer 230, wherein the passive device layer 230 includes a passive device 231, and the first redistribution layer 240 is bonded to the transfer substrate 200, wherein the first redistribution layer 240 includes a second conductive pad 241, and one end of the second conductive pad 241 is connected to the first redistribution layer 240.
  • the first conductive pad 201 is electrically connected to the passive device 231 at one end, and the other end is electrically connected to the first conductive pad 201.
  • the device substrate 220 has a groove 260, and the groove 260 exposes the transfer substrate 200.
  • the silicon bridge 270 is arranged in the groove 260, and the silicon bridge 270 includes a third conductive pad 271.
  • the functional chip 290 is arranged on a side of the device substrate 220 away from the transfer substrate 200, and the functional chip 290 is electrically connected to the third conductive pad 271.
  • the adapter substrate 200 and the silicon bridge 270 constitute an adapter board, and the passive device 231 is integrated inside the adapter board, which greatly saves the area of the adapter board and is conducive to the miniaturization of the packaging structure;
  • the functional chip 290 and the passive device 231 are arranged on the same side of the adapter board, so that the passive device 231 is close to the functional chip 290, thereby improving the performance of the packaging structure; and the passive device 231 and the functional chip 290 can be accurately matched.
  • the transfer substrate 200 further includes a first dielectric layer 202, and the first conductive pad 201 is formed in the first dielectric layer 202.
  • the first dielectric layer 202 includes but is not limited to an organic dielectric layer.
  • the first conductive pad 201 may be a metal pad.
  • the first conductive pad 201 is a copper pad.
  • the first conductive pad 201 may penetrate the first dielectric layer 202.
  • the transfer substrate 200 further includes a conductive interconnection line and at least one bottom conductive pad.
  • the conductive interconnection line is disposed in the first dielectric layer 202, and the first conductive pad 201 is electrically connected to the conductive interconnection line.
  • the bottom conductive pad is disposed at the bottom of the first dielectric layer 202, and the bottom conductive pad is electrically connected to the conductive interconnection line, that is, the first conductive pad 201 is electrically connected to the bottom conductive pad through the conductive interconnection line, and the bottom conductive pad serves as an external connection area at the bottom of the transfer substrate 200.
  • the passive device 231 includes but is not limited to a resistor, a capacitor, and an inductor.
  • the passive device 231 is a capacitor
  • the passive device layer 230 is a capacitor device layer
  • the capacitor includes but is not limited to a deep trench capacitor.
  • the second conductive pad 241 is electrically connected to the passive device 231 and serves as a pin of the passive device 231.
  • the first redistribution layer 240 is disposed between the transfer substrate 200 and the passive device layer 230.
  • the first redistribution layer 240 includes a second dielectric layer 242, the second dielectric layer 242 is disposed between the transfer substrate 200 and the passive device layer 230, and the second conductive pad 241 penetrates the second dielectric layer 242.
  • the second conductive pad 241 is only disposed in a partial area below the top surface of the second dielectric layer 242, and is electrically led out on the bottom surface of the second dielectric layer 242 through a conductive interconnection line disposed in the second dielectric layer 242, that is, the second conductive pad 241 is electrically connected to the passive device 231 through the conductive interconnection line.
  • the second dielectric layer 242 is an organic dielectric layer, and the second conductive pad 241 is a metal pad.
  • the first dielectric layer 202 and the second dielectric layer 242 are made of the same material, and the first conductive pad 201 and the second conductive pad 241 are made of the same material, so as to improve the bonding strength between the first redistribution layer 240 and the transfer substrate 200.
  • the transfer substrate 200 further includes a fourth conductive pad 203
  • the device substrate 220 further includes a first conductive column 250
  • the first conductive column 250 penetrates the device substrate 220
  • the fourth conductive pad 203 is electrically connected to the first conductive column 250 .
  • the groove 260 has the device substrate 220 as a side wall and the transfer substrate 200 as a As the bottom surface, in some other embodiments, the groove 260 uses the device substrate 220 as the sidewall and the first redistribution layer 240 as the bottom surface.
  • the silicon bridge 270 is disposed on the surface of the transfer substrate 200 or the first redistribution layer 240 .
  • the packaging structure also includes a plastic package 272, which fills the groove 260 and covers the silicon bridge 270 to protect and seal the silicon bridge 270.
  • the plastic package 272 also covers the side of the third conductive pad 271 to support and protect the third conductive pad 271.
  • the packaging structure further includes a second redistribution layer 280, the second redistribution layer 280 covers the surface of the device substrate 220 away from the transfer substrate 200 and the surface of the silicon bridge 270, the functional chip 290 is disposed on the second redistribution layer 280, and the second redistribution layer 280 includes a fifth conductive pad 281, one end of the fifth conductive pad 281 is electrically connected to the third conductive pad 271, and the other end is electrically connected to the functional chip 290.
  • the second redistribution layer 280 further includes a seventh conductive pad 284, one end of the seventh conductive pad 284 is electrically connected to the first conductive column 250, and the other end is electrically connected to the functional chip 290.
  • the conductive pads of the functional chip 290 may be electrically connected to the adapter substrate 200 via the first conductive pillar 250 .
  • the packaging structure further includes a plastic packaging structure 291 , which covers the functional chip 290 and fills the gap between the functional chip 290 and the second redistribution layer 280 to seal and support the functional chip 290 .
  • the packaging structure provided by the embodiment of the present invention can greatly save the area of the adapter board, which is conducive to the miniaturization of the packaging structure; and, the passive device 231 is close to the functional chip 290, which improves the performance of the packaging structure. At the same time, the passive device 231 and the functional chip 290 can be accurately matched.

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Abstract

一种封装结构的形成方法包括：提供转接基板，包括第一导电衬垫，且第一导电衬垫暴露于转接基板的第一表面；提供器件基板，包括无源器件层及覆盖无源器件层的第一重布线层，无源器件层包括无源器件，第一重布线层包括第二导电衬垫，第二导电衬垫与无源器件电连接，且第二导电衬垫暴露于第一重布线层的第一表面；以转接基板的第一表面及第一重布线层的第一表面为键合面，采用混合键合工艺将转接基板与器件基板键合；自器件基板背离转接基板的表面去除部分器件基板，形成凹槽，凹槽暴露出转接基板或第一重布线层；在凹槽内形成硅桥，硅桥包括第三导电衬垫；在器件基板背离转接基板的一侧，贴装功能芯片，功能芯片与第三导电衬垫电连接。

Description

封装结构及其形成方法
相关申请引用说明
本申请要求于2023年06月05日递交的中国专利申请号202310659565.X申请名为“封装结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及封装领域，尤其涉及一种封装结构及其形成方法。
背景技术
随着先进封装技术的不断演进，基于先进封装技术的芯粒(Chiplet)技术已成为驱动设计效率提升的重要方式。芯粒技术是指预先制造好、具有特定功能、可组合集成的晶片(Die)，应用系统级封装(System in Package，SiP)技术，通过有效的片间互联和封装架构，将不同功能、不同工艺节点制造的芯片封装到一起，形成一个系统芯片。
目前采用转接板连接是实现芯片之间以及芯片与基板之间电互连的有效方式之一。但是，现有的转接板中并未集成无源器件(例如电容)，无源器件需要通过额外的表面贴装(Surface Mounted Technology，SMT)等工艺与转接板连接，其与芯片之间以及芯片与基板之间的倒装工艺不匹配，且无源器件的尺寸较大，造成转接板面积浪费，不利于封装结构的小型化。
因此如何实现无源器件与转接板之间的封装成为研究的重点。
发明内容
本发明所要解决的技术问题是，提供一种封装结构及其形成方法，其能够提高封装工艺的兼容性，且有利于封装结构的小型化。
为了解决上述问题，本发明提供了一种封装结构的形成方法，包括：提供转接基板，所述转接基板包括第一导电衬垫，且所述第一导电衬垫暴露于所述转接基板的第一表面；提供器件基板，所述器件基板包括无源器件层及覆盖所述无源器件层的第一重布线层，所述无源器件层包括无源器件，所述第一重布线层包括第二导电衬垫，所述第二导电衬垫与所述无源器件电连接，且所述第二导电衬垫暴露于所述第一重布线层的第一表面；以所述转接基板的第一表面及所述第一重布线层的第一表面为键合面，采用混合键合工艺将所述转接基板与所述器件基板键合，其中，所述第一导电衬垫与所述第二导电衬垫电连接；自所述器件基板背离所述转接基板的表面去除部分所述器件基板，形成凹槽，所述凹槽暴露出所述转接基板或所述第一重布线层，所述无源器件层具有所述无源器件的区域被保留； 在所述凹槽内形成硅桥，所述硅桥包括第三导电衬垫；在所述器件基板背离所述转接基板的一侧，贴装功能芯片，所述功能芯片与所述第三导电衬垫电连接。
在一实施例中，所述转接基板还包括第四导电衬垫，且所述第四导电衬垫暴露于所述转接基板的第一表面；所述器件基板还包括第一导电柱，所述第一导电柱设置在所述器件基板内且其一表面暴露于所述第一重布线层的第一表面；在采用混合键合工艺将所述转接基板与所述器件基板键合的步骤中，所述第四导电衬垫与所述第一导电柱电连接。
在一实施例中，在所述凹槽内形成硅桥的步骤之后还包括：塑封，以形成塑封体，所述塑封体填满所述凹槽，且所述第三导电衬垫暴露于所述塑封体。
在一实施例中，塑封，以形成塑封体的步骤包括：填充塑封料，所述塑封料填满所述凹槽，且所述塑封料还覆盖所述器件基板背离所述转接基板的表面；减薄所述塑封料，以去除所述器件基板背离所述转接基板的表面的所述塑封料，并暴露出所述第三导电衬垫，剩余的所述塑封料作为所述塑封体。
在一实施例中，塑封，以形成塑封体的步骤之后还包括：自所述器件基板背离所述转接基板的表面减薄所述器件基板，以暴露出所述第一导电柱的表面。
在一实施例中，自所述器件基板背离所述转接基板的表面减薄所述器件基板的步骤之后还包括：对所述器件基板背离所述转接基板的表面、所述塑封体表面及所述硅桥的表面进行平坦化处理。
在一实施例中，在所述凹槽内形成硅桥的步骤之后还包括：形成第二重布线层，所述第二重布线层覆盖所述器件基板背离所述转接基板的表面以及所述硅桥的表面，所述第二重布线层包括第五导电衬垫，所述第五导电衬垫与所述第三导电衬垫电连接，且所述第五导电衬垫暴露于所述第二重布线层的表面；在所述器件基板背离所述转接基板的一侧，贴装功能芯片的步骤中，所述功能芯片与所述第五导电衬垫电连接。
在一实施例中，所述第二重布线层还包括第七导电衬垫，所述第七导电衬垫与所述第一导电柱电连接，且所述第七导电衬垫暴露于所述第二重布线层的表面；在所述器件基板背离所述转接基板的一侧，贴装功能芯片的步骤中，所述功能芯片还与所述第七导电衬垫电连接。
本发明实施例还提供一种封装结构，包括：转接基板，包括第一导电衬垫；器件基板，包括无源器件层及覆盖所述无源器件层的第一重布线层，所述无源器件层包括无源器件，所述第一重布线层与所述转接基板键合连接，其中，所述第一重布线层包括第二导电衬垫， 所述第二导电衬垫的一端与所述无源器件电连接，另一端与所述第一导电衬垫电连接，所述器件基板具有凹槽，所述凹槽暴露出所述转接基板或所述第一重布线层；硅桥，设置在所述凹槽内，所述硅桥包括第三导电衬垫；功能芯片，设置在所述器件基板背离所述转接基板的一侧，且所述功能芯片与所述第三导电衬垫电连接。
在一实施例中，所述转接基板还包括第四导电衬垫，所述器件基板还包括第一导电柱，所述第一导电柱贯穿所述器件基板，且所述第四导电衬垫与所述第一导电柱电连接。
在一实施例中，还包括第二重布线层，所述第二重布线层覆盖所述器件基板背离所述转接基板的表面以及所述硅桥的表面，所述功能芯片设置在所述第二重布线层上，所述第二重布线层包括第五导电衬垫，所述第五导电衬垫的一端与所述第三导电衬垫电连接，另一端与所述功能芯片电连接。
在一实施例中，所述第二重布线层还包括第七导电衬垫，所述第七导电衬垫的一端与所述第一导电柱电连接，另一端与所述功能芯片电连接。
在一实施例中，还包括塑封体，所述塑封体填满所述凹槽。
本发明实施例提供的形成方法中，在设置所述功能芯片之前利用晶圆级封装工艺直接在所述转接基板内部集成无源器件，集成所述无源器件之后形成所述硅桥，进而形成由所述转接基板与所述硅桥构成的转接板，再将所述功能芯片与所述转接板电连接，形成所述封装结构。本发明形成方法无需采用额外的表面贴装工艺将所述无源器件与转接板连接，大大提高了工艺的兼容性；并且该种形成方法大大节省了转接基板的面积，有利于封装结构的小型化；所述功能芯片与所述无源器件设置在所述转接基板的同一侧，使得所述无源器件与所述功能芯片的距离较近，提高了封装结构的性能。另外，还可在器件基板中的无源器件的制造过程中调整无源器件的参数(例如电容的容值)，实现所述无源器件与功能芯片的精确匹配。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍。显而易见地，下面描述中的附图仅是本发明的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本发明一实施例提供的封装结构的形成方法的步骤示意图；
图2A～图2J是本发明一实施例提供的形成方法的主要步骤形成的结构示意图。
具体实施方式
下面结合附图对本发明提供的封装结构及其形成方法的具体实施方式做详细说明。
图1是本发明一实施例提供的封装结构的形成方法的步骤示意图，请参阅图1，所述形成方法包括：步骤S10，提供转接基板，所述转接基板包括第一导电衬垫，且所述第一导电衬垫暴露于所述转接基板的第一表面；步骤S11，提供器件基板，所述器件基板包括无源器件层及覆盖所述无源器件层的第一重布线层，所述无源器件层包括无源器件，所述第一重布线层包括第二导电衬垫，所述第二导电衬垫与所述无源器件电连接，且所述第二导电衬垫暴露于所述第一重布线层的第一表面；步骤S12，以所述转接基板的第一表面及所述第一重布线层的第一表面为键合面，采用混合键合工艺将所述转接基板与所述器件基板键合，其中，所述第一导电衬垫与所述第二导电衬垫电连接；步骤S13，自所述器件基板背离所述转接基板的表面去除部分所述器件基板，形成凹槽，所述凹槽暴露出所述转接基板或所述第一重布线层，所述无源器件层具有所述无源器件的区域被保留；步骤S14，在所述凹槽内形成硅桥，所述硅桥包括第三导电衬垫；步骤S15，在所述器件基板背离所述转接基板的一侧，贴装功能芯片，所述功能芯片与所述第三导电衬垫电连接。
在本发明一实施例提供的封装结构的形成方法中，在设置所述功能芯片之前利用晶圆级封装工艺直接在所述转接基板内部集成无源器件，集成所述无源器件之后形成所述硅桥，进而形成由所述转接基板与所述硅桥构成的转接板，再将所述功能芯片与所述转接板电连接，形成所述封装结构。本发明形成方法无需采用额外的表面贴装工艺将所述无源器件与转接板连接，大大提高了工艺的兼容性；并且该种形成方法大大节省了转接基板的面积，有利于封装结构的小型化；所述功能芯片与所述无源器件设置在所述转接基板的同一侧，使得所述无源器件与所述功能芯片的距离较近，提高了封装结构的性能。另外，还可在器件基板中的无源器件的制造过程中调整无源器件的参数(例如电容的容值)，实现所述无源器件与功能芯片的精确匹配。
图2A～图2J是本发明一实施例提供的形成方法的主要步骤形成的结构示意图。
请参阅图1及图2A，步骤S10，提供转接基板200，所述转接基板200包括第一导电衬垫201，且所述第一导电衬垫201暴露于所述转接基板200的第一表面200A。
在一实施例中，所述转接基板200还包括第一介质层202，所述第一导电衬垫201形成在所述第一介质层202内，且暴露于所述第一介质层202的顶表面，该顶表面作为所述转接基板200的第一表面200A。所述第一介质层202包括但不限于有机介质层。所述有机介 质层的材料可为有机树脂，所述有机树脂包括但不限于：环氧树脂(FR4)、BT树脂(双马来酰亚胺三嗪树脂)、PPE树脂(聚苯醚树脂)、PI树脂(聚酰亚胺树脂)。
在一些实施例中，所述第一导电衬垫201可为金属衬垫。例如，在一实施例中，所述第一导电衬垫201为铜衬垫。
在一实施例中，所述第一导电衬垫201可贯穿所述第一介质层202，即所述第一导电衬垫201的上表面及下表面分别暴露于所述第一介质层202的顶表面及底表面。在另一些实施例中，所述转接基板200还包括导电互连线及至少一个底部导电衬垫。所述导电互连线设置在所述第一介质层202内，且所述第一导电衬垫201与所述导电互连线电连接。所述底部导电衬垫设置在所述第一介质层202的底部，且所述底部导电衬垫与所述导电互连线的电连接，即所述第一导电衬垫201与所述底部导电衬垫通过所述导电互连线电连接。所述底部导电衬垫的表面暴露于所述第一介质层202的底表面，用于作为所述转接基板200底部的对外连接区域。
在一些实施例中，所述转接基板200还包括第四导电衬垫203，且所述第四导电衬垫203暴露于所述转接基板200的第一表面200A。具体地说，在一实施例中，所述第四导电衬垫203形成在所述第一介质层202内且贯穿所述第一介质层202，其上表面及下表面分别暴露于所述第一介质层202的顶表面及底表面。在另一些实施例中，所述第四导电衬垫203的上表面暴露于所述第一介质层202的顶表面，其下表面还可通过所述导电互连线与底部导电衬垫电连接。
作为示例，本发明提供一种形成所述转接基板200的方法。所述方法包括：提供载体基板210；在所述载体基板210上形成牺牲层211；在所述牺牲层211上形成第一介质层202，所述第一介质层202包括过孔；在所述过孔内填充导电材料，形成所述第一导电衬垫201以及所述第四导电衬垫203。所述第一导电衬垫201以及所述第四导电衬垫203为同种材料结构，其在同一步骤中形成。
在一些实施例中，所述形成方法还包括对所述转接基板200进行平坦化处理的步骤。即在执行混合键合工艺之前对所述转接基板200的第一表面200A进行平坦化处理，提高后续混合键合形成的封装结构的键合牢固度。所述平坦化处理包括但不限于化学机械研磨(Chemical mechanical polishing，简称CMP)。在一些实施例中，在形成所述转接基板200时，所述导电材料不仅填充所述过孔，还覆盖所述第一介质层202的部分表面，则在执行平坦化处理时，可同时去除所述第一介质层202表面的导电材料。
请参阅图1及图2B，步骤S11，提供器件基板220，所述器件基板220包括无源器件层230及覆盖所述无源器件层230的第一重布线层240，所述无源器件层230包括无源器件231，所述第一重布线层240包括第二导电衬垫241，所述第二导电衬垫241与所述无源器件231电连接，且所述第二导电衬垫241暴露于所述第一重布线层240的第一表面240A。
所述无源器件231包括但不限于电阻，电容，电感。例如，在一实施例中，所述无源器件231为电容，所述无源器件层230为电容器件层，其可通过在一晶圆上采用半导体工艺制备电容而获得。所述电容包括但不限于深沟槽电容。
所述第二导电衬垫241与所述无源器件231电连接，作为所述无源器件231的引脚。例如，在一实施例中，所述无源器件231为电容，所述第二导电衬垫241与所述电容的正极或负极电连接，作为所述电容的正极或负极的引脚。
在一些实施例中，所述第一重布线层240包括第二介质层242，所述第二介质层242覆盖所述无源器件层230，且所述第二导电衬垫241贯穿所述第二介质层242，所述第二导电衬垫241的一表面与所述无源器件231电连接，另一表面暴露于所述第二介质层242的顶表面，该顶表面作为所述第一重布线层240的第一表面240A。
在一些实施例中，所述第二介质层242为有机介质层，所述有机介质层的材料可为有机树脂，所述有机树脂包括但不限于：环氧树脂(FR4)、BT树脂(双马来酰亚胺三嗪树脂)、PPE树脂(聚苯醚树脂)、PI树脂(聚酰亚胺树脂)。在一些实施例中，所述第一介质层202与所述第二介质层242为同种材料层，则在后续键合工艺中，所述第一介质层202与所述第二介质层242结合牢固度更高。
在一些实施例中，所述第一导电衬垫201及所述第二导电衬垫241可均为金属衬垫，其材料可相同也可不同。例如，在一实施例中，所述第一导电衬垫201及所述第二导电衬垫241材料相同，且均为铜衬垫，则在后续键合工艺中，所述第一导电衬垫201及所述第二导电衬垫241的结合牢固度更高。
在一实施例中，所述第二导电衬垫241贯穿所述第二介质层242，而在另一些实施例中，所述第二导电衬垫241仅设置在所述第二介质层242顶表面下方的部分区域，其通过设置在第二介质层242中的导电互连线在第二介质层242的底表面电学引出，即所述第二导电衬垫241通过导电互连线与所述无源器件231电连接。
在本发明实施例提供的形成方法中，可在器件基板220中的无源器件231的制造过程中调整无源器件231的参数，例如通过加工工艺的改变或者调整电容矩阵面积调整电容的 容值，使得无源器件的参数能够趋于仿真设计中的计算值，实现无源器件231与后续设置的功能芯片290的精确匹配。
在一些实施例中，所述器件基板220还包括第一导电柱250，所述第一导电柱250设置在所述器件基板220内且其一表面暴露于所述第一重布线层240的第一表面240A，其另一表面并未暴露。具体地说，在一实施例中，所述第一导电柱250沿垂直所述第二介质层242的方向自所述第二介质层242延伸至所述器件基板220内，且所述第一导电柱250的一表面暴露于所述第二介质层242的顶表面，另一表面位于所述器件基板220内，且并未被暴露。
作为示例，本公开实施例提供一种形成所述器件基板220的方法。所述方法包括：提供一晶圆，所述晶圆包括无源器件层230；在所述无源器件层230表面形成所述第一重布线层240；形成第一导电柱250，所述第一导电柱250自所述第一重布线层240的第一表面240A延伸至所述无源器件层230内。形成所述第一导电柱250的方法包括但不限于硅通孔(Through Silicon Vias，简称TSV)技术。
在一实施例中，所述形成方法还包括对所述器件基板220进行平坦化处理的步骤。即在执行混合键合工艺之前对所述第一重布线层240的第一表面240A进行平坦化处理，提高后续混合键合形成的封装结构的键合牢固度。所述平坦化处理包括但不限于化学机械研磨(Chemical mechanical polishing，简称CMP)。
请参阅图1及图2C，步骤S12，以所述转接基板200的第一表面200A及所述第一重布线层240的第一表面240A为键合面，采用混合键合工艺将所述转接基板200与所述器件基板220键合，其中，所述第一导电衬垫201与所述第二导电衬垫241电连接。采用混合键合(Hybrid Bonding)工艺形成的结构具有更高的电流负载能力以及具有更好的热性能。在一些实施例中，所述第一介质层202的顶表面与所述第二介质层242的顶表面也键合连接。在一些实施例中，在该步骤中，所述第四导电衬垫203与所述第一导电柱250电连接。
所述混合键合工艺包括：将所述转接基板200的第一表面200A与所述第一重布线层240的第一表面240A贴合，其中，所述第一介质层202与所述第二介质层242接合；进行退火处理，所述第一导电衬垫201与所述第二导电衬垫241接合，形成键合结构。
在一些实施例中，在执行混合键合工艺之前还包括：对所述转接基板200的第一表面200A和\或所述第一重布线层240的第一表面240A进行活化处理，以在所述转接基板200的第一表面200A和\或所述第一重布线层240的第一表面240A形成活化点位，能够提高混 合键合中所述转接基板200与所述第一重布线层240的接合牢固度。所述活化处理包括但不限于等离子体活化处理。具体地说，在执行键合工艺之前，对所述转接基板200的第一表面200A和\或对所述第一重布线层240的第一表面240A进行活化处理，以使得第一介质层202和\或第二介质层242表面形成活化点位，从而可提高所述第一介质层202与所述第二介质层242的接合牢固度。
在一实施例中，在执行混合键合工艺之前对所述转接基板200的第一表面200A和所述第一重布线层240的第一表面240A均进行活化处理；在另一实施例中，在执行键合工艺之前对所述转接基板200的第一表面200A或所述第一重布线层240的第一表面240A其中之一进行活化处理。
请参阅图1及图2D，步骤S13，自所述器件基板220背离所述转接基板200的表面去除部分所述器件基板220，形成凹槽260，所述凹槽260暴露出所述转接基板200或所述第一重布线层240，所述无源器件层230具有所述无源器件231的区域被保留。
在该步骤中，所述无源器件层230中设置有无源器件231的区域被保留，未设置有所述无源器件231的区域被去除，所述无源器件层230被去除后，与去除的所述无源器件层230对应的第一重布线层240也被去除，进而暴露出所述转接基板200。其中，所述凹槽260以所述器件基板220作为侧壁，以所述转接基板200作为底面。在另一些实施例中，也可仅去除部分所述无源器件层230，所述第一重布线层240并未被去除，或者所述第一重布线层240仅被部分去除。
去除部分所述无源器件层230的方法包括但不限于刻蚀工艺。例如，在一些实施例中，去除部分所述无源器件层230的方法包括：在所述器件基板220背离所述转接基板200的表面形成图案化的掩膜层，所述掩膜层遮挡所述无源器件层230设置有所述无源器件231的区域，并暴露出所述无源器件层230未设置所述无源器件231的区域；以所述掩膜层为掩膜，刻蚀所述无源器件层230及所述第一重布线层240，至暴露出所述转接基板200；去除所述掩膜层。
请参阅图1及图2E，步骤S14，在所述凹槽260内形成硅桥(si bridge)270，所述硅桥270包括第三导电衬垫271。所述硅桥270内部具有互连线，从而在后续形成的封装结构中功能芯片290能够通过所述第三导电衬垫271及互连结构实现芯片之间或者芯片自身的电连接。在该步骤中，所述硅桥270可通过贴装的方法贴附在所述转接基板200的表面。所述第三导电衬垫271包括但不限于铜衬垫。
在该步骤中，所述凹槽260能够起到限位及对准的作用，使得无需额外在所述转接基板200内形成贴装所述硅桥270的凹槽，也无需执行精确的对准工艺，降低了工艺难度。
在一些实施例中，所述硅桥270的本体贴附在所述转接基板200的表面，所述第三导电衬垫271的顶面突出于所述硅桥270的本体，且突出于所述器件基板220的表面。在另一些实施例中，所述硅桥270的本体贴附在所述转接基板200的表面，所述第三导电衬垫271的顶面突出于所述硅桥270的本体，且低于所述器件基板220的表面，或者与所述器件基板220的表面平齐。
在一些实施例中，在所述凹槽260内形成硅桥270的步骤之后还包括如下步骤：请参阅图2G，塑封，以形成塑封体272，所述塑封体272填满所述凹槽260，且所述第三导电衬垫271暴露于所述塑封体272。所述塑封体272能够保护及密封所述硅桥270。
具体地说，在一实施例中，塑封，以形成塑封体272的步骤包括：请参阅图2F，填充塑封料300，所述塑封料300填满所述凹槽260，且所述塑封料300还覆盖所述器件基板220背离所述转接基板200的表面。在该步骤中，所述塑封料300还覆盖所述第三导电衬垫271的顶面。请参阅图2G，减薄所述塑封料300，以去除所述器件基板220背离所述转接基板200的表面的所述塑封料300，并暴露出所述第三导电衬垫271，剩余的所述塑封料300作为所述塑封体272。在该步骤中，若所述第三导电衬垫271的顶面所突出于所述器件基板220的表面，则在减薄所述塑封料300时，所述第三导电衬垫271被同时减薄。
请参阅图2H，在一些实施例中，在形成塑封体272的步骤之后还包括：自所述器件基板220背离所述转接基板200的表面减薄所述器件基板220，以暴露出所述第一导电柱250的表面。在该步骤中，可采用化学机械研磨(Chemical mechanical polishing，简称CMP)工艺或者机械研磨工艺减薄所述器件基板220。
在一些实施例中，自所述器件基板220背离所述转接基板200的表面减薄所述器件基板220的步骤之后还包括：对所述器件基板220背离所述转接基板200的表面、所述塑封体272表面及所述硅桥270的表面进行平坦化处理，以为后续形成其他结构提供平坦的表面。平坦化处理工艺包括但不限于化学机械研磨工艺。
请参阅图2I，在一些实施例中，在所述凹槽260内形成硅桥270的步骤之后还包括：形成第二重布线层280，所述第二重布线层280覆盖所述器件基板220背离所述转接基板200的表面以及所述硅桥270的表面，所述第二重布线层280包括第五导电衬垫281，所述第五导电衬垫281与所述第三导电衬垫271电连接，且所述第五导电衬垫281暴露于所述 第二重布线层280的第一表面280A。在一些实施例中，所述塑封体272覆盖所述硅桥270的表面，则所述第二重布线层280还覆盖所述塑封体272的表面。所述第五导电衬垫281可为金属衬垫，例如铜衬垫。
在一些实施例中，所述第二重布线层280包括第三介质层282，所述第五导电衬垫281形成在所述第三介质层282内，且暴露于所述第三介质层282的顶表面，该顶表面作为所述第二重布线层280的第一表面280A。所述第三介质层282包括但不限于有机介质层。所述有机介质层的材料可为有机树脂，所述有机树脂包括但不限于：环氧树脂(FR4)、BT树脂(双马来酰亚胺三嗪树脂)、PPE树脂(聚苯醚树脂)、PI树脂(聚酰亚胺树脂)。
在一实施例中，所述第五导电衬垫281可贯穿所述第三介质层282，即所述第五导电衬垫281的上表面及下表面分别暴露于所述第三介质层282的顶表面及底表面。在另一些实施例中，所述第二重布线层280还包括导电互连线283。所述导电互连线283设置在所述第三介质层282内，且所述第五导电衬垫281与所述导电互连线283的一端电连接，所述导电互连线283的另一端与所述第三导电衬垫271电连接，即所述第五导电衬垫281与所述第三导电衬垫271通过所述导电互连线283电连接。
在一些实施例中，所述第二重布线层280还包括第七导电衬垫284，所述第七导电衬垫284与所述第一导电柱250电连接，且所述第七导电衬垫284暴露于所述第二重布线层280的表面。所述第七导电衬垫284可为金属衬垫，例如铜衬垫。在一些实施例中，所述第七导电衬垫284可贯穿所述第三介质层282，即所述第七导电衬垫284的上表面及下表面分别暴露于所述第三介质层282的顶表面及底表面。在另一些实施例中，所述第七导电衬垫284与所述导电互连线283的一端电连接，所述导电互连线283的另一端与所述第一导电柱250电连接，即所述第七导电衬垫284与所述第一导电柱250通过所述导电互连线283电连接。
在一些实施例中，在形成所述第二重布线层280的步骤中，可执行多次重布线工艺，形成所述导电互连线283、所述第五导电衬垫281及所述第七导电衬垫284。
请参阅图1及图2J，步骤S15，在所述器件基板220背离所述转接基板200的一侧，贴装功能芯片290，所述功能芯片290与所述第三导电衬垫271电连接，进而形成所述封装结构。
在所述封装结构中，所述功能芯片290与所述无源器件231设置在所述转接基板200的同一侧，使得所述无源器件231与所述功能芯片290的距离较近，提高了封装结构的性能。
在一些实施例中，所述功能芯片290设置在所述第二重布线层280的第一表面280A，且与所述第五导电衬垫281电连接，并通过所述第五导电衬垫281与所述第三导电衬垫271电连接。进一步的，所述功能芯片290还与所述第七导电衬垫284电连接，并通过所述第七导电衬垫284与所述第一导电柱250电连接。
所述功能芯片290可为一个或者多个，其均设置在所述第二重布线层280的第一表面上，所述功能芯片290朝向所述器件基板220一侧的导电焊垫与所述第五导电衬垫281及所述第七导电衬垫284电连接。在一些实施例中，可采用倒装工艺将所述功能芯片290与所述第五导电衬垫281及所述第七导电衬垫284电连接。可以理解的是，不同的所述功能芯片290的导电焊垫可通过所述硅桥270实现电连接，所述功能芯片290的导电焊垫可通过所述第一导电柱250实现与所述转接基板200的电连接。
在一些实施例中，在贴装功能芯片290的步骤之后，还包括形成塑封结构291的步骤，所述塑封结构291包覆所述功能芯片290，并填充在所述功能芯片290与所述第二重布线层280之间的空隙，以密封及支撑所述功能芯片290。
本发明实施例提供的封装结构的形成方法无需采用额外的表面贴装工艺将所述无源器件231与转接板连接，大大提高了工艺的兼容性；并且该种形成方法大大节省了转接基板200的面积，有利于封装结构的小型化。另外，还可在器件基板220中的无源器件231的制造过程中调整无源器件231的参数(例如电容的容值)，实现所述无源器件231与功能芯片290的精确匹配。
本发明还提供一种采用上述形成方法形成的封装结构。
请参阅图2A～图2J，所述封装结构包括：转接基板200，包括第一导电衬垫201；器件基板220，包括无源器件层230及覆盖所述无源器件层230的第一重布线层240，所述无源器件层230包括无源器件231，所述第一重布线层240与所述转接基板200键合连接，其中，所述第一重布线层240包括第二导电衬垫241，所述第二导电衬垫241的一端与所述无源器件231电连接，另一端与所述第一导电衬垫201电连接，所述器件基板220具有凹槽260，所述凹槽260暴露出所述转接基板200；硅桥270，设置在所述凹槽260内，所述硅桥270包括第三导电衬垫271；功能芯片290，设置在所述器件基板220背离所述转接基板200的一侧，且所述功能芯片290与所述第三导电衬垫271电连接。
本发明实施例提供的封装结构中，所述转接基板200与所述硅桥270构成转接板，所述无源器件231集成在转接板内部，大大节省了转接板的面积，有利于封装结构的小型化； 所述功能芯片290与所述无源器件231设置在转接板的同一侧，使得所述无源器件231与所述功能芯片290的距离较近，提高了封装结构的性能；并且，无源器件231与功能芯片290能够精确匹配。
在一些实施例中，所述转接基板200还包括第一介质层202，所述第一导电衬垫201形成在所述第一介质层202内。所述第一介质层202包括但不限于有机介质层。所述第一导电衬垫201可为金属衬垫。例如，在一实施例中，所述第一导电衬垫201为铜衬垫。
在一实施例中，所述第一导电衬垫201可贯穿所述第一介质层202。在另一些实施例中，所述转接基板200还包括导电互连线及至少一个底部导电衬垫。所述导电互连线设置在所述第一介质层202内，且所述第一导电衬垫201与所述导电互连线电连接。所述底部导电衬垫设置在所述第一介质层202的底部，且所述底部导电衬垫与所述导电互连线的电连接，即所述第一导电衬垫201与所述底部导电衬垫通过所述导电互连线电连接，所述底部导电衬垫作为所述转接基板200底部的对外连接区域。
所述无源器件231包括但不限于电阻，电容，电感。例如，在一实施例中，所述无源器件231为电容，所述无源器件层230为电容器件层，所述电容包括但不限于深沟槽电容。所述第二导电衬垫241与所述无源器件231电连接，作为所述无源器件231的引脚。
所述第一重布线层240设置在所述转接基板200与所述无源器件层230之间。在一些实施例中，所述第一重布线层240包括第二介质层242，所述第二介质层242设置在所述转接基板200与所述无源器件层230之间，且所述第二导电衬垫241贯穿所述第二介质层242。而在另一些实施例中，所述第二导电衬垫241仅设置在所述第二介质层242顶表面下方的部分区域，其通过设置在第二介质层242中的导电互连线在第二介质层242的底表面电学引出，即所述第二导电衬垫241通过导电互连线与所述无源器件231电连接。
在一些实施例中，所述第二介质层242为有机介质层，所述第二导电衬垫241为金属衬垫。在一些实施例中，所述第一介质层202与所述第二介质层242为同种材料层，所述第一导电衬垫201及所述第二导电衬垫241为同种材料，以提高所述第一重布线层240及所述转接基板200的结合牢固度。
在一些实施例中，所述转接基板200还包括第四导电衬垫203，所述器件基板220还包括第一导电柱250，所述第一导电柱250贯穿所述器件基板220，且所述第四导电衬垫203与所述第一导电柱250电连接。
在一些实施例中，所述凹槽260以所述器件基板220作为侧壁，以所述转接基板200 作为底面，在另一些实施例中，所述凹槽260以所述器件基板220作为侧壁，以所述第一重布线层240为底面。所述硅桥270设置在所述转接基板200或者所述第一重布线层240的表面。
在一些实施例中，所述封装结构还包括塑封体272，所述塑封体272填满所述凹槽260，并覆盖所述硅桥270，以保护及密封所述硅桥270，所述塑封体272还包覆所述第三导电衬垫271的侧面，以支撑及保护所述第三导电衬垫271。
在一些实施例中，所述封装结构还包括第二重布线层280，所述第二重布线层280覆盖所述器件基板220背离所述转接基板200的表面以及所述硅桥270的表面，所述功能芯片290设置在所述第二重布线层280上，所述第二重布线层280包括第五导电衬垫281，所述第五导电衬垫281的一端与所述第三导电衬垫271电连接，另一端与所述功能芯片290电连接。在一些实施例中，所述第二重布线层280还包括第七导电衬垫284，所述第七导电衬垫284的一端与所述第一导电柱250电连接，另一端与所述功能芯片290电连接。
所述功能芯片290可为一个或者多个，不同的所述功能芯片290的导电焊垫可通过所述硅桥270实现电连接，所述功能芯片290的导电焊垫可通过所述第一导电柱250实现与所述转接基板200的电连接。
在一些实施例中，所述封装结构还包括一塑封结构291，所述塑封结构291包覆所述功能芯片290，并填充在所述功能芯片290与所述第二重布线层280之间的空隙，以密封及支撑所述功能芯片290。
本发明实施例提供的封装结构能够大大节省转接板的面积，有利于封装结构的小型化；并且，所述无源器件231与所述功能芯片290的距离较近，提高了封装结构的性能，同时，无源器件231与功能芯片290能够精确匹配。
需要说明的是，本发明的文件中涉及的术语“包括”和“具有”以及它们的变形，意图在于覆盖不排他的包含。术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序，除非上下文有明确指示，应该理解这样使用的数据在适当情况下可以互换。术语“一个或多个”至少部分取决于上下文，可以用于以单数意义描述特征、结构或特性，或可以用于以复数意义描述特征、结构或特征的组合。术语“基于”可以被理解为不一定旨在表达一组排他性的因素，而是可以替代地，同样至少部分地取决于上下文，允许存在不一定明确描述的其它因素。另外，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。此外，在以上说明中，省略了对公知组件和技术的 描述，以避免不必要地混淆本发明的概念。上述各个实施例中，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同/相似的部分互相参见即可。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (13)

  1. 一种封装结构的形成方法，包括：
    提供转接基板，所述转接基板包括第一导电衬垫，且所述第一导电衬垫暴露于所述转接基板的第一表面；
    提供器件基板，所述器件基板包括无源器件层及覆盖所述无源器件层的第一重布线层，所述无源器件层包括无源器件，所述第一重布线层包括第二导电衬垫，所述第二导电衬垫与所述无源器件电连接，且所述第二导电衬垫暴露于所述第一重布线层的第一表面；
    以所述转接基板的第一表面及所述第一重布线层的第一表面为键合面，采用混合键合工艺将所述转接基板与所述器件基板键合，其中，所述第一导电衬垫与所述第二导电衬垫电连接；
    自所述器件基板背离所述转接基板的表面去除部分所述器件基板，形成凹槽，所述凹槽暴露出所述转接基板或所述第一重布线层，所述无源器件层具有所述无源器件的区域被保留；
    在所述凹槽内形成硅桥，所述硅桥包括第三导电衬垫；
    在所述器件基板背离所述转接基板的一侧，贴装功能芯片，所述功能芯片与所述第三导电衬垫电连接。
  2. 根据权利要求1所述的封装结构的形成方法，其中，所述转接基板还包括第四导电衬垫，且所述第四导电衬垫暴露于所述转接基板的第一表面；所述器件基板还包括第一导电柱，所述第一导电柱设置在所述器件基板内且其一表面暴露于所述第一重布线层的第一表面；在采用混合键合工艺将所述转接基板与所述器件基板键合的步骤中，所述第四导电衬垫与所述第一导电柱电连接。
  3. 根据权利要求2所述的封装结构的形成方法，其中，在所述凹槽内形成硅桥的步骤之后还包括：塑封，以形成塑封体，所述塑封体填满所述凹槽，且所述第三导电衬垫暴露于所述塑封体。
  4. 根据权利要求3所述的封装结构的形成方法，其中，塑封，以形成塑封体的步骤包括：
    填充塑封料，所述塑封料填满所述凹槽，且所述塑封料还覆盖所述器件基板背离所述转接基板的表面；
    减薄所述塑封料，以去除所述器件基板背离所述转接基板的表面的所述塑封料，并暴露出所述第三导电衬垫，剩余的所述塑封料作为所述塑封体。
  5. 根据权利要求3所述的封装结构的形成方法，其中，塑封，以形成塑封体的步骤之后还 包括：自所述器件基板背离所述转接基板的表面减薄所述器件基板，以暴露出所述第一导电柱的表面。
  6. 根据权利要求5所述的封装结构的形成方法，其中，自所述器件基板背离所述转接基板的表面减薄所述器件基板的步骤之后还包括：对所述器件基板背离所述转接基板的表面、所述塑封体表面及所述硅桥的表面进行平坦化处理。
  7. 根据权利要求2～6任一项所述的封装结构的形成方法，其中，在所述凹槽内形成硅桥的步骤之后还包括：形成第二重布线层，所述第二重布线层覆盖所述器件基板背离所述转接基板的表面以及所述硅桥的表面，所述第二重布线层包括第五导电衬垫，所述第五导电衬垫与所述第三导电衬垫电连接，且所述第五导电衬垫暴露于所述第二重布线层的表面；
    在所述器件基板背离所述转接基板的一侧，贴装功能芯片的步骤中，所述功能芯片与所述第五导电衬垫电连接。
  8. 根据权利要求7所述的封装结构的形成方法，其中，所述第二重布线层还包括第七导电衬垫，所述第七导电衬垫与所述第一导电柱电连接，且所述第七导电衬垫暴露于所述第二重布线层的表面；
    在所述器件基板背离所述转接基板的一侧，贴装功能芯片的步骤中，所述功能芯片还与所述第七导电衬垫电连接。
  9. 一种封装结构，其中，包括：
    转接基板，包括第一导电衬垫；
    器件基板，包括无源器件层及覆盖所述无源器件层的第一重布线层，所述无源器件层包括无源器件，所述第一重布线层与所述转接基板键合连接，其中，所述第一重布线层包括第二导电衬垫，所述第二导电衬垫的一端与所述无源器件电连接，另一端与所述第一导电衬垫电连接，所述器件基板具有凹槽，所述凹槽暴露出所述转接基板或所述第一重布线层；
    硅桥，设置在所述凹槽内，所述硅桥包括第三导电衬垫；
    功能芯片，设置在所述器件基板背离所述转接基板的一侧，且所述功能芯片与所述第三导电衬垫电连接。
  10. 根据权利要求9所述的封装结构，其中，所述转接基板还包括第四导电衬垫，所述器件基板还包括第一导电柱，所述第一导电柱贯穿所述器件基板，且所述第四导电衬垫与所 述第一导电柱电连接。
  11. 根据权利要求10所述的封装结构，其中，还包括第二重布线层，所述第二重布线层覆盖所述器件基板背离所述转接基板的表面以及所述硅桥的表面，所述功能芯片设置在所述第二重布线层上，所述第二重布线层包括第五导电衬垫，所述第五导电衬垫的一端与所述第三导电衬垫电连接，另一端与所述功能芯片电连接。
  12. 根据权利要求11所述的封装结构，其中，所述第二重布线层还包括第七导电衬垫，所述第七导电衬垫的一端与所述第一导电柱电连接，另一端与所述功能芯片电连接。
  13. 根据权利要求9～12任一项所述的封装结构，其中，还包括塑封体，所述塑封体填满所述凹槽。
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