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WO2024244848A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2024244848A1
WO2024244848A1 PCT/CN2024/089967 CN2024089967W WO2024244848A1 WO 2024244848 A1 WO2024244848 A1 WO 2024244848A1 CN 2024089967 W CN2024089967 W CN 2024089967W WO 2024244848 A1 WO2024244848 A1 WO 2024244848A1
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WO
WIPO (PCT)
Prior art keywords
line
area
array substrate
virtual
driving circuit
Prior art date
Application number
PCT/CN2024/089967
Other languages
English (en)
French (fr)
Inventor
周茂秀
杨海鹏
戴珂
程敏
张春旭
姜晓婷
杨越
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024244848A1 publication Critical patent/WO2024244848A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a display device.
  • a driving module including a multi-level driving circuit can be disposed on the upper side or the lower side of an array substrate.
  • an embodiment of the present disclosure provides an array substrate, comprising a base substrate and a first data line, a dummy signal line and a driving module arranged on the base substrate, wherein the first data line, the dummy signal line and the driving module are arranged in a peripheral area of the array substrate, the peripheral area at least partially surrounds a display area, the display area comprises a first gate line extending along a first direction and a second data line extending along a second direction, the first data line and the second data line are electrically connected, and the first direction and the second direction intersect;
  • the driving module is arranged on a first side of the array substrate; the first side is a side arranged in the extending direction of the second data line;
  • the driving module comprises a multi-stage driving circuit; the multi-stage driving circuit is arranged along the first direction; the driving circuit is used to provide a driving signal;
  • the first data line is arranged between at least two adjacent driving circuits, and the first data line is used to provide a data voltage
  • the virtual signal line is also arranged between at least two adjacent driving circuits; the virtual signal line is in a floating state.
  • the first data line and the virtual signal line are formed in the same conductive layer.
  • At least one of the virtual signal lines is arranged between two adjacent first data lines;
  • the dummy signal line extends along the second direction.
  • the peripheral area includes a driving circuit area and a side area; the driving module is arranged in the driving circuit area;
  • the side regions are arranged on two opposite sides of the arrangement direction of the driving circuit region;
  • the side area includes a first signal line area and a first electrostatic release area;
  • the array substrate also includes a A plurality of clock signal lines in the first signal line area, and a first electrostatic discharge circuit arranged in the first electrostatic discharge area;
  • the first electrostatic discharge circuit is electrically connected to the clock signal line and is used for performing electrostatic protection on the clock signal line.
  • the array substrate further includes a first low voltage line, a second low voltage line, a frame reset line, a first control voltage line, a second control voltage line and a start voltage line arranged in the first signal line area;
  • the first electrostatic discharge circuit is also electrically connected to the first first low voltage line, the second low voltage line, the frame reset line, the first control voltage line, the second control voltage line and the starting voltage line, respectively, for performing electrostatic protection on the first first low voltage line, the second low voltage line, the frame reset line, the first control voltage line, the second control voltage line and the starting voltage line;
  • the first first low voltage line is used to provide a first low voltage signal
  • the frame reset line is used to provide a frame reset signal
  • the first control voltage line is used to provide a first control voltage
  • the second control voltage line is used to provide a second control voltage
  • the start voltage line is used to provide a start voltage
  • the clock signal line, the second low voltage line, the frame reset line, the first control voltage line and the second control voltage line are arranged on the first side, the second side and the third side of the first electrostatic release circuit;
  • the first first low voltage line is arranged on the first side and the second side of the first electrostatic release circuit;
  • the start voltage line is arranged on the fourth side of the first electrostatic release circuit;
  • the first side and the fourth side are opposite sides, and the second side and the third side are opposite sides.
  • the array substrate includes a driving circuit area and a display area, and the driving module is arranged in the driving circuit area; the driving circuit area includes a line collection area;
  • the array substrate further includes a second first low voltage line disposed between the driving circuit area and the display area, and a cascade line disposed in the line collection area;
  • the cascade line is a signal line used for cascading between the driving circuits of each level included in the driving module; the second first low voltage line is used to provide a first low voltage signal;
  • the orthographic projection of the virtual signal line on the substrate overlaps with the orthographic projection of the cascade line on the substrate;
  • An orthographic projection of the dummy signal line on the base substrate partially overlaps with an orthographic projection of the second first low voltage line on the base substrate.
  • the peripheral area includes a virtual driving circuit area
  • the array substrate includes a virtual driving module arranged in the virtual driving circuit area, and the virtual driving circuit area is arranged between the side area and the display area;
  • the virtual driving module includes a plurality of virtual driving circuits arranged along a first direction;
  • the virtual driving circuit includes a virtual driving output terminal and a virtual input terminal;
  • the virtual input terminal of the virtual driving circuit is disconnected from the virtual driving output terminal of the virtual driving circuit other than the virtual driving circuit included in the virtual driving module.
  • the array substrate further comprises a floating signal line arranged between adjacent dummy driving circuits;
  • the floating signal line is in a floating state.
  • the array substrate includes a peripheral area and a display area, the peripheral area includes a driving circuit area; the driving module is arranged in the driving circuit area;
  • the peripheral area further includes a common electrode wiring area arranged on a side of the driving circuit area away from the display area, and a second signal line area arranged between the common electrode wiring area and the driving circuit area;
  • the array substrate further comprises a common electrode wiring, a common electrode connecting wire and a common electrode arranged in the display area; the common electrode wiring is electrically connected to the common electrode through the common electrode connecting wire;
  • the common electrode wiring is located in the common electrode wiring area
  • the common electrode connection line passes through the second signal line area and the driving circuit area.
  • the array substrate further includes a plurality of clock signal lines, a first control voltage line, a second control voltage line, a frame reset line and a second low voltage line arranged in the second signal line region.
  • the array substrate includes a peripheral area and a display area, the peripheral area includes a driving circuit area; the driving module is arranged in the driving circuit area;
  • the peripheral area further includes a second signal line area arranged on a side of the driving circuit area away from the display area;
  • the array substrate further comprises a plurality of clock signal lines arranged in the second signal line region; the clock signal lines extend along a first direction, and the plurality of clock signal lines are arranged along the second direction;
  • the clock signal connection line electrically connected to the clock signal line near the display area includes a winding portion relative to the clock signal connection line electrically connected to the clock signal line near the common electrode wiring area.
  • the first gate line and the second data line intersect to define a sub-pixel area, and the sub-pixel area includes a sub-electrode;
  • the length of the sub-electrode included in the sub-pixel region farthest from the driving module along the second direction is shorter than the first length
  • the first length is the shortest length of the sub-electrodes included in the sub-pixel regions except the sub-pixel region farthest from the driving module along the second direction.
  • the array substrate includes a display area and a peripheral area
  • the peripheral area includes a first virtual pattern area arranged on a first side of the display area and/or a second virtual pattern area arranged on a fourth side of the display area; the first side and the fourth side are opposite sides;
  • the array substrate comprises a first virtual pattern array arranged in the first virtual pattern area, and/or a second virtual pattern array arranged in the second virtual pattern area;
  • the first virtual pattern array includes a plurality of first virtual patterns arranged in an array
  • the second virtual pattern array includes a plurality of second virtual patterns arranged in an array; the first virtual pattern is used to support the frame sealing glue, and the second virtual pattern is used to support the frame sealing glue.
  • the array substrate includes a peripheral area; the peripheral area includes a binding area; the array substrate includes including a binding pad disposed in the binding area;
  • the binding pad is electrically connected to the first data line, and the binding pad is electrically connected to the conductive connection pattern through a via hole, and the edge of the via hole is serrated.
  • the array substrate described in at least one embodiment of the present disclosure further includes a second gate line extending along the second direction;
  • the first gate line is electrically connected to the second gate line, and the second gate line is electrically connected to the driving module.
  • the first gate line and the second data line cross to define a sub-pixel area
  • the number of first data lines between adjacent driving circuits is greater than or equal to m/(n+2) and less than or equal to m/(n-1);
  • n is the number of the first gate lines
  • m is the number of the second data lines corresponding to the sub-pixel areas
  • m and n are positive integers.
  • the number of the virtual signal lines is less than the number of the first data lines.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned array substrate.
  • FIG1 is a layout diagram of two driving circuits included in an array substrate of the present disclosure and a signal line disposed between the two driving circuits;
  • FIG2A is a structural diagram of an array substrate according to at least one embodiment of the present disclosure.
  • FIG2B is a structural diagram of an array substrate according to at least one embodiment of the present disclosure.
  • FIG2C is a structural diagram of an array substrate according to at least one embodiment of the present disclosure.
  • 3A and 3B are structural diagrams of a side region included in an array substrate according to at least one embodiment of the present disclosure
  • FIG3C is a partial enlarged schematic diagram of the first electrostatic discharge circuit ED1 in FIG3A ;
  • FIG3D is a circuit diagram of at least one embodiment of a first electrostatic discharge subcircuit
  • FIG. 4 is a layout diagram of a driving circuit region 30 included in an array substrate according to at least one embodiment of the present disclosure
  • FIG. 5 is a layout diagram of a virtual driving circuit area XA included in an array substrate according to at least one embodiment of the present disclosure
  • FIG. 6 is a layout diagram of a virtual driving circuit area XA included in an array substrate according to at least one embodiment of the present disclosure
  • FIG. 7 is a layout diagram of a virtual driving circuit area XA included in an array substrate according to at least one embodiment of the present disclosure
  • FIG. 8 is a layout diagram of a driving circuit area 30, a second signal line area 71, and a common electrode wiring area VMA included in an array substrate according to at least one embodiment of the present disclosure
  • FIGS. 9 and 10 are schematic diagrams of a driving circuit located in the middle included in an array substrate according to at least one embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of the side region 20 and the virtual driving circuit region XA in at least one embodiment of the present disclosure
  • FIG12 is a schematic diagram of a driving circuit located on the left side and included in an array substrate in at least one embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of a driving circuit located in the middle included in an array substrate according to at least one embodiment of the present disclosure
  • FIG14 is a schematic diagram of a driving circuit located on the right side and included in an array substrate according to at least one embodiment of the present disclosure
  • FIG15 is a structural diagram of at least one embodiment of a driving circuit in an array substrate according to the present disclosure.
  • FIG16A is a schematic diagram showing the addition of markings for transistors and capacitors in the driving circuit based on FIG14;
  • FIG16B is a partial enlarged view of the first part of the driving circuit from top to bottom;
  • FIG16C is a partial enlarged view of the second portion of the driving circuit from top to bottom;
  • FIG16D is a partial enlarged view of the third portion from top to bottom of the driving circuit
  • FIG16E is a partial enlarged view of the fourth portion from top to bottom of the driving circuit.
  • FIG16F is a partial enlarged view of FIG16A
  • 17 is a schematic diagram of a common electrode VM included in a sub-pixel region closer to the driving module and a pixel electrode PX included in a sub-pixel region closer to the driving module;
  • FIG. 18 is a schematic diagram of a common electrode VM included in a sub-pixel region farthest from the driving module, and a pixel electrode PX included in a sub-pixel region farthest from the driving module;
  • FIG19 is a layout diagram of a dummy pattern area included in the array substrate of the present disclosure.
  • FIG20 is a top view of a via area AG occupied by a via passing through an organic film layer
  • FIG21 is a cross-sectional view of a via hole in an array substrate according to the present disclosure.
  • FIG22 is a top view of the via area AG
  • FIG. 23 is a layout diagram of the gate metal layer in FIG. 22 .
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the array substrate of the embodiment of the present disclosure comprises a base substrate and a first data line, a dummy signal line and a driving module arranged on the base substrate, wherein the first data line, the dummy signal line and the driving module are arranged in a peripheral area of the array substrate, wherein the peripheral area at least partially surrounds a display area, wherein the display area comprises a first gate line extending along a first direction and a second data line extending along a second direction, wherein the first data line and the second data line are electrically connected, and the first direction and the second direction intersect;
  • the driving module is arranged on a first side of the array substrate; the first side is a side arranged in the extending direction of the second data line;
  • the driving module comprises a multi-stage driving circuit; the multi-stage driving circuit is arranged along the first direction; the driving circuit is used to provide a driving signal;
  • the first data line is arranged between at least two adjacent driving circuits, and the first data line is used to provide data According to voltage;
  • the virtual signal line is also arranged between at least two adjacent driving circuits; the virtual signal line is in a floating state.
  • a first data line, a virtual signal line and a driving module are arranged in the peripheral area of the array substrate, and a first data line and a virtual signal line are arranged between at least two adjacent driving circuits, and the virtual signal line is in a floating state.
  • the embodiment of the present disclosure can ensure etching uniformity by setting the virtual signal line.
  • the first direction may be a horizontal direction
  • the second direction may be a vertical direction, but the present invention is not limited thereto.
  • the first side may be a side arranged in the extension direction of the second data line; for example, when the extension direction of the second data line is a vertical direction, the first side may be an upper side and/or a lower side.
  • the first data line and the virtual signal line are formed in the same conductive layer.
  • the first data line and the dummy signal line may be formed in the same conductive layer; for example, the first data line and the dummy signal line may both be formed in a source-drain metal layer, but the present invention is not limited thereto.
  • At least one of the virtual signal lines is disposed between two adjacent first data lines
  • the dummy signal line extends along the second direction.
  • the virtual signal line may be disposed between adjacent first data lines, and the virtual signal line may extend along the second direction.
  • the circuit labeled GA1 is the first driving circuit, and the circuit labeled GA2 is the second driving circuit;
  • a first first data line DL11, a second first data line DL21, a third first data line DL31, a first dummy signal line XL1, and a second dummy signal line XL2 are provided between the first driving circuit GA1 and the second driving circuit GA2;
  • the first first data line DL11, the second first data line DL21, the third first data line DL31, the first dummy signal line XL1 and the second dummy signal line XL2 extend in the vertical direction;
  • the first virtual signal line XL1 is disposed between the first first data line DL11 and the second first data line DL21;
  • the first first data line DL11 , the second first data line DL21 , the third first data line DL31 , the first dummy signal line XL1 , and the second dummy signal line XL2 are all formed in the source-drain metal layer.
  • the display area of the array substrate described in at least one embodiment of the present disclosure further includes a second gate line extending along the second direction;
  • the first gate line is electrically connected to the second gate line, and the first gate line and the second gate line are arranged in different layers.
  • the first gate line can be arranged in a gate metal layer (gate layer), and the second gate line and the second data line in the display area are in the same layer, that is, arranged in a source-drain metal layer (SD layer).
  • the first gate line and the second gate line are electrically connected through a via hole penetrating the insulating layer, and the second gate line is electrically connected to the driving module.
  • the array substrate may include a first first gate line GL11, a second first gate line GL21, a third first gate line GL31, an A-2 first gate line GL41, an A-1 first gate line GL5 ...51, an A-3 first gate line GL61, an A-4 first gate line GL71, an A-5 first gate line GL81, an A-6 first gate line GL91, an A-7 first gate line GL101, an A-8 first gate line GL11, an A-9 first gate line GL121, an A-10 first gate line GL131, an A-11 first gate line GL141, an A-12 first gate line GL151, an A-13 first gate line GL161, an A-14 first gate line
  • the first first gate line GL11, the second first gate line GL21, the third first gate line GL31, the A-2th first gate line GL41, the A-1th first gate line GL51 and the Ath first gate line GL61 all extend in the horizontal direction;
  • the first second gate line GL12, the second second gate line GL22, the third second gate line GL32, the D-1 second gate line GL42, the D-2 second gate line GL52, the B-2 second gate line GL62, the B-1 second gate line GL72 and the B-82 second gate line all extend in the vertical direction;
  • A is an integer greater than 5
  • D is an integer greater than 4
  • B is an integer greater than 7.
  • the first second data line is labeled DL12
  • the second second data line is labeled DL22
  • the third second data line is labeled DL32
  • the C-2 second data line is labeled DL42
  • the C-1 second data line is labeled DL52
  • the C-2 second data line is labeled DL62
  • C is an integer greater than 5.
  • the element labeled Z0 is an array substrate.
  • DL12 , DL22 , DL32 , DL42 , DL52 , and DL62 all extend in the vertical direction;
  • Each second data line, each first gate line and each second gate line are disposed in the display area A1.
  • the first side is labeled B1
  • the driving module M0 is disposed on the first side B1 ;
  • the first side B1 is a side arranged in the extending direction of each second data line.
  • the driving module M0 is electrically connected to GL12, GL22, GL32, GL42, GL52, GL62, GL72 and GL82, respectively, for providing corresponding driving signals to GL12, GL22, GL32, GL42, GL52, GL62, GL72 and GL82, respectively;
  • Each first gate line is electrically connected to each second gate line
  • DL12 , DL22 , DL32 , DL42 , DL52 , and DL62 are all electrically connected to the source driver S0 , and receive corresponding data voltages from the source driver S0 .
  • the first gate line and the second data line in the display area intersect to define a sub-pixel area
  • the second gate line and the second data line can be set between adjacent sub-pixel areas, or partially overlap with the sub-pixel area in a direction perpendicular to the base substrate, which is not limited here.
  • the area labeled A1 is the display area
  • the area labeled Z1 is the peripheral area.
  • the peripheral area Z1 is arranged around the display area A1.
  • a binding pad may be provided on the first side, and the source driver S0 may be electrically connected to each data line through the binding pad, or the binding pad may be electrically connected to a flexible circuit board, and the source driver is provided on the flexible circuit board, so that the second data line provides a data signal.
  • the first gate line and the second data line cross to define a sub-pixel area
  • the number of first data lines between adjacent driving circuits is greater than or equal to m/(n+2) and less than or equal to m/(n-1);
  • n is the number of the first gate lines, and m is the number of the second data lines corresponding to the sub-pixel area;
  • n are positive integers.
  • the number of the virtual signal lines is less than the number of the first data lines, so that a narrow frame can be achieved while ensuring etching uniformity.
  • the number of the first data lines may be 3, and the number of the virtual signal lines may be 2, but is not limited thereto.
  • the peripheral area includes a driving circuit area and a side area; the driving module is disposed in the driving circuit area;
  • the side regions are arranged on two opposite sides of the arrangement direction of the driving circuit region, that is, the side regions are arranged on two opposite sides extending in the first direction;
  • the side area includes a first signal line area and a first electrostatic release area;
  • the array substrate further includes a plurality of clock signal lines arranged in the first signal line area, and a first electrostatic release circuit arranged in the first electrostatic release area;
  • the first electrostatic discharge circuit is electrically connected to the clock signal line and is used for performing electrostatic protection on the clock signal line.
  • the area labeled 20 is a side area
  • the side area 20 includes a first signal line area 21 and a first electrostatic release area 22;
  • a plurality of signal lines are disposed in the first signal line region 21 .
  • a first electrostatic discharge circuit ED1 is disposed in the first electrostatic discharge region 22 .
  • CK1 is a first clock signal line
  • CK2 is a second clock signal line
  • CK3 is a third clock signal line
  • CK4 is a fourth clock signal line
  • CK5 is a fifth clock signal line
  • CK6 is a sixth clock signal line
  • CK7 is a seventh clock signal line
  • CK8 is an eighth clock signal line (eight clock signal lines are used as an example, but not limited thereto);
  • the line labeled VGL11 is the first low voltage line
  • the line labeled LVGL is the second low voltage line
  • the line labeled STV0 is the frame reset line
  • the line labeled VDDE is the second control voltage line
  • the line labeled VDDO is the first control voltage line
  • the line labeled STV1 is the starting voltage line.
  • each clock signal line, a first low voltage line VGL11, a second low voltage line LVGL, a frame reset line STV0, a first control voltage line VDDO, a second control voltage line VDDE and a start voltage line STV1 may be formed in a gate metal layer, and these signal lines may be electrically connected to a first electrostatic release circuit via a cross-line, and the cross-line may be an electrode layer in the same layer as a pixel electrode or a common electrode in a display area, such as an ITO (indium tin oxide) layer, but is not limited thereto.
  • ITO indium tin oxide
  • the array substrate further includes a first low voltage line, a second low voltage line, a frame reset line, a first control voltage line, a second control voltage line and a start voltage line arranged in the first signal line region;
  • the first electrostatic discharge circuit is also electrically connected to the first first low voltage line, the second low voltage line, the frame reset line, the first control voltage line, the second control voltage line and the start voltage line, respectively, for discharging the first first low voltage line, the second low voltage line, the frame reset line, the first control voltage line, the second control voltage line and the start voltage line.
  • the second control voltage line and the starting voltage line are provided with electrostatic protection;
  • the first first low voltage line is used to provide a first low voltage signal
  • the frame reset line is used to provide a frame reset signal
  • the first control voltage line is used to provide a first control voltage
  • the second control voltage line is used to provide a second control voltage
  • the start voltage line is used to provide a start voltage to the gate drive circuit.
  • the first electrostatic release circuit ED1 is electrically connected to the first low voltage line VGL11, the second low voltage line LVGL, the frame reset line STV0, the second control voltage line VDDE, the first control voltage line VDDO and the starting voltage line STV1, respectively, and is used to perform electrostatic protection on the first low voltage line VGL, the second low voltage line LVGL, the frame reset line STV0, the second control voltage line VDDE, the first control voltage line VDDO and the starting voltage line STV1.
  • the first low voltage line VGL11 is used to provide a first low voltage signal
  • the frame reset line STV0 is used to provide a frame reset signal
  • the second control voltage line VDDE is used to provide a second control voltage
  • the first control voltage line VDDO is used to provide a first control voltage
  • the start voltage line STV1 is used to provide a start voltage.
  • the clock signal line, the second low voltage line, the frame reset line, the first control voltage line and the second control voltage line are arranged on the first side, the second side and the third side of the first electrostatic discharge circuit;
  • the first first low voltage line is arranged on the first side and the second side of the first electrostatic discharge circuit;
  • the start voltage line is arranged on the fourth side of the first electrostatic discharge circuit;
  • the first side and the fourth side are opposite sides, and the second side and the third side are opposite sides.
  • the first side may be the left side
  • the second side may be the upper side
  • the third side may be the lower side
  • the fourth side may be the right side, but is not limited thereto.
  • each clock signal line can be arranged on the left side, the upper side and the lower side of the first electrostatic discharge circuit ED1
  • the first first low voltage line VGL11 can be arranged on the left side and the upper side of the first electrostatic discharge circuit ED1
  • the starting voltage line STV1 can be arranged on the right side of the first electrostatic discharge circuit
  • the second low voltage line LVGL, the frame reset line STV0, the first control voltage line VDDO and the second control voltage line VDDE are arranged on the left side, the upper side and the lower side of the first electrostatic discharge circuit ED1.
  • the clock signal line and the first electrostatic discharge circuit are electrically connected through a jumper line, and the jumpers extend along the first direction, that is, the portion of the clock signal line on the left side of the first electrostatic discharge circuit is electrically connected to the first electrostatic discharge circuit through a jumper line
  • other signal lines including the second low voltage line LVGL, the frame reset line STV0, the first control voltage line VDDO and the second control voltage line VDDE
  • the wide line extends along the second direction, that is, the portion of other signal lines on the upper side of the first electrostatic discharge circuit is electrically connected to the first electrostatic discharge circuit through a jumper line.
  • the line realizes electrical connection with the first electrostatic release circuit.
  • the starting voltage line STV1 and the first electrostatic release circuit are electrically connected through a jumper line.
  • the jumper line extends along the first direction, that is, the starting voltage line STV1 on the right side of the first electrostatic release circuit is electrically connected to the first electrostatic release circuit through a jumper line.
  • the electrical connection with the first electrostatic release circuit is realized by leading out the jumper line from the left side, the top side and the right side respectively including three parts of signal lines, so that the first electrostatic release circuit is arranged within the range surrounded by the signal lines, which can reduce the space occupied by the first electrostatic release circuit, and further realize the effect of narrow frame.
  • the common electrode near-end signal line is labeled VJ
  • the common electrode far-end signal line is labeled VY
  • the common electrode far-end feedback line is labeled VF
  • the common electrode proximal signal line VJ is electrically connected to the first electrostatic discharge circuit ED1, and the first electrostatic discharge circuit ED1 is used to provide electrostatic protection for the common electrode proximal signal line VJ;
  • test line TL The label is test line TL.
  • the common electrode proximal signal line VJ, the common electrode distal signal line VY, the common electrode distal feedback line VF and the test line TL may all be formed in the gate metal layer, but the present invention is not limited thereto.
  • the common electrode remote end signal line VY is electrically connected to the remote end of the common electrode voltage line to provide a common electrode voltage to the remote end of the common electrode voltage line;
  • the common electrode proximal end signal line VJ is electrically connected to the proximal end of the common electrode voltage line, and is used to provide a common electrode voltage to the proximal end of the common electrode voltage line;
  • the common electrode remote feedback line VF is electrically connected to the remote end of the common electrode voltage line, and is used to receive a remote feedback signal of the common electrode voltage line;
  • the distal end of the common electrode voltage line is an end of the common electrode voltage line away from the first side;
  • the proximal end of the common electrode voltage line is an end of the common electrode voltage line close to the first side.
  • the test line TL is electrically connected to the output end of the last-stage driving circuit included in the driving module, and the test line TL is also electrically connected to a driving integrated circuit, which receives a signal from the test line TL to determine whether the driving signal provided by the output end of the last-stage driving circuit is accurate.
  • FIG3C is a partial enlarged schematic diagram of the first electrostatic discharge circuit ED1 in FIG3A .
  • the first electrostatic discharge circuit ED1 includes a plurality of electrostatic discharge sub-circuits, and the structures of the plurality of electrostatic discharge sub-circuits may be the same; but not limited thereto; in actual operation, the structures of at least two of the plurality of electrostatic discharge sub-circuits may also be different from each other;
  • the first electrostatic discharge sub-circuit ED11 may include a first protection transistor T1, a second protection transistor T2, a third protection transistor T3 and a fourth protection transistor T4; when the electrostatic discharge sub-circuit is used to perform electrostatic protection on the first clock signal line CK1,
  • the gate of the first protection transistor T1 and the first electrode of the first protection transistor T1 may both be electrically connected to the first clock signal line CK1, and the second electrode of the first protection transistor T1 is electrically connected to the second electrode of the second protection transistor T2;
  • the gate of the second protection transistor T2 is electrically connected to the second electrode of the second protection transistor T2; the first electrode of the second protection transistor T2 is electrically connected to the first clock signal line CK1;
  • the gate of the third protection transistor T3 and the first electrode of the third protection transistor T3 are both electrically connected to the gate of the second protection transistor T2;
  • the gate of the fourth protection transistor T4 is electrically connected to the second electrode of the fourth protection transistor T4, and the first electrode of the fourth protection transistor T4 is electrically connected to the gate of the second protection transistor T2;
  • the second electrode of the third protection transistor T3 and the second electrode of the fourth protection transistor T4 are both connected to the electrostatic ring SR Electrical connection.
  • the second electrode of the third protection transistor T3 and the second electrode of the fourth protection transistor T4 may also be replaced to be electrically connected to the common electrode voltage terminal;
  • the gate of the first protection transistor T1 and the first electrode of the first protection transistor T1 can be replaced by other clock signal lines, the first low voltage line VGL11, the second low voltage line LVGL, the frame reset line STV0, the second control voltage line VDDE, the first control voltage line VDDO or the start voltage line STV1, which is not limited here.
  • the array substrate includes a driving circuit area and a display area, and the driving module is arranged in the driving circuit area; the driving circuit area includes a line collection area;
  • the array substrate further includes a second first low voltage line arranged between the drive circuit area and the display area, and a cascade line arranged in the line collection area (the cascade line includes a carry signal line and a reset signal line, the carry signal line is used for the upper GOA circuit (Gate On Array, a gate drive circuit arranged on the array substrate) to provide a carry signal to the input module of the lower GOA circuit, and the reset signal line is used for the lower GOA circuit to provide a reset signal to the reset module of the upper GOA, and the reset signal can be, for example, a reset signal to the pull-up node or the output end of the GOA circuit);
  • the cascade line includes a carry signal line and a reset signal line
  • the carry signal line is used for the upper GOA circuit (Gate On Array, a gate drive circuit arranged on the array substrate) to provide a carry signal to the input module of the lower GOA circuit
  • the reset signal line is used for the lower GOA circuit to provide a reset signal to the reset module
  • the cascade line is a signal line used for cascading between the driving circuits of each level included in the driving module; the second first low voltage line is used to provide a first low voltage signal;
  • the orthographic projection of the virtual signal line on the substrate overlaps with the orthographic projection of the cascade line on the substrate;
  • An orthographic projection of the dummy signal line on the base substrate partially overlaps with an orthographic projection of the second first low voltage line on the base substrate.
  • a driving circuit included in a driving module is disposed in the driving circuit area 30 , and the area labeled J1 is a line collection area;
  • the array substrate further includes a second first low voltage line VGL21 disposed between the driving circuit area 30 and the display area;
  • the second first low voltage line VGL21 is used for providing a first low voltage signal.
  • the first first low voltage line VGL11 and the second first low voltage line VGL21 may be electrically connected to each other.
  • the peripheral area includes a virtual driving circuit area
  • the array substrate further includes a virtual driving module disposed in the virtual driving circuit area, and the virtual driving circuit area is disposed between the side area and the display area;
  • the virtual driving module includes a plurality of virtual driving circuits arranged along a first direction;
  • the virtual driving circuit includes a virtual driving output terminal and a virtual input terminal;
  • the virtual input terminal of the virtual driving circuit is disconnected from the virtual driving output terminal of the virtual driving circuit other than the virtual driving circuit included in the virtual driving module, that is, the virtual driving area is the area where the virtual driving circuit is set, and the cascade line in the line collection area does not cascade the GOA circuit included in the virtual driving module, presenting a disconnected state.
  • Setting the virtual driving circuit can achieve the same as the driving circuit for providing the gate signal to the second gate line of the display area. Stability of the preparation process.
  • the virtual driving circuit area is labeled XA, and the virtual driving circuit area is arranged between the side area and the display area;
  • the virtual driving module is labeled XZ, and the virtual driving module XZ includes a plurality of virtual driving circuits arranged in a horizontal direction;
  • the one labeled X1 is the first virtual driving circuit
  • the one labeled X2 is the second virtual driving circuit
  • the one labeled X3 is the third virtual driving circuit
  • the one labeled X4 is the fourth virtual driving circuit
  • the one labeled X5 is the fifth virtual driving circuit
  • the one labeled X6 is the sixth virtual driving circuit
  • the one labeled X7 is the seventh virtual driving circuit.
  • IP3 is a virtual input terminal of X3
  • OT3 is a virtual drive output terminal of X3 .
  • the virtual input terminal included in the virtual driving circuit is disconnected from the virtual driving output terminal included in the virtual driving module.
  • the array substrate further comprises a floating signal line disposed between adjacent dummy driving circuits, for maintaining etching uniformity in the manufacturing process;
  • the floating signal line is in a floating state.
  • the array substrate further includes a floating signal line in a floating state and arranged between adjacent dummy driving circuits.
  • the first floating signal line is labeled FL11 and includes a first floating signal line portion
  • the second floating signal line is labeled FL12 and includes a second floating signal line portion
  • the third floating signal line is labeled FL13 and includes a third floating signal line portion
  • the first floating signal line is disposed between the first dummy driving circuit X1 and the second dummy driving circuit X2.
  • a floating signal line is also provided on the left side of the first virtual driving circuit X1;
  • a cross-shaped alignment mark DB1 is disposed on the left side of the first virtual driving circuit X1 ; in order to save the frame, the alignment mark DB1 is designed close to the first virtual driving circuit X1 , thereby dividing the upper part of the floating signal line located in the line collection area into two parts.
  • the array substrate includes a peripheral area and a display area, the peripheral area includes a driving circuit area; the driving module is arranged in the driving circuit area;
  • the peripheral area further includes a common electrode wiring area arranged on a side of the driving circuit area away from the display area, and a second signal line area arranged between the common electrode wiring area and the driving circuit area;
  • the array substrate further comprises a common electrode wiring, a common electrode connecting wire and a common electrode arranged in the display area; the common electrode wiring is electrically connected to the common electrode through the common electrode connecting wire;
  • the common electrode wiring is located in the common electrode wiring area
  • the common electrode connection line passes through the second signal line area and the driving circuit area.
  • the array substrate further includes a plurality of clock signal lines arranged in the second signal line area, a first A control voltage line, a second control voltage line, a frame reset line and a second low voltage line.
  • the peripheral area includes a driving circuit area 30 , and the driving circuit included in the driving module is arranged in the driving circuit area 30 ;
  • the peripheral area further includes a common electrode wiring area VMA disposed on a side of the driving circuit area 30 away from the display area, and a second signal line area 71 disposed between the common electrode wiring area VMA and the driving circuit area 30;
  • the array substrate further includes common electrode wiring VML, common electrode connecting wires LX and common electrodes arranged in the display area;
  • the common electrode trace VML is electrically connected to the common electrode through the common electrode connection line LX;
  • the common electrode wiring VML is arranged in the common electrode wiring area VMA;
  • the common electrode connection line LX passes through the second signal line area 71 and the driving circuit area 30 , and then extends to the display area.
  • the common electrode trace VML may be formed in the gate metal layer, and the common electrode connection line LX may be formed in the source-drain metal layer, but not limited thereto, and the two may be electrically connected via an electrode layer deposited in a via hole in the insulating layer.
  • CK1 is the first clock signal line
  • CK2 is the second clock signal line
  • CK3 is the third clock signal line
  • CK4 is the fourth clock signal line
  • CK5 is the fifth clock signal line
  • CK6 is the sixth clock signal line
  • CK7 is the seventh clock signal line
  • CK8 is the eighth clock signal line.
  • the line labeled VDDO is a first control voltage line
  • the line labeled VDDE is a second control voltage line
  • the line labeled STV0 is a frame reset line
  • the line labeled LVGL is a second low voltage line.
  • the array substrate includes a peripheral area and a display area, the peripheral area includes a driving circuit area; the driving module is arranged in the driving circuit area;
  • the peripheral area further includes a second signal line area arranged on a side of the driving circuit area away from the display area;
  • the array substrate further comprises a plurality of clock signal lines arranged in the second signal line region; the clock signal lines extend along a first direction, and the plurality of clock signal lines are arranged along the second direction;
  • the clock signal connection line electrically connected to the clock signal line near the display area includes a winding portion relative to the clock signal connection line electrically connected to the clock signal line near the common electrode wiring area.
  • a first clock signal line CK1 , a second clock signal line CK2 , a third clock signal line CK3 , a fourth clock signal line CK4 , a fifth clock signal line CK5 , a sixth clock signal line CK6 , a seventh clock signal line CK7 and an eighth clock signal line CK8 are provided in the second signal line area 71 ;
  • Each of the clock signal lines extends in a horizontal direction, and each of the clock signal lines is arranged in a vertical direction;
  • the clock signal connection line electrically connected to the clock signal line near the display area is opposite to the clock signal line near the common electrode.
  • the clock signal connection lines electrically connected to the clock signal lines in the routing area include a winding portion to enable compensation so that the lengths of the connection lines between the clock signal lines and the drive circuits are approximately equal;
  • CK1 is the clock signal line closest to the common electrode routing area, and CK1 is electrically connected to the first clock signal connection line L1; the first clock signal connection line L1 does not have a winding portion; optionally, the clock signal line is arranged in the gate metal layer, and the connection line L1 is arranged in the source and drain metal layer, and the two can be electrically connected through the electrode layer deposited in the via hole of the insulating layer.
  • the connection line and the clock signal line overlap vertically to the substrate, and at the overlapping position, the clock signal line at least partially has a hollow portion to reduce the coupling capacitance between the connection line and the clock signal line.
  • CK8 is a clock signal line closest to the display area, CK8 is electrically connected to an eighth clock signal connection line, and the eighth clock signal connection line includes an eighth winding portion R8;
  • CK7 is a clock signal line second closest to the display area, CK7 is electrically connected to a seventh clock signal connection line, and the seventh clock signal connection line includes a seventh winding portion R7;
  • CK6 is a third clock signal line close to the display area, CK6 is electrically connected to a sixth clock signal connection line, and the sixth clock signal connection line includes a sixth winding portion R6;
  • CK5 is a fourth clock signal line close to the display area, CK5 is electrically connected to a fifth clock signal connection line, and the fifth clock signal connection line includes a fifth winding portion R5;
  • CK4 is a fifth clock signal line close to the display area, CK4 is electrically connected to a fourth clock signal connection line, and the fourth clock signal connection line includes a fourth winding portion R4;
  • CK3 is a sixth clock signal line close to the display area, CK3 is electrically connected to the third clock signal connection line, and the third clock signal connection line includes a third winding portion R3;
  • CK2 is a seventh clock signal line close to the display area, CK2 is electrically connected to a second clock signal connection line L2, and the second clock signal connection line includes a second winding portion R2;
  • the length of R8 is greater than that of R7, the length of R7 is greater than that of R6, the length of R6 is greater than that of R5, the length of R5 is greater than that of R4, the length of R4 is greater than that of R3, and the length of R3 is greater than that of R2.
  • the length of R8 is set to be greater than the length of R7
  • the length of R7 is set to be greater than the length of R6
  • the length of R6 is set to be greater than the length of R5
  • the length of R5 is set to be greater than the length of R4
  • the length of R4 is set to be greater than the length of R3
  • the length of R3 is set to be greater than the length of R2, so that the impedance of the connection between each clock signal line and the driving circuit is approximately the same to balance the impedance.
  • FIG. 11 is a schematic diagram of the side region 20 and the virtual driving circuit region XA in at least one embodiment of the present disclosure.
  • the virtual driving circuit area XA is disposed on a side of the side area 20 close to the display area.
  • the first low voltage line is labeled VGL11
  • the second low voltage line is labeled VGL21 .
  • VGL11 and VGL21 may be electrically connected via the conductive line on the left.
  • FIG. 12 is a schematic diagram of a driving circuit located on the left side and included in the array substrate in at least one embodiment of the present disclosure.
  • the third signal line region is labeled 121
  • the second electrostatic discharge region is labeled 122 .
  • the number 123 is the fourth signal line region
  • the number 71 is the second signal line region
  • the number 30 is the driving circuit region
  • the number 124 is the fifth signal line region.
  • the third signal line region 121 , the second electrostatic discharge region 122 , the fourth signal line region 123 , the second signal line region 71 , the driving circuit region 30 and the fifth signal line region 124 are sequentially arranged in a direction close to the display region.
  • a first data line formed in a gate metal layer is disposed in the third signal line region 121 ;
  • An electrostatic discharge circuit is provided in the second electrostatic discharge area 122, and the electrostatic discharge circuit is used to provide electrostatic protection for the data line;
  • a first data line formed in a source-drain metal layer is disposed in the fourth signal line region 123;
  • a clock signal line, a first control voltage line, a second control voltage line, and a second low voltage line formed in the gate metal layer are disposed in the second signal line region 71;
  • a plurality of driving circuits arranged in a horizontal direction are arranged in the driving circuit area 30, and a first data line formed in the source-drain metal layer passes between two adjacent driving circuits to extend toward the display area;
  • the fifth signal line region 124 is provided with a first data line formed in a source-drain metal layer.
  • the third signal line region 121 is also a fan-out region, and a binding pad may be provided in the fan-out region.
  • the binding pad is electrically connected to the source driver or to a binding region of the flexible circuit board.
  • FIG. 13 is a schematic diagram of a driving circuit located in the middle of an array substrate according to at least one embodiment of the present disclosure.
  • VMA is the common electrode wiring area
  • 123 is the fourth signal line area
  • 71 is the second signal line area
  • 30 is the driving circuit area
  • 123 is the fourth signal line area.
  • the common electrode wiring area VMA, the fourth signal line area 123 , the second signal line area 71 , the driving circuit area 30 and the fifth signal line area 124 are sequentially arranged in a direction close to the display area.
  • a mesh common electrode wiring formed in a gate metal layer is provided in the common electrode wiring area VMA;
  • the fourth signal line region 123 is provided with a first data line formed in the source-drain metal layer;
  • the second signal line region 71 is provided with a common electrode connection line formed in the source-drain metal layer and a first data line formed in the source-drain metal layer;
  • a plurality of driving circuits arranged in a horizontal direction are arranged in the driving circuit area 30, and a first data line and a common electrode connection line formed in the source-drain metal layer pass between two adjacent driving circuits to extend toward the display area;
  • the fifth signal line region 124 is provided with a first data line formed in a source-drain metal layer.
  • reference numeral 130 indicates a display area, in which a common electrode VMP is disposed.
  • the common electrode VMP may be electrically connected to a common electrode wiring.
  • FIG. 14 is a schematic diagram of a driving circuit located on the right side and included in the array substrate according to at least one embodiment of the present disclosure.
  • the third signal line region is labeled 121
  • the second electrostatic discharge region is labeled 122 .
  • the number 123 is the fourth signal line region
  • the number 71 is the second signal line region
  • the number 30 is the driving circuit region
  • the number 124 is the fifth signal line region.
  • the third signal line region 121 , the second electrostatic discharge region 122 , the fourth signal line region 123 , the second signal line region 71 , the driving circuit region 30 and the fifth signal line region 124 are sequentially arranged in a direction close to the display region.
  • a first data line formed in a gate metal layer is disposed in the third signal line region 121 ;
  • An electrostatic discharge circuit is provided in the second electrostatic discharge area 122, and the electrostatic discharge circuit is used to provide electrostatic protection for the data line;
  • a first data line formed in a source-drain metal layer is disposed in the fourth signal line region 123;
  • a clock signal line, a first control voltage line, a second control voltage line, and a second low voltage line formed in the gate metal layer are disposed in the second signal line region 71;
  • a plurality of driving circuits arranged in a horizontal direction are arranged in the driving circuit area 30, and a first data line formed in the source-drain metal layer passes between two adjacent driving circuits to extend toward the display area;
  • the fifth signal line region 124 is provided with a first data line formed in a source-drain metal layer.
  • the third signal line region 121 is also a fan-out region, and a bonding pad may be provided in the fan-out region, and the bonding pad is electrically connected to the source driver.
  • FIG. 15 is a structural diagram of at least one embodiment of a driving circuit in an array substrate described in the present disclosure.
  • the driving circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19 and
  • the first capacitor C1 the connection relationship of the transistors of the GOA circuit in this case is shown in FIG15, for example, the gate of the third transistor M3 is electrically connected to the pull-up node, the first electrode of the third transistor M3 is electrically connected to the clock signal line CK, the second electrode of the third transistor M3 is electrically connected to the drive signal output terminal O1, the gate of the seventh transistor M7
  • labeled I1 is the input terminal
  • labeled STV0 is the frame reset line (used to reset the GOA circuit before one frame)
  • labeled R1 is the first reset terminal (the first reset terminal R1 of the upper GOA circuit can be electrically connected to the drive signal output terminal O1 of the lower GOA circuit)
  • labeled PU is the pull-up node
  • labeled PD1 is the first pull-down node
  • labeled PD2 is the second pull-down node
  • labeled VDDO is the first control voltage line
  • labeled VDDE is the second control voltage line
  • labeled CK is the clock signal line
  • labeled VGL21 is the second first low voltage line
  • labeled O1 is the drive signal output terminal
  • labeled RST is the second reset terminal.
  • the second first low voltage line VGL21 and the first first low voltage line The VGLs 11 may be electrically connected to each other.
  • FIG16A is a schematic diagram showing the addition of labels for transistors and capacitors in the driving circuit based on FIG14 .
  • the second first voltage line is labeled VGL21
  • the second first voltage line VGL21 is disposed on a side of the fourth transistor M4 close to the display area.
  • FIG16B is a partial enlarged view of the first part of the driving circuit from top to bottom;
  • FIG16C is a partial enlarged view of the second portion of the driving circuit from top to bottom;
  • FIG16D is a partial enlarged view of the third portion from top to bottom of the driving circuit
  • FIG16E is a partial enlarged view of the fourth portion from top to bottom of the driving circuit.
  • FIG. 16F is a partial enlarged view of FIG. 16A .
  • the signal line electrically connected to the gate of the seventh transistor M7 and a signal line located above M7 are both the frame reset line STV0 ;
  • the frame reset line STV0 may be formed in a gate metal layer
  • the signal line electrically connected to the gate of the seventh transistor M7 and the signal line located above M7 may be electrically connected to a connection line LX disposed on the source-drain metal layer, and there may be a plurality of connection lines LX.
  • the first gate line and the second data line intersect to define a sub-pixel region, and the sub-pixel region includes a sub-electrode;
  • the length of the sub-electrode included in the sub-pixel region farthest from the driving module along the second direction is shorter than the first length
  • the first length is the shortest length of the sub-electrodes included in the sub-pixel regions except the sub-pixel region farthest from the driving module along the second direction.
  • the first gate line and the second data line intersect to define a sub-pixel area.
  • the sub-pixel driver may include a pixel electrode and a common electrode.
  • the common electrode is an integral electrode, and the pixel electrode is separate.
  • the length of the sub-electrode included in the sub-pixel area farthest from the driving module along the vertical direction is smaller than the length of other pixel circuits along the vertical direction.
  • an AT (Array Test) component can be set to enable normal AT detection while achieving an ultra-narrow border.
  • this design can also be used on borderless screens and can be mass-produced.
  • the sub-electrode may include a common electrode and a pixel electrode, and the common electrode and the pixel electrode are both dual-domain structures, and the dual-domain structure includes an upper domain structure and a lower domain structure electrically connected to each other, and the extension direction of the upper domain structure is different from the extension direction of the lower domain structure.
  • Reducing the length of the sub-electrode included in the sub-pixel area farthest from the driving module along the second direction can be achieved in the following three ways: reducing the length of the upper domain structure along the second direction, reducing the length of the lower domain structure along the second direction, or reducing the length of the upper domain structure along the second direction and the length of the lower domain structure along the second direction.
  • the pixel electrode and the common electrode are arranged in the same layer, and are arranged alternately in a comb-tooth shape, and the pixel electrode includes a plurality of branch electrode portions, and the end of the branch electrode includes a widening portion, and the design of the widening portion can improve the problem of darkening of the edge area of the pixel.
  • the black matrix can be used to block part of the luminous area of the sub-pixel area farthest from the driving module, and the blocked part cannot see the picture.
  • At least one embodiment of the present disclosure directly removes part of the luminous area, which is equivalent to the row of pixels farthest from the driving module being 2/3 of the height of normal pixels, so that the saved space can be used for other designs.
  • the length of the common electrode VM included in the sub-pixel region closer to the driving module along the vertical direction, and the length of the pixel electrode PX included in the sub-pixel region closer to the driving module along the vertical direction are larger;
  • the vertical length of the common electrode VM included in the sub-pixel region farthest from the driving module and the vertical length of the pixel electrode PX included in the sub-pixel region farthest from the driving module are relatively small.
  • space is saved by reducing the length of the lower domain structure included in the common electrode along the vertical direction and reducing the length of the lower domain structure included in the pixel electrode along the vertical direction.
  • the common electrode and the pixel circuit may both be formed on an ITO (indium tin oxide) layer, but the present invention is not limited thereto.
  • the array substrate includes a display area and a peripheral area
  • the peripheral area includes a first virtual pattern area arranged on a first side of the display area and/or a second virtual pattern area arranged on a fourth side of the display area; the first side and the fourth side are opposite sides;
  • the array substrate comprises a first virtual pattern array arranged in the first virtual pattern area, and/or a second virtual pattern array arranged in the second virtual pattern area;
  • the first virtual pattern array includes a plurality of first virtual patterns arranged in an array
  • the second virtual pattern array includes a plurality of second virtual patterns arranged in an array; the first virtual pattern is used to support the frame sealing glue, and the second virtual pattern is used to support the frame sealing glue.
  • the first side may be a left side
  • the second side may be a right side, but the present invention is not limited thereto.
  • At least one embodiment of the present disclosure sets a virtual pattern area on the first side of the display area and/or the second side of the display area, and a virtual pattern array is set in the virtual pattern area, and the virtual pattern array includes a plurality of virtual patterns arranged in an array for supporting the frame sealant to improve the peripheral yellowing phenomenon.
  • the first dummy pattern may be formed in a gate metal layer or a source-drain metal layer
  • the second dummy pattern may be formed in a gate metal layer or a source-drain metal layer.
  • the area labeled A1 is the display area
  • the one labeled BD1 is the first boundary, and the one labeled BD2 is the second boundary;
  • the display area A1 is disposed on a side of the first boundary BD1 away from the second boundary BD2;
  • the first virtual pattern area PT1 is arranged on the left side of the display area A1, and the array substrate includes a first virtual pattern array arranged in the first virtual pattern area PT1;
  • the first dummy pattern array includes a plurality of first dummy patterns TX1 arranged in an array
  • the first dummy pattern TX1 is used to support the frame sealing glue.
  • the first dummy pattern array may be formed in a gate metal layer, and the first dummy pattern TX1 is a rectangular dummy pattern.
  • the mark DW1 is a first alignment mark
  • the mark DW2 is a second alignment mark.
  • the first alignment mark DW1 and the second alignment mark DW2 may both be formed in the gate metal layer, and DW1 and DW2 may be used to align the cutting line.
  • the first virtual pattern may also be a field-shaped virtual pattern or an eight-shaped virtual pattern, but is not limited thereto.
  • the array substrate includes a peripheral area; the peripheral area includes a binding area; the array substrate includes a binding pad disposed in the binding area;
  • the binding pad is electrically connected to the first data line, and the binding pad is electrically connected to the conductive connection pattern through a via hole, and the edge of the via hole is serrated.
  • the peripheral area includes a binding area
  • the array substrate includes a binding pad
  • the binding pad is arranged in the binding area
  • the pad of the flexible circuit board is electrically connected to the binding pad through a conductive connection pattern.
  • the conductive connection pattern can be formed in the ITO layer, but is not limited to this.
  • the binding pad can be formed on the gate metal layer, and the binding pad is electrically connected to the conductive connection pattern.
  • the conductive connection pattern can be electrically connected to the pad of the flexible circuit board through a via that penetrates the organic film layer.
  • the binding area needs to be crimped using a tool, so there is a risk of the edge of the via being crushed. Therefore, at least one embodiment of the present disclosure sets the edge of the via to a serrated shape to share the pressure caused by the sudden change of the via edge and prevent the via edge from being crushed.
  • the via can be used in borderless screen display products.
  • Fig. 20 is a top view of a via area AG occupied by a via hole passing through an organic film layer. As shown in Fig. 20, the edge of the via area AG is zigzag-shaped.
  • H1 is a via hole
  • 200 is a substrate
  • 201 is a gate metal layer
  • 202 is a gate insulating layer
  • 203 is a passivation layer
  • 204 is an organic film layer
  • L1 is a conductive connection pattern
  • the via hole H1 is a via hole that penetrates the passivation layer 202, the gate insulating layer 203 and the organic film layer 204.
  • the bonding pad and the first data line are formed on the gate metal layer 201.
  • the conductive connection pattern LD1 is formed on the ITO layer.
  • the electrical connection pattern LD1 is electrically connected to the source driver through the via H1.
  • the via region is labeled AG, and the edge of the via region AG is jagged.
  • FIG. 23 is a layout diagram of the gate metal layer in FIG. 22 . As shown in FIG. 23 , the one labeled HB is a binding pad, and the one labeled DL1 is a first data line.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned array substrate.

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Abstract

本公开提供一种阵列基板和显示装置。阵列基板包括衬底基板和设置于衬底基板上的第一数据线、虚拟信号线和驱动模组，所述驱动模组包括多级驱动电路；所述多级驱动电路沿所述第一方向排布；所述驱动电路用于提供驱动信号；在至少两个相邻的驱动电路之间设置有所述第一数据线，所述第一数据线用于提供数据电压；在至少两个相邻的驱动电路之间还设置有虚拟信号线；所述虚拟信号线处于浮空状态。本公开实施例通过设置所述虚拟信号线，可以保证刻蚀均一性。

Description

阵列基板和显示装置
相关申请的交叉引用
本申请主张在2023年5月26日在中国提交的中国专利申请号No.202310610233.2的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板和显示装置。
背景技术
显示面板的品质提升是一个持续的话题，超窄边框显示面板越来越多的应用，在相关技术中，为了实现窄边框，可以将包括多级驱动电路的驱动模组设置于阵列基板的上侧边或下侧边。
发明内容
在一个方面中，本公开实施例提供了一种阵列基板，包括衬底基板和设置于衬底基板上的第一数据线、虚拟信号线和驱动模组，所述第一数据线、所述虚拟信号线和所述驱动模组设置于所述阵列基板的周边区域，所述周边区域至少部分围绕显示区域，所述显示区域包括沿第一方向延伸的第一栅线和沿第二方向延伸的第二数据线，所述第一数据线和所述第二数据线电连接，所述第一方向和所述第二方向相交；
所述驱动模组设置于所述阵列基板的第一侧边；所述第一侧边为设置于所述第二数据线延伸方向的侧边；
所述驱动模组包括多级驱动电路；所述多级驱动电路沿所述第一方向排布；所述驱动电路用于提供驱动信号；
在至少两个相邻的驱动电路之间设置有所述第一数据线，所述第一数据线用于提供数据电压；
在至少两个相邻的驱动电路之间还设置有所述虚拟信号线；所述虚拟信号线处于浮空状态。
可选的，所述第一数据线和所述虚拟信号线形成于同一导电层。
可选的，至少一所述虚拟信号线设置于相邻的两个所述第一数据线之间；
所述虚拟信号线沿所述第二方向延伸。
可选的，所述周边区域包括驱动电路区域和侧边区域；所述驱动模组设置于所述驱动电路区域；
所述侧边区域设置于所述驱动电路区域排布方向的相对的两侧；
所述侧边区域包括第一信号线区域和第一静电释放区域；所述阵列基板还包括设置于 所述第一信号线区域的多条时钟信号线，以及，设置于所述第一静电释放区域的第一静电释放电路；
所述第一静电释放电路与所述时钟信号线电连接，用于对所述时钟信号线进行静电防护。
可选的，所述阵列基板还包括设置于所述第一信号线区域的第一条第一低电压线、第二低电压线、帧复位线、第一控制电压线、第二控制电压线和起始电压线；
所述第一静电释放电路还分别与所述第一条第一低电压线、所述第二低电压线、所述帧复位线、所述第一控制电压线、所述第二控制电压线和所述起始电压线电连接，用于对所述第一条第一低电压线、所述第二低电压线、所述帧复位线、所述第一控制电压线、所述第二控制电压线和所述起始电压线进行静电防护；
所述第一条第一低电压线用于提供第一低电压信号，所述帧复位线用于提供帧复位信号，所述第一控制电压线用于提供第一控制电压，所述第二控制电压线用于提供第二控制电压，所述起始电压线用于提供起始电压。
可选的，所述时钟信号线、所述第二低电压线、所述帧复位线、所述第一控制电压线和所述第二控制电压线设置于所述第一静电释放电路的第一侧、第二侧和第三侧；所述第一条第一低电压线设置于所述第一静电释放电路的第一侧和第二侧；所述起始电压线设置于所述第一静电释放电路的第四侧；
所述第一侧与所述第四侧为相对的两侧，所述第二侧和所述第三侧为相对的两侧。
可选的，所述阵列基板包括驱动电路区域和显示区域，所述驱动模组设置于所述驱动电路区域；所述驱动电路区域包括集线区域；
所述阵列基板还包括设置于在所述驱动电路区域与所述显示区域之间的第二条第一低电压线，以及，设置于所述集线区域的级联线；
所述级联线为所述驱动模组包括的各级驱动电路之间的用于级联的信号线；所述第二条第一低电压线用于提供第一低电压信号；
所述虚拟信号线在所述衬底基板上的正投影与所述级联线在所述衬底基板上的正投影部分交叠；
所述虚拟信号线在所述衬底基板上的正投影与所述第二条第一低电压线在所述衬底基板上的正投影部分交叠。
可选的，所述周边区域包括虚拟驱动电路区域；所述阵列基板包括设置于虚拟驱动电路区域的虚拟驱动模组，所述虚拟驱动电路区域设置于所述侧边区域与所述显示区域之间；
所述虚拟驱动模组包括沿第一方向排列的多个虚拟驱动电路；
所述虚拟驱动电路包括虚拟驱动输出端和虚拟输入端；
所述虚拟驱动电路的虚拟输入端与所述虚拟驱动模组包括的除了该虚拟驱动电路之外的虚拟驱动电路的虚拟驱动输出端之间断开。
可选的，所述阵列基板还包括设置于相邻的所述虚拟驱动电路之间的浮空信号线；
所述浮空信号线处于浮空状态。
可选的，所述阵列基板包括周边区域和显示区域，所述周边区域包括驱动电路区域；所述驱动模组设置于所述驱动电路区域；
所述周边区域还包括设置于所述驱动电路区域远离所述显示区域的一侧的公共电极走线区域，以及，设置于所述公共电极走线区域和所述驱动电路区域之间的第二信号线区域；
所述阵列基板还包括公共电极走线、公共电极连接线和设置于显示区域的公共电极；所述公共电极走线通过所述公共电极连接线与所述公共电极电连接；
所述公共电极走线位于所述公共电极走线区域；
所述公共电极连接线贯穿所述第二信号线区域和所述驱动电路区域。
可选的，所述阵列基板还包括设置于所述第二信号线区域中的多条时钟信号线、第一控制电压线、第二控制电压线、帧复位线和第二低电压线。
可选的，所述阵列基板包括周边区域和显示区域，所述周边区域包括驱动电路区域；所述驱动模组设置于所述驱动电路区域；
所述周边区域还包括设置于所述驱动电路区域远离所述显示区域的一侧的第二信号线区域；
所述阵列基板还包括设置于所述第二信号线区域的多条时钟信号线；所述时钟信号线沿第一方向延伸，所述多条时钟信号线沿所述第二方向排列；
与靠近所述显示区域一侧的时钟信号线电连接的时钟信号连接线，相对于与靠近所述公共电极走线区域的时钟信号线电连接的时钟信号连接线，包括绕线部。
可选的，所述第一栅线和所述第二数据线交叉限定子像素区域，所述子像素区域包括子电极；
距离所述驱动模组最远的子像素区域包括的子电极沿所述第二方向的长度小于第一长度；
所述第一长度为除了距离所述驱动模组最远的子像素区域之外的子像素区域包括的子电极沿第二方向的最短长度。
可选的，所述阵列基板包括显示区域和周边区域；
所述周边区域包括设置于所述显示区域的第一侧的第一虚拟图案区域和/或设置于所述显示区域的第四侧的第二虚拟图案区域；所述第一侧和所述第四侧为相对的两侧；
所述阵列基板包括设置于所述第一虚拟图案区域的第一虚拟图案阵列，和/或，设置于所述第二虚拟图案区域的第二虚拟图案阵列；
所述第一虚拟图案阵列包括阵列设置的多个第一虚拟图案，所述第二虚拟图案阵列包括阵列设置的多个第二虚拟图案；所述第一虚拟图案用于支撑封框胶，所述第二虚拟图案用于支撑封框胶。
可选的，所述阵列基板包括周边区域；所述周边区域包括绑定区域；所述阵列基板包 括设置于所述绑定区域的绑定焊盘；
所述绑定焊盘与所述第一数据线电连接，所述绑定焊盘与导电连接图形通过过孔电连接，所述过孔的边缘为锯齿状。
可选的，本公开至少一实施例所述的阵列基板还包括沿第二方向延伸的第二栅线；
所述第一栅线与所述第二栅线电连接，所述第二栅线与所述驱动模组电连接。
可选的，所述第一栅线和所述第二数据线交叉限定子像素区域；
相邻的驱动电路之间的第一数据线的数量大于或等于m/(n+2)而小于或等于m/(n-1)；
n为所述第一栅线的数量，m为所述子像素区域对应的第二数据线的数量，m和n为正整数。
可选的，所述虚拟信号线的数量小于所述第一数据线的数量。
在第二个方面中，本公开实施例提供一种显示装置，包括上述的阵列基板。
附图说明
图1是本公开所述的阵列基板包括的两个驱动电路及设置于所述两个驱动电路之间的信号线的布局图；
图2A是本公开至少一实施例所述的阵列基板的结构图；
图2B是本公开至少一实施例所述的阵列基板的结构图；
图2C是本公开至少一实施例所述的阵列基板的结构图；
图3A和图3B是本公开至少一实施例所述的阵列基板包括的侧边区域的结构图；
图3C是图3A中的第一静电释放电路ED1部分局部放大示意图；
图3D是第一静电释放子电路的至少一实施例的电路图；
图4是本公开至少一实施例所述的阵列基板包括的驱动电路区域30的布局图；
图5是本公开至少一实施例所述的阵列基板包括的虚拟驱动电路区域XA的布局图；
图6是本公开至少一实施例所述的阵列基板包括的虚拟驱动电路区域XA的布局图；
图7是本公开至少一实施例所述的阵列基板包括的虚拟驱动电路区域XA的布局图；
图8是本公开至少一实施例所述的阵列基板包括的驱动电路区域30、第二信号线区域71和公共电极走线区域VMA的布局图；
图9和图10是本公开至少一实施例所述的阵列基板包括的位于中间的驱动电路的示意图；
图11是在本公开至少一实施例中，侧边区域20和虚拟驱动电路区域XA的示意图；
图12是本公开至少一实施例中，阵列基板包括的位于左侧的驱动电路的示意图；
图13是本公开至少一实施例所述的阵列基板包括的位于中间的驱动电路的示意图；
图14是本公开至少一实施例所述的阵列基板包括的位于右侧的驱动电路的示意图；
图15是本公开所述的阵列基板中的驱动电路的至少一实施例的结构图；
图16A是在图14的基础上增设对驱动电路中的各晶体管和电容的标示的示意图；
图16B为所述驱动电路的从上至下第一部分的局部放大图；
图16C为所述驱动电路的从上至下第二部分的局部放大图；
图16D为所述驱动电路的从上至下第三部分的局部放大图；
图16E为所述驱动电路的从上至下第四部分的局部放大图。
图16F是图16A中的局部放大图；
图17是距离所述驱动模组较近的子像素区域包括的公共电极VM和距离所述驱动模组较近的子像素区域该子像素区域包括的像素电极PX的示意图；
图18是距离所述驱动模组最远的子像素区域包括的公共电极VM，以及，距离所述驱动模组最远的子像素区域包括的像素电极PX的示意图；
图19是本公开所述的阵列基板包括的虚拟图案区域的布局图；
图20是穿过有机膜层的过孔占用的过孔区域AG的俯视图；
图21是本公开所述的阵列基板中的过孔的截面图；
图22是过孔区域AG的俯视图；
图23是图22中的栅金属层的布局图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的阵列基板包括衬底基板和设置于衬底基板上的第一数据线、虚拟信号线和驱动模组，所述第一数据线、所述虚拟信号线和所述驱动模组设置于所述阵列基板的周边区域，所述周边区域至少部分围绕显示区域，所述显示区域包括沿第一方向延伸的第一栅线和沿第二方向延伸的第二数据线，所述第一数据线和所述第二数据线电连接，所述第一方向和所述第二方向相交；
所述驱动模组设置于所述阵列基板的第一侧边；所述第一侧边为设置于所述第二数据线延伸方向的侧边；
所述驱动模组包括多级驱动电路；所述多级驱动电路沿所述第一方向排布；所述驱动电路用于提供驱动信号；
在至少两个相邻的驱动电路之间设置有所述第一数据线，所述第一数据线用于提供数 据电压；
在至少两个相邻的驱动电路之间还设置有所述虚拟信号线；所述虚拟信号线处于浮空状态。
在具体实施时，在阵列基板的周边区域，设置有第一数据线、虚拟信号线和驱动模组，在至少两个相邻的驱动电路之间设置有第一数据线和虚拟信号线，所述虚拟信号线处于浮空状态，本公开实施例通过设置所述虚拟信号线，可以保证刻蚀均一性。
在本公开至少一实施例中，所述第一方向可以为水平方向，所述第二方向可以为竖直方向，但不以此为限。
在本公开至少一实施例中，所述第一侧边可以为设置于所述第二数据线延伸方向的侧边；例如，当，所述第二数据线的延伸方向为竖直方向时，所述第一侧边可以为上侧边/或下侧边。
可选的，所述第一数据线和所述虚拟信号线形成于同一导电层。
在具体实施时，所述第一数据线和所述虚拟信号线可以形成于同一导电层；例如，所述第一数据线和所述虚拟信号线可以都形成于源漏金属层，但不以此为限。
在本公开至少一实施例中，至少一所述虚拟信号线设置于相邻的两个所述第一数据线之间；
所述虚拟信号线沿所述第二方向延伸。
在具体实施时，所述虚拟信号线可以设置于相邻的第一数据线之间，所述虚拟信号线可以沿第二方向延伸。
如图1所示，标号为GA1的为第一驱动电路，标号为GA2的为第二驱动电路；
在第一驱动电路GA1和第二驱动电路GA2之间设置有第一条第一数据线DL11、第二条第一数据线DL21、第三条第一数据线DL31、第一虚拟信号线XL1和第二虚拟信号线XL2；
第一条第一数据线DL11、第二条第一数据线DL21、第三条第一数据线DL31、第一虚拟信号线XL1和第二虚拟信号线XL2沿竖直方向延伸；
第一虚拟信号线XL1设置于第一条第一数据线DL11和第二条第一数据线DL21之间；
第一条第一数据线DL11、第二条第一数据线DL21、第三条第一数据线DL31、第一虚拟信号线XL1和第二虚拟信号线XL2都形成于源漏金属层。
本公开至少一实施例所述的阵列基板的显示区域还包括沿第二方向延伸的第二栅线；
所述第一栅线与所述第二栅线电连接，第一栅线和第二栅线不同层设置，可选的，第一栅线可以设置于栅金属层(gate层)，第二栅线和显示区域的第二数据线同层，即设置在源漏金属层(SD层)，第一栅线和第二栅线通过贯穿绝缘层的过孔实现电连接，所述第二栅线与所述驱动模组电连接。
如图2A所示，所述阵列基板可以包括第一条第一栅线GL11、第二条第一栅线GL21、第三条第一栅线GL31、第A-2条第一栅线GL41、第A-1条第一栅线GL51、第A条第一 栅线GL61、第一条第二栅线GL12、第二条第二栅线GL22、第三条第二栅线GL32、第B-2条第二栅线GL42、第B-1条第二栅线GL52和第B条第二栅线GL62；
第一条第一栅线GL11、第二条第一栅线GL21、第三条第一栅线GL31、第A-2条第一栅线GL41、第A-1条第一栅线GL51和第A条第一栅线GL61都沿水平方向延伸；
第一条第二栅线GL12、第二条第二栅线GL22、第三条第二栅线GL32、第D-1条第二栅线GL42、第D条第二栅线GL52、第B-2条第二栅线GL62、第B-1条第二栅线GL72和第B条第二栅线GL82都沿竖直方向延伸；
A为大于5的整数，D为大于4的整数，B为大于7的整数。
在图2A中，标号为DL12的为第一条第二数据线，标号为DL22的为第二条第二数据线，标号为DL32的为第三条第二数据线，标号为DL42的为第C-2条第二数据线，标号为DL52的为第C-1条第二数据线，标号为DL62的为第C条第二数据线；C为大于5的整数。
在图2A、图2B和图2C中，标号为Z0的为阵列基板。
如图2A所示，DL12、DL22、DL32、DL42、DL52和DL62都沿竖直方向延伸；
各第二数据线、各第一栅线和各第二栅线都设置于显示区域A1。
在图2B中，标号为B1的为第一侧边，驱动模组M0设置于第一侧边B1；
第一侧边B1为设置于各第二数据线延伸方向的侧边。
如图2A所示，所述驱动模组M0分别与GL12、GL22、GL32、GL42、GL52、GL62、GL72和GL82电连接，用于分别为GL12、GL22、GL32、GL42、GL52、GL62、GL72和GL82提供相应的驱动信号；
各第一栅线与各第二栅线之间相互电连接；
DL12、DL22、DL32、DL42、DL52和DL62都与源极驱动器S0电连接，接收来自所述源极驱动器S0的相应的数据电压。
本案中，可选的，在显示区域的第一栅线和第二数据线交叉限定子像素区域，第二栅线和第二数据线可以设置在相邻的子像素区域之间的位置，或者与子像素区域在垂直于衬底基板的方向上有部分交叠，在此不限定。
在图2C中，标号为A1的为显示区域，标号为Z1的为周边区域，周边区域Z1围绕显示区域A1设置。
在具体实施时，在所述第一侧边可以设置有绑定焊盘，所述源极驱动器S0可以通过所述绑定焊盘与各数据线电连接，或者，绑定焊盘可与柔性电路板电连接，源极驱动器设置在柔性电路板上，进而第二数据线提供数据信号。
可选的，所述第一栅线和所述第二数据线交叉限定子像素区域；
相邻的驱动电路之间的第一数据线的数量大于或等于m/(n+2)而小于或等于m/(n-1)；
n为所述第一栅线的数量，m为所述子像素区域对应的第二数据线的数量；
m和n为正整数。
在本公开至少一实施例中，所述虚拟信号线的数量小于所述第一数据线的数量，以能够在保证刻蚀均一性的前提下实现窄边框。
可选的，所述第一数据线的数量可以为3，所述虚拟信号线的数量可以为2，但不以此为限。
在本公开至少一实施例中，所述周边区域包括驱动电路区域和侧边区域；所述驱动模组设置于所述驱动电路区域；
所述侧边区域设置于所述驱动电路区域排布方向的相对的两侧，即侧边区域设置在第一方向延伸的相对两侧；
所述侧边区域包括第一信号线区域和第一静电释放区域；所述阵列基板还包括设置于所述第一信号线区域的多条时钟信号线，以及，设置于所述第一静电释放区域的第一静电释放电路；
所述第一静电释放电路与所述时钟信号线电连接，用于对所述时钟信号线进行静电防护。
在图3B中，标号为20的为侧边区域；
侧边区域20包括第一信号线区域21和第一静电释放区域22；
在所述第一信号线区域21中设置有多条信号线，如图3A所示，在所述第一静电释放区域22设置有第一静电释放电路ED1。
在图3A中，标号为CK1的为第一时钟信号线，标号为CK2的为第二时钟信号线，标号为CK3的为第三时钟信号线，标号为CK4的为第四时钟信号线，标号为CK5的为第五时钟信号线，标号为CK6的为第六时钟信号线，标号为CK7的为第七时钟信号线，标号为CK8的为第八时钟信号线(以8条时钟信号线示例，但不限于此)；
标号为VGL11的为第一条第一低电压线，标号为LVGL的为第二低电压线，标号为STV0的为帧复位线，标号为VDDE的为第二控制电压线，标号为VDDO的为第一控制电压线，标号为STV1的为起始电压线。
在图3A所示的至少一实施例中，各时钟信号线、第一条第一低电压线VGL11、第二低电压线LVGL，帧复位线STV0、第一控制电压线VDDO、第二控制电压线VDDE和起始电压线STV1可以形成于栅金属层，这些信号线可以通过跨线和第一静电释放电路实现电连接，跨线可以是与显示区域的像素电极或者公共电极同层的电极层，例如是ITO(氧化铟锡)层，但不以此为限。
在本公开至少一实施例中，所述阵列基板还包括设置于所述第一信号线区域的第一条第一低电压线、第二低电压线、帧复位线、第一控制电压线、第二控制电压线和起始电压线；
所述第一静电释放电路还分别与所述第一条第一低电压线、所述第二低电压线、所述帧复位线、所述第一控制电压线、所述第二控制电压线和所述起始电压线电连接，用于对所述第一条第一低电压线、所述第二低电压线、所述帧复位线、所述第一控制电压线、所 述第二控制电压线和所述起始电压线进行静电防护；
所述第一条第一低电压线用于提供第一低电压信号，所述帧复位线用于提供帧复位信号，所述第一控制电压线用于提供第一控制电压，所述第二控制电压线用于提供第二控制电压，所述起始电压线用于给栅极驱动电路提供起始电压。
如图3A所示，第一静电释放电路ED1分别与第一条第一低电压线VGL11、第二低电压线LVGL、帧复位线STV0、第二控制电压线VDDE、第一控制电压线VDDO和起始电压线STV1电连接，用于对第一条第一低电压线VGL、第二低电压线LVGL、帧复位线STV0、第二控制电压线VDDE、第一控制电压线VDDO和起始电压线STV1进行静电防护。
第一条第一低电压线VGL11用于提供第一低电压信号，所述帧复位线STV0用于提供帧复位信号，第二控制电压线VDDE用于提供第二控制电压，第一控制电压线VDDO用于提供第一控制电压，所述起始电压线STV1用于提供起始电压。
在本公开至少一实施例中，所述时钟信号线、所述第二低电压线、所述帧复位线、所述第一控制电压线和所述第二控制电压线设置于所述第一静电释放电路的第一侧、第二侧和第三侧；所述第一条第一低电压线设置于所述第一静电释放电路的第一侧和第二侧；所述起始电压线设置于所述第一静电释放电路的第四侧；
所述第一侧与所述第四侧为相对的两侧，所述第二侧和所述第三侧为相对的两侧。
可选的，第一侧可以为左侧，第二侧可以为上侧，第三侧可以为下侧，第四侧可以为右侧，但不以此为限。
如图3A所示，各时钟信号线可以设置于第一静电释放电路ED1的左侧、上侧和下侧，第一条第一低电压线VGL11可以设置于所述第一静电释放电路ED1的左侧和上侧；起始电压线STV1可以设置于所述第一静电释放电路的右侧；
所述第二低电压线LVGL、所述帧复位线STV0、所述第一控制电压线VDDO和所述第二控制电压线VDDE设置于所述第一静电释放电路ED1的左侧、上侧和下侧。继续参考图3A，本案中，时钟信号线和第一静电释放电路通过跨线实现电连接，跨线均沿着第一方向延伸，即时钟信号线在第一静电释放电路左侧的部分通过跨接线实现和第一静电释放电路的电连接，其他信号线(包括所述第二低电压线LVGL、所述帧复位线STV0、所述第一控制电压线VDDO和所述第二控制电压线VDDE)通过跨线实现和第一静电释放电路电连接，宽线沿着第二方向延伸，即其他信号线在第一静电释放电路上侧的部分通过跨接线实现和第一静电释放电路的电连接，另外起始电压线STV1和第一静电释放电路通过跨线实现电连接，跨线沿着第一方向延伸，即起始电压线STV1在第一静电释放电路右侧的部分通过跨接线实现和第一静电释放电路的电连接，本案中通过包含着三部分信号线分别从左侧，上侧和右侧引出跨线实现和第一静电释放电路的电连接，使得第一静电释放电路在信号线包围的范围内设置，可以减小第一静电释放电路占据的空间，进而进一步实现窄边框的效果。
在图3A中，标号为VJ的为公共电极近端信号线，标号为VY的为公共电极远端信号线，标号为VF的为公共电极远端反馈线；
公共电极近端信号线VJ与所述第一静电释放电路ED1电连接，所述第一静电释放电路ED1用于为所述公共电极近端信号线VJ进行静电防护；
标号为测试线TL。
在图3A所示的至少一实施例中，公共电极近端信号线VJ、公共电极远端信号线VY、公共电极远端反馈线VF和测试线TL可以都形成于栅金属层，但不以此为限。
在图3A所示的至少一实施例中，公共电极远端信号线VY与公共电极电压线的远端电连接，用于为公共电极电压线的远端提供公共电极电压；
公共电极近端信号线VJ与公共电极电压线的近端电连接，用于为公共电极电压线的近端提供公共电极电压；
公共电极远端反馈线VF与公共电极电压线的远端电连接，用于接收所述公共电极电压线的远端反馈的信号；
所述公共电极电压线的远端为所述公共电极电压线远离第一侧边的一端；
所述公共电极电压线的近端为所述公共电极电压线靠近第一侧边的一端。
在图3A所示的至少一实施例中，测试线TL与驱动模组包括的最后一级驱动电路的输出端电连接，所述测试线TL还与驱动集成电路电连接，所述驱动集成电路接收来自所述测试线TL的信号，以判断所述最后一级驱动电路的输出端提供的驱动信号是否准确。
图3C是图3A中的第一静电释放电路ED1部分局部放大示意图，第一静电释放电路ED1包括多个静电释放子电路，所述多个静电释放子电路的结构可以相同；但不以此为限；在实际操作时，所述多个静电释放子电路中的至少两个静电释放子电路的结构也可以互不相同；
如图3C和3D所示，第一静电释放子电路ED11可以包括第一保护晶体管T1、第二保护晶体管T2、第三保护晶体管T3和第四保护晶体管T4；当该静电释放子电路用于对第一时钟信号线CK1进行静电保护时，
所述第一保护晶体管T1的栅极与所述第一保护晶体管T1的第一极可以都与第一时钟信号线CK1电连接，所述第一保护晶体管T1的第二极与第二保护晶体管T2的第二极电连接；
所述第二保护晶体管T2的栅极与所述第二保护晶体管T2的第二极电连接；所述第二保护晶体管T2的第一极与所述第一时钟信号线CK1电连接；
所述第三保护晶体管T3的栅极和所述第三保护晶体管T3的第一极都与所述第二保护晶体管T2的栅极电连接；
所述第四保护晶体管T4的栅极与所述第四保护晶体管T4的第二极电连接，所述第四保护晶体管T4的第一极与所述第二保护晶体管T2的栅极电连接；
所述第三保护晶体管T3的第二极与所述第四保护晶体管T4的第二极都与静电环SR 电连接。
可选的，所述第三保护晶体管T3的第二极与所述第四保护晶体管T4的第二极也可以被替换为都与公共电极电压端电连接；
所述第一保护晶体管T1的栅极和所述第一保护晶体管T1的第一极可以被替换为其他的时钟信号线、第一条第一低电压线VGL11、第二低电压线LVGL、帧复位线STV0、第二控制电压线VDDE、第一控制电压线VDDO或起始电压线STV1，在此不做限定。
在本公开至少一实施例中，所述阵列基板包括驱动电路区域和显示区域，所述驱动模组设置于所述驱动电路区域；所述驱动电路区域包括集线区域；
所述阵列基板还包括设置于在所述驱动电路区域与所述显示区域之间的第二条第一低电压线，以及，设置于所述集线区域的级联线(级联线包括进位信号线和复位信号线，进位信号线用于上级GOA电路(Gate On Array，设置于阵列基板上的栅极驱动电路)给下级GOA电路的输入模块提供进位信号，复位信号线用于下级GOA电路给上级GOA的复位模块提供复位信号，复位信号例如可以是给上拉节点或者GOA电路的输出端复位)；
所述级联线为所述驱动模组包括的各级驱动电路之间的用于级联的信号线；所述第二条第一低电压线用于提供第一低电压信号；
所述虚拟信号线在所述衬底基板上的正投影与所述级联线在所述衬底基板上的正投影部分交叠；
所述虚拟信号线在所述衬底基板上的正投影与所述第二条第一低电压线在所述衬底基板上的正投影部分交叠。
如图4所示，在驱动电路区域30中设置有驱动模组包括的驱动电路，标号为J1的为集线区域；
所述阵列基板还包括设置于所述驱动电路区域30与显示区域之间的第二条第一低电压线VGL21；
所述第二条第一低电压线VGL21用于提供第一低电压信号。
在本公开至少一实施例中，所述第一条第一低电压线VGL11和第二条第一低电压线VGL21可以相互电连接。
在本公开至少一实施例中，所述周边区域包括虚拟驱动电路区域，所述阵列基板还包括设置于所述虚拟驱动电路区域的虚拟驱动模组，所述虚拟驱动电路区域设置于所述侧边区域与所述显示区域之间；
所述虚拟驱动模组包括沿第一方向排列的多个虚拟驱动电路；
所述虚拟驱动电路包括虚拟驱动输出端和虚拟输入端；
所述虚拟驱动电路的虚拟输入端与所述虚拟驱动模组包括的除了该虚拟驱动电路之外的虚拟驱动电路的虚拟驱动输出端之间断开，即虚拟驱动区域即为设置虚拟驱动电路的区域，集线区域中的级联线没有将虚拟驱动模组包括的GOA电路实现级联，呈现断开的状态。设置虚拟驱动电路可以实现和用于给显示区域第二栅线提供栅信号的驱动电路保持 制备工艺的稳定性。
在图5中，标号为XA的为虚拟驱动电路区域，虚拟驱动电路区域设置于侧边区域与显示区域之间；
在图5中，标号XZ的为虚拟驱动模组，虚拟驱动模组XZ包括沿水平方向排列的多个虚拟驱动电路；
在图5中，标号为X1的为第一虚拟驱动电路，标号为X2的为第二虚拟驱动电路，标号为X3的为第三虚拟驱动电路，标号为X4的为第四虚拟驱动电路，标号为X5的为第五虚拟驱动电路，标号为X6的为第六虚拟驱动电路，标号为X7的为第七虚拟驱动电路。
在图6中，标号为IP3的为X3的虚拟输入端，标号为OT3的为X3的虚拟驱动输出端。
如图5和图6所示，虚拟驱动电路包括的虚拟输入端与所述虚拟驱动模组包括的虚拟驱动输出端之间断开。
可选的，所述阵列基板还包括设置于相邻的所述虚拟驱动电路之间的浮空信号线，用于保持制备工艺刻蚀均一性；
所述浮空信号线处于浮空状态。
在具体实施时，所述阵列基板还包括设置于相邻的虚拟驱动电路之间的处于浮空状态的浮空信号线。
如图7所示，标号为FL11的为第一浮空信号线包括的第一浮空信号线部，标号为FL12的为第一浮空信号线包括的第二浮空信号线部，标号为FL13的为第一浮空信号线包括的第三浮空信号线部；
第一浮空信号线设置于第一虚拟驱动电路X1和第二虚拟驱动电路X2之间。
如图7所示，在第一虚拟驱动电路X1左侧也设置有浮空信号线；
在所述第一虚拟驱动电路X1左侧设置有十字形的对位标记DB1；为了节省边框，所述对位标记DB1靠近第一虚拟驱动电路X1设计，因此将浮空信号线的位于集线区域的上部分为两个部分。
在本公开至少一实施例中，所述阵列基板包括周边区域和显示区域，所述周边区域包括驱动电路区域；所述驱动模组设置于所述驱动电路区域；
所述周边区域还包括设置于所述驱动电路区域远离所述显示区域的一侧的公共电极走线区域，以及，设置于所述公共电极走线区域和所述驱动电路区域之间的第二信号线区域；
所述阵列基板还包括公共电极走线、公共电极连接线和设置于显示区域的公共电极；所述公共电极走线通过所述公共电极连接线与所述公共电极电连接；
所述公共电极走线位于所述公共电极走线区域；
所述公共电极连接线贯穿所述第二信号线区域和所述驱动电路区域。
可选的，所述阵列基板还包括设置于所述第二信号线区域中的多条时钟信号线、第一 控制电压线、第二控制电压线、帧复位线和第二低电压线。
如图8所示，所述周边区域包括驱动电路区域30，驱动模组包括的驱动电路设置于驱动电路区域30；
所述周边区域还包括设置于所述驱动电路区域30远离显示区域的一侧的公共电极走线区域VMA，以及，设置于所述公共电极走线区域VMA与所述驱动电路区域30之间的第二信号线区域71；
所述阵列基板还包括公共电极走线VML、公共电极连接线LX和设置于显示区域的公共电极；
公共电极走线VML通过公共电极连接线LX与公共电极电连接；
所述公共电极走线VML设置于公共电极走线区域VMA；
所述公共电极连接线LX贯穿所述的第二信号线区域71和驱动电路区域30，进而延伸至显示区域。
在图8所示的至少一实施例中，公共电极走线VML可以形成于栅极金属层，所述公共电极连接线LX可以形成于源漏金属层，但不以此为限，二者可以通过沉积在绝缘层过孔中的电极层实现电连接。
在图9中，标号为CK1的为第一时钟信号线，标号为CK2的为第二时钟信号线，标号为CK3的为第三时钟信号线，标号为CK4的为第四时钟信号线，标号为CK5的为第五时钟信号线，标号为CK6的为第六时钟信号线，标号为CK7的为第七时钟信号线，标号为CK8的为第八时钟信号线，
标号为VDDO的为第一控制电压线，标号为VDDE的为第二控制电压线，标号为STV0的为帧复位线，标号为LVGL的为第二低电压线。
在本公开至少一实施例中，所述阵列基板包括周边区域和显示区域，所述周边区域包括驱动电路区域；所述驱动模组设置于所述驱动电路区域；
所述周边区域还包括设置于所述驱动电路区域远离所述显示区域的一侧的第二信号线区域；
所述阵列基板还包括设置于所述第二信号线区域的多条时钟信号线；所述时钟信号线沿第一方向延伸，所述多条时钟信号线沿所述第二方向排列；
与靠近所述显示区域一侧的时钟信号线电连接的时钟信号连接线，相对于与靠近所述公共电极走线区域的时钟信号线电连接的时钟信号连接线，包括绕线部。
如图8所示，在第二信号线区域71内设置有第一时钟信号线CK1、第二时钟信号线CK2、第三时钟信号线CK3、第四时钟信号线CK4、第五时钟信号线CK5、第六时钟信号线CK6、第七时钟信号线CK7和第八时钟信号线CK8；
各所述时钟信号线都沿水平方向延伸，各所述时钟信号线沿竖直方向排列；
与靠近显示区域的时钟信号线电连接的时钟信号连接线，相对于与靠近所述公共电极 走线区域的时钟信号线电连接的时钟信号连接线，包括绕线部，以能够进行补偿，使得各时钟信号线与驱动电路之间的连接线的长度近似相等；
在图9、图10所示的至少一实施例中，CK1是最靠近公共电极走线区域的时钟信号线，CK1与第一时钟信号连接线L1电连接；第一时钟信号连接线L1不具有绕线部；可选的，时钟信号线设置在栅极金属层，连接线L1设置在源漏金属层，二者可以通过沉积在绝缘层过孔中的电极层实现电连接。连接线和时钟信号线在垂直于衬底基板上有交叠，交叠位置处，时钟信号线至少部分有镂空部，用于减小连接线和时钟信号线二者之间的耦合电容。
CK8是最靠近显示区域的时钟信号线，CK8与第八时钟信号连接线电连接，第八时钟信号连接线包括第八绕线部R8；
CK7是第二靠近显示区域的时钟信号线，CK7与第七时钟信号连接线电连接，第七时钟信号连接线包括第七绕线部R7；
CK6是第三靠近显示区域的时钟信号线，CK6与第六时钟信号连接线电连接，第六时钟信号连接线包括第六绕线部R6；
CK5是第四靠近显示区域的时钟信号线，CK5与第五时钟信号连接线电连接，第五时钟信号连接线包括第五绕线部R5；
CK4是第五靠近显示区域的时钟信号线，CK4与第四时钟信号连接线电连接，第四时钟信号连接线包括第四绕线部R4；
CK3是第六靠近显示区域的时钟信号线，CK3与第三时钟信号连接线电连接，第三时钟信号连接线包括第三绕线部R3；
CK2是第七靠近显示区域的时钟信号线，CK2与第二时钟信号连接线L2电连接，第二时钟信号连接线包括第二绕线部R2；
R8的长度大于R7的长度，R7的长度大于R6的长度，R6的长度大于R5的长度，R5的长度大于R4的长度，R4的长度大于R3的长度，R3的长度大于R2的长度。
在图10所示的至少一实施例中，由于CK2、CK3、CK4、CK5、CK6、CK7、CK8沿着靠近显示区域的方向依次排列，因此将R8的长度设置为大于R7的长度，将R7的长度设置为大于R6的长度，将R6的长度设置为大于R5的长度，将R5的长度设置为大于R4的长度，将R4的长度设置为大于R3的长度，将R3的长度设置为大于R2的长度，以使得各时钟信号线与驱动电路之间的连线的阻抗大致相同，以平衡阻抗。
图11是在本公开至少一实施例中，侧边区域20和虚拟驱动电路区域XA的示意图。
所述虚拟驱动电路区域XA设置于所述侧边区域20靠近显示区域的一侧。
在图11中，标号为VGL11的为第一条第一低电压线，标号为VGL21的为第二条第一低电压线，如图11所示，VGL11和VGL21可以通过左侧的导电线电连接。
图12是本公开至少一实施例中，阵列基板包括的位于左侧的驱动电路的示意图。
在图12中，标号为121的为第三信号线区域，标号为122的为第二静电释放区域， 标号为123的为第四信号线区域，标号为71的为第二信号线区域，标号为30的为驱动电路区域，标号为124的为第五信号线区域。
如图12所示，第三信号线区域121、第二静电释放区域122、第四信号线区域123、第二信号线区域71、驱动电路区域30和第五信号线区域124沿着靠近显示区域的方向依次排列。
在图12所示的至少一实施例中，在所述第三信号线区域121设置有形成于栅金属层的第一数据线；
在第二静电释放区域122设置有静电释放电路，所述静电释放电路用于对该数据线进行静电防护；
在所述第四信号线区域123中设置有形成于源漏金属层的第一数据线；
在第二信号线区域71设置有形成于栅金属层的时钟信号线、第一控制电压线、第二控制电压线和第二低电压线；
在所述驱动电路区域30中设置有多个沿水平方向排列的驱动电路，形成于源漏金属层的第一数据线穿过相邻的两个驱动电路之间，以向所述显示区域延伸；
在第五信号线区域124设置有形成于源漏金属层的第一数据线。
所述第三信号线区域121也即为扇出区域，在所述扇出区域可以设置有绑定焊盘，该绑定焊盘与源极驱动器电连接或者和柔性电路板的绑定区域实现电连接。
图13是本公开至少一实施例所述的阵列基板包括的位于中间的驱动电路的示意图。
在图13中，标号为VMA的为公共电极走线区域，标号为123的为第四信号线区域，标号为71的为第二信号线区域，标号为30的为驱动电路区域，标号为123的为第四信号线区域。
如图13所示，公共电极走线区域VMA、第四信号线区域123、第二信号线区域71、驱动电路区域30和第五信号线区域124沿着靠近显示区域的方向依次排列。
在图13所示的至少一实施例中，在所述公共电极走线区域VMA设置有形成于栅金属层的网状的公共电极走线；
在所述第四信号线区域123中设置有形成于源漏金属层的第一数据线；在所述第二信号线区域71中设置有形成于源漏金属层的公共电极连接线和形成于源漏金属层的第一数据线；
在所述驱动电路区域30中设置有多个沿水平方向排列的驱动电路，形成于源漏金属层的第一数据线和公共电极连接线穿过相邻的两个驱动电路之间，以向所述显示区域延伸；
在第五信号线区域124设置有形成于源漏金属层的第一数据线。
在图13中，标号为130的为显示区域，在显示区域中设置有公共电极VMP，所述公共电极VMP可以与公共电极走线电连接。
图14是本公开至少一实施例所述的阵列基板包括的位于右侧的驱动电路的示意图。
在图14中，标号为121的为第三信号线区域，标号为122的为第二静电释放区域， 标号为123的为第四信号线区域，标号为71的为第二信号线区域，标号为30的为驱动电路区域，标号为124的为第五信号线区域。
如图14所示，第三信号线区域121、第二静电释放区域122、第四信号线区域123、第二信号线区域71、驱动电路区域30和第五信号线区域124沿着靠近显示区域的方向依次排列。
在图14所示的至少一实施例中，在所述第三信号线区域121设置有形成于栅金属层的第一数据线；
在第二静电释放区域122设置有静电释放电路，所述静电释放电路用于对该数据线进行静电防护；
在所述第四信号线区域123中设置有形成于源漏金属层的第一数据线；
在第二信号线区域71设置有形成于栅金属层的时钟信号线、第一控制电压线、第二控制电压线和第二低电压线；
在所述驱动电路区域30中设置有多个沿水平方向排列的驱动电路，形成于源漏金属层的第一数据线穿过相邻的两个驱动电路之间，以向所述显示区域延伸；
在第五信号线区域124设置有形成于源漏金属层的第一数据线。
所述第三信号线区域121也即为扇出区域，在所述扇出区域可以设置有绑定焊盘，该绑定焊盘与源极驱动器电连接。
图15是本公开所述的阵列基板中的驱动电路的至少一实施例的结构图。
如图15所示，所述驱动电路的至少一实施例可以包括第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13、第十四晶体管M14、第十五晶体管M15、第十六晶体管M16、第十七晶体管M17、第十八晶体管M18、第十九晶体管M19和第一电容C1，本案中GOA电路的晶体管的连接关系参考图15，例如，第三晶体管M3的栅极与上拉节点电连接，第三晶体管M3的第一极与时钟信号线CK电连接，第三晶体管M3的第二极与驱动信号输出端O1电连接，第七晶体管M7的栅极与帧复位线STV0电连接，第七晶体管M7的第一极和上拉节点PU电连接，第七晶体管M7的第二极和第二低电压线LVGL电连接，其他晶体管的连接关系参考图15，在这里不详细叙述；
在图15中，标号为I1的为输入端，标号为STV0的为帧复位线(用于在一帧前给GOA电路进行复位)，标号为R1的为第一复位端(上级GOA电路的第一复位端R1可以与下级GOA电路的驱动信号输出端O1实现电连接)，标号为PU的为上拉节点，标号为PD1的为第一下拉节点，标号为PD2的为第二下拉节点，标号为VDDO的为第一控制电压线，标号为VDDE的为第二控制电压线，标号为CK的为时钟信号线，标号为VGL21的为第二条第一低电压线，标号为O1的为驱动信号输出端，标号为RST的为第二复位端。
在本公开至少一实施例中，第二条第一低电压线VGL21和第一条第一低电压线 VGL11可以相互电连接。
图16A是在图14的基础上增设对驱动电路中的各晶体管和电容的标示的示意图。
在图16A所示的至少一实施例中，标号为VGL21的第二条第一电压线，第二条第一电压线VGL21设置于第四晶体管M4的靠近显示区域的一侧。
图16B为所述驱动电路的从上至下第一部分的局部放大图；
图16C为所述驱动电路的从上至下第二部分的局部放大图；
图16D为所述驱动电路的从上至下第三部分的局部放大图；
图16E为所述驱动电路的从上至下第四部分的局部放大图。
图16F是图16A中的局部放大图。
如图16F所示，与第七晶体管M7的栅极电连接的信号线，以及位于M7上方的一信号线都为帧复位线STV0；
所述帧复位线STV0可以形成于栅金属层；
所述与第七晶体管M7的栅极电连接的信号线和所述位于M7上方的一信号线之间可以同设置于源漏金属层上的连接线LX相互电连接，所述连接线LX的个数可以为多条。
在本公开至少一实施例中，所述第一栅线和所述第二数据线交叉限定子像素区域，所述子像素区域包括子电极；
距离所述驱动模组最远的子像素区域包括的子电极沿所述第二方向的长度小于第一长度；
所述第一长度为除了距离所述驱动模组最远的子像素区域之外的子像素区域包括的子电极沿第二方向的最短长度。
在具体实施时，在显示区域，第一栅线和第二数据线交叉限定子像素区域，所述子像素驱动可以包括像素电极和公共电极，公共电极是一个整体的电极，像素电极是分开的，距离所述驱动模组最远的子像素区域包括的子电极沿竖直方向的长度小于其他像素电路沿竖直方向上的长度，这样节约出来的空间可以用于其它设计，例如可以设置AT(Array Test，阵列测试)部件，以能够在实现超窄边框的同时实现AT正常检出；目前该设计也可以在无界屏上使用，可以量产。
在本公开至少一实施例中，所述子电极可以包括公共电极和像素电极，所述公共电极和所述像素电极都为双畴结构，双畴结构包括相互电连接的上畴结构和下畴结构，上畴结构的延伸方向与下畴结构的延伸方向不同。减小距离驱动模组最远的子像素区域包括的子电极沿所述第二方向的长度可以通过以下三种方式实现：减小所述上畴结构的沿第二方向的长度、减小所述下畴结构的沿第二方向的长度，或者，减小所述上畴结构的沿第二方向的长度和所述下畴结构的沿第二方向的长度。参考图17，本案中显示区域的像素，可选的，像素电极和公共电极设置在同层，且呈现梳齿状交替排布，像素电极包括多个支电极部，支电极端部包括加宽部，加宽部的设计可改善像素便缘区域发暗的问题。
在相关技术中，在DPO(Data Pad Opposite，数据绑定对侧)侧，由于边框紧张，不 够其他工序的设计空间，因此可以通过黑矩阵遮挡住距离所述驱动模组最远的子像素区域的部分发光区，被遮挡的部分看不到画面。本公开至少一实施例通过将部分发光区直接去掉，相当于距离驱动模组最远的一行像素是正常像素的2/3高度，这样节约出来的空间可以用于其它设计。
如图17所示，距离所述驱动模组较近的子像素区域包括的公共电极VM沿竖直方向的长度，以及，距离所述驱动模组较近的子像素区域该子像素区域包括的像素电极PX沿竖直方向的长度较大；
如图18所示，距离所述驱动模组最远的子像素区域包括的公共电极VM竖直方向的长度，以及，距离所述驱动模组最远的子像素区域包括的像素电极PX沿竖直方向的长度较小。
在图18所示的至少一实施例中，通过减小公共电极包括的下畴结构的沿竖直方向的长度，并减小像素电极包括的下畴结构的沿竖直方向的长度，以节约空间。
在本公开至少一实施例中，所述公共电极和所述像素电路可以都形成于ITO(氧化铟锡)层，但不以此为限。
可选的，所述阵列基板包括显示区域和周边区域；
所述周边区域包括设置于所述显示区域的第一侧的第一虚拟图案区域和/或设置于所述显示区域的第四侧的第二虚拟图案区域；所述第一侧和所述第四侧为相对的两侧；
所述阵列基板包括设置于所述第一虚拟图案区域的第一虚拟图案阵列，和/或，设置于所述第二虚拟图案区域的第二虚拟图案阵列；
所述第一虚拟图案阵列包括阵列设置的多个第一虚拟图案，所述第二虚拟图案阵列包括阵列设置的多个第二虚拟图案；所述第一虚拟图案用于支撑封框胶，所述第二虚拟图案用于支撑封框胶。
在本公开至少一实施例中，所述第一侧可以为左侧，所述第二侧可以为右侧，但不以此为限。
在相关技术中，窄边框显示产品在设计时会考虑产品设计极致低成本，因此会需要兼容大的边框设计需求，因此在大边框Panel(显示面板)边与小边框Panel边之间如果是空白区设计，在后续的Cell(成盒)工程中会出现一些问题，导致显示产品不能正常生产，因此需要增加虚拟图案设计。在Cell工程中会出现的问题例如可以为：在做大边框显示面板时，封框胶会涂覆在增加的边框区域，如果不增加虚拟图案，周边封框胶的高度会有问题，会出现周边发黄不良。基于此，本公开至少一实施例在显示区域的第一侧和/或所述显示区域的第二侧设置虚拟图案区域，在所述虚拟图案区域内设置有虚拟图案阵列，所述虚拟图案阵列包括阵列设置的多个用于支撑封框胶的虚拟图案，以改善周边发黄不良的现象。
可选的，所述第一虚拟图案可以形成于栅金属层或源漏金属层，所述第二虚拟图案可以形成于栅金属层或源漏金属层。
如图19所示，标号为A1的为显示区域；
标号为BD1的为第一边界，标号为BD2的为第二边界；
显示区域A1设置于第一边界BD1远离第二边界BD2的一侧；
第一虚拟图案区域PT1设置于显示区域A1左侧，所述阵列基板包括设置于第一虚拟图案区域PT1的第一虚拟图案阵列；
第一虚拟图案阵列包括阵列设置的多个第一虚拟图案TX1；
所述第一虚拟图案TX1用于支撑封框胶。
在图19所示的至少一实施例中，所述第一虚拟图案阵列可以形成于栅金属层，所述第一虚拟图案TX1为长方形虚拟图案。
在图19中，标号为DW1的为第一对位标记，标号为DW2的为第二对位标记，第一对位标记DW1和第二对位标记DW2可以都形成于栅金属层，DW1和DW2可以用于对位切割线。
当需要制作窄边框显示面板时，从第一边界BD1切割，当需要制作大边框显示面板时，可以从第二边界BD2切割。
可选的，所述第一虚拟图案也可以为田字形虚拟图案或八字形虚拟图案，但不以此为限。
在本公开至少一实施例中，所述阵列基板包括周边区域；所述周边区域包括绑定区域；所述阵列基板包括设置于所述绑定区域的绑定焊盘；
所述绑定焊盘与所述第一数据线电连接，所述绑定焊盘与导电连接图形通过过孔电连接，所述过孔的边缘为锯齿状。
在具体实施时，所述周边区域包括绑定区域，所述阵列基板包括绑定焊盘，所述绑定焊盘设置于所述绑定区域，柔性电路板的焊盘通过导电连接图形与所述绑定焊盘电连接，该导电连接图形可以形成于ITO层，但不以此为限。
可选的，所述绑定焊盘可以形成于栅金属层，所述绑定焊盘与所述导电连接图形电连接，所述导电连接图形通过贯穿有机膜层的过孔可与柔性电路板的焊盘电连接，但是由于所述有机膜层的厚度较厚，绑定区域需要使用工具压接，因此会所述过孔的边缘有被压裂的风险，因此，本公开至少一实施例将所述过孔的边缘设置为锯齿形，分担过孔边缘突变导致的压力，防止所述过孔边缘被压裂，该过孔可以用于无界屏显示产品。
图20是穿过有机膜层的过孔占用的过孔区域AG的俯视图。如图20所示，所述过孔区域AG的边缘为锯齿形。
在图21中，标号为H1的为过孔，标号为200的为衬底基板，标号为201的为栅金属层，标号为202的为栅绝缘层，标号为203的为钝化层，标号为204的为有机膜层，标号为L1的为导电连接图形；
过孔H1为贯穿钝化层202、栅绝缘层203和有机膜层204的过孔，绑定焊盘和第一数据线都形成于栅金属层201，导电连接图形LD1形成于ITO层，在制作显示面板时，导 电连接图形LD1通过过孔H1与源极驱动器电连接。
在图22中，标号为AG的为过孔区域，过孔区域AG的边缘为锯齿状。
图23是图22中的栅金属层的布局图，如图23所示，标号为HB的为绑定焊盘，标号为DL1的为第一数据线。
本公开实施例所述的显示装置包括上述的阵列基板。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (19)

  1. 一种阵列基板，包括衬底基板和设置于衬底基板上的第一数据线、虚拟信号线和驱动模组，所述第一数据线、所述虚拟信号线和所述驱动模组设置于所述阵列基板的周边区域，所述周边区域至少部分围绕显示区域，所述显示区域包括沿第一方向延伸的第一栅线和沿第二方向延伸的第二数据线，所述第一数据线和所述第二数据线电连接，所述第一方向和所述第二方向相交；
    所述驱动模组设置于所述阵列基板的第一侧边；所述第一侧边为设置于所述第二数据线延伸方向的侧边；
    所述驱动模组包括多级驱动电路；所述多级驱动电路沿所述第一方向排布；所述驱动电路用于提供驱动信号；
    在至少两个相邻的驱动电路之间设置有所述第一数据线，所述第一数据线用于提供数据电压；
    在至少两个相邻的驱动电路之间还设置有所述虚拟信号线；所述虚拟信号线处于浮空状态。
  2. 如权利要求1所述的阵列基板，其中，所述第一数据线和所述虚拟信号线形成于同一导电层。
  3. 如权利要求2所述的阵列基板，其中，至少一所述虚拟信号线设置于相邻的两个所述第一数据线之间；
    所述虚拟信号线沿所述第二方向延伸。
  4. 如权利要求1至3中任一权利要求所述的阵列基板，其中，所述周边区域包括驱动电路区域和侧边区域；所述驱动模组设置于所述驱动电路区域；
    所述侧边区域设置于所述驱动电路区域排布方向的相对的两侧；
    所述侧边区域包括第一信号线区域和第一静电释放区域；所述阵列基板还包括设置于所述第一信号线区域的多条时钟信号线，以及，设置于所述第一静电释放区域的第一静电释放电路；
    所述第一静电释放电路与所述时钟信号线电连接，用于对所述时钟信号线进行静电防护。
  5. 如权利要求4所述的阵列基板，其中，所述阵列基板还包括设置于所述第一信号线区域的第一条第一低电压线、第二低电压线、帧复位线、第一控制电压线、第二控制电压线和起始电压线；
    所述第一静电释放电路还分别与所述第一条第一低电压线、所述第二低电压线、所述帧复位线、所述第一控制电压线、所述第二控制电压线和所述起始电压线电连接，用于对所述第一条第一低电压线、所述第二低电压线、所述帧复位线、所述第一控制电压线、所述第二控制电压线和所述起始电压线进行静电防护；
    所述第一条第一低电压线用于提供第一低电压信号，所述帧复位线用于提供帧复位信号，所述第一控制电压线用于提供第一控制电压，所述第二控制电压线用于提供第二控制电压，所述起始电压线用于提供起始电压。
  6. 如权利要求5所述的阵列基板，其中，所述时钟信号线、所述第二低电压线、所述帧复位线、所述第一控制电压线和所述第二控制电压线设置于所述第一静电释放电路的第一侧、第二侧和第三侧；所述第一条第一低电压线设置于所述第一静电释放电路的第一侧和第二侧；所述起始电压线设置于所述第一静电释放电路的第四侧；
    所述第一侧与所述第四侧为相对的两侧，所述第二侧和所述第三侧为相对的两侧。
  7. 如权利要求1至3中任一权利要求所述的阵列基板，其中，所述阵列基板包括驱动电路区域和显示区域，所述驱动模组设置于所述驱动电路区域；所述驱动电路区域包括集线区域；
    所述阵列基板还包括设置于在所述驱动电路区域与所述显示区域之间的第二条第一低电压线，以及，设置于所述集线区域的级联线；
    所述级联线为所述驱动模组包括的各级驱动电路之间的用于级联的信号线；所述第二条第一低电压线用于提供第一低电压信号；
    所述虚拟信号线在所述衬底基板上的正投影与所述级联线在所述衬底基板上的正投影部分交叠；
    所述虚拟信号线在所述衬底基板上的正投影与所述第二条第一低电压线在所述衬底基板上的正投影部分交叠。
  8. 如权利要求4所述的阵列基板，其中，所述周边区域包括虚拟驱动电路区域；所述阵列基板包括设置于虚拟驱动电路区域的虚拟驱动模组，所述虚拟驱动电路区域设置于所述侧边区域与所述显示区域之间；
    所述虚拟驱动模组包括沿第一方向排列的多个虚拟驱动电路；
    所述虚拟驱动电路包括虚拟驱动输出端和虚拟输入端；
    所述虚拟驱动电路的虚拟输入端与所述虚拟驱动模组包括的除了该虚拟驱动电路之外的虚拟驱动电路的虚拟驱动输出端之间断开。
  9. 如权利要求8所述的阵列基板，其中，所述阵列基板还包括设置于相邻的所述虚拟驱动电路之间的浮空信号线；
    所述浮空信号线处于浮空状态。
  10. 如权利要求1至3中任一权利要求所述的阵列基板，其中，所述阵列基板包括周边区域和显示区域，所述周边区域包括驱动电路区域；所述驱动模组设置于所述驱动电路区域；
    所述周边区域还包括设置于所述驱动电路区域远离所述显示区域的一侧的公共电极走线区域，以及，设置于所述公共电极走线区域和所述驱动电路区域之间的第二信号线区域；
    所述阵列基板还包括公共电极走线、公共电极连接线和设置于显示区域的公共电极；所述公共电极走线通过所述公共电极连接线与所述公共电极电连接；
    所述公共电极走线位于所述公共电极走线区域；
    所述公共电极连接线贯穿所述第二信号线区域和所述驱动电路区域。
  11. 如权利要求10所述的阵列基板，其中，所述阵列基板还包括设置于所述第二信号线区域中的多条时钟信号线、第一控制电压线、第二控制电压线、帧复位线和第二低电压线。
  12. 如权利要求10所述的阵列基板，其中，所述阵列基板包括周边区域和显示区域，所述周边区域包括驱动电路区域；所述驱动模组设置于所述驱动电路区域；
    所述周边区域还包括设置于所述驱动电路区域远离所述显示区域的一侧的第二信号线区域；
    所述阵列基板还包括设置于所述第二信号线区域的多条时钟信号线；所述时钟信号线沿第一方向延伸，所述多条时钟信号线沿所述第二方向排列；
    与靠近所述显示区域一侧的时钟信号线电连接的时钟信号连接线，相对于与靠近所述公共电极走线区域的时钟信号线电连接的时钟信号连接线，包括绕线部。
  13. 如权利要求1至3中任一权利要求所述的阵列基板，其中，所述第一栅线和所述第二数据线交叉限定子像素区域，所述子像素区域包括子电极；
    距离所述驱动模组最远的子像素区域包括的子电极沿所述第二方向的长度小于第一长度；
    所述第一长度为除了距离所述驱动模组最远的子像素区域之外的子像素区域包括的子电极沿第二方向的最短长度。
  14. 如权利要求1至3中任一权利要求所述的阵列基板，其中，所述阵列基板包括显示区域和周边区域；
    所述周边区域包括设置于所述显示区域的第一侧的第一虚拟图案区域和/或设置于所述显示区域的第四侧的第二虚拟图案区域；所述第一侧和所述第四侧为相对的两侧；
    所述阵列基板包括设置于所述第一虚拟图案区域的第一虚拟图案阵列，和/或，设置于所述第二虚拟图案区域的第二虚拟图案阵列；
    所述第一虚拟图案阵列包括阵列设置的多个第一虚拟图案，所述第二虚拟图案阵列包括阵列设置的多个第二虚拟图案；所述第一虚拟图案用于支撑封框胶，所述第二虚拟图案用于支撑封框胶。
  15. 如权利要求14所述的阵列基板，其中，所述阵列基板包括周边区域；所述周边区域包括绑定区域；所述阵列基板包括设置于所述绑定区域的绑定焊盘；
    所述绑定焊盘与所述第一数据线电连接，所述绑定焊盘与导电连接图形通过过孔电连接，所述过孔的边缘为锯齿状。
  16. 如权利要求1至3中任一权利要求所述的阵列基板，其中，还包括沿第二方向延 伸的第二栅线；
    所述第一栅线与所述第二栅线电连接，所述第二栅线与所述驱动模组电连接。
  17. 如权利要求1至3中任一权利要求所述的阵列基板，其中，所述第一栅线和所述第二数据线交叉限定子像素区域；
    相邻的驱动电路之间的第一数据线的数量大于或等于m/(n+2)而小于或等于m/(n-1)；
    n为所述第一栅线的数量，m为所述子像素区域对应的第二数据线的数量，m和n为正整数。
  18. 如权利要求1至3中任一权利要求所述的阵列基板，其中，所述虚拟信号线的数量小于所述第一数据线的数量。
  19. 一种显示装置，包括如权利要求1至18中任一权利要求所述的阵列基板。
PCT/CN2024/089967 2023-05-26 2024-04-26 阵列基板和显示装置 WO2024244848A1 (zh)

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