WO2024241163A1 - Memory element - Google Patents

Abstract

The present invention provides a memory element with a reduced occupied area. A vertical-channel transistor is used as a transistor connected to a memory element, namely a spin-orbit torque magnetic tunnel junction element (SOT-MTJ element). Using a vertical-channel transistor allows for a reduction in the area occupied by the memory element. In addition, by using an oxide semiconductor in the channel formation region of the vertical-channel transistor, write and read operations are stable even in high-temperature environments, and a highly reliable memory element can be achieved.

Description

Memory element

One aspect of the present invention relates to a memory element.

Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, power storage devices, imaging devices, memory devices (memories), signal processing devices, sensors, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

In recent years, with the increase in the amount of data being handled, there is a demand for storage devices with larger storage capacities. In order to increase the storage capacity per unit area, it is effective to form memory elements (also called "memory cells") in a stacked manner, such as in 3D NAND type storage devices (see Patent Documents 1 to 3). By stacking memory elements, the storage capacity per unit area can be increased according to the number of stacked memory cells.

US Patent Application Publication No. 2011/0065270 US Patent Application Publication No. 2016/0149004 US Patent Application Publication No. 2013/0069052

In order to increase the memory capacity per unit area, it is important not only to stack memory elements, but also to reduce the area occupied by each memory element.

An object of one embodiment of the present invention is to provide a memory element with a reduced occupancy area. Alternatively, an object of the present invention is to provide a memory element with high reliability. Alternatively, an object of the present invention is to provide a memory element with low power consumption. Alternatively, an object of the present invention is to provide a new memory element. Alternatively, an object of the present invention is to provide a memory device with a reduced occupancy area. Alternatively, an object of the present invention is to provide a memory device with high memory density (storage capacity per unit area). Alternatively, an object of the present invention is to provide a memory device with high reliability. Alternatively, an object of the present invention is to provide a memory device with low power consumption. Alternatively, an object of the present invention is to provide a new memory device.

Note that the problems associated with one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention does not need to solve all of the problems listed above and other problems. One embodiment of the present invention solves at least one of the problems listed above and other problems.

(1) One aspect of the present invention is a memory element having a conductive layer, a magnetic tunnel junction element, and a transistor, the magnetic tunnel junction element being provided overlapping the conductive layer, one of the source electrode or drain electrode of the transistor being electrically connected to the conductive layer, one of the source electrode or drain electrode of the transistor having a region above the insulating layer, the other of the source electrode or drain electrode of the transistor having a region below the insulating layer, and the channel formation region of the transistor having a region along the side of the insulating layer.

In addition, in (1), the resistance value of the magnetic tunnel junction element is controlled by the direction of the current supplied to the conductive layer via the transistor. It is preferable to use an oxide semiconductor as the semiconductor layer of the transistor. In addition, the conductive layer may have a region in contact with the semiconductor layer of the transistor.

(2) Another aspect of the present invention is a memory element having a conductive layer, a magnetic tunnel junction element, a first transistor, and a second transistor, the magnetic tunnel junction element being provided overlapping the conductive layer, one of the source electrode or drain electrode of the first transistor being electrically connected to one of the source electrode or drain electrode of the second transistor through at least a region of the conductive layer that overlaps with the magnetic tunnel junction element, one of the source electrode or drain electrode of the first transistor having a region above the insulating layer, the other of the source electrode or drain electrode of the first transistor having a region below the insulating layer, the channel formation region of the first transistor having a region along a first side of the insulating layer, one of the source electrode or drain electrode of the second transistor having a region above the insulating layer, the other of the source electrode or drain electrode of the second transistor having a region below the insulating layer, and the channel formation region of the second transistor having a region along a second side of the insulating layer.

In addition, in (2), the resistance value of the magnetic tunnel junction element is controlled by the direction of the current supplied to the conductive layer via the first transistor or the second transistor. It is preferable to use an oxide semiconductor as the semiconductor layer of the transistor. It is preferable to use an oxide semiconductor as the semiconductor layer of the first transistor. It is preferable to use an oxide semiconductor as the semiconductor layer of the second transistor. The conductive layer may have a region in contact with the semiconductor layer of the first transistor, or may have a region in contact with the semiconductor layer of the second transistor.

According to one aspect of the present invention, a memory element with a reduced occupancy area can be provided. Or a memory element with high reliability can be provided. Or a memory element with low power consumption can be provided. Or a new memory element can be provided. Or a memory device with a reduced occupancy area can be provided. Or a memory device with high memory density can be provided. Or a memory device with high reliability can be provided. Or a memory device with low power consumption can be provided. Or a new memory device can be provided.

Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Therefore, one embodiment of the present invention may not have the effects listed above. Note that the other effects are effects not mentioned in this section, which will be described below. Those skilled in the art can derive the other effects from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects.

1A is a plan view of a memory element, and FIG IB is a cross-sectional view of the memory element.
2A to 2C are equivalent circuit diagrams of a memory element.
3A and 3B are plan and cross-sectional views of a memory element.
4A is a cross-sectional view of a memory element, and FIG 4B is an equivalent circuit diagram of the memory element.
5A and 5B are plan and cross-sectional views of a memory element.
6A and 6B are plan and cross-sectional views of a memory element.
7A and 7B are plan and cross-sectional views of a memory element.
8A is a cross-sectional view of a memory element, and FIG 8B is an equivalent circuit diagram of the memory element.
9A and 9B are plan and cross-sectional views of a memory element.
FIG. 10 is a cross-sectional view of a memory element.
11A is a plan view of a memory element, and FIG 11B is a cross-sectional view of the memory element.
12A is a plan view of a memory element, and FIG 12B is a cross-sectional view of the memory element.
13A is a cross-sectional view of a memory element, and FIG 13B is an equivalent circuit diagram of the memory element.
FIG. 14 is a cross-sectional view of a memory element.
FIG. 15 is a cross-sectional view of a memory element.
16A to 16E are diagrams illustrating examples of the structure of transistors.
17A and 17B are diagrams illustrating examples of the configuration of a transistor.
FIG. 18 is a diagram illustrating an example of the configuration of a transistor.
19A and 19B are diagrams illustrating examples of the configuration of a transistor.
20A to 20C are diagrams illustrating a storage device.
FIG. 21 is a diagram illustrating an example of the configuration of a storage device.
FIG. 22 is a perspective view of the semiconductor device.
23A and 23B are diagrams showing various storage devices by hierarchical level.
24A to 24J are perspective views or schematic diagrams illustrating an example of an electronic device.
25A to 25C are diagrams illustrating an example of an electronic device.

The following describes the embodiments with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the form and details can be modified in various ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments below.

In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may have semiconductor devices.

In the drawings and the like relating to this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited. Note that the drawings are schematic representations of ideal examples, and the shapes, values, etc. shown in the drawings are not limited.

In the configuration of the invention in the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Also, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be given. Also, to make the drawings easier to understand, the illustrations of some components may be omitted in perspective views, plan views, etc.

In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

In this specification, terms indicating position such as "above," "below," "upward," and "below" may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing shown by 180 degrees.

Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

In this specification, terms such as "overlap" do not limit the state of the stacking order of components. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A, the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

In this specification, the terms "adjacent" and "close to" do not limit components to being in direct contact. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact, and does not exclude the inclusion of other components between insulating layer A and electrode B.

In this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the situation, it is possible to replace the terms "film" and "layer" with other terms without using the terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, the term "conductor" may be changed to the term "conductive layer" or "conductive film". Or, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator". Or, the term "insulator" may be changed to the term "insulating layer" or "insulating film".

Note that voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) of a unit charge in an electrostatic field at a certain point. However, in general, the potential difference between the potential at a certain point and a reference potential (e.g., ground potential) is simply called potential or voltage, and potential and voltage are often used as synonyms. For this reason, in this specification and elsewhere, potential may be read as voltage, and voltage may be read as potential, unless otherwise specified.

In this specification, terms such as "electrode", "wiring", and "terminal" do not limit the functions of these components. For example, "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally. Furthermore, for example, "terminal" may be used as a part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes", "wiring", "terminals", etc. are formed integrally. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", and for example, a "terminal" can be a part of a "wiring" or "electrode". Furthermore, terms such as "electrode", "wiring", and "terminal" may be replaced with terms such as "region" depending on the circumstances.

In this specification, terms such as "wiring", "signal line", and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to "signal line". For example, the term "wiring" may be changed to "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to "wiring". Terms such as "power line" may be changed to "signal line". The opposite is also true, and terms such as "signal line" may be changed to "power line". The term "potential" applied to the wiring may be changed to "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to "potential".

In this specification, when it is explicitly stated that X and Y are connected, this includes the case where X and Y are electrically connected and the case where X and Y are functionally connected. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, this is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, but also includes connection relationships other than those shown in a figure or text.

Examples of cases where X and Y are electrically connected include cases where X and Y are directly connected in the equivalent circuit, and cases where one or more elements (e.g., switches, transistors, inductors, resistive elements, etc.) that enable the electrical connection between X and Y are connected between X and Y.

As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

In this specification and elsewhere, when referring to counting values and measurement values, terms such as "same," "equal," "uniform" (including synonyms thereof) are used, and unless otherwise specified, this includes an error of plus or minus 20%.

In addition, in the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, the "X direction" is the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and "Z direction." In addition, the X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

In this specification and the like, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying reference numeral such as "A", "b", "_1", "[n]", "[m, n]", etc. For example, opening 162 may be referred to as opening 162a, opening 162b, opening 162c, etc.

(Embodiment 1)
A memory element 100A according to one embodiment of the present invention will be described. Figures 1A and 1B are schematic diagrams illustrating a configuration example of the memory element 100A, which is a type of semiconductor device. Figure 1A is a plan view of the memory element 100A. Figure 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in Figure 1A.

The memory element 100A according to one embodiment of the present invention includes a resistance change element 600, a transistor 233, and a transistor 234. The resistance change element 600 includes an MTJ (Magnetic Tunnel Junction) element (also called a "magnetic tunnel junction element") 620 and a conductive layer 610.

MTJ elements are known as two-terminal memory elements (also called "STT-MTJ elements") that use the spin torque transfer (STT) method to read and write data, and three-terminal memory elements (also called "SOT-MTJ elements") that use the spin orbit torque (SOT) method to read and write data. SOT-MTJ elements have more terminals than STT-MTJ elements, and therefore occupy a larger area than STT-MTJ elements. On the other hand, SOT-MTJ elements have a faster write speed and higher rewrite resistance than STT-MTJ elements.

Note that a memory device constructed using multiple STT-MTJ elements is called an STT-MRAM (Spin Transfer Torque-Magnetoresistive Random Access Memory). A memory device constructed using multiple SOT-MTJ elements is called an SOT-MRAM (Spin Orbit Torque-Magnetoresistive Random Access Memory).

The memory element 100A according to one embodiment of the invention is a three-terminal type memory element that functions as an SOT-MTJ element. The memory element 100A according to one embodiment of the invention is a non-volatile memory element, and can retain written data for a long period of time even if the power supply is stopped.

<Configuration example of memory element>
A configuration example of the memory element 100A shown in Figures 1A and 1B will be described. The memory element 100A has a conductive layer 155a and a conductive layer 155b over an insulating layer 154. In addition, an insulating layer 157 is provided over the insulating layer 154, the conductive layer 155a, and the conductive layer 155b, an insulating layer 158 is provided over the insulating layer 157, and an insulating layer 159 is provided over the insulating layer 158. Note that the insulating layer 157, the insulating layer 158, and the insulating layer 159 may be collectively referred to as an insulating layer 156 or a spacer layer. In addition, a conductive layer 161a and a conductive layer 161b are provided over the insulating layer 159.

In addition, in a region overlapping with a portion of conductive layer 155a when viewed from the Z direction, conductive layer 161a, insulating layer 159, insulating layer 158, and insulating layer 157 have opening 162a. In addition, in a region overlapping with a portion of conductive layer 155b when viewed from the Z direction, conductive layer 161b, insulating layer 159, insulating layer 158, and insulating layer 157 have opening 162b.

In addition, a semiconductor layer 163a is provided on the opening 162a to cover the opening 162a, and a semiconductor layer 163b is provided on the opening 162b to cover the opening 162b.

The semiconductor layer 163a has a region that overlaps with the bottom of the opening 162a and a region that overlaps with the side of the opening 162a. The semiconductor layer 163a has a region that contacts the side of the insulating layer 156 in the opening 162a. That is, the semiconductor layer 163a has a region that contacts the side of the insulating layer 157, a region that contacts the side of the insulating layer 158, and a region that contacts the side of the insulating layer 159 in the opening 162a.

The semiconductor layer 163a also has a region in contact with the conductive layer 155a and a region in contact with the conductive layer 161a. That is, a part of the semiconductor layer 163a is electrically connected to the conductive layer 155a, and another part of the semiconductor layer 163a is electrically connected to the conductive layer 161a. The semiconductor layer 163a may also have a region that extends beyond the end of the conductive layer 161a (see FIG. 1A).

The semiconductor layer 163b has a region that overlaps with the bottom of the opening 162b and a region that overlaps with the side of the opening 162b. The semiconductor layer 163b has a region that contacts the side of the insulating layer 156 in the opening 162b. That is, the semiconductor layer 163b has a region that contacts the side of the insulating layer 157, a region that contacts the side of the insulating layer 158, and a region that contacts the side of the insulating layer 159.

The semiconductor layer 163b has a region in contact with the conductive layer 155b and a region in contact with the conductive layer 161b. That is, a part of the semiconductor layer 163b is electrically connected to the conductive layer 155b, and another part of the semiconductor layer 163b is electrically connected to the conductive layer 161b. The semiconductor layer 163b may also have a region that extends beyond the end of the conductive layer 161b (see FIG. 1A).

In addition, an insulating layer 164 is provided on the insulating layer 159, the conductive layer 161a, the conductive layer 161b, the semiconductor layer 163a, and the semiconductor layer 163b. In addition, a conductive layer 165a and a conductive layer 165b are provided on the insulating layer 164. The conductive layer 165a has a region that overlaps with the opening 162a, and in this region, the conductive layer 165a has a region that overlaps with the side and bottom of the opening 162a through the insulating layer 164 and the semiconductor layer 163a. The conductive layer 165b has a region that overlaps with the opening 162b, and in this region, the conductive layer 165b has a region that overlaps with the side and bottom of the opening 162b through the insulating layer 164 and the semiconductor layer 163b. Note that the configuration example shown in Figures 1A and 1B shows an example in which a part of the conductive layer 165 functions as the conductive layer 165a, and another part functions as the conductive layer 165b. Therefore, in this specification, the conductive layer 165 may include the conductive layer 165a and the conductive layer 165b.

The thickness of the semiconductor layer 163 is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 15 nm or less, more preferably 5 nm or more and 12 nm or less, and even more preferably 5 nm or more and 10 nm or less. The thickness of the insulating layer 164 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less. It is sufficient that at least a part of the insulating layer 164 has a region with the above-mentioned thickness.

In addition, an insulating layer 166 is provided on the insulating layer 164. It is preferable that the positions (positions in the Z direction) of the upper surfaces of the conductive layer 165a, the conductive layer 165b, and the insulating layer 166 are aligned or approximately aligned. For example, the positions of the upper surfaces of the conductive layer 165 and the insulating layer 166 can be aligned or approximately aligned by performing a chemical mechanical polishing process (CMP (Chemical Mechanical Polishing) process). By aligning or approximately aligning the positions of the upper surfaces of the conductive layer 165 and the insulating layer 166, the coverage of the insulating layer and the conductive layer formed later can be improved.

Also, it has an insulating layer 167 on the conductive layer 165 and the insulating layer 166, and a conductive layer 610 on the insulating layer 167. Also, in the region overlapping with the conductive layer 161a when viewed from the Z direction, it has a conductive layer 168a penetrating the insulating layer 167, the insulating layer 166, and the insulating layer 164. Also, in the region overlapping with the conductive layer 161b when viewed from the Z direction, it has a conductive layer 168b penetrating the insulating layer 167, the insulating layer 166, and the insulating layer 164. The conductive layer 168a is electrically connected to the first region 611 of the conductive layer 610, and the conductive layer 168b is electrically connected to the second region 612 of the conductive layer 610. Therefore, the conductive layer 610 is electrically connected to the conductive layer 161a through the conductive layer 168a. Also, the conductive layer 610 is electrically connected to the conductive layer 161b through the conductive layer 168b. Conductive layer 168a and conductive layer 168b each function as a contact plug.

In addition, when viewed from the Z direction, the conductive layer 610 has an MTJ element 620 in a region that does not overlap with the conductive layers 168a and 168b. The region on the conductive layer 610 where the MTJ element 620 overlaps is sometimes called a third region 613. The third region 613 is located between the first region 611 and the second region 612. More specifically, when viewed from the Z direction, the third region 613 is located midway along the path that connects the first region 611 to the second region 612 along the conductive layer 610.

The MTJ element 620 has a first magnetic layer 601, an insulating layer 602, and a second magnetic layer 603. The first magnetic layer 601 is provided overlapping a conductive layer 610. The insulating layer 602 is provided on the first magnetic layer 601, and the second magnetic layer 603 is provided on the insulating layer 602. The first magnetic layer 601 and the second magnetic layer 603 have an overlapping region with the insulating layer 602 interposed therebetween.

In addition, an insulating layer 614 is provided on the insulating layer 167, the conductive layer 610, and the MTJ element 620. In addition, an insulating layer 615 is provided on the insulating layer 614. In the region overlapping with the second magnetic layer 603, a conductive layer 616 is provided that penetrates the insulating layer 615 and the insulating layer 614.

In addition, a conductive layer 617 is provided on the insulating layer 615 and the conductive layer 616. The conductive layer 617 is electrically connected to the second magnetic layer 603 via the conductive layer 616. The conductive layer 616 functions as a contact plug.

The conductive layer 165 functions as a wiring WL for writing data to the memory element 100A and controlling the reading of data from the memory element 100A. The on and off states of the transistors 233 and 234 can be controlled by the potential supplied to the conductive layer 165. The conductive layer 617 functions as a wiring RBL for reading data. The conductive layer 155a functions as a wiring WBLa for writing data, and the conductive layer 155b functions as a wiring WBLb for writing data. The data to be written to the memory element 100A is determined by the direction of the current flowing between the wiring WBLa and the wiring WBLb.

When viewed from the Z direction, the memory element 100A has a transistor 233, a resistance change element 600, and a transistor 234, each of which has an area overlapping with the conductive layer 617, and which are arranged in a straight line (see FIG. 1A). By overlapping the transistor 233, the resistance change element 600, and the transistor 234 with the conductive layer 617, the area occupied by the memory element 100A can be reduced.

The conductive layer 161a functions as one of the source electrode or drain electrode of the transistor 233, and the conductive layer 155a functions as the other of the source electrode or drain electrode of the transistor 233. More specifically, a region of the conductive layer 161a in contact with the semiconductor layer 163a functions as one of the source electrode or drain electrode of the transistor 233. In addition, a region of the conductive layer 155a in contact with the semiconductor layer 163a functions as the other of the source electrode or drain electrode of the transistor 233.

The conductive layer 161b functions as one of the source electrode or drain electrode of the transistor 234, and the conductive layer 155b functions as the other of the source electrode or drain electrode of the transistor 234. More specifically, a region of the conductive layer 161b in contact with the semiconductor layer 163b functions as one of the source electrode or drain electrode of the transistor 234. In addition, a region of the conductive layer 155b in contact with the semiconductor layer 163b functions as the other of the source electrode or drain electrode of the transistor 234.

Transistor 233 and transistor 234 function as vertical transistors (transistors whose channel length direction has a component in the Z direction, the height direction, or a direction perpendicular to the surface on which the transistor is formed). Vertical transistors will be described in detail later.

Furthermore, it is preferable to use transistors having an oxide semiconductor in a channel formation region (also referred to as "OS transistors") as the transistors 233 and 234. Since the off-state current of an OS transistor is extremely small, leakage current can be significantly reduced when the memory element 100A is in a standby state (a state in which data is not written or read). Therefore, the power consumption of the memory element 100A can be reduced. Furthermore, when multiple memory elements 100A are arranged in a matrix and used in a memory device, crosstalk due to leakage current between the multiple memory elements 100A is less likely to occur by using OS transistors as transistors constituting the memory elements 100A. Therefore, the reliability of the memory device can be improved.

In addition, in the memory element 100A, the conductive layer 165 and the conductive layer 617 each extend in the X direction. In addition, in the memory element 100A, the conductive layer 155a and the conductive layer 155b each extend in the Y direction. The conductive layer 165 functioning as the wiring WL preferably intersects with at least one of the wiring WBLa and the wiring WBLb. In addition, the conductive layer 617 functioning as the wiring RBL preferably intersects with at least one of the conductive layer 155a functioning as the wiring WBLa and the conductive layer 155b functioning as the wiring WBLb. Note that the wiring WBLa and the wiring WBLb do not have to extend parallel to each other.

Figure 2A shows an equivalent circuit diagram of memory element 100A.

<Resistance change element>
The configuration of the variable resistance element 600 will be described. As described above, the variable resistance element 600 is composed of an MTJ element 620 and a conductive layer 610. A material that generates the spin Hall effect is used as the conductive layer 610. Specifically, it is preferable to use a metal material that has a strong spin-orbit interaction as the metal material. Examples of the metal material include tungsten, platinum, and tantalum. Ruthenium oxide may also be used. The conductive layer 610 may also have a topological insulator that generates the spin Hall effect, and in this case, an alloy of bismuth and antimony, an alloy of bismuth and selenium, or the like may be used.

The first magnetic layer 601 functions as a free layer in the MTJ element 620. The first magnetic layer 601 can have a magnetic moment state that is parallel or antiparallel to the magnetization direction of the second magnetic layer 603. The ferromagnetic material used in the first magnetic layer 601 is preferably, for example, a material whose magnetization is reversed by a small spin current. It is also preferable that the material is one in which magnetization reversal is unlikely to occur due to thermal energy. The ferromagnetic material used in the first magnetic layer 601 can be, for example, an alloy of one or more of iron, cobalt, and nickel. For example, an alloy of cobalt, iron, and boron (CoFeB) can be used. Other examples include an alloy of manganese and gallium (MgGa) and an alloy of manganese and germanium (MgGe).

The magnetic moment of the first magnetic layer 601 is subjected to a spin torque by the spin current generated in the conductive layer 610. The magnetization direction of the magnetic moment of the first magnetic layer 601 is reversed when the spin torque exceeds a threshold value. In other words, a current is passed from the first region 611 to the second region 612 of the conductive layer 610, and the magnetization direction of the first magnetic layer 601 can be determined by the direction of the current. For example, 1 bit of data can be recorded in the MTJ element 620 by setting the magnetization directions of the first magnetic layer 601 and the second magnetic layer 603 to be parallel as data "0" and antiparallel as data "1."

The insulating layer 602 functions as a tunnel insulating layer in the MTJ element 620. The insulating layer 602 can pass a tunnel current by applying a voltage between the first magnetic layer 601 and the second magnetic layer 603. At this time, the electrical resistance value of the MTJ element 620 changes depending on the direction of the magnetic moment of the first magnetic layer 601. Specifically, the electrical resistance value of the MTJ element 620 changes depending on whether the magnetization directions of the first magnetic layer 601 and the second magnetic layer 603 are parallel or antiparallel. This phenomenon is called the tunnel magnetoresistance effect (TMR effect). The magnitude of the TMR effect is expressed as the difference between the resistance value when the magnetization directions are parallel and antiparallel divided by the resistance value when the magnetization directions are parallel (magnetic resistance ratio, also called "MR ratio"). Note that the MTJ element is sometimes called a TMR element because it is an element that utilizes the TMR effect.

For example, magnesium oxide, aluminum oxide, etc. can be used as the insulating layer 602 that functions as a tunnel insulating layer. In particular, it is preferable to use magnesium oxide that has crystallinity. By using magnesium oxide that has crystallinity for the tunnel insulating layer, it becomes easier to achieve a high MR ratio.

The second magnetic layer 603 functions as a fixed layer (or a "reference layer") in the MTJ element 620. The second magnetic layer 603 has a ferromagnetic material. Note that the ferromagnetic material of the second magnetic layer 603 has a fixed magnetization direction, unlike the ferromagnetic material of the first magnetic layer 601. The ferromagnetic material used for the second magnetic layer 603 can be, for example, the same ferromagnetic material as the first magnetic layer 601.

Note that it is preferable to combine the ferromagnetic material and the tunnel insulating layer material contained in the MTJ element 620 so as to increase the MR ratio of the MTJ element 620.

<Example of operation of memory element>
Here, an example of a method for writing data to and reading data from the memory element 100A will be described with reference to the equivalent circuit diagram in FIG. 2A. Note that, as an example, a low-level potential (potential L) is applied to the wiring WBLb.

[Data Write]
When writing data to the memory element 100A, first, a high level potential (potential H) is applied to the wiring WL to turn on the transistors 233 and 234. Next, a level potential (potential L) is applied to the wiring WBLb, and a first potential, which is a potential higher than the potential L, is applied to the wiring WBLa. As a result, a current according to the potential difference flows from the first region 611 to the second region 612 of the conductive layer 610. Then, a spin current is generated in the conductive layer 610, and the magnetization direction of the first magnetic layer 601 is determined by the spin current. Also, when the potential L is applied to the wiring WBLa and the first potential is applied to the wiring WBLb, the direction of the current flowing through the conductive layer 610 is reversed. Then, the magnetization direction of the first magnetic layer 601 is also reversed.

In this way, the magnetization direction of the ferromagnetic material in the first magnetic layer 601 is controlled by the direction of the current flowing through the conductive layer 610. By controlling the direction of the current flowing through the conductive layer 610, data "0" or data "1" can be selected and written to the memory element 100A.

[Data Read]
When data is read from the memory element 100A, a potential L is applied to the wiring WBLa and the wiring WBLb. A potential H is also applied to the wiring WL to turn on the transistors 233 and 234. Next, a second potential higher than the potential L and lower than the first potential is applied to the wiring RBL. Then, a current flows between the wiring RBL and the wiring WBLa and between the wiring RBL and the wiring WBLb. At this time, the electric resistance value of the MTJ element 620 changes depending on whether the magnetization directions of the first magnetic layer 601 and the second magnetic layer 603 are parallel or antiparallel. Therefore, the amount of tunnel current flowing through the insulating layer 602 of the MTJ element 620 also changes. By measuring the amount of current flowing through at least one of the wiring RBL, the wiring WBLa, and the wiring WBLb, the data written in the memory element 100A can be read.

The electrical resistance value of the MTJ element 620 changes depending on the magnetization direction of the first magnetic layer 601. Therefore, the MTJ element 620 can be represented as a variable resistor, as shown in the equivalent circuit diagram of FIG. 2B.

<Modification 1 of memory element>
As shown in the equivalent circuit diagram of Fig. 2C, a configuration may be adopted in which the transistor 234 is not provided. Figs. 3A and 3B show a configuration example of a memory element 100B in which the transistor 234 is removed from the memory element 100A. Fig. 3A is a plan view of the memory element 100B. Fig. 3B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in Fig. 3A. The equivalent circuit diagram of Fig. 2C is an equivalent circuit diagram of the memory element 100B. In order to reduce repetition of explanation, differences from the memory element 100A will be mainly described.

Note that, although this embodiment shows a configuration in which transistor 234 is removed and transistor 233 is left as memory element 100B, a configuration in which transistor 233 is removed and transistor 234 is left may also be used.

The memory element 100B shown in Figures 3A and 3B has a configuration in which the conductive layer 155b, the opening 162b, and the semiconductor layer 163b are removed from the memory element 100A. Since the memory element 100B has fewer components than the memory element 100A, the area occupied by the memory element can be further reduced.

In the memory element 100B, a reference potential (for example, a ground potential (GND) or a common potential (COM)) is applied to the second region 612 of the conductive layer 610 through the conductive layer 161b. When writing data, it is necessary to change the direction of the current flowing through the conductive layer 610 depending on the value of the data to be written. That is, it is necessary to apply a potential higher or lower than the reference potential to the wiring WBLa. For this reason, the memory element 100B requires more power supply for driving than the memory element 100A. In addition, when the reference potential is a fixed potential, the amplitude of the voltage applied between the source and drain of the transistor 233 is larger than that of the memory element 100A. Therefore, it is preferable to use an OS transistor as the transistor 233. The OS transistor has a high withstand voltage between the source and drain (also referred to as a drain withstand voltage). By using an OS transistor as the transistor 233, the operation is stable even when driven at a high voltage, and high reliability is obtained.

By connecting a selection transistor to the conductive layer 617 that functions as the wiring RBL, an arbitrary wiring RBL can be selected and data stored in the memory element 100A or memory element 100B connected to the selected wiring RBL can be read. Figure 4A shows an example of a cross-sectional configuration of a memory element in which a transistor 235 is electrically connected to the conductive layer 617. Figure 4B shows an equivalent circuit diagram corresponding to the example cross-sectional configuration.

In FIG. 4A, the conductive layer 617 is electrically connected to the conductive layer 161c. Specifically, the conductive layer 617 is electrically connected to the conductive layer 161c through the conductive layer 632, the conductive layer 631, and the conductive layer 168c. The conductive layer 161c functions as one of the source electrode or drain electrode of the transistor 235. The conductive layer 155c functions as the other of the source electrode or drain electrode of the transistor 235. The conductive layer 161c can be formed at the same time as the conductive layer 161a using the same material and in the same process. The conductive layer 155c can be formed at the same time as the conductive layer 155a using the same material and in the same process. The conductive layer 165c functions as the gate electrode of the transistor 235. The conductive layer 165c can be formed at the same time as the conductive layer 165a using the same material and in the same process. The opening 162c can be formed in the same manner as the opening 162a. The semiconductor layer 163c can be formed at the same time as the semiconductor layer 163a using the same material and in the same process. Transistor 235 can be formed at the same time as transistor 233 using the same materials and in the same process.

Note that in this specification, conductive layer 155a, conductive layer 155b, and conductive layer 155c may be referred to as conductive layer 155. Also, in this specification, conductive layer 161a, conductive layer 161b, and conductive layer 161c may be referred to as conductive layer 161. Also, in this specification, opening 162a, opening 162b, and opening 162c may be referred to as opening 162. Also, in this specification, semiconductor layer 163a, semiconductor layer 163b, and semiconductor layer 163c may be referred to as semiconductor layer 163.

A conductive layer 631 is provided on the insulating layer 167. The conductive layer 631 can be formed in the same process and at the same time as the conductive layer 610 using the same material. The conductive layer 632 is provided so as to penetrate the insulating layer 615 and the insulating layer 614. The conductive layer 632 can be formed in the same process and at the same time as the conductive layer 616 using the same material. The conductive layer 168c is provided so as to penetrate the insulating layer 167, the insulating layer 166, and the insulating layer 164. The conductive layer 168c can be formed in the same process and at the same time as the conductive layer 168a using the same material.

<Modification 2 of memory element>
5A and 5B show a configuration example of a memory element 100C. The memory element 100C is a modified example of the memory element 100A. FIG. 5A is a plan view of the memory element 100C. FIG. 5B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 5A. In order to reduce repetition of explanation, differences from the memory element 100A will be mainly described.

The memory element 100C has a configuration in which a part of the conductive layer 610 is used as one of the source electrode or drain electrode of the transistor 233, and another part of the conductive layer 610 is used as one of the source electrode or drain electrode of the transistor 234. Specifically, a region of the conductive layer 610 in contact with the semiconductor layer 163a functions as one of the source electrode or drain electrode of the transistor 233. A region of the conductive layer 610 in contact with the semiconductor layer 163b functions as one of the source electrode or drain electrode of the transistor 234.

By making the conductive layer 610 function not only as a layer that generates the spin Hall effect but also as a source electrode or drain electrode of a transistor, the formation of the conductive layer 161a and the conductive layer 161b is unnecessary. This improves the productivity of the memory element 100C and reduces the manufacturing cost. This improves the productivity of a semiconductor device including the memory element 100C and reduces the manufacturing cost.

In the configuration of the memory element 100C, a region of the conductive layer 610 used as one of the source electrode or drain electrode of the transistor 233 functions as the first region 611. In addition, in the configuration of the memory element 100C, a region of the conductive layer 610 used as one of the source electrode or drain electrode of the transistor 234 functions as the second region 612.

In addition, in the configuration of memory element 100C shown in Figures 5A and 5B, in addition to conductive layer 161a and conductive layer 161b, it is not necessary to form insulating layer 166, insulating layer 167, conductive layer 168a, conductive layer 168b, and insulating layer 164. Therefore, the productivity of memory element 100C can be further improved.

In addition, in the configuration of the memory element 100C shown in Figures 5A and 5B, a part of the insulating layer 614 is used as a gate insulating layer for the transistor 233, and another part of the insulating layer 614 is used as a gate insulating layer for the transistor 234.

In addition, the memory element 100C has a conductive layer 618a that penetrates the insulating layer 615 in a region that overlaps with the conductive layer 165a when viewed from the Z direction. In addition, the memory element 100C has a conductive layer 618b that penetrates the insulating layer 615 in a region that overlaps with the conductive layer 165b when viewed from the Z direction. The conductive layer 618 (conductive layer 618a and conductive layer 618b) can be formed simultaneously in the same process using the same material as the conductive layer 616. Therefore, no new manufacturing process is required to form the conductive layer 618. Like the conductive layer 616, the conductive layer 618 also functions as a contact plug.

In addition, a conductive layer 619 is provided over the insulating layer 615, the conductive layer 618a, and the conductive layer 618b. The conductive layer 619 can be formed simultaneously with and in the same process as the conductive layer 617 using the same material. Therefore, no additional manufacturing process is required to form the conductive layer 619.

In the memory element 100A and the memory element 100B, the transistor 233, the resistance change element 600, and the transistor 234 are arranged in a line when viewed from the Z direction, but the transistor 233, the resistance change element 600, and the transistor 234 do not have to be arranged in a line. In the memory element 100C, the conductive layer 610 has a bent portion when viewed from the Z direction. In FIG. 5A, the conductive layer 610 is U-shaped when viewed from the Z direction. In the memory element 100C, the transistor 233 and the transistor 234 each have an area that overlaps with the conductive layer 619 when viewed from the Z direction. Also, the resistance change element 600 has an area that overlaps with the conductive layer 617.

In memory element 100C, when viewed from the Z direction, conductive layer 165a and conductive layer 165b do not overlap conductive layer 617. Therefore, the parasitic capacitance generated between conductive layer 617 and conductive layer 165a, and the parasitic capacitance generated between conductive layer 617 and conductive layer 165b are reduced. By reducing the parasitic capacitance, power consumption is reduced. In addition, the signal delay time is shortened, and the operating speed is improved.

Also, as shown in Figures 6A and 6B, the formation of the conductive layer 619, the conductive layer 618a, and the conductive layer 618b may be omitted. Figure 6A is a plan view of a memory element 100C different from that in Figure 5A. Also, Figure 6B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 6A.

The configuration of memory element 100C reduces the area occupied and also reduces the number of manufacturing steps. This improves the productivity of memory element 100C and reduces manufacturing costs. This improves the productivity of a semiconductor device including memory element 100C and reduces manufacturing costs.

Furthermore, the memory element 100C may be configured without either the transistor 233 or the transistor 234, as in the memory element 100B shown in Figures 3A and 3B.

<Modification 3 of memory element>
7A and 7B show a configuration example of a memory element 100D. The memory element 100D is a modified example of the memory element 100A. FIG. 7A is a plan view of the memory element 100D. FIG. 7B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 7A. In order to reduce repetition of explanation, differences from the memory element 100A will be mainly described.

Transistor 233 and transistor 234 may be provided in a layer above resistance change element 600. Memory element 100D has transistor 233 and transistor 234 on resistance change element 600. Specifically, memory element 100D has insulating layer 154 on insulating layer 615. Also, conductive layer 617, conductive layer 155a, and conductive layer 155b are provided on insulating layer 154. In the configuration of memory element 100D, conductive layer 155a and conductive layer 155b can be formed simultaneously in the same process using the same material as conductive layer 617.

In addition, the memory element 100D has an insulating layer 157 on the insulating layer 154, the conductive layer 155a, the conductive layer 155b, and the conductive layer 617.

In addition, in the memory element 100D, the conductive layer 618a and the conductive layer 618b are provided penetrating the insulating layer 614, the insulating layer 615, and the insulating layer 154. In the memory element 100D, the conductive layer 155a is electrically connected to the conductive layer 610 through the conductive layer 618a. In addition, the conductive layer 155b is electrically connected to the conductive layer 610 through the conductive layer 618b. The conductive layer 618a is electrically connected to the first region 611 of the conductive layer 610, and the conductive layer 618b is electrically connected to the second region 612 of the conductive layer 610.

In the memory element 100D, the conductive layer 155a can be referred to as one of the source electrode or drain electrode of the transistor 233. The conductive layer 161a can be referred to as the other of the source electrode or drain electrode of the transistor 233. Similarly, in the memory element 100D, the conductive layer 155b can be referred to as one of the source electrode or drain electrode of the transistor 234. The conductive layer 161b can be referred to as the other of the source electrode or drain electrode of the transistor 234.

In the configuration of memory element 100D, conductive layer 155a and conductive layer 155b can be simultaneously formed in the same process using the same material as conductive layer 617, so the number of manufacturing steps is reduced compared to memory element 100A. This improves the productivity of memory element 100D and reduces manufacturing costs. This improves the productivity of a semiconductor device including memory element 100D and reduces manufacturing costs.

By connecting a selection transistor to the conductive layer 617 that functions as the wiring RBL, an arbitrary wiring RBL can be selected and data held in the memory element 100D connected to the selected wiring RBL can be read. Figure 8A shows an example of a cross-sectional configuration of a memory element in which a transistor 235 is electrically connected to the conductive layer 617 of the memory element 100D. Also, Figure 8B shows an equivalent circuit diagram corresponding to the example cross-sectional configuration.

In FIG. 8A, the conductive layer 617 of the memory element 100D is electrically connected to the conductive layer 155c. As in the above-described transistors 233 and 234, in the memory element 100D, the conductive layer 155c can be one of the source electrode or drain electrode of the transistor 235. Also, the conductive layer 161c can be the other of the source electrode or drain electrode of the transistor 235.

In addition, the memory element 100D may also be configured without either the transistor 233 or the transistor 234, as in the memory element 100B shown in Figures 3A and 3B.

<Modification 4 of memory element>
The transistor 233, the transistor 234, and the resistance change element 600 may be provided over the same layer. 9A and 9B show a configuration example of a memory element 100E. In the memory element 100E shown in FIG. 9A and FIG. 9B, the transistor 233, the transistor 234, and the resistance change element 600 are provided over an insulating layer 154.

The memory element 100E shown in Figures 9A and 9B is a modified example of memory element 100A. Memory element 100E is also a modified example of memory element 100C and also a modified example of memory element 100D. Figure 9A is a plan view of memory element 100E. Figure 9B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Figure 9A. In order to reduce repetition of explanation, differences from memory element 100A, memory element 100C, or memory element 100D will be mainly described.

The memory element 100E has a configuration in which a part of the conductive layer 610 is used as one of the source electrode or drain electrode of the transistor 233, and another part of the conductive layer 610 is used as one of the source electrode or drain electrode of the transistor 234. Specifically, in the memory element 100E, a region of the conductive layer 610 in contact with the semiconductor layer 163a functions as one of the source electrode or drain electrode of the transistor 233. In addition, in the memory element 100E, a region of the conductive layer 610 in contact with the semiconductor layer 163b functions as one of the source electrode or drain electrode of the transistor 234.

Similar to the memory element 100D, in the memory element 100E, the conductive layer 161a can be referred to as the other of the source electrode or drain electrode of the transistor 233. Also, the conductive layer 161b can be referred to as the other of the source electrode or drain electrode of the transistor 234.

By making the conductive layer 610 function not only as a layer that generates the spin Hall effect but also as a source electrode or drain electrode of the transistor, the formation of the conductive layer 155a and the conductive layer 155b is unnecessary. Therefore, the productivity of the memory element 100E can be improved.

The memory element 100E has a conductive layer 610 on the insulating layer 154, and an MTJ element 620 on the conductive layer 610. Also, an insulating layer 158 is on the insulating layer 154, the MTJ element 620, and the insulating layer 614. In the configuration shown in Figures 9A and 9B, the insulating layer 158 and the insulating layer 614 correspond to the insulating layer 156. Note that the memory element 100E shown in Figures 9A and 9B does not have the insulating layer 157 and the insulating layer 159, but the insulating layer 157 and the insulating layer 159 may be provided as in the other exemplary memory elements. Also, the insulating layer 157 may be provided instead of the insulating layer 614.

In addition, the memory element 100E shown in Figures 9A and 9B has a conductive layer 168 that penetrates the insulating layer 167, the insulating layer 166, the insulating layer 164, the insulating layer 158, and the insulating layer 614 in the region that overlaps with the MTJ element 620 when viewed from the Z direction. Also, a conductive layer 617 is provided on the insulating layer 167. The conductive layer 617 is electrically connected to the MTJ element 620 via the conductive layer 168.

In addition, in the memory element 100E shown in Figures 9A and 9B, the region of the conductive layer 610 that overlaps with the opening 162a when viewed from the Z direction functions as the first region 611. In the first region 611, the conductive layer 610 is connected to the semiconductor layer 163a. Therefore, the first region 611 of the conductive layer 610 corresponds to the conductive layer 155a described above.

In addition, in the memory element 100E shown in Figures 9A and 9B, the region of the conductive layer 610 that overlaps with the opening 162b when viewed from the Z direction functions as the second region 612. In the second region 612, the conductive layer 610 is connected to the semiconductor layer 163b. Therefore, the second region 612 of the conductive layer 610 corresponds to the conductive layer 155b described above.

In addition, in the configuration of the memory element 100E shown in Figures 9A and 9B, in addition to the conductive layer 155a, the conductive layer 155b, etc., it is not necessary to form the insulating layer 615, the conductive layer 616, and the conductive layer 619. This further improves the productivity of the memory element 100E and further reduces the manufacturing cost. This further improves the productivity of the semiconductor device including the memory element 100E and further reduces the manufacturing cost.

Also, in the memory element 100A or the memory element 100B described above, a transistor 236 electrically connected to the conductive layer 617 may be provided in a layer above the resistance change element 600. As an example, FIG. 10 shows a cross-sectional configuration example in which a transistor 236 is provided above the memory element 100A or the memory element 100B.

In FIG. 10, insulating layer 257, insulating layer 258, and insulating layer 259 are provided on conductive layer 617, and conductive layer 261c is provided on insulating layer 259. Note that insulating layer 257, insulating layer 258, and insulating layer 259 may be collectively referred to as insulating layer 256 or spacer layer. Also, in the region overlapping with a part of conductive layer 617 when viewed from the Z direction, conductive layer 261c, insulating layer 259, insulating layer 258, and insulating layer 257 have opening 262c. Also, semiconductor layer 263c is provided on opening 262c to cover opening 262c.

In addition, an insulating layer 264 is provided on the insulating layer 259, the conductive layer 261c, and the semiconductor layer 263c. In addition, a conductive layer 265c is provided on the insulating layer 264. The conductive layer 265c has an area that overlaps with the opening 262c, and in this area, has an area that overlaps with the side and bottom of the opening 262c via the insulating layer 264 and the semiconductor layer 263c. In addition, an insulating layer 266 is provided on the insulating layer 264. Note that it is preferable that the positions (positions in the Z direction) of the upper surfaces of the conductive layer 265c and the insulating layer 266 are aligned or approximately aligned. In addition, in FIG. 10, an insulating layer 267 is provided on the conductive layer 265c and the insulating layer 266.

Transistor 236 functions in the same manner as transistor 235. Thus, insulating layer 257 corresponds to insulating layer 157, insulating layer 258 corresponds to insulating layer 158, insulating layer 259 corresponds to insulating layer 159, and insulating layer 256 corresponds to insulating layer 156. Conductive layer 261c corresponds to conductive layer 161c, and opening 262c corresponds to opening 162c. Semiconductor layer 263c corresponds to semiconductor layer 163c, insulating layer 264 corresponds to insulating layer 164, and conductive layer 265c corresponds to conductive layer 165c. Insulating layer 266 corresponds to insulating layer 166, and insulating layer 267 corresponds to insulating layer 167. Thus, transistor 236 can also be a vertical transistor, like transistors 233 and 234.

In the transistor 236, a part of the conductive layer 617 functions as one of the source electrode or drain electrode of the transistor 236. More specifically, a region of the conductive layer 617 in contact with the semiconductor layer 263c functions as one of the source electrode or drain electrode of the transistor 236. The conductive layer 261c functions as the other of the source electrode or drain electrode of the transistor 236. The conductive layer 265c functions as the gate electrode of the transistor 236.

Because the transistors 233 to 236 are thin film transistors, they can be provided on the same layer or on different layers. For example, the transistor 236 can be stacked on top of the transistor 233. This increases the design freedom of the memory element. In addition, the design freedom of the semiconductor device can be increased.

In addition, the memory element 100E may be configured without either the transistor 233 or the transistor 234, as in the memory element 100B shown in Figures 3A and 3B.

<Modification 5 of memory element>
11A and 11B show a configuration example of a memory element 100F. The memory element 100F is a modified example of the memory element 100A. FIG. 11A is a plan view of the memory element 100F. FIG. 11B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 11A. In order to reduce repetition of explanation, differences from the memory element 100A will be mainly described.

Memory element 100F has transistor 333 instead of transistor 233, and has transistor 334 instead of transistor 234. Transistors 333 and 334 are also vertical transistors like transistors 233 and 234.

In transistor 233, a part of conductive layer 165a functioning as a gate electrode is provided inside opening 162a. On the other hand, in transistor 333, conductive layer 175a functioning as a gate electrode is provided outside opening 162a when viewed from the Z direction. Also, in transistor 234, a part of conductive layer 165b functioning as a gate electrode is provided inside opening 162b. On the other hand, in transistor 334, conductive layer 175b functioning as a gate electrode is provided outside opening 162b when viewed from the Z direction.

In the case of the structures shown in transistors 233 and 234, if the width of opening 162 as viewed in the Z direction (or the diameter if opening 162 is circular) is reduced in order to miniaturize the memory element, the conductive layer 165 functioning as the gate electrode is less likely to be formed inside opening 162. In the case of the structures shown in transistors 333 and 334, the conductive layer 175 functioning as the gate electrode is outside opening 162, so the above-mentioned concern does not arise. Therefore, it is easy to reduce the area and miniaturize the memory element, and the design freedom can be increased. In addition, the memory density of a memory device using a memory element according to one embodiment of the present invention can be further increased.

The memory element 100F shown in Figures 11A and 11B has conductive layers 175a and 175b on the insulating layer 157, has an insulating layer 159 on the conductive layers 175a and 175b, and has conductive layers 161a and 161b on the insulating layer 159.

In addition, in the region overlapping with conductive layer 155a, there is an opening 162a penetrating conductive layer 161a, insulating layer 159, conductive layer 175a, and insulating layer 157. In opening 162a, there is an insulating layer 181a including a region overlapping with the side of opening 162a. Insulating layer 181a has a region overlapping with the side of conductive layer 161a, a region overlapping with the side of insulating layer 159, a region overlapping with the side of conductive layer 175a, and a region overlapping with the side of insulating layer 157.

In addition, a semiconductor layer 163a is provided on the opening 162a to cover the opening 162a. In the opening 162a, the semiconductor layer 163a has a region that overlaps with a side surface of the insulating layer 159, a region that overlaps with a side surface of the conductive layer 175a, and a region that overlaps with a side surface of the insulating layer 157, via the insulating layer 181a. The semiconductor layer 163a also has a region that contacts the conductive layer 155a and a region that contacts the conductive layer 161a. The insulating layer 181a functions as a gate insulating layer for the transistor 333, and the conductive layer 175a functions as a gate electrode for the transistor 333.

In addition, in the region overlapping with conductive layer 155b, there is an opening 162b penetrating conductive layer 161b, insulating layer 159, conductive layer 175b, and insulating layer 157. In opening 162b, there is an insulating layer 181b including a region overlapping with the side of opening 162b. Insulating layer 181b has a region overlapping with the side of conductive layer 161b, a region overlapping with the side of insulating layer 159, a region overlapping with the side of conductive layer 175b, and a region overlapping with the side of insulating layer 157.

In addition, a semiconductor layer 163b is provided on the opening 162b to cover the opening 162b. In the opening 162b, the semiconductor layer 163b has a region that overlaps with a side surface of the insulating layer 159, a region that overlaps with a side surface of the conductive layer 175b, and a region that overlaps with a side surface of the insulating layer 157, via the insulating layer 181b. The semiconductor layer 163b also has a region that contacts the conductive layer 155b and a region that contacts the conductive layer 161b. The insulating layer 181b functions as a gate insulating layer for the transistor 334, and the conductive layer 175b functions as a gate electrode for the transistor 334.

In addition, in the memory element 100F, the conductive layer 175 and the conductive layer 617 each extend in the X direction. A part of the conductive layer 175 functions as the conductive layer 175a, and another part of the conductive layer 175 functions as the conductive layer 175b. The conductive layer 175 functions as the wiring WL. As described above, it is preferable that the wiring WL intersect with at least one of the wiring WBLa or the wiring WBLb.

Furthermore, the memory element 100F may be configured without either the transistor 333 or the transistor 334, as in the memory element 100B shown in Figures 3A and 3B.

<Modification 6 of memory element>
12A and 12B show a configuration example of a memory element 100G. The memory element 100G is a modified example of the memory element 100C and is also a modified example of the memory element 100F. FIG. 12A is a plan view of the memory element 100G. FIG. 12B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 12A. In order to reduce repetition of explanation, differences from the memory element 100C or the memory element 100F will be mainly described.

Like the memory element 100C, the memory element 100G has a configuration in which a part of the conductive layer 610 is used as one of the source electrode or drain electrode of the transistor 333, and another part of the conductive layer 610 is used as one of the source electrode or drain electrode of the transistor 334. By making the conductive layer 610 function not only as a layer that generates the spin Hall effect but also as the source electrode or drain electrode of the transistor, the formation of the conductive layer 161a and the conductive layer 161b is unnecessary. This improves the productivity of the memory element 100G and reduces the manufacturing cost. This improves the productivity of a semiconductor device including the memory element 100G and reduces the manufacturing cost.

Furthermore, the memory element 100G may be configured without either the transistor 333 or the transistor 334, as in the memory element 100B shown in Figures 3A and 3B.

Also, as in the configuration example shown in FIG. 4, by connecting a selection transistor to the conductive layer 617 that functions as the wiring RBL, an arbitrary wiring RBL can be selected and data held in the memory element 100G connected to the selected wiring RBL can be read. FIG. 13A shows a cross-sectional configuration example of a memory element in which a transistor 335 is electrically connected to the conductive layer 617. FIG. 13B shows an equivalent circuit diagram corresponding to the cross-sectional configuration example.

Note that in order to reduce repetition of the description, mainly differences from the previously described configuration will be described. The description of FIG. 13 may refer to the description of FIG. 4. The transistor 335 can be formed at the same time as the transistor 333 shown in the configuration of the memory element 100F using the same material and in the same process. The conductive layer 175c of the transistor 335 can be formed at the same time as the conductive layer 175a of the transistor 333 using the same material and in the same process. The opening 162c of the transistor 335 can be formed in the same manner as the opening 162a of the transistor 333. The insulating layer 181c of the transistor 335 can be formed at the same time as the insulating layer 181a of the transistor 333 using the same material and in the same process. Note that in this specification, the insulating layers 181a, 181b, and 181c may be referred to as the insulating layer 181.

Furthermore, similar to the configuration example shown in FIG. 10, in the memory element 100F or the memory element 100G, a transistor 336 electrically connected to the conductive layer 617 may be provided in a layer above the resistance change element 600. As an example, FIG. 14 shows a cross-sectional configuration example in which a transistor 336 is provided above the memory element 100F. The transistor 336 is electrically connected to the resistance change element 600 via the conductive layer 617. Note that in order to reduce repetition of the description, mainly differences from the configuration already described will be described. The description of FIG. 14 may be explained with reference to the description of FIG. 10, etc.

In FIG. 14, insulating layer 257 and insulating layer 259 are provided on conductive layer 617, and conductive layer 261c is provided on insulating layer 259. In addition, in a region overlapping with a part of conductive layer 617 when viewed from the Z direction, conductive layer 261c, insulating layer 259, conductive layer 275c, and insulating layer 257 have opening 262c. In addition, semiconductor layer 263c is provided on opening 262c to cover opening 262c.

The opening 262c has an insulating layer 281c that includes a region that overlaps with the side of the opening 262c. The insulating layer 281c has a region that overlaps with the side of the conductive layer 261c, a region that overlaps with the side of the insulating layer 259, a region that overlaps with the side of the conductive layer 275c, and a region that overlaps with the side of the insulating layer 257. The conductive layer 275c corresponds to the conductive layer 175c in the transistor 335.

In addition, an insulating layer 264 is provided over the insulating layer 259, the conductive layer 261c, and the semiconductor layer 263c. In addition, an insulating layer 266 is provided over the insulating layer 264. Note that the surface of the insulating layer 266 is preferably flat. The transistor 336 functions in the same manner as the transistor 335.

In the transistor 336 shown in FIG. 14, a part of the conductive layer 617 functions as one of the source electrode and the drain electrode. More specifically, a region of the conductive layer 617 in contact with the semiconductor layer 263c functions as one of the source electrode and the drain electrode of the transistor 336. The conductive layer 261c functions as the other of the source electrode and the drain electrode. The conductive layer 275c functions as the gate electrode of the transistor 336.

Because the transistors 333 to 336 are thin film transistors, they can be provided on the same layer or on different layers. For example, the transistor 336 can be provided on the transistor 333. This increases the design freedom of the memory element. In addition, the design freedom of the semiconductor device can be increased.

Also, as shown in FIG. 15, a transistor 236 can be provided instead of the transistor 336. For example, when a transistor with a large on-state current is to be used as a transistor connected to the conductive layer 617 in order to speed up the potential change of the conductive layer 617 functioning as the wiring RBL, the transistor 236 can be used as the conductive layer 617. By using the transistor 333 as the transistor connected to the conductive layer 610 and the transistor 236 as the transistor connected to the conductive layer 617, a memory device with high memory density and high operating speed can be realized.

Note that the transistor connected to the conductive layer 617 is not limited to a vertical transistor. As the transistor connected to the conductive layer 617, transistors of various structures can be used, such as a top-gate type (e.g., a planar type, a staggered type, etc.), a bottom-gate type (e.g., an inverted planar type, an inverted staggered type, etc.), a dual-gate type (a structure in which gates are arranged on both sides (e.g., above and below) of a channel formation region), a FIN type, a TRI-GATE type, etc.

The transistor connected to the conductive layer 617 may be a transistor of a different conductivity type from the transistors 233 and 234. The transistor connected to the conductive layer 617 may be a transistor of a different conductivity type from the transistors 333 and 334.

<Transistor>
The conductive layer 161a functions as one of a source electrode or a drain electrode of the transistor 233. The conductive layer 155a functions as the other of the source electrode or the drain electrode of the transistor 233. The semiconductor layer 163a functions as a semiconductor layer of the transistor 233. The insulating layer 164 functions as a gate insulating layer of the transistor 233, and the conductive layer 165a functions as a gate electrode of the transistor 233.

The conductive layer 161b functions as one of the source electrode and drain electrode of the transistor 234. The conductive layer 155b functions as the other of the source electrode and drain electrode of the transistor 234. The semiconductor layer 163b functions as the semiconductor layer of the transistor 234. The insulating layer 164 functions as the gate insulating layer of the transistor 234, and the conductive layer 165b functions as the gate electrode of the transistor 234.

Transistors 233 and 234 shown in Figures 1A and 1B are transistors whose source and drain electrodes are arranged in the Z direction. That is, the sources and drains of transistors 233 and 234 are arranged at different heights. In other words, the sources and drains of transistors 233 and 234 are arranged at different positions in the Z direction. Such transistors are also called "vertical channel transistors," "vertical channel transistors," "vertical transistors," or "Vertical Field Effect Transistors (VFETs)."

Also, vertical transistors can be used for the transistors 235 and 236 shown in this specification. Also, vertical transistors can be used for the transistors 333 to 336 shown in this specification. A vertical transistor can occupy a smaller area than a conventional transistor (e.g., a planar transistor) in which a channel formation region, a source region, and a drain region are separately provided on the XY plane. Therefore, by using a vertical channel transistor, the area occupied by the memory element 100 (memory elements 100A to 100G) can be reduced. Therefore, the area occupied by a memory device including the memory element 100 can be reduced. Also, the memory density of the memory device including the memory element 100 can be increased. Also, the memory capacity per unit area of a semiconductor device using the memory element 100 can be increased. Also, by using a vertical channel transistor in a semiconductor device, the area of the semiconductor device can be reduced and the semiconductor device can be highly integrated.

In addition, in conventional transistors, the channel length is limited by the exposure limit of photolithography. In a vertical channel transistor, the channel formation region is formed along the side of the insulating layer 156 or the insulating layer 158. Therefore, the channel length can be set by the film thickness of the insulating layer 156 or the insulating layer 158. Therefore, the channel length of the transistor can be made into a very fine structure (for example, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 1 nm to 10 nm) that is less than the exposure limit of photolithography. As a result, the on-current of the transistor 233 and the transistor 234 increases, and the frequency characteristics can be improved. Since the vertical transistor has a structure that makes it easy to reduce the channel length, it is a structure that makes it easy to increase the on-current (reduce the on-resistance). By using a vertical channel transistor, a semiconductor device with a high operating speed can be provided.

Transistors 233 to 236 and transistors 333 to 336 may be n-channel transistors or p-channel transistors. N-channel transistors have a larger on-state current than p-channel transistors, and therefore the data writing speed and data reading speed can be improved. Furthermore, p-channel transistors are easier to realize as normally-off transistors (transistors that are turned off when the voltage between the source and gate is 0 V) than n-channel transistors, and therefore the operating state (on or off) of the transistors can be easily controlled, the operation of the semiconductor device can be stabilized, and the reliability of the semiconductor device can be improved.

In addition, since the operating states of the transistors 233 and 234 are switched simultaneously, it is preferable that the transistors 233 and 234 have the same conductivity type. By using the transistors 233 and 234 as transistors of the same conductivity type, both transistors can be controlled simultaneously by one wiring, and therefore the area occupied by the memory element according to one embodiment of the present invention can be reduced. For the same reason, it is also preferable that the transistors 333 and 334 have the same conductivity type.

<Constituent Materials>
Here, examples of materials that can be used for the memory element and the semiconductor device including the memory element according to one embodiment of the present invention will be described.

[substrate]
When a memory element and a semiconductor device including a memory element are provided on a substrate, there is no significant limitation on the material used for the substrate. The substrate may be determined in consideration of the presence or absence of light transmission, heat resistance to a degree that can withstand heat treatment, and the like, depending on the purpose. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. As the insulating substrate, for example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), or the like may be used. In addition, a semiconductor substrate, a flexible substrate, a resin substrate, or the like may also be used.

Semiconductor substrates include, for example, semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. In addition, there are semiconductor substrates having an insulating region inside the aforementioned semiconductor substrate, such as SOI (Silicon On Insulator) substrates. In addition, the semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.

Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc., as well as substrates having metal nitrides and substrates having metal oxides. Furthermore, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulator substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate.

Examples of materials that can be used for flexible substrates, resin substrates, etc. include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resins, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamides (nylon, aramid, etc.), polysiloxane, cycloolefin resins, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resins, and cellulose nanofibers.

By using the above materials as the substrate, a lightweight semiconductor device can be provided. In addition, by using the above materials as the substrate, a semiconductor device that is resistant to impacts can be provided. In addition, by using the above materials as the substrate, a semiconductor device that is less likely to break can be provided.

Alternatively, elements may be provided on these substrates. Elements that may be provided on the substrate include capacitance elements, resistance elements, switching elements, light-emitting elements, memory elements, etc.

[Insulating layer]
As the insulating layer, an oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, or the like having insulating properties can be used. For example, as the insulating layer, an insulating material selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or the like is used in a single layer or a stacked layer. In addition, a plurality of oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.

In this specification, an oxynitride refers to a material that contains more nitrogen than oxygen. An oxynitride refers to a material that contains more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

As transistors become finer and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a high-k material (high dielectric constant material, material with a high relative dielectric constant) for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants such as lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), and (Ba, Sr)TiO ₃ (BST) may be used as the insulating layer. On the other hand, by using a material with a low relative dielectric constant for the insulating layer that functions as the interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select a material according to the function required for the insulating layer.

Furthermore, materials with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxide nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxide nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

Materials with low dielectric constants include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, and resin.

The method for forming the insulating material is not particularly limited, and various methods such as vapor deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, and spin coating can be used.

For example, the insulating layer 154 and the insulating layer 167 are preferably formed using an insulating material that is difficult for impurities to permeate. For example, an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Examples of insulating materials that are difficult for impurities to permeate include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride.

By using an insulating material that is difficult for impurities to penetrate for the insulating layer 154, it is possible to suppress the diffusion of impurities from below and improve the reliability of the transistor. In other words, it is possible to improve the reliability of the semiconductor device including the transistor. By using an insulating material that is difficult for impurities to penetrate for the insulating layer 167, it is possible to suppress the diffusion of impurities from above the insulating layer 167 and improve the reliability of the transistor. In other words, it is possible to improve the reliability of the semiconductor device including the transistor.

In addition, an insulating layer that can function as a planarizing layer may be used as the insulating layer. Examples of materials that function as a planarizing layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimide amide, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors thereof. In addition to the above organic materials, low-k materials (low dielectric constant materials; materials with a small relative dielectric constant), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), and the like can be used. Note that multiple insulating layers made of these materials may be stacked.

The siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may also have a fluoro group.

[Conductive layer]
As a conductive material used for conductive layers such as wiring and electrodes, a metal element selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), ruthenium (Ru), etc., an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements can be used.

For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. In addition, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used. The method of forming the conductive material is not particularly limited, and various formation methods such as evaporation, ALD, CVD, sputtering, and spin coating can be used.

In addition, a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive material. A layer formed of a Cu-X alloy can be processed by a wet etching process, which makes it possible to reduce manufacturing costs. In addition, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.

In addition, as a conductive material that can be used for the conductive layer, a conductive material containing oxygen, such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with added silicon oxide, can be used. In addition, a conductive material containing nitrogen, such as titanium nitride, tantalum nitride, or tungsten nitride, can be used. In addition, the conductive layer can have a layered structure in which a conductive material containing oxygen, a conductive material containing nitrogen, or a material containing the above-mentioned metal element is appropriately combined.

For example, the conductive layer may have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is laminated on an aluminum layer, a two-layer structure in which a titanium layer is laminated on a titanium nitride layer, a two-layer structure in which a tungsten layer is laminated on a titanium nitride layer, a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer, or a three-layer structure in which a titanium layer is laminated on an aluminum layer on the titanium layer, and a titanium layer is further laminated on the aluminum layer.

In addition, multiple conductive layers formed of the above-mentioned conductive materials may be stacked. For example, the conductive layer may have a layered structure that combines the above-mentioned material containing a metal element and a conductive material containing oxygen. In addition, the conductive layer may have a layered structure that combines the above-mentioned material containing a metal element and a conductive material containing nitrogen. In addition, the conductive layer may have a layered structure that combines the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

For example, the conductive layer may have a three-layer structure in which a conductive layer containing at least one of indium or zinc and oxygen is laminated on a conductive layer containing copper, and a conductive layer containing at least one of indium or zinc and oxygen is further laminated on top of that. In this case, it is preferable to cover the side surface of the conductive layer containing copper with a conductive layer containing at least one of indium or zinc and oxygen. In addition, for example, multiple conductive layers containing at least one of indium or zinc and oxygen may be laminated as the conductive layer.

[Semiconductor layer]
As the semiconductor layer, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, not only a single semiconductor whose main component is a single element (e.g., silicon, germanium, etc.) but also a compound semiconductor (e.g., silicon germanium, silicon carbide, gallium arsenide, nitride semiconductor, etc.) can be used. As the compound semiconductor, an organic material having semiconductor properties or a metal oxide having semiconductor properties (also called an "oxide semiconductor") can be used. Note that these semiconductor materials may contain impurities as dopants.

For example, the semiconductor layer may be made of single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon. As the polycrystalline silicon, for example, low temperature polysilicon (LTPS) may be used.

Transistors that use amorphous silicon for the semiconductor layer can be formed on large glass substrates and can be manufactured at low cost. Transistors that use polycrystalline silicon for the semiconductor layer have high field effect mobility and can operate at high speed. Transistors that use microcrystalline silicon for the semiconductor layer have higher field effect mobility and can operate at high speed than transistors that use amorphous silicon.

The semiconductor layer may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS ₂ ), molybdenum selenide (representatively MoSe ₂ ), molybdenum tellurium (representatively MoTe ₂ ), tungsten sulfide (representatively WS ₂ ), tungsten selenide (representatively WSe ₂ ), tungsten tellurium (representatively WTe ₂ ), hafnium sulfide (representatively HfS ₂ ), hafnium selenide (representatively HfSe ₂ ), zirconium sulfide (representatively ZrS ₂ ), zirconium selenide (representatively ZrSe ₂ ), and the like.

In addition, since an oxide semiconductor has a band gap of 2 eV or more, a transistor having an oxide semiconductor in a channel formation region (also referred to as an "OS transistor") has an extremely low off-state current. The off-state current value of an OS transistor per 1 μm of channel width in a room temperature environment can be 1 aA (1×10 ⁻¹⁸ A) or less, 1 zA (1×10 ⁻²¹ A) or less, or 1 yA (1×10 ⁻²⁴ A) or less. In addition, the OS transistor operates stably even in a high-temperature environment, has little fluctuation in characteristics, and has high reliability. For example, the off-state current of an OS transistor hardly increases even in a high-temperature environment of 125° C. or more and 200° C. or less. In addition, the on-state current is not easily decreased even in a high-temperature environment. Thus, good switching operation can be achieved even in a high-temperature environment.

In addition, OS transistors have a high drain withstand voltage. Therefore, a semiconductor device using an OS transistor has stable operation and high reliability even when driven at a high voltage.

Examples of metal oxides used in oxide semiconductors include indium oxide, gallium oxide, and zinc oxide. Metal oxides used in oxide semiconductors preferably contain at least indium (In) or zinc (Zn). Metal oxides used in oxide semiconductors preferably contain two or three elements selected from indium, element M, and zinc. Element M is a metal element or semimetal element that has a high bond energy with oxygen, for example, a metal element or semimetal element that has a higher bond energy with oxygen than indium.

Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

For example, metal oxides used in oxide semiconductors include indium oxide (In oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as "GZO"), aluminum zinc oxide (Al-Zn oxide, also written as "AZO"), Indium aluminum zinc oxide (In-Al-Zn oxide, also written as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as "IGAZO" or "IAGZO"), etc., can be used. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide used in the oxide semiconductor, the field-effect mobility of the OS transistor can be increased.

Note that the metal oxide may have one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may have one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field effect mobility of the transistor may be increased. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

The metal oxide may also contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field effect mobility of the transistor may be increased. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the number of atoms of the metal elements among the main component elements contained in the metal oxide, a metal oxide with high crystallinity can be obtained, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of the metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

The electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that combines excellent electrical characteristics and high reliability can be realized.

When In-Zn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc may be used. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a ratio close to these may be used.

When an In-Sn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin may be used. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a ratio close to these may be used.

When an In-Sn-Zn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of tin may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of tin. For example, the atomic ratios of metal elements are In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, I It is also possible to use metal oxides such as In:Sn:Zn = 10:1:3, In:Sn:Zn = 10:1:6, In:Sn:Zn = 10:1:7, In:Sn:Zn = 10:1:8, In:Sn:Zn = 5:2:5, In:Sn:Zn = 10:1:10, In:Sn:Zn = 20:1:10, In:Sn:Zn = 40:1:10, or similar metal oxides.

When an In-Al-Zn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of aluminum may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum. For example, the atomic ratios of metal elements are In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1:6, I n:Al:Zn = 10:1:3, In:Al:Zn = 10:1:6, In:Al:Zn = 10:1:7, In:Al:Zn = 10:1:8, In:Al:Zn = 5:2:5, In:Al:Zn = 10:1:10, In:Al:Zn = 20:1:10, In:Al:Zn = 40:1:10, or metal oxides close to these may also be used.

When an In-Ga-Zn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of gallium may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. For example, the semiconductor layer may have an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1: 6, In:Ga:Zn = 10:1:3, In:Ga:Zn = 10:1:6, In:Ga:Zn = 10:1:7, In:Ga:Zn = 10:1:8, In:Ga:Zn = 5:2:5, In:Ga:Zn = 10:1:10, In:Ga:Zn = 20:1:10, In:Ga:Zn = 40:1:10, or metal oxides close to these may also be used.

When In-M-Zn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of element M may be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M. For example, the semiconductor layer may have an atomic ratio of metal elements of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1: 6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides close to these may also be used.

When In-M-Zn oxide is used for the semiconductor layer, the atomic ratio of the metal elements may be In:M:Zn = 1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn = 1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn = 1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn = 4:2:3 [atomic ratio] or a composition close thereto. Note that the composition close thereto includes a range of ±30% of the desired atomic ratio. It is also preferable to use gallium as the element M.

When element M has multiple metal elements, the sum of the atomic ratios of the metal elements can be the atomic ratio of element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be the atomic ratio of element M. In addition, it is preferable that the atomic ratios of indium, element M, and zinc are within the above-mentioned range.

It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the sum of the atomic numbers of the metal elements among the main component elements contained in the metal oxide is 30 atomic % or more and 100 atomic %, preferably 30 atomic % or more and 95 atomic %, more preferably 35 atomic % or more and 95 atomic %, more preferably 35 atomic % or more and 90 atomic %, more preferably 40 atomic % or more and 90 atomic %, more preferably 45 atomic % or more and 90 atomic %, more preferably 50 atomic % or more and 80 atomic %, more preferably 60 atomic % or more and 80 atomic %, more preferably 70 atomic % or more and 80 atomic %. For example, when In-M-Zn oxide is used for the semiconductor layer, it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is in the above-mentioned range.

As described above, the field-effect mobility of an OS transistor can be increased by increasing the ratio of the number of indium atoms to the sum of the number of atoms of the metal elements among the main component elements contained in the metal oxide. By using such a transistor, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced.

The composition of metal oxides can be analyzed using, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. In addition, for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

The metal oxide is preferably formed by sputtering or ALD. When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be about 40% to 90% of the atomic ratio of zinc contained in the target.

When a metal oxide film is formed by sputtering, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.

Here, we will explain the reliability of transistors. One of the indicators for evaluating the reliability of transistors is the GBT (Gate Bias Temperature) stress test, in which an electric field is applied to the gate and the transistor is held at high temperature. Among these, a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and drain potential and the transistor is held at high temperature is called a PBTS (Positive Bias Temperature Stress) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at high temperature is called an NBTS (Negative Bias Temperature Stress) test. Additionally, the PBTS test and NBTS test performed under light irradiation are called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

In the case of n-type transistors, a positive potential is applied to the gate when the transistor is turned on, so the amount of variation in threshold voltage during PBTS testing is one of the important items to note as an indicator of the reliability of the transistor.

By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability when a positive bias is applied can be obtained. In other words, a transistor with a small amount of variation in threshold voltage in a PBTS test can be obtained. In addition, when using a metal oxide that contains gallium, it is preferable to make the gallium content lower than the indium content. This makes it possible to realize a highly reliable transistor.

One of the factors that causes the threshold voltage to vary during the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the more significant the degradation during the PBTS test. By lowering the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of these defect levels can be suppressed.

The reason why the use of a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer can suppress the variation in threshold voltage in the PBTS test is thought to be, for example, as follows. The gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, gallium combines with excess oxygen in the gate insulating layer, making it easier to create carrier (here, electron) trap sites. Therefore, it is thought that when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, causing the threshold voltage to vary.

More specifically, when In-Ga-Zn oxide is used for the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than that of gallium can be applied to the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. In other words, it is preferable to apply a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga to the semiconductor layer.

For example, the atomic ratio of metal elements in the semiconductor layer of an OS transistor is In:Ga:Zn = 2:1:3, In:Ga:Zn = 3:1:2, In:Ga:Zn = 4:2:3, In:Ga:Zn = 4:2:4.1, In:Ga:Zn = 5:1:3, In:Ga:Zn = 5:1:6, In:Ga:Zn = 5:1:7, In:Ga:Zn = 5:1:8, In:Ga:Zn = 6:1:6, In:Ga:Zn = 10:1:3, In:Ga:Zn = 10:1:6, In:Ga:Zn = 10:1:7, In:Ga:Zn = 10:1:8, In:Ga:Zn = 5:2:5, In:Ga:Zn = 10:1:10, In:Ga:Zn = 20:1:10, In:Ga:Zn = 40:1:10, or metal oxides close to these can be used.

The semiconductor layer of the OS transistor preferably uses a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is higher than 0 atomic % and 50 atomic % or less, preferably 0.1 atomic % to 40 atomic % or less, more preferably 0.1 atomic % to 35 atomic % or less, more preferably 0.1 atomic % to 30 atomic % or less, more preferably 0.1 atomic % to 25 atomic % or less, more preferably 0.1 atomic % to 20 atomic % or less, more preferably 0.1 atomic % to 15 atomic % or less, and more preferably 0.1 atomic % to 10 atomic % or less. By lowering the content of gallium in the semiconductor layer, a transistor with high resistance to a PBTS test can be obtained. Note that by containing gallium in the metal oxide, an effect is achieved in that oxygen vacancy ( _VO : oxygen vacancy) is less likely to occur in the metal oxide.

A metal oxide that does not contain gallium may be applied to the semiconductor layer of an OS transistor. For example, In-Zn oxide may be applied to the semiconductor layer. In this case, the field effect mobility of the transistor can be increased by increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide. On the other hand, by increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide, the metal oxide becomes highly crystalline, so that the fluctuation in the electrical characteristics of the transistor is suppressed and the reliability can be increased. In addition, a metal oxide that does not contain gallium and zinc, such as indium oxide, may be applied to the semiconductor layer. By using a metal oxide that does not contain gallium, the fluctuation in the threshold voltage, particularly in a PBTS test, can be made extremely small.

For example, an oxide containing indium and zinc can be used for the semiconductor layer. In this case, a metal oxide having an atomic ratio of metal elements of, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these can be used.

Note that, although gallium has been used as a representative example, the present invention can also be applied to the case where element M is used instead of gallium. It is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M for the semiconductor layer. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.

By applying a metal oxide with a low content of element M to the semiconductor layer, a transistor with high reliability when a positive bias is applied can be realized. By applying this transistor to a transistor that requires high reliability when a positive bias is applied, a semiconductor device with high reliability can be realized.

The semiconductor layer may have a stacked structure having two or more metal oxide layers. The two or more metal oxide layers of the semiconductor layer may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, they can be formed using the same sputtering target, thereby reducing manufacturing costs.

The two or more metal oxide layers in the semiconductor layer may have different compositions. For example, a laminate structure of a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto provided on the first metal oxide layer is preferable. In addition, it is particularly preferable to use gallium or aluminum as the element M. For example, a laminate structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.

In addition, for example, a laminated structure may be used, which includes a first metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, and a second metal oxide layer having a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto, which is provided on the first metal oxide layer.

The semiconductor layer is preferably a crystalline metal oxide layer. For example, a metal oxide layer having a CAAC (c-axis aligned crystalline) structure, a polycrystalline (polycrystalline) structure, a nanocrystalline (nc: nanocrystalline) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer, the defect level density in the semiconductor layer can be reduced, and a highly reliable display device can be realized. The CAAC structure is a crystal structure in which multiple microcrystals (typically multiple IGZO microcrystals) have a c-axis orientation, and the multiple microcrystals are connected without being oriented in the a-b plane. The CAAC structure has fewer crystal grain boundaries and grains in the a-b plane than the polycrystalline structure, and therefore a highly reliable semiconductor device can be realized.

The higher the crystallinity of the metal oxide layer used in the semiconductor layer, the more the density of defect states in the semiconductor layer can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

When a metal oxide layer is formed by sputtering, the higher the substrate temperature (stage temperature) during formation, the more crystalline the metal oxide layer can be formed. Also, the higher the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), the more crystalline the metal oxide layer can be formed.

The semiconductor layer of the OS transistor may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer may be used, and the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers in the semiconductor layer may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the stacked structure, which can reduce manufacturing costs. For example, the same sputtering target may be used to form a stacked structure of two or more metal oxide layers with different crystallinity by changing the oxygen flow rate ratio. Note that the two or more metal oxide layers in the semiconductor layer may have different compositions.

When an oxide semiconductor is used for the semiconductor layer 163 of the transistors 233 to 236, it is preferable to use a material containing hydrogen for the insulating layers 157 and 159. When the insulating layer containing hydrogen is in contact with the oxide semiconductor, the oxide semiconductor in the region in contact with the insulating layer becomes n-type and can function as a source region or a drain region. For example, a material containing silicon, nitrogen, and hydrogen may be used for the insulating layer. Specifically, silicon nitride containing hydrogen, silicon nitride oxide containing hydrogen, or the like may be used.

The thickness of each of insulating layer 157 and insulating layer 159 is preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, more preferably 3 nm or more and 7 nm or less, and even more preferably 3 nm or more and 5 nm or less. When an oxide semiconductor is used for semiconductor layer 163, a region of semiconductor layer 163 in contact with insulating layer 157 containing hydrogen and a region in contact with insulating layer 159 containing hydrogen function as a source region or a drain region. By adjusting the thickness of insulating layer 157 and insulating layer 159, the size of the source region and the drain region formed in semiconductor layer 163 can be controlled.

The thickness of the insulating layer 158 is preferably 1 nm or more and 50 nm or less, more preferably 2 nm or more and 30 nm or less, and even more preferably 3 nm or more and 20 nm or less. By adjusting the thickness of the insulating layer 158, the size of the channel formation region of the semiconductor layer 163 can be controlled.

The film thicknesses of insulating layers 157, 158, and 159 may be set appropriately according to the characteristics desired for the transistor.

In addition, it is preferable to deposit insulating layers 157, 158, and 159 in succession without exposing them to the atmospheric environment in between. By depositing insulating layers 157, 158, and 159 in succession without exposing them to the atmospheric environment in between, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the interface between insulating layers 157 and 158 and their vicinity, and to the interface between insulating layers 158 and 159 and their vicinity.

When an oxide semiconductor is used for the semiconductor layer 163, it is preferable that the conductive layer 155 in contact with the semiconductor layer 163 and the conductive layer 161 in contact with the semiconductor layer 163 are made of a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Another conductive material may be provided over the conductive material containing nitrogen.

On the other hand, when an oxide semiconductor is used for the semiconductor layer 163 of the transistors 233 to 236, it is preferable to use a material in which hydrogen is reduced and which contains oxygen for the insulating layer 158. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Since hydrogen is an impurity element in an oxide semiconductor, when the semiconductor layer 163 which is an oxide semiconductor is in contact with the insulating layer 158 in which hydrogen is reduced, the semiconductor layer 163 is less likely to become n-type. Furthermore, when the semiconductor layer 163 which is an oxide semiconductor is in contact with the insulating layer 158 which contains oxygen, oxygen vacancies in the semiconductor layer 163 are reduced, and the characteristics of the transistor are stabilized, leading to improved reliability.

Note that in the structures of the transistors 333 to 336, the semiconductor layer 163 is not in contact with the insulating layer 157 and the insulating layer 159. In the structures of the transistors 333 to 336, the semiconductor layer 163 is in contact with the insulating layer 181a and the insulating layer 164. When an oxide semiconductor is used for the semiconductor layer 163 of the transistors 333 to 336, it is preferable to use a material in which hydrogen is reduced and which contains oxygen for each of the insulating layer 181a and the insulating layer 164.

When an oxide semiconductor is used for the semiconductor layer 163 of the transistors 233 to 236, the insulating layer 158 preferably contains excess oxygen. In this specification and the like, the term "excess oxygen" refers to oxygen that is released by heating. When a material containing excess oxygen is used for the insulating layer 158, it is preferable to use a material through which oxygen is unlikely to permeate for the insulating layer 157 and the insulating layer 159. As a material through which oxygen is unlikely to permeate, for example, an oxide containing one or both of aluminum and hafnium, a nitride of silicon, or the like can be used. By using a material through which oxygen is unlikely to permeate for the insulating layer 157 and the insulating layer 159, the excess oxygen contained in the insulating layer 158 is unlikely to be released to the lower or upper layer. Thus, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure may be used in which an insulating layer (insulating layer 158) containing silicon and oxygen is provided between two insulating layers (insulating layer 157 and insulating layer 159) containing silicon and nitrogen.

For the same reason, when an oxide semiconductor is used for the semiconductor layer 163 of the transistors 333 to 336, it is preferable that the insulating layer 181 contain excess oxygen. In addition, it is preferable that the insulating layer 164 in contact with the semiconductor layer 163 also contain excess oxygen.

In addition, by using an oxide semiconductor for the semiconductor layer 163 of the transistors 233 to 236 and using a material containing hydrogen for the insulating layer 157 and the insulating layer 159, hydrogen is supplied to the region of the semiconductor layer 163 in contact with the insulating layer 157 and the region of the semiconductor layer 163 in contact with the insulating layer 159, and each region of the semiconductor layer 163 becomes n-type. Therefore, the region of the semiconductor layer 163 in contact with the conductive layer 161 and the region of the semiconductor layer 163 in contact with the insulating layer 159 function as one of the source (source region) and the drain (drain region). In addition, the region of the semiconductor layer 163 in contact with the conductive layer 155 and the region of the semiconductor layer 163 in contact with the insulating layer 157 function as the other of the source (source region) and the drain (drain region).

Figure 16A shows an enlarged cross-section of the transistor 233 shown in Figure 1B. In the above configuration, in the transistor 233, which is a VFET, the length of the side of the insulating layer 158 at the opening 162a when viewed from the X direction or the Y direction becomes the channel length L (channel length L1). Therefore, the channel length L of the transistor 233 is determined according to the thickness t1 of the insulating layer 158.

In addition, the insulating layer 157 and the insulating layer 159 may be made of a material that does not contain hydrogen or contains very little hydrogen. For example, silicon nitride containing very little hydrogen or silicon nitride oxide containing very little hydrogen may be used. In this case, the region where the semiconductor layer 163a is in contact with the insulating layer 157 and the region where the semiconductor layer 163a is in contact with the insulating layer 159 are not made n-type. Therefore, the region of the semiconductor layer 163a in contact with the conductive layer 161a functions as one of the source (source region) and the drain (drain region). The region of the semiconductor layer 163a in contact with the conductive layer 155a functions as the other of the source (source region) and the drain (drain region). The region of the semiconductor layer 163a in contact with the side of the insulating layer 158 functions as a channel formation region.

In this case, the sum of the lengths of the sides of insulating layers 157, 158, and 159 in opening 162a when viewed from the X or Y direction is channel length L (channel length L2). Therefore, the channel length L of transistor 233 is determined according to thickness t2, which is the sum of the thicknesses of insulating layers 157, 158, and 159.

17A and 17B show a modified example of FIG. 16A. For example, only insulating layer 158 may be provided without providing insulating layer 157 and insulating layer 159, and insulating layer 158 may be in contact with conductive layer 155a and conductive layer 161a (see FIG. 17A). In this case, the length of the side surface of insulating layer 158 in opening 162a when viewed from the X direction or Y direction becomes channel length L (channel length L2). Therefore, the channel length L of transistor 233 is determined according to the thickness of insulating layer 158. In addition, in the case of the configuration shown in FIG. 17A, insulating layer 158 may be called insulating layer 156. Note that channel length L2 shown in FIG. 17A is synonymous with channel length L2 shown in FIG. 16A, and thickness t2 shown in FIG. 17A is synonymous with thickness t2 shown in FIG. 16A.

Furthermore, if an oxide semiconductor is used for the semiconductor layer 163a, a material containing hydrogen is used for the insulating layers 157 and 159, and a material containing excess oxygen is used for the insulating layer 158, the hydrogen contained in the insulating layers 157 and 159 will combine with the excess oxygen contained in the insulating layer 158, and sufficient hydrogen will not be supplied to the region of the semiconductor layer 163a in contact with the insulating layer 157 and the region of the semiconductor layer 163a in contact with the insulating layer 159, making it difficult to make the semiconductor layer 163a n-type. Similarly, sufficient oxygen will not be supplied to the region of the semiconductor layer 163a in contact with the insulating layer 158.

To solve this problem, insulating layer 171, which is difficult for oxygen and nitrogen to permeate, may be provided between insulating layer 157 and insulating layer 158, and insulating layer 172, which is difficult for oxygen and nitrogen to permeate, may be provided between insulating layer 159 and insulating layer 158 (see FIG. 17B). The material that is difficult for oxygen and nitrogen to permeate may be realized using, for example, silicon nitride. In the configuration shown in FIG. 17B, insulating layer 157, insulating layer 171, insulating layer 158, insulating layer 172, and insulating layer 159 may be collectively referred to as insulating layer 156.

By using a material that is difficult for oxygen to permeate for insulating layers 171 and 172, the bonding between the hydrogen contained in insulating layers 157 and 159 and the excess oxygen contained in insulating layer 158 is inhibited. Therefore, sufficient hydrogen is supplied to the region of semiconductor layer 163a that contacts insulating layer 157 and the region of semiconductor layer 163a that contacts insulating layer 159. Similarly, sufficient oxygen is supplied to the region of semiconductor layer 163a that contacts insulating layer 158.

In this case, the sum of the lengths of the sides of insulating layer 171, insulating layer 158, and insulating layer 172 at opening 162a when viewed from the X direction or Y direction is channel length L3. Therefore, the channel length L of transistor 233 is determined according to thickness t3, which is the sum of the thicknesses of insulating layer 171, insulating layer 158, and insulating layer 172.

The channel length L of the transistor 233 is determined according to the thickness of the insulating layer provided between the conductive layer 161a and the conductive layer 155a. Therefore, a transistor with a short channel length L can be manufactured with high precision. In addition, the characteristic variation between multiple transistors is also reduced. Therefore, the operation of a semiconductor device including the transistor 233 is stabilized, and the reliability can be improved. Furthermore, the reduction in the characteristic variation increases the degree of freedom in the circuit design of the semiconductor device, and the operating voltage can also be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

Note that in this embodiment, a configuration having three insulating layers (insulating layer 157, insulating layer 158, insulating layer 159) or five insulating layers (insulating layer 157, insulating layer 158, insulating layer 159, insulating layer 171, insulating layer 172) between conductive layer 155a and conductive layer 161a is shown, but the number of insulating layers between conductive layer 155a and conductive layer 161a is not limited to this. The number of insulating layers between conductive layer 155a and conductive layer 161a may be one or two, or may be four or six or more.

In addition, to improve the coverage of the semiconductor layer 163a, insulating layer 164, and conductive layer 165a formed in the opening 162a, the taper angle θ of the side of the opening 162a, i.e., the taper angle θ of each of the side of the insulating layer 157, insulating layer 158, and insulating layer 159, may be set to 45 degrees or more and 90 degrees or less, preferably 50 degrees or more and 75 degrees or less. Note that the taper angle θ of the side of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle between the bottom surface of the layer and the side surface (see FIG. 16A).

Also, as shown in FIG. 18, if there is no problem with the coverage of the semiconductor layer 163a, the insulating layer 164, and the conductive layer 165a, the side of the opening 162a may be perpendicular or approximately perpendicular to the surface on which the opening 162a is formed (for example, the top surface of the conductive layer 155a). By making the side of the opening 162a perpendicular or approximately perpendicular, the area occupied by the transistor 233 can be reduced. Therefore, the area occupied by the memory element including the transistor 233 can be reduced.

In addition, since the semiconductor layer 163a is provided in the opening 162a, the perimeter of the opening 162a when viewed from the Z direction is the channel width W of the transistor 233 (see FIG. 16B). The perimeter may be determined, for example, at a position halfway to the thickness t1 or halfway to the thickness t2 of the insulating layer 158. If necessary, the perimeter of any position of the opening 162a may be taken as the channel width W. For example, the perimeter of the bottom of the opening 162a may be taken as the channel width W, or the perimeter of the top of the opening 162a may be taken as the channel width W.

In addition, in a memory device according to one embodiment of the present invention, the channel length L is preferably at least smaller than the channel width W. In one embodiment of the present invention, the channel length L is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W.

In addition, in FIG. 16B, the outline (planar shape) of the opening 162a viewed from the Z direction is shown as a circle, but is not limited to this. For example, the outline of the opening 162a viewed from the Z direction may be an ellipse (see FIG. 16C) or a rectangle (see FIG. 16D). Note that FIG. 16D shows a rectangle with curved corners. In addition, for example, the outline of the opening 162a viewed from the Z direction may be a shape that includes one or both of straight and curved portions (see FIG. 16E).

It is preferable that the opening 162a is fine. For example, the maximum width of the opening 162a as viewed from the Z direction is preferably 60 nm or less, more preferably 50 nm or less, even more preferably 40 nm or less, and most preferably 30 nm or less. The maximum width of the opening 162a as viewed from the Z direction may be 20 nm or less. It is preferable that the minimum width of the opening 162a as viewed from the Z direction is 1 nm or more, and more preferably 5 nm or more. To form such fine openings 162a, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

Note that transistors 234 to 236 have the same structure as transistor 233. To reduce repetition of the explanation, the explanation of transistors 234 to 236 will be omitted.

Figure 19A shows an enlarged cross-section of transistor 333 shown in Figure 11B. Transistor 333 is also a modified example of transistor 233. In transistor 333, which is a VFET, the length of the side of conductive layer 175a in opening 162a becomes channel length L (channel length L4) when viewed from the X direction or Y direction. Therefore, the channel length L of transistor 333 is determined according to thickness t4 of conductive layer 175a. When viewed from the X direction or Y direction, the region of semiconductor layer 163a that overlaps with conductive layer 175a functions as a channel formation region.

In addition, the transistor 333 has a structure in which the channel formation region is electrically surrounded by the electric field of the conductive layer 175a that functions as the gate electrode, so it can also be said to have a GAA (Gate All Around) structure.

Figure 19B shows a modified example of Figure 19A. The transistor 333 may have a conductive layer 165 on the insulating layer 164 in a region overlapping with the opening 162a when viewed from the Z direction. In the configuration shown in Figure 19B, both the conductive layer 165 and the conductive layer 175 can function as gate electrodes. In the configuration shown in Figure 19B, one of the conductive layer 165 or the conductive layer 175 may be called a "gate electrode" and the other may be called a "back gate electrode." In addition, one of the conductive layer 165 or the conductive layer 175 may be called a "first gate electrode" and the other may be called a "second gate electrode." For example, the conductive layer 165 may be called a "gate electrode" and the conductive layer 175 may be called a "back gate electrode."

The gate electrode and the back gate electrode are arranged so as to sandwich the semiconductor layer between them. Both the gate electrode and the back gate electrode are formed of a conductive layer. When the gate electrode is used to control the on and off states of the transistor, the potential of the back gate electrode may be the same as that of the gate electrode, or may be GND or any other potential. The threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently of the gate electrode. In addition, since the gate electrode and the back gate electrode are formed of a conductor, they have a function of preventing an electric field generated outside the transistor from acting on the semiconductor in which the channel is formed (particularly an electric field shielding function against static electricity, etc.). By providing a back gate electrode in addition to the gate electrode, the characteristic variation between transistors can be reduced.

19B, when the conductive layer 165 is used as a gate electrode, the distance from the upper surface of the conductive layer 155a to the upper surface of the conductive layer 161a when viewed from the X direction or the Y direction is the channel length L (channel length L5). In this case, when viewed from the X direction or the Y direction, the total length of each side of the insulating layer 157, the conductive layer 175a, the insulating layer 159, and the conductive layer 161a in the opening 162a is the channel length L5. Therefore, the channel formation region of the transistor 333 has a region along the side of the insulating layer 157, a region along the side of the conductive layer 175a, a region along the side of the insulating layer 159, and a region along the side of the conductive layer 161a. The channel length L of the transistor 333 shown in FIG. 19B is determined according to the thickness t5 obtained by adding up the thicknesses of the insulating layer 157, the conductive layer 175a, the insulating layer 159, and the conductive layer 161a.

Note that transistors 334 to 336 have the same structure as transistor 333. To reduce repetition of the description, the description of transistors 334 to 336 will be omitted.

The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

(Embodiment 2)
In this embodiment, a memory cell array 200 including a memory element 100 according to one embodiment of the present invention and a memory device 300 including the memory cell array 200 will be described.

<Storage device 300>
20A is a block diagram illustrating a configuration example of a memory device 300 including the memory element 100 of one embodiment of the present invention. The memory device 300 illustrated in FIG.

The memory cell array 200 includes a plurality of memory elements 100 arranged in a matrix of m rows and n columns (m and n are each an integer greater than or equal to 1). By arranging a plurality of memory elements 100 in a matrix, a memory device with a large memory capacity can be realized.

In FIG. 20A, the memory element 100 in the first row and first column is indicated as memory element 100[1,1], the memory element 100 in the mth row and nth column is indicated as memory element 100[m,n], the memory element 100 in the mth row and first column is indicated as memory element 100[m,1], the memory element 100 in the first row and nth column is indicated as memory element 100[1,n], the memory element 100 in the mth row and nth column is indicated as memory element 100[m,n], and the memory element 100 in the ith row and jth column is indicated as memory element 100[i,j]. Note that i is an integer of 1 to m indicating an arbitrary row, and j is an integer of 1 to n indicating an arbitrary column.

Note that rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction (direction along the X axis) is referred to as the "row" and the Y direction (direction along the Y axis) is referred to as the "column", but the X direction may be referred to as the "column" and the Y direction as the "row".

The drive circuit 21 has a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 has a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

In the memory device 300, each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal.

Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by control circuit 32.

The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

The voltage generation circuit 33 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when a signal of potential H is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a voltage.

The peripheral circuit 41 is a circuit for writing and reading data to the memory element 100. The peripheral circuit 41 has a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit 48.

The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to be accessed, and the column decoder 44 is a circuit for specifying the column to be accessed. The row driver 43 has the function of selecting the wiring specified by the row decoder 42. The column driver 45 has the function of writing data to the memory element 100, reading data from the memory element 100, and retaining the read data.

The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) to be written to the memory element 100. The data (Dout) read from the memory element 100 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is the signal RDA.

PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply potential of the memory device 300 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to set the word line to potential H, and is higher than VDD. The on/off of PSW22 is controlled by signal PON1, and the on/off of PSW23 is controlled by signal PON2. In FIG. 20A, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it is also possible to have multiple power domains. In this case, a power switch can be provided for each power supply domain.

The memory cell array 200 and the drive circuit 21 may be stacked. By stacking the memory cell array 200 and the drive circuit 21, the area occupied by the memory device 300 can be reduced. For example, as shown in FIG. 20B, the memory device 300 has a stacked structure of layers 10 and 20, the drive circuit 21 is formed in layer 10, and the memory cell array 200 is formed in layer 20.

For example, a silicon substrate may be used as layer 10, and drive circuit 21 may be formed on the silicon substrate. By using a silicon substrate as layer 10, transistors that have silicon in their channel formation regions (Si transistors) may be used as transistors that make up drive circuit 21. In addition, by using a single-crystal silicon substrate as layer 10, single-crystal Si transistors that have single-crystal semiconductor in their channel formation regions and have high operating speeds may be used as transistors that make up drive circuit 21.

Also, for example, an SOI substrate may be used as the layer 10. As the SOI substrate, a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer at a certain depth from the surface and eliminate defects in the surface layer, a Smart Cut method in which a semiconductor substrate is cleaved by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment, an ELTRAN method (registered trademark: Epitaxial Layer Transfer), or the like may be used. A Si transistor fabricated using an SOI substrate has reduced parasitic capacitance and can achieve high-speed operation.

The OS transistor constituting the memory element 100 according to one embodiment of the present invention is a thin film transistor, and therefore can be easily provided as layer 20 overlapping layer 10. In addition, as described above, the operation of OS transistors is stable even in high-temperature environments, and there is little fluctuation in characteristics. Therefore, even if a memory cell array 200 including an OS transistor is provided overlapping a driver circuit 21 including a Si transistor, it is not easily affected by heat generated by the driver circuit 21, and high reliability can be obtained.

Also, as shown in FIG. 20C, a layer 20 including a memory cell array 200 may be repeatedly stacked on a layer 10 including a drive circuit 21. FIG. 20C shows an example in which k layers (k is an integer of 2 or more) of layers 20 are stacked on a layer 10. The layer 20 provided as the first layer on the layer 10 is indicated as layer 20[1], and the layer 20 provided as the kth layer is indicated as layer 20[k].

By stacking the layer 10 including the drive circuit 21 and the layer 20 including the memory cell array 200, the signal propagation distance between the drive circuit 21 and the memory cell array 200 can be shortened. Therefore, the parasitic resistance and parasitic capacitance between the drive circuit 21 and the memory cell array 200 are reduced, and power consumption and signal delay can be reduced. In addition, the memory device 300 can be made smaller. In addition, the memory capacity per unit area can be increased.

Figure 21 shows a more specific example of the stacked configuration of the memory device 300. In Figure 21, the configuration shown in Figures 1A and 1B is shown as an example of the memory element 100 included in layer 20. To reduce repetition, the description of the memory element 100 will be omitted here.

21 also illustrates a transistor 800 as an example of a transistor included in the driver circuit 21. The transistor 800 is provided on a substrate 371 and has a conductive layer 376 functioning as a gate, an insulating layer 375 functioning as a gate insulating layer, a semiconductor region 373 formed of a part of the substrate 371, and low-resistance regions 374a and 374b functioning as source and drain regions. The transistor 800 may be a p-channel transistor or an n-channel transistor. For example, a single crystal silicon substrate can be used as the substrate 371.

In the transistor 800 shown in FIG. 21, the semiconductor region 373 (part of the substrate 371) where the channel is formed has a convex shape. In addition, a conductive layer 376 is provided so as to cover the side and top surface of the semiconductor region 373 via an insulating layer 375. Note that the conductive layer 376 may be made of a material that adjusts the work function. Such a transistor 800 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate. Note that an insulating layer that contacts the upper part of the convex portion and functions as a mask for forming the convex portion may be provided. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

Note that the transistor 800 shown in FIG. 21 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

Layer 10 and layer 20 may be provided with a wiring layer and an interlayer insulating layer, including a conductive layer such as a contact plug. Also, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the contact plug electrically connected to the wiring may be integrated. That is, a part of the conductive layer may function as the wiring, and another part of the conductive layer may function as the contact plug.

For example, on the transistor 800, insulating layer 390, insulating layer 391, insulating layer 393, and insulating layer 394 are stacked in this order as an interlayer insulating layer. In addition, conductive layer 392 is provided penetrating insulating layer 390 and insulating layer 391. In addition, conductive layer 395 is provided penetrating insulating layer 393 and insulating layer 394.

The insulating layer that functions as an interlayer insulating layer may also function as a planarizing film that covers the uneven shape below it. For example, a CMP process or the like may be performed on the upper surface of the insulating layer 391 to improve flatness.

An interlayer insulating layer and a wiring layer may be provided on the insulating layer 394 and the conductive layer 395. For example, in FIG. 21, insulating layer 396, insulating layer 381, insulating layer 382, insulating layer 383, insulating layer 384, insulating layer 385, insulating layer 386, and insulating layer 387 are stacked in order on the insulating layer 394 and the conductive layer 395. In addition, there is a conductive layer 361 penetrating the insulating layer 396 and the insulating layer 381, a conductive layer 362 penetrating the insulating layer 382, a conductive layer 363 penetrating the insulating layer 383, a conductive layer 364 penetrating the insulating layer 384, a conductive layer 365 penetrating the insulating layer 385, a conductive layer 366 penetrating the insulating layer 386, and a conductive layer 367 penetrating the insulating layer 387.

21, the low resistance region 374b of the transistor 800 and the conductive layer 155b of the transistor 234 are electrically connected through the conductive layer 392, the conductive layer 395, the conductive layer 361, the conductive layer 362, the conductive layer 363, the conductive layer 364, the conductive layer 365, the conductive layer 366, and the conductive layer 367. The conductive layer 392, the conductive layer 395, the conductive layer 361, the conductive layer 362, the conductive layer 363, the conductive layer 364, the conductive layer 365, the conductive layer 366, and the conductive layer 367 function as contact plugs or wiring.

The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

(Embodiment 3)
In this embodiment, an example of a processing device including a memory element 100 according to one embodiment of the present invention will be described.

In addition to the driver circuit 21, various other functional circuits can be provided in the layer 10 shown in the above embodiment. FIG. 22 shows a schematic perspective view of a processing device 1100, which is a type of semiconductor device. The processing device 1100 has a layer 20 including a memory cell array 200 including a memory element 100, which is stacked on the layer 10. To make the configuration of the processing device 1100 easier to understand, the layers 10 and 20 are shown separately in FIG. 22.

The arithmetic processing device 1100 shown in FIG. 22 has a driver circuit 21, an ALU 1191 (ALU: Arithmetic Logic Unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198), a cache 1199, and a cache interface 1189 in layer 10. It may also have a rewritable ROM and a ROM interface. The cache 1199 and the cache interface 1189 may be provided on a separate chip. The arithmetic processing device 1100 shown in FIG. 22 functions, for example, as a central processing unit (CPU: Central Processing Unit).

The cache 1199 is connected to a main memory provided on a separate chip via a cache interface 1189. The cache interface 1189 has a function of supplying a portion of the data stored in the main memory to the cache 1199. The cache 1199 has a function of storing that data.

The arithmetic processing device 1100 shown in FIG. 22 is merely one example of a simplified configuration, and the actual arithmetic processing device 1100 has a wide variety of configurations depending on its application. For example, the arithmetic processing device 1100 shown in FIG. 22 may be configured as one core, and may include multiple such cores, each of which operates in parallel, that is, a configuration like a GPU (Graphics Processing Unit). In addition, the number of bits that the arithmetic processing device 1100 can handle in its internal arithmetic circuit and data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

Instructions input to the arithmetic processing unit 1100 via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Furthermore, while the arithmetic processing device 1100 is executing a program, the interrupt controller 1194 determines and processes interrupt requests from external input/output devices and peripheral circuits based on their priority and mask state. The register controller 1197 generates an address for the register 1196, and reads or writes to the register 1196 depending on the state of the arithmetic processing device 1100.

The timing controller 1195 also generates signals that control the timing of the operations of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

In the arithmetic processing device 1100 shown in FIG. 22, the register controller 1197 selects the holding operation in the register 1196 according to instructions from the ALU 1191. That is, it selects whether the memory cells in the register 1196 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 1196. If holding data in capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply potential to the memory cells in the register 1196 can be stopped.

The arithmetic processing device 1100 shown in FIG. 22 has a memory device that functions as a register 1196 and a cache 1199. The memory device may be a memory cell array 200 including a memory element 100 according to one embodiment of the present invention.

By stacking the layer 10 in which the functional circuits are provided and the layer 20 in which the memory cell array 200 including the memory element 100 is provided, the connection distance between the two can be shortened. By shortening the connection distance, parasitic resistance and parasitic capacitance are reduced. This makes it possible to increase the communication speed between the two. In addition, power consumption can be reduced.

Furthermore, the memory element 100 is a non-volatile memory element. Therefore, a part or all of the memory cell array 200 can be used as storage. Further, a part or all of the memory cell array 200 can be used as a main memory. Further, a part or all of the memory cell array 200 can be used as a cache memory.

In addition, a portion of the memory cell array 200 can function as a main memory, and another portion can function as storage. The memory cell array 200 including the memory element 100 according to one aspect of the present invention can function as a cache, a main memory, and a storage. The memory cell array 200 including the memory element 100 according to one aspect of the present invention can function as a universal memory, for example.

In addition, if the storage capacity of the cache 1199 is insufficient, the storage capacity of the cache 1199 can be supplemented by using part or all of the memory cell array 200 including the storage element 100 according to one embodiment of the present invention. In addition, when data is exchanged between the cache 1199 and the main memory, if one of the cache 1199 and the main memory is processing another item, the operation of the other may be stopped until the processing is completed, resulting in a wait time. The aforementioned wait time can be eliminated by temporarily storing the data to be exchanged in the memory cell array 200 including the storage element 100 according to one embodiment of the present invention. This can improve the operating efficiency of the arithmetic processing device.

The memory element 100 according to one embodiment of the present invention is suitable for power gating, which temporarily stops the supply of power to an inactive arithmetic circuit to reduce power consumption. A normally-off processor using power gating is sometimes called a "normally-off processor" or "Noff processor." In a normally-off processor, data required for recovery must be saved to a non-volatile memory before the power supply is stopped, and must be read out at the time of recovery. The memory element 100 according to one embodiment of the present invention is a non-volatile memory element and can be stacked on the arithmetic processing device, so that a normally-off processor with high save and recovery speeds can be realized without increasing the area occupied by the arithmetic processing device.

The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

(Embodiment 4)
In this embodiment, application examples of a memory device including a memory element according to one embodiment of the present invention (hereinafter also referred to as a "memory device according to one embodiment of the present invention") will be described.

Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 23A shows various memory devices used in semiconductor devices by layer. The higher the layer, the faster the operating speed is required for the memory device, and the lower the layer, the larger the memory capacity and higher the memory density are required for the memory device. From the top layer, Figure 23A shows memory integrated as a register in a processor such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

Memory integrated as a register in a processor such as a CPU is used for temporary storage of calculation results, and is therefore accessed frequently by the processor. Therefore, a faster operating speed is required rather than a larger memory capacity. Registers also have the function of storing setting information for the processor.

SRAM is used, for example, in caches. Caches have the function of duplicating and storing part of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased. The storage capacity required for a cache is smaller than that of main memory, but it is required to operate at a faster speed than main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

DRAM is used, for example, as a main memory. The main memory has a function of holding programs and data read from storage. The memory density of DRAM is approximately 0.1 to 0.3 Gbit/ ^mm2 .

3D NAND memory is used, for example, for storage. Storage has a function of holding data that needs to be stored for a long time and various programs used in a processing unit. Therefore, storage requires a larger memory capacity and a higher memory density than an operating speed. The memory density of a memory device used for storage is approximately 0.6 to 6.0 Gbit/ ^mm2 .

A storage device according to one aspect of the present invention has a high operating speed and is capable of retaining data for a long period of time. A storage device according to one aspect of the present invention is suitable as a storage device located in a boundary area 901 that includes both the hierarchical level where the cache is located and the hierarchical level where the main memory is located. A storage device according to one aspect of the present invention is also suitable as a storage device located in a boundary area 902 that includes both the hierarchical level where the main memory is located and the hierarchical level where the storage is located.

Furthermore, a storage device according to one aspect of the present invention is suitable for both the hierarchical level where main memory is located and the hierarchical level where storage is located. Further, a storage device according to one aspect of the present invention is suitable for the hierarchical level where cache is located. Figure 23B shows various hierarchical levels of storage devices different from those shown in Figure 23A.

In FIG. 23B, from the top layer, a memory embedded as a register in an arithmetic processing device such as a CPU, an SRAM used as a cache, and a memory device 300 according to one embodiment of the present invention are shown. The memory device 300 according to one embodiment of the present invention can be used for the cache, main memory, and storage. Note that when a high-speed memory of 1 GHz or more is required as the cache, the cache is embedded in an arithmetic processing device such as a CPU.

The memory device 300 including a memory element according to one embodiment of the present invention can be applied to, for example, memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare-related devices, etc. Note that here, the term "computer" includes tablet computers, notebook computers, and desktop computers, as well as large computers such as server systems.

An example of an electronic device including a memory device according to one embodiment of the present invention will be described. Note that FIGS. 24A to 24J each illustrate an electronic device including an electronic component 4700 including a memory device according to one embodiment of the present invention.

[mobile phone]
24A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 includes a housing 5510, a display unit 5511, and an electronic component 4700. As an input interface, a touch panel is provided on the display unit 5511, and a button is provided on the housing 5510.

The information terminal 5500 can store temporary files (e.g., cache when using a web browser) generated when an application is executed in an electronic component 4700 including a storage device according to one embodiment of the present invention.

[Wearable devices]
24B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, the electronic components 4700, and the like.

Similar to the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed in an electronic component 4700 including a memory device according to one embodiment of the present invention.

[Information terminal]
24C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, a keyboard 5303, and electronic components 4700.

Like the information terminal 5500 described above, the desktop information terminal 5300 can store temporary files generated when an application is executed in an electronic component 4700 that includes a storage device according to one embodiment of the present invention.

In the above description, a smartphone, a wearable terminal, and a desktop information terminal are shown as examples of electronic devices in FIGS. 24A to 24C, respectively, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[electric appliances]
24D illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and electronic components 4700. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT.

A storage device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as ingredients stored in the electric refrigerator-freezer 5800 and the expiration date of the ingredients to an information terminal or the like via the Internet or the like. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in an electronic component 4700 including a storage device according to one embodiment of the present invention.

In this embodiment, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, and audiovisual equipment.

[Gaming consoles]
24E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, a button 5203, an electronic component 4700, and the like.

Furthermore, FIG. 24F illustrates a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 has a main body 7520, electronic components 4700, and a controller 7522. The controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not shown in FIG. 24F, the controller 7522 can include a display unit that displays game images, a touch panel and stick that serve as an input interface other than buttons, a rotary knob, a sliding knob, and the like. The shape of the controller 7522 is not limited to the shape shown in FIG. 24F, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, in a shooting game such as FPS (First Person Shooter), a controller with a trigger as a button and a shape imitating a gun can be used. In addition, for example, in a music game, a controller with a shape imitating a musical instrument, a musical device, or the like can be used. Furthermore, a stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures, voice, etc.

In addition, the images from the above-mentioned game machines can be output by display devices such as television sets, personal computer displays, game displays, and head-mounted displays.

By applying a storage device according to one embodiment of the present invention to the portable game machine 5200 or the stationary game machine 7500, it is possible to realize a portable game machine 5200 or a stationary game machine 7500 with low power consumption. In addition, the reduction in power consumption leads to a reduction in heat generation from the circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules is reduced.

Furthermore, the electronic component 4700 of the portable game console 5200 or the stationary game console 7500 can store temporary files and the like necessary for calculations that occur during game execution.

As an example of a game machine, FIG. 24E shows a portable game machine, and FIG. 24F shows a stationary game machine for home use. Note that electronic devices according to one embodiment of the present invention are not limited to this. Examples of electronic devices according to one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[Mobile object]
The storage device described in the above embodiment can be applied to a moving object such as an automobile and the vicinity of the driver's seat of the automobile.

Figure 24G shows an automobile 5700, which is an example of a moving object. The automobile 5700 has electronic components 4700. Around the driver's seat of the automobile 5700, there is an instrument panel that provides various information such as driving speed, engine RPM, mileage, remaining fuel, gear status, and air conditioning settings. In addition, around the driver's seat, there may be a display device that shows this information.

By displaying on the display device an image outside the vehicle captured by an imaging device (not shown) installed in the automobile 5700, it is possible to compensate for the field of view blocked by pillars and blind spots in the driver's seat, thereby improving safety. In other words, by displaying on the display device an image outside the vehicle captured by the imaging device, it is possible to compensate for blind spots and improve safety.

The electronic component 4700 including a storage device according to one embodiment of the present invention can hold information necessary for an automatic driving system of the automobile 5700, a system that provides road guidance, hazard prediction, and the like. Information such as road guidance and hazard prediction may be displayed on the display device of the automobile 5700. Furthermore, the electronic component 4700 including a storage device according to one embodiment of the present invention may hold image capture information from a driving recorder installed in the automobile 5700.

Note that, although automobiles have been described above as an example of a moving body, moving bodies are not limited to automobiles. For example, moving bodies can also include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[camera]
A storage device according to one embodiment of the present invention can be applied to a camera. Fig. 24H illustrates a digital camera 6240 as an example of an imaging device. The digital camera 6240 includes a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, an electronic component 4700, and the like, and a detachable lens 6246 is attached to the digital camera 6240. Note that the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may be configured such that a strobe device, a viewfinder, and the like can be separately attached.

By applying the electronic component 4700 including a memory device according to one embodiment of the present invention to the digital camera 6240, it is possible to realize a digital camera 6240 with low power consumption. In addition, the reduction in power consumption leads to a reduction in heat generation from the circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules is reduced.

[Video Camera]
A storage device according to one embodiment of the present invention can be applied to a video camera. FIG. 24I illustrates a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, an electronic component 4700, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by a connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

When recording video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using a storage device according to one embodiment of the present invention, the video camera 6300 can store temporary files generated during encoding.

[ICD]
A memory device according to one embodiment of the present invention can be applied to an implantable cardioverter defibrillator (ICD). Fig. 24J is a schematic cross-sectional view showing an example of an ICD. An ICD main body 5400 includes at least a battery 5401, an electronic component 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, a wire 5403 to the right ventricle, and the electronic component 4700.

The ICD body 5400 is placed in the body by surgery, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve through pacing (fast ventricular tachycardia or ventricular fibrillation, for example), treatment is provided by administering an electric shock.

The ICD main body 5400 must constantly monitor the heart rate to perform appropriate pacing and electric shocks. For this reason, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store heart rate data acquired by the sensor, the number of times pacing treatment has been performed, the time, etc., in the electronic component 4700 including a memory device according to one aspect of the present invention.

In addition, the antenna 5404 can receive power, which is then charged into the battery 5401. The ICD main body 5400 also has multiple batteries, which can increase safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 also functions as an auxiliary power source.

In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system may be configured to monitor cardiac activity such that physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[Calculator]
25A is an example of a large-scale computer. The computer 5600 includes a rack 5610 and a plurality of rack-mounted computers 5620 stored therein.

The computer 5620 can have the configuration shown in the perspective view of FIG. 25B, for example. In FIG. 25B, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

The PC card 5621 shown in FIG. 25C is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that FIG. 25C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for those semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

The connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).

The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected to the terminals by, for example, reflow soldering to wiring on the board 5622. Examples of the semiconductor device 5627 include a field programmable gate array (FPGA), a GPU, and a CPU. For example, the electronic component 4700 including a memory device according to one embodiment of the present invention can be used as the semiconductor device 5627.

The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected to the terminals by, for example, reflow soldering to wiring on the board 5622. An example of the semiconductor device 5628 is a memory device. The electronic component 4700 including the memory device of one embodiment of the present invention can be used as the semiconductor device 5628.

The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, artificial intelligence learning and inference.

By using a memory device according to one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller, faster, or consume less power. In addition, the memory device according to one embodiment of the present invention consumes less power, so heat generation from the circuit can be reduced. Therefore, adverse effects of the heat on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using a memory device according to one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

10: Layer, 20: Layer, 21: Drive circuit, 22: PSW, 23: PSW, 31: Peripheral circuit, 32: Control circuit, 33: Voltage generation circuit, 41: Peripheral circuit, 42: Row decoder, 43: Row driver, 44: Column decoder, 45: Column driver, 47: Input circuit, 48: Output circuit, 100: Memory element

Claims (8)

a conductive layer, a magnetic tunnel junction element, and a transistor;
the magnetic tunnel junction element is disposed over the conductive layer;
one of a source electrode and a drain electrode of the transistor is electrically connected to the conductive layer;
one of the source electrode or the drain electrode of the transistor has a region on an insulating layer;
the other of the source electrode or the drain electrode of the transistor has an area under the insulating layer;
A memory element in which a channel formation region of the transistor has a region along a side surface of the insulating layer. In claim 1,
A memory element in which a semiconductor layer of the transistor contains an oxide semiconductor. In claim 1 or 2,
The resistance value of the magnetic tunnel junction element is
A memory element controlled by the direction of a current supplied to the conductive layer via the transistor. In claim 1,
The conductive layer has a region in contact with a semiconductor layer of the transistor. a conductive layer, a magnetic tunnel junction element, a first transistor, and a second transistor;
the magnetic tunnel junction element is disposed over the conductive layer;
one of a source electrode or a drain electrode of the first transistor is electrically connected to one of a source electrode or a drain electrode of the second transistor through at least a region of the conductive layer that overlaps with the magnetic tunnel junction element;
one of a source electrode or a drain electrode of the first transistor has a region on an insulating layer;
the other of the source electrode or the drain electrode of the first transistor has an area under the insulating layer;
a channel formation region of the first transistor having a region along a first side surface of the insulating layer;
one of a source electrode or a drain electrode of the second transistor has an area on the insulating layer;
the other of the source electrode or the drain electrode of the second transistor has an area under the insulating layer;
A memory element, wherein the channel formation region of the second transistor has a region along the second side surface of the insulating layer. In claim 5,
a semiconductor layer of the first transistor includes an oxide semiconductor;
A memory element in which a semiconductor layer of the second transistor includes an oxide semiconductor. In claim 5 or 6,
The resistance value of the magnetic tunnel junction element is
A memory element controlled by a direction of a current supplied to the conductive layer via the first transistor or the second transistor. In claim 5,
The conductive layer is
a region in contact with a semiconductor layer of the first transistor;
A memory element having a region in contact with the semiconductor layer of the second transistor.

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