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WO2024221781A1 - 数据读写电路及其方法、存储器及其驱动方法、电子设备 - Google Patents

数据读写电路及其方法、存储器及其驱动方法、电子设备 Download PDF

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Publication number
WO2024221781A1
WO2024221781A1 PCT/CN2023/126717 CN2023126717W WO2024221781A1 WO 2024221781 A1 WO2024221781 A1 WO 2024221781A1 CN 2023126717 W CN2023126717 W CN 2023126717W WO 2024221781 A1 WO2024221781 A1 WO 2024221781A1
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WO
WIPO (PCT)
Prior art keywords
transistor
data
voltage
electrode
signal line
Prior art date
Application number
PCT/CN2023/126717
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English (en)
French (fr)
Inventor
朱正勇
康卜文
赵超
Original Assignee
北京超弦存储器研究院
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Publication of WO2024221781A1 publication Critical patent/WO2024221781A1/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of storage technology, and in particular to a data reading and writing circuit and method thereof, a memory and a driving method thereof, and an electronic device.
  • the 2T architecture of the memory cell can effectively solve the problem of difficult capacitor preparation process caused by the reduction of key dimensions when the memory cell adopts the 1T1C architecture.
  • the present disclosure provides a data reading and writing method on one hand, which is applied to a storage unit.
  • the storage unit is configured to store data, including a capacitor and a first transistor and a second transistor connected to a first electrode of the capacitor. The intersection where the first electrode of the capacitor, the first transistor and the second transistor are connected is a storage node.
  • the capacitor also includes a second electrode arranged opposite to the first electrode.
  • the data reading and writing cycle of the storage unit includes: a pre-charging stage and a data writing stage.
  • the data reading and writing method includes the following steps.
  • the data signal line provides a first reference voltage to the first transistor
  • the auxiliary signal line provides a first reference voltage to the first transistor and the second transistor at the same time
  • a first write control voltage is applied to the second electrode of the capacitor, the second transistor is turned on, and the storage node is pre-charged; wherein the sum of the maximum data voltage corresponding to the data and the threshold voltage of the first transistor is the reference voltage, and the first reference voltage is greater than the reference voltage.
  • the auxiliary signal line In the data writing phase, in response to a write command, the auxiliary signal line floats, the data signal line provides a data voltage to the first transistor, and the first transistor is turned on; the storage node is discharged to a stable state, and data corresponding to the data voltage is written.
  • the data read and write cycle further includes: a data holding phase located after the data writing phase.
  • the data read and write method further includes: in the data holding phase, pulling up the voltage of the data signal line to a first reference voltage, and turning off the second transistor after the voltage of the data signal line reaches the first reference voltage, and then pulling up the voltage of the auxiliary signal line to the first reference voltage; wherein, after turning off the second transistor, applying a second write control voltage to the second electrode of the capacitor; and the second write control voltage is less than the first write control voltage.
  • the data read and write cycle further includes: a data holding phase located after the data writing phase.
  • the data read and write method further includes: in the data holding phase, first applying a second write control voltage to the second electrode of the capacitor to pull up the voltage of the data signal line to the first reference voltage; then turning off the second transistor to pull up the voltage of the auxiliary signal line to the first reference voltage; wherein the second write control voltage is less than the first write control voltage.
  • the data read/write cycle further includes a data read phase.
  • the data read/write method further includes: in the data read phase, in response to a read command, applying a read control voltage to the second electrode of the capacitor, and simultaneously providing a second reference voltage to the first transistor and the second transistor through an auxiliary signal line; wherein the data signal line reads data in response to whether the first transistor is turned on.
  • the data written to the storage node includes "1" or "0".
  • the first transistor In the data reading phase, when the data written to the storage node is "1", the first transistor is in the on state. When the data written to the storage node is "0", the first transistor is in the off state.
  • the data read and write cycle further includes: a standby phase before the pre-charging phase and/or before the data reading phase.
  • the data read and write method further includes: in the standby phase, the first transistor and the second transistor are in an off state, the data signal line provides a first reference voltage to the first transistor, and the auxiliary signal line provides the first reference voltage to the first transistor and the second transistor at the same time.
  • the data read/write cycle further includes: a data holding phase after the data writing phase.
  • the standby phase includes: a first standby phase before the pre-charging phase, and a second standby phase after the data holding phase and before the data reading phase.
  • the present disclosure also provides a data read and write circuit on another aspect, including a storage unit, a data signal line and an auxiliary signal line.
  • the storage unit is configured to store data, including a capacitor and a first transistor and a second transistor connected to the first electrode of the capacitor.
  • the capacitor also includes a second electrode arranged opposite to the first electrode.
  • the data signal line is connected to the first transistor, and is configured to provide a first reference voltage to the first transistor in the standby stage and the pre-charging stage, provide a data voltage to the first transistor in the data writing stage, and read data in response to whether the first transistor is turned on in the data reading stage.
  • the auxiliary signal line is connected to the first transistor and the second transistor, and is configured to provide a first reference voltage to the first transistor in the standby stage and the pre-charging stage, float in the data writing stage, and provide a second reference voltage to the first transistor and the second transistor at the same time in the data reading stage.
  • the sum of the maximum data voltage corresponding to the data and the threshold voltage of the first transistor is the reference voltage; the first reference voltage is greater than the reference voltage.
  • the data read and write circuit further includes a first control signal line and a second control signal line.
  • the first control signal line is connected to the second electrode of the capacitor and is configured to: apply a first write control voltage to the second electrode of the capacitor in the pre-charging stage and the data writing stage, and apply a read control voltage to the second electrode of the capacitor in the data reading stage.
  • the second control signal line is connected to the second transistor and is configured to control the second transistor to be turned off in the standby stage and the data reading stage, and to control the second transistor to be turned on in the pre-charging stage and the data writing stage.
  • the data signal line is further configured to provide a first reference voltage to the first transistor during a data holding phase.
  • the second control signal line is further configured to control the second transistor to be turned off after the voltage of the data signal line reaches the first reference voltage during a data holding phase.
  • the auxiliary signal line is further configured to provide the first reference voltage to both the first transistor and the second transistor during a data holding phase after the second transistor is turned off.
  • the first control signal line is further configured to: in the data retention phase, after turning off the second transistor, apply a second write control voltage to the second electrode of the capacitor; wherein the second write control voltage is less than the first write control voltage.
  • the first control signal line is further configured to: apply a second write control voltage to the second electrode of the capacitor during the data holding stage; wherein the second write control voltage is less than the first write control voltage.
  • the data signal line is further configured to: provide a first reference voltage to the first transistor after the voltage of the second electrode is the second write control voltage during the data holding stage.
  • the second control signal line is further configured to: control the second transistor to be turned off after the data signal line provides the first reference voltage during the data holding stage.
  • the auxiliary signal line is further configured to: provide the first reference voltage to both the first transistor and the second transistor after the second transistor is turned off during the data holding stage.
  • the first transistor includes a first gate, a first electrode, and a second electrode.
  • the second transistor includes a second gate, a first electrode, and a second electrode.
  • the first gate and the first electrode of the second transistor are both connected to the first electrode of the capacitor.
  • the second electrode of the capacitor is connected to the first control signal line.
  • the second gate is connected to the second control signal line.
  • the first electrode of the first transistor is connected to the data signal line.
  • the second electrode of the first transistor and the second electrode of the second transistor are respectively connected to the auxiliary signal line.
  • the multiple storage units are arranged in rows along the first direction and in columns along the second direction; the first direction and the second direction intersect.
  • a row of storage units shares a first control signal line and a second control signal line.
  • a column of storage units shares a data signal line and an auxiliary signal line.
  • the data read/write circuit further includes a first reference voltage terminal and a second reference voltage terminal.
  • the first reference voltage terminal is connected to the data signal line through the first gating circuit, and is connected to the auxiliary signal line through the second gating circuit.
  • the first reference voltage terminal is configured to provide a first reference voltage.
  • the first gating circuit is configured to: select and connect the first reference voltage terminal and the data signal line in the standby stage and the pre-charge stage.
  • the second gating circuit The device is configured to selectively connect the first reference voltage terminal and the auxiliary signal line in the standby stage and the pre-charging stage.
  • the second reference voltage terminal is connected to the auxiliary signal line through the third gating circuit, wherein the second reference voltage terminal is configured to provide a second reference voltage, and the third gating circuit is configured to select the second reference voltage terminal and the auxiliary signal line for connection during the data reading phase.
  • the present disclosure further provides a memory on another aspect, including at least one memory cell, and a first bit line, a second bit line, a first word line and a second word line connected to the memory cell correspondingly; wherein the memory cell includes: a capacitor, a first transistor and a second transistor.
  • the capacitor includes a first electrode and a second electrode insulated.
  • the first transistor and the second transistor each include a gate and a first electrode and a second electrode.
  • the first electrode, the gate of the first transistor and the first electrode of the second transistor are connected, and the connection intersection of the three is a storage node.
  • the first word line is connected to the second electrode, and the second word line is connected to the gate of the second transistor.
  • the first bit line is connected to the first electrode of the first transistor, and the second bit line is connected to the second electrode of the first transistor and the second electrode of the second transistor at the same time.
  • the first bit line is configured to: provide a data voltage for data to be written in the data writing phase, and read the data written to the storage node in response to whether the first transistor is turned on in the data reading phase.
  • the present disclosure further provides a memory driving method, which is applied to the memory as described above.
  • the method includes the following steps.
  • the first bit line provides a first reference voltage to the first electrode of the first transistor.
  • the second bit line provides a first reference voltage to the second electrode of the first transistor and the second electrode of the second transistor at the same time.
  • the first word line applies a first write control voltage to the second electrode.
  • the second word line applies a third write control voltage to the gate of the second transistor to control the conduction of the second transistor to precharge the storage node.
  • the first reference voltage is greater than the sum of the maximum data voltage to be written into the storage cell and the threshold voltage of the first transistor.
  • the second bit line is floated, and the first bit line provides a data voltage to the first electrode of the first transistor.
  • the first transistor is turned on, the storage node is discharged to a stable state, and data corresponding to the data voltage is written.
  • the second word line applies a fourth write control voltage to the gate of the second transistor, and the second transistor is in an off state.
  • the first word line applies a read control voltage to the second electrode.
  • the second bit line simultaneously provides a second reference voltage to the second electrode of the first transistor and the second electrode of the second transistor. The first bit line reads the data written to the storage node in response to whether the first transistor is turned on.
  • the present disclosure further provides an electronic device on another aspect, including: a data reading and writing circuit as described in some of the above embodiments; or a memory as described in some of the above embodiments.
  • FIG1 is a circuit diagram of a 2T0C architecture memory cell provided in the related art
  • FIG2 is a circuit diagram of a data reading and writing circuit or memory provided in some embodiments of the present disclosure.
  • FIG3 is a structural block diagram of another data reading and writing circuit or memory provided in some embodiments of the present disclosure.
  • FIG4 is an equivalent circuit diagram of the data reading and writing circuit or memory shown in FIG3 ;
  • FIG5 is a timing diagram of a data reading and writing method or a memory driving method provided in some embodiments of the present disclosure
  • FIG6 is a timing diagram of another data reading and writing method or another memory driving method provided in some embodiments of the present disclosure.
  • FIG. 7 is another data reading and writing method or another memory driving method provided in some embodiments of the present disclosure. Timing diagram of
  • FIG. 8 is a graph showing changes in the current-voltage characteristics of a first transistor when different read control voltages are applied during a data reading phase provided in some embodiments of the present disclosure.
  • references to "embodiments” herein mean that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present disclosure.
  • the appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
  • first, second, third, “fourth”, etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.
  • a first transistor may be referred to as a second transistor, and similarly, a second transistor may be referred to as a first transistor. Both the first transistor and the second transistor are transistors, but they are not the same transistor.
  • connection in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.
  • each memory cell may adopt a 1T1C architecture, a 2T0C architecture, a 2T1C architecture, etc.
  • a 2T1C architecture it is also easy to face more new challenges.
  • a memory cell using a 2T1C architecture includes: a read transistor T_r, a write transistor T_w, and a capacitor C having a first electrode connected to both a second electrode of the read transistor T_r and a second electrode of the write transistor T_w; wherein the second electrode of the capacitor C is connected to a ground voltage terminal.
  • the gate of the read transistor T_r is connected to a read word line Read-WL, and the first electrode is connected to a read bit line Read-BL.
  • the gate of the write transistor T_w is connected to a write word line Write-WL, and the first electrode is connected to a write bit line Write-BL.
  • Some embodiments of the present disclosure provide a new memory cell circuit design and a driving method, wherein the memory cell has 2T and 1C, 2T participates in precharging at the same time, and 2T participates in writing data at the same time, so as to realize compensation for the read transistor Vth in the writing stage.
  • the read transistor T_r and the write transistor T_w of the storage unit work relatively independently when implementing data writing and data reading, that is: data is written to the capacitor C by relying on the write transistor T_w being turned on, while the read transistor T_r is kept in the off state; data is read from the capacitor C by relying on whether the read transistor T_r is turned on, while the write transistor T_w is kept in the off state.
  • data is written to the capacitor C by relying on the write transistor T_w being turned on, while the read transistor T_r is kept in the off state
  • data is read from the capacitor C by relying on whether the read transistor T_r is turned on, while the write transistor T_w is kept in the off state.
  • the read transistor is used for precharging and writing data in the data writing phase, and is used for reading data in the reading phase.
  • Some embodiments of the present disclosure provide a data reading and writing circuit and method thereof, a memory and a driving method thereof, an electronic device
  • the data signal line (or the first bit line) and the auxiliary signal line (or the second bit line) can be used to provide different electrical signals to the first transistor and the second transistor in the storage unit at different stages of the data read and write cycle, and combined with the control voltage of the capacitor and the second transistor in the storage unit, the threshold compensation voltage of the first transistor is retained at the storage node while writing data at the storage node during the data writing stage.
  • the data signal line (or the first bit line) can not only provide the data voltage of the data to be written during the data writing stage, but also read the written data in response to whether the first transistor is turned on during the data reading stage.
  • the memory usually includes multiple storage units, and each storage unit can be distributed in a two-dimensional single layer or a three-dimensional multi-layer distribution.
  • the data reading and writing circuits and data reading and writing methods in some of the following embodiments are introduced by taking a storage unit and its corresponding drive as an example.
  • the data reading and writing circuits mentioned in the embodiments of the present disclosure mainly refer to the circuits within the storage unit array, and do not include peripheral circuits (such as row addressing drive circuits, column addressing drive circuits, etc.).
  • the data reading and writing circuit includes components of at least one storage unit and drive leads connected to the storage unit.
  • the data reading and writing circuit includes: a storage unit U, a data signal line BL1 and an auxiliary signal line BL2 .
  • the memory unit U is configured to store data, and includes a first transistor T1, a second transistor T2, and a capacitor C;
  • the capacitor C includes two electrodes insulated from each other, one of which is a first electrode A, which is connected to the first gate G1 of the first transistor T1 and the first electrode S/D21 of the second transistor T2.
  • the capacitor C also includes a second electrode B arranged opposite to the first electrode A, and the second electrode B is connected to the first control signal line WL.
  • the intersection of the first electrode A of the capacitor C, the first gate G1 of the first transistor T1, and the first electrode S/D21 of the second transistor T2 is a storage node SN.
  • the data reading and writing timing of the storage unit U includes: a data writing stage, a data reading stage, and a standby stage before data writing or reading (which can be understood as a stand by stage); wherein, in the embodiment of the present application, a pre-charging stage is also included before the data writing stage, and a data holding stage is also included after the data writing stage.
  • the data signal line BL1 is connected to the first transistor T1, and is configured to provide a first reference voltage to the first transistor T1 in the standby stage and the pre-charge stage, provide a data voltage to the first transistor T1 in the data writing stage, and read data in response to whether the first transistor T1 is turned on in the data reading stage.
  • the data of the data voltage can be stored.
  • the auxiliary signal line BL2 is connected to the first transistor T1 and the second transistor T2, and is configured to provide a first reference voltage to the first transistor T1 in the standby stage and the pre-charging stage, float in the data writing stage, and provide a second reference voltage to the first transistor T1 and the second transistor T2 simultaneously in the data reading stage.
  • the sum of the maximum data voltage corresponding to the data stored in the storage unit U and the threshold voltage of the first transistor T1 is the reference voltage, and the first reference voltage provided by the data signal line BL1 and the auxiliary signal line BL2 is greater than the reference voltage.
  • the maximum data voltage corresponding to the data that the storage unit U can store refers to: among the data that the storage unit U can store, such as data "1" or data "0", the voltage corresponding to the data voltage with the largest absolute value.
  • the data that the storage unit U can store includes data “0” and data "1", wherein the data voltage Vdata1 corresponding to the data "1” and the data voltage Vdata0 corresponding to the data "0” can be both positive voltages or both negative voltages.
  • the absolute value of the data voltage Vdata1 corresponding to the data "1” is greater than the absolute value of the data voltage Vdata0 corresponding to the data "0". Based on this, the data voltage corresponding to the data "1" can be the maximum data voltage of the data that the storage unit U can store. And vice versa.
  • the data voltage Vdata1 corresponding to the data "1" is the maximum data voltage that the memory cell U can store data
  • the sum of the maximum data voltage and the threshold voltage Vth of the first transistor T1 is the reference voltage, that is, the reference voltage is Vdata1+Vth.
  • the reference voltage is for the convenience of description
  • the maximum data voltage given is the sum of the threshold voltage Vth of the first transistor T1.
  • the definition of the sum of the threshold voltage Vth of T1 is only used to illustrate the value range of the first reference voltage when the reference voltage is used as a reference standard.
  • the first reference voltage is greater than the reference voltage (that is, greater than Vdata1+Vth).
  • the difference between the first reference voltage and the reference voltage can be reasonably set according to requirements.
  • the second reference voltage is less than the first reference voltage.
  • the first transistor T1 and the second transistor T2 are both N-type transistors
  • the first reference voltage can be provided by a first reference voltage terminal, which is, for example, a power supply voltage terminal that can provide a rated high level voltage
  • the second reference voltage can be provided by a second reference voltage terminal, which is, for example, a common voltage terminal that can provide a rated low level voltage.
  • the second reference voltage is greater than a minimum data voltage that can store data in the memory cell U, and less than a maximum data voltage that can store data in the memory cell U.
  • the second reference voltage V2 can be greater than the sum of the minimum data voltage and the voltage variable (vector) caused by the coupling effect, and less than the sum of the maximum data voltage and the voltage variable (vector) caused by the coupling effect, so as to clearly distinguish the voltage change or current change caused by data "1" and data "0" in the data reading stage.
  • the aforementioned voltage variable (vector) can be specifically determined in combination with actual conditions.
  • the data read/write circuit further includes a first control signal line WL and a second control signal line WWL.
  • the capacitor C includes a first electrode A and a second electrode B.
  • the first transistor T1 includes a first gate G1, a first electrode S/D11 and a second electrode S/D12.
  • the second transistor T2 includes a second gate G2, a first electrode S/D21 and a second electrode S/D22.
  • the first gate G1 and the first electrode S/D21 of the second transistor T2 are both connected to the first electrode A, and the intersection of the first gate G1, the first electrode S/D21 of the second transistor T2 and the first electrode A is the storage node SN.
  • the second electrode B is connected to the first control signal line WL.
  • the second gate G2 is connected to the second control signal line WWL.
  • the first electrode S/D11 of the first transistor T1 is connected to the data signal line BL1.
  • the second electrode S/D12 of the first transistor T1 and the second electrode S/D22 of the second transistor T2 are respectively connected to the auxiliary signal line BL2.
  • one of the first electrode S/D11 and the second electrode S/D12 of the first transistor T1 may be a source and the other may be a drain.
  • One of the first electrode S/D21 and the second electrode S/D22 of the second transistor T2 may be a source and the other may be a drain.
  • the two transistors are both n-type transistors, and the type of transistor is not limited in practical applications.
  • the storage unit U includes a capacitor C and a first transistor T1 and a second transistor T2 connected to the first electrode A of the capacitor C.
  • the data signal line BL1 and the auxiliary signal line BL2 can be used to provide different electrical signals to the first transistor T1 and the second transistor T2 at different stages of the data read and write cycle, and combined with the control of the control voltages of the second electrode B of the capacitor C and the second transistor T2, the threshold compensation voltage of the first transistor T1 is retained at the storage node SN while the data is written at the storage node SN during the data writing phase.
  • the first control signal line WL is connected to the second electrode B of the capacitor C and is configured to apply a first write control voltage to the second electrode B of the capacitor C during the pre-charging stage and the data writing stage.
  • the first control signal line WL can also be configured to apply a second write control voltage to the second electrode B of the capacitor C as required.
  • the second control signal line WWL is connected to the second gate G2 of the second transistor T2, and is configured to control the second transistor T2 to be turned off in the standby stage and the data reading stage, and to control the second transistor T2 to be turned on in the pre-charging stage and the data writing stage.
  • the control voltage of the second control signal line WWL to control the second transistor T2 to be turned on is the third write control voltage.
  • the second transistor T2 can be turned off by the second control signal line WWL to the second gate G2.
  • the turn-off control voltage (eg, the fourth write control voltage) applied by the pole G2 controls the realization.
  • the first transistor T1 and the second transistor T2 are both N-type transistors. Accordingly, the first write control voltage and the third write control voltage are both high-level voltages. The second write control voltage and the fourth write control voltage are both low-level voltages. Further, the first write control voltage may be less than the third control voltage, and the first write control voltage may be reasonably set according to requirements. The second write control voltage and the fourth write control voltage may be the same, for example, both are ground voltages.
  • the write cycle further includes a data holding phase after the data writing phase.
  • the data signal line BL1 is further configured to provide a first reference voltage to the first transistor T1 during the data holding phase.
  • the second control signal line WWL is further configured to control the second transistor T2 to be turned off after the voltage of the data signal line BL1 reaches the first reference voltage during the data holding phase.
  • the auxiliary signal line BL2 is further configured to provide the first reference voltage to both the first transistor T1 and the second transistor T2 during the data holding phase after the second transistor T2 is turned off.
  • the first control signal line WL is further configured to: in the data retention phase, after turning off the second transistor T2, apply a second write control voltage to the second electrode B of the capacitor C.
  • the second write control voltage is less than the first write control voltage.
  • the difference between the second write control voltage and the first write control voltage can be reasonably set according to needs.
  • the voltage of the data signal line BL1 is pulled up to the first reference voltage V1, and the voltage difference between the first electrode S/D11 of the first transistor T1 and the storage node SN can make the first transistor T1 in the off state.
  • the second transistor T2 connected to the storage node SN and the auxiliary signal line BL2 is in the on state, and based on the coupling effect between the capacitor C, the data signal line BL1 and the auxiliary signal line BL2, the voltage of the storage node SN can be kept stable.
  • the second transistor T2 is turned off first, and then the first reference voltage is provided to the first transistor T1 and the second transistor T2 at the same time through the auxiliary signal line BL2, which can avoid the second transistor T2 from generating leakage current, thereby keeping the data data in the storage node SN.
  • the data signal line BL1 reads the data data in response to whether the first transistor T1 is turned on, which can be expressed as reading the data data through the change of the current or voltage transmitted by the data signal line BL1. Therefore, in the data retention stage, after turning off the second transistor T2, the first control signal line WL can also be used to apply a second write control voltage to the second electrode B of the capacitor C.
  • the second write control voltage is less than the first write control voltage, and the voltage of the storage node SN can be pulled down.
  • the first control signal line WL is further configured to: provide a second write control voltage to the second electrode B of the capacitor C during the data holding stage, and the second write control voltage is less than the first write control voltage.
  • the data signal line BL1 is further configured to: provide a first reference voltage to the first transistor T1 after the voltage of the second electrode B is the second write control voltage during the data holding stage.
  • the second control signal line WWL is further configured to: control the second transistor T2 to be turned off after the data signal line BL1 provides the first reference voltage during the data holding stage.
  • the auxiliary signal line BL2 is further configured to: provide the first reference voltage to the first transistor T1 and the second transistor T2 at the same time after the second transistor T2 is turned off during the data holding stage.
  • a second write control voltage is first provided to the second electrode B of the capacitor C.
  • the second write control voltage is less than the first write control voltage, and can pull down the voltage of the storage node SN to control the first transistor T1 to be in an off state.
  • the voltage of the data signal line BL1 is pulled up to the first reference voltage V1. Since the second transistor T2 connected to the storage node SN and the auxiliary signal line BL2 remains in an on state at this time, the voltage of the storage node SN remains stable.
  • the second transistor T2 is turned off, and the first reference voltage is provided to the first transistor T1 and the second transistor T2 at the same time through the auxiliary signal line BL2, which can avoid the second transistor T2 from generating leakage current and stabilize the data data at the storage node SN.
  • control of the voltage on the second electrode B of the capacitor C by the first control signal line WL and the control of the voltage on the second gate G2 of the second transistor T2 by the second control signal line WWL can be found in the data reading and writing method described later. Introduced.
  • each write control voltage provided by the first control signal line WL and the second control signal line WWL is a pulse voltage.
  • the first write control voltage provided by the first control signal line WL in a write cycle and the read control voltage provided by the first control signal line WL in a read cycle may be the same or different.
  • the first write control voltage and the read control voltage are the same.
  • the first transistor T1 and the second transistor T2 are both N-type transistors
  • the first write control voltage and the read control voltage can both be high-level voltages.
  • the first transistor T1 and the second transistor T2 are both P-type transistors
  • the first write control voltage and the read control voltage can both be low-level voltages.
  • the first write control voltage is smaller than the read control voltage.
  • the absolute value of the first write control voltage is smaller than the absolute value of the read control voltage.
  • the above is the storage unit and the driving method of the storage unit provided in the embodiments of the present application.
  • the storage array of the storage unit will be introduced below.
  • the number of memory cells U is multiple.
  • the multiple memory cells U are arranged in rows along the first direction and in columns along the second direction; m ⁇ n memory cells are schematically shown in the figure.
  • the first direction intersects with the second direction.
  • the first direction is the row direction, which is also the extension direction of the first control signal line WL and/or the second control signal line WWL.
  • the second direction is the column direction, which is also the extension direction of the data signal line BL1 and/or the auxiliary signal line BL2.
  • the first direction and the second direction are, for example, orthogonal.
  • a row of memory cells U share a first control signal line WL and a second control signal line WWL.
  • a column of memory cells U share a data signal line BL1 and an auxiliary signal line BL2.
  • the transistors in each memory cell in the figure are taken as N-type transistors as an example.
  • the coupling capacitance between the data signal line BL1 and the storage node SN is less than the first target threshold.
  • the coupling capacitance between the auxiliary signal line BL2 and the storage node SN is less than the second target threshold.
  • the first target threshold and the second target threshold may be the same or different.
  • both the first target threshold and the second target threshold may be smaller values.
  • the coupling capacitance between the data signal line BL1 and the storage node SN is the first coupling capacitance.
  • the total coupling capacitance between the data signal line BL1 and the capacitor C and the auxiliary signal line BL2 is the second coupling capacitance.
  • the ratio of the first coupling capacitance to the second coupling capacitance is less than the target value. And, the smaller the target value, the better.
  • the data read-write circuit further includes a first reference voltage terminal v1 and a second reference voltage terminal v2 .
  • the first reference voltage terminal v1 is connected to the data signal line BL1 through the first gating circuit 10, and is connected to the auxiliary signal line BL2 through the second gating circuit 20.
  • the first reference voltage terminal v1 is configured to provide a first reference voltage.
  • the first gating circuit 10 is configured to: in the standby stage and the pre-charging stage, select the first reference voltage terminal v1 and the data signal line BL1 to be connected;
  • the second gating circuit 20 is configured to: in the standby stage and the pre-charging stage, select the first reference voltage terminal v1 and the auxiliary signal line BL2 to be connected.
  • the second reference voltage terminal v2 is connected to the auxiliary signal line BL2 via the third selection circuit 30.
  • the second reference voltage terminal v2 is configured to provide a second reference voltage.
  • the third selection circuit 30 is configured to select the second reference voltage terminal v2 and the auxiliary signal line BL2 to be connected during the data reading phase.
  • the first reference voltage terminal v1 connected to the data signal line BL1 and the first reference voltage terminal v1 connected to the auxiliary signal line BL2 may be the same voltage terminal, or may be different voltage terminals providing the same voltage.
  • first reference voltage terminal v1 connected to the data signal line BL1 and the first reference voltage terminal v1 connected to the auxiliary signal line BL2 are different voltage terminals providing the same voltage, and the different voltage terminals can be arranged in different areas, for example, respectively arranged on two opposite sides of the memory cell U array.
  • the first selection circuit 10 includes first selection transistors TC1 connected to each data signal line BL1 in a one-to-one correspondence; wherein the gate of each first selection transistor TC1 is connected to the first selection signal line BL1.
  • the first electrodes of the first selection transistors TC1 are connected to the corresponding data signal lines BL1; the second electrodes of the first selection transistors TC1 are connected to the first reference voltage terminal v1.
  • the second selection circuit 20 includes second selection transistors TC2 connected to each auxiliary signal line BL2 in a one-to-one correspondence; wherein the gate of each second selection transistor TC2 is connected to the second selection signal line CTL2; the first electrode of each second selection transistor TC2 is respectively connected to the corresponding auxiliary signal line BL2; the second electrode of each second selection transistor TC2 is connected to the first reference voltage terminal v1.
  • the third selection circuit 30 includes third selection transistors TC3 connected to each auxiliary signal line BL2 in a one-to-one correspondence; wherein the gate of each third selection transistor TC3 is connected to the read selection signal line CTL-R; the first electrode of each third selection transistor TC3 is respectively connected to the corresponding auxiliary signal line BL2; the second electrode of each third selection transistor TC3 is connected to the second reference voltage terminal v2.
  • each selection transistor may be a source electrode and the other may be a drain electrode.
  • each selection transistor may be selectively turned on in response to a selection signal mentioned on a corresponding selection signal line to realize read and write control of each storage unit U.
  • the data read and write circuit may further include one or more sense amplifier circuits 40.
  • the data read and write circuit includes a plurality of sense amplifier circuits 40 corresponding to the data signal lines BL1 one by one.
  • one end of each data signal line BL1 away from the first reference voltage terminal v1 is respectively connected to the corresponding sense amplifier circuit 40 to read data.
  • the sensing amplifier circuit 40 may be a current sensing amplifier circuit or a voltage sensing amplifier circuit.
  • the sensing amplifier circuit 40 is a current sensing amplifier circuit.
  • the data signal line BL1 continuously provides the first reference voltage, and in response to whether the first transistor T1 is turned on, the sensing amplifier circuit 40 can read data by sensing the change of the current transmitted by the data signal line BL1.
  • the sensing amplifier circuit 40 is a voltage sensing amplifier circuit.
  • the first reference voltage pre-provided by the data signal line BL1 may change or not change, so that the sensing amplifier circuit 40 can read data by sensing the change of the voltage transmitted by the data signal line BL1.
  • the embodiment of the present disclosure does not limit the circuit structure of the sensing amplifier circuit 40.
  • the sensing amplifier circuit 40 is a voltage sensing amplifier circuit, such as a comparison amplifier circuit, and the sensing amplifier circuit 40 can be connected to the third reference voltage terminal v3 to read data by comparing the difference between the third reference voltage provided by the third reference voltage terminal v3 and the voltage transmitted by the data signal line BL.
  • the first write control voltage provided by the first control signal line WL and the third write control voltage provided by the second control signal line WWL are both control voltages provided for the storage unit U when performing data writing. Based on this, it can be understood that for the storage unit U array, in addition to providing the aforementioned first write control voltage and third write control voltage to the row where the storage unit U performing data writing is located, the first control signal line WL corresponding to the storage unit U in other rows provides the second write control voltage, and the second control signal line WWL corresponding to the storage unit U in other rows provides the fourth write control voltage, so as to realize the row scanning writing of the storage unit U array.
  • Some embodiments of the present disclosure also provide a data reading and writing method to implement the data reading and writing process of the above-mentioned data reading and writing circuit.
  • the data reading and writing method can be applied to any storage unit U, and the storage unit U is configured to store data. Its structure can refer to the relevant description in some of the above-mentioned embodiments.
  • the data reading and writing method also has the technical advantages of the above-mentioned data reading and writing circuit.
  • the data reading and writing cycle t of the storage unit U includes a write cycle tW, a read cycle tR and a standby stage (for example, a first standby stage tD1 and a second standby stage tD2).
  • the write cycle tW includes a pre-charge phase tW1 and a data writing phase tW2.
  • the data reading and writing method includes steps S100 and S200.
  • the data signal line BL1 provides the first reference voltage V1 to the first transistor T1
  • the auxiliary signal line BL2 provides a first reference voltage V1 to the first transistor T1 and the second transistor T2 at the same time; the second electrode B of the capacitor C applies a first write control voltage VCW1, the second transistor T2 is turned on, and the storage node SN is pre-charged; wherein, the sum of the maximum data voltage corresponding to the data and the threshold voltage Vth of the first transistor T1 is the reference voltage, and the first reference voltage V1 is greater than the reference voltage.
  • the voltage of the storage node SN is the first reference voltage V1.
  • the data that can be stored in the memory cell U includes data “0” and data "1", wherein the data voltage Vdata1 corresponding to the data "1" is greater than the data voltage Vdata0 corresponding to the data "0". Based on this, the data voltage Vdata1 corresponding to the data "1" can be the maximum data voltage that can be stored in the memory cell U. Vice versa.
  • the reference voltage is Vdata1+Vth
  • the first reference voltage is greater than Vdata1+Vth.
  • the difference between the first reference voltage and the reference voltage can be reasonably set according to requirements.
  • the reference voltage is defined as the sum of the maximum data voltage and the threshold voltage Vth of the first transistor T1 for the convenience of description, and is only used to illustrate the value range of the first reference voltage when the reference voltage is used as a reference standard.
  • the first transistor T1 and the second transistor T2 are N-type transistors or P-type transistors, which are also allowed.
  • the first transistor T1 and the second transistor T2 are N-type transistors or P-type transistors, which are also allowed.
  • some of the following embodiments are described by taking the first transistor T1 and the second transistor T2 as N-type transistors as examples.
  • the first control signal line WL applies the first write control voltage VCW1 to the capacitor C.
  • the second control signal line WWL provides the third write control voltage VCW3 to the second gate G2 of the second transistor T2.
  • the data signal line BL1 provides the first reference voltage V1 to the first electrode S/D11 of the first transistor T1
  • the auxiliary signal line BL2 provides the first reference voltage V1 to the second electrode S/D12 of the first transistor T1
  • the first transistor T1 is in a non-conducting state.
  • the first write control voltage VCW1 and the third write control voltage VCW3 are both high-level voltages.
  • the first write control voltage VCW1 is less than the third write control voltage VCW3 , and the first write control voltage VCW1 can be reasonably set according to requirements.
  • the auxiliary signal line BL2 floats, the data signal line BL1 provides the data voltage Vdata to the first transistor T1, and the first transistor T1 is turned on.
  • the storage node SN is discharged to a stable state, and the data data corresponding to the data voltage Vdata is written.
  • the storage node SN is discharged to a stable state, which means that the voltage of the storage node SN changes toward 0.
  • the voltage of the storage node SN is Vdata+Vth (including approximately equal to).
  • the first control signal line WL continuously applies the first write control voltage VCW1 to the second electrode B of the capacitor C.
  • the second control signal line WWL continuously provides the third write control voltage VCW3 to the second gate G2 of the second transistor T2.
  • the data signal line BL1 provides the data voltage Vdata to the first electrode S/D11 of the first transistor T1, and the auxiliary signal line BL2 floats.
  • the data voltage Vdata provided by the data signal line BL1 is related to the data to be written.
  • the data to be written is data "1”
  • the data voltage provided by the data signal line BL1 during the data writing phase tW2 is Vdata1.
  • the data to be written is data "0”
  • the data voltage provided by the data signal line BL1 during the data writing phase tW2 is Vdata0.
  • the auxiliary signal line BL2 is connected to the first reference voltage terminal v1 through the second gating circuit 20, and is connected to the second reference voltage terminal v2 through the third gating circuit 30.
  • the auxiliary signal line BL2 is floating, which means that the second gating circuit 20 and the third gating circuit 30 connected to the auxiliary signal line BL2 are both in the off state, and no signal is input to the end of the auxiliary signal line BL2 connecting the second gating circuit 20 and the third gating circuit 30.
  • the write cycle tW further includes: a data holding phase tW3 after the data writing phase tW2 .
  • the data reading and writing method further includes step S300 .
  • the voltage of the data signal line BL1 is pulled up to the first reference voltage V1
  • the second transistor T2 is turned off first, and then the auxiliary signal line BL2 is pulled up. to the first reference voltage V1.
  • the data reading and writing method further includes: applying a second write control voltage VCW2 to the second electrode B of the capacitor C, the second write control voltage VCW2 being less than the first write control voltage VCW1.
  • the difference between the second write control voltage and the first write control voltage can be reasonably set according to the requirements.
  • the voltage of the data signal line BL1 can be pulled up to the first reference voltage V1, and the voltage difference between the first electrode S/D11 of the first transistor T1 and the storage node SN makes the first transistor T1 in the off state.
  • the second transistor T2 connecting the storage node SN and the auxiliary signal line BL2 is in the on state, and based on the coupling effect between the capacitor C, the data signal line BL1 and the auxiliary signal line BL2, the voltage of the storage node SN can be kept stable (for example, kept at Vdata+Vth).
  • the second transistor T2 is turned off first, and then the first reference voltage V1 is provided to the first transistor T1 and the second transistor T2 at the same time through the auxiliary signal line BL2, so that the data data can be retained in the storage node SN (the voltage of the storage node SN includes Vdata+Vth).
  • the data signal line BL1 reads the data data in response to whether the first transistor T1 is turned on, which can be expressed as reading the data data through the change of the current or voltage transmitted by the data signal line BL1. Therefore, in the data holding stage tW3, after turning off the second transistor T2, the first control signal line WL can also be used to apply the second write control voltage VCW2 to the second electrode B of the capacitor C.
  • the second write control voltage VCW2 is less than the first write control voltage VCW1, and can pull down the voltage of the storage node SN.
  • the voltage of the auxiliary signal line BL2 is first pulled up to the first reference voltage V1, or the second write control voltage VCW2 is first applied to the second electrode B of the capacitor C through the first control signal line WL, or both are performed at the same time, which is also allowed.
  • the voltage of the storage node SN changes accordingly.
  • the second write control voltage VCW2 is a low-level voltage, and if the data written to the storage node SN is data "1", the voltage of the storage node SN can be changed to: Vdata1+Vth- ⁇ V; if the data written to the storage node SN is data "0", the voltage of the storage node SN can be changed to: Vdata0+Vth- ⁇ V.
  • the voltage of the storage node SN will change accordingly.
  • the read control voltage VCR is a high-level voltage. If the data written to the storage node SN is data "1", the voltage of the storage node SN can be changed to: Vdata1+Vth- ⁇ V+ ⁇ V'; if the data written to the storage node SN is data "0", the voltage of the storage node SN can be changed to: Vdata0+Vth- ⁇ V+ ⁇ V'.
  • the voltage of the storage node SN changes after the first control signal line WL applies the second write control voltage VCW2 or the read control voltage VCR to the second electrode B of the capacitor C
  • the voltage of the storage node SN always includes the data voltage Vdata corresponding to the write data and the threshold voltage Vth of the first transistor T1, and corresponding to different data voltages (for example, Vdata1 and Vdata0), the voltage change of the storage node SN is the same, which does not affect the accurate reading of data in the data reading stage tR.
  • the data reading and writing method further includes step S300 ′.
  • the turning off of the second transistor T2 can be achieved by controlling the turning off control voltage (ie, the fourth write control voltage VCW4 ) applied by the second control signal line WWL to the second gate G2 .
  • the turning off control voltage ie, the fourth write control voltage VCW4
  • the second write control voltage VCW2 and the fourth write control voltage VCW4 are the same.
  • the first transistor T1 and the second transistor T2 are both N-type transistors. Accordingly, the second write control voltage VCW2 and the fourth write control voltage VCW4 are both low-level voltages.
  • the second write control voltage VCW2 is first applied to the second electrode B of the capacitor C.
  • the second write control voltage VCW2 is less than the first write control voltage VCW1, and can pull down the voltage of the storage node SN to control the first transistor T1 to be in an off state.
  • the voltage of the data signal line BL1 is pulled up to the first reference voltage V1. Since the second transistor T2 connecting the storage node SN and the auxiliary signal line BL2 remains in an on state at this time, the voltage of the storage node SN remains stable (for example, maintained at Vdata+Vth).
  • the second transistor T2 is turned off, and the first reference voltage V1 is provided to the first transistor T1 and the second transistor T2 at the same time through the auxiliary signal line BL2, which can avoid the second transistor T2 from generating leakage current and stabilize the data data at the storage node SN (for example, the voltage of the storage node SN is Vdata+Vth).
  • the read cycle tR includes: a data reading phase tR.
  • the data reading and writing method further includes step S400.
  • a read control voltage VCR is applied to the second electrode B of the capacitor C, and a second reference voltage V2 is simultaneously provided to the first transistor T1 and the second transistor T2 through the auxiliary signal line BL2; wherein the data signal line BL1 is also configured to read data in response to whether the first transistor T1 is turned on.
  • the second reference voltage V2 is lower than the first reference voltage V1.
  • the second reference voltage V2 is greater than a minimum data voltage that can store data in the memory cell U, and less than a maximum data voltage that can store data in the memory cell U.
  • the second reference voltage V2 can be greater than the sum of the minimum data voltage and the voltage variable (vector) caused by the coupling effect, and less than the sum of the maximum data voltage and the voltage variable (vector) caused by the coupling effect.
  • the first write control voltage VCW1 provided by the first control signal line WL in the write period tW and the read control voltage VCR provided by the first control signal line WL in the read period tR may be the same or different.
  • the first write control voltage VCW1 is the same as the read control voltage VCR.
  • the first write control voltage VCW1 is smaller than the read control voltage VCR.
  • the read control voltage VCR applied to the second electrode B of the capacitor C in response to the read command refers to a suitable voltage applied by the first control signal line WL, which can ensure that the first transistor T1 is in different states when the storage node SN stores different data.
  • Figures (a) and (b) in Figure 8 respectively show the current-voltage characteristic curves of the first transistor T1 when two different read control voltages VCR are applied to the second electrode B of the capacitor C; wherein the read control voltage VCR corresponding to Figure (a) is smaller than the read control voltage VCR corresponding to Figure (b).
  • Figures (a) and (b) in Figure 8 it can be seen that a reasonable selection of the magnitude of the read control voltage VCR can ensure that the first transistor T1 can be in an obvious on or off state when the storage node SN stores data "0" or data "1", so as to facilitate reading data.
  • the data written to the storage node SN includes “1” or “0”.
  • the data reading phase tR after applying the read control voltage VCR to the second electrode B of the capacitor C:
  • the gate-source voltage VGS of the first transistor T1 ie, the voltage difference between the first gate G1 and its second electrode S/D12
  • VGS of the first transistor T1 is large and greater than the threshold voltage Vth of the first transistor T1
  • the first transistor T1 is in the on state.
  • the gate-source voltage VGS of the first transistor T1 ie, the voltage difference between the first gate G1 and its second electrode S/D12
  • the threshold voltage Vth of the first transistor T1 is in the off state.
  • FIG. 5 and FIG. 7 are used as examples below, and the data reading method shown in FIG. 6 can be understood adaptively.
  • the voltage of the second electrode S/D12 in the first transistor T1 is the voltage of the auxiliary signal line BL2
  • the second reference voltage V2 is provided.
  • the gate-source voltage VGS of the first transistor T1 Vdata1 + Vth - V2. Since V2 is less than Vdata1, the gate-source voltage VGS of the first transistor T1 is greater than Vth.
  • the voltage of the second electrode S/D12 in the first transistor T1 is the second reference voltage V2 provided by the auxiliary signal line BL2.
  • the gate-source voltage VGS of the first transistor T1 Vdata0 + Vth-V2. Since V2 is greater than Vdata0, the gate-source voltage VGS of the first transistor T1 is less than Vth.
  • the matching data read and write circuit reads data in a manner in which the data signal line BL1 responds to whether the first transistor T1 is turned on and reads data in a manner that can be expressed as: current sensing reading or voltage sensing reading.
  • the data signal line BL1 continuously provides the first reference voltage V1.
  • the sensing amplifier circuit 40 connected to the data signal line BL1 can read data by sensing the change of the current transmitted by the data signal line BL1.
  • the sensing amplifier circuit 40 can read data by sensing the change of the voltage transmitted by the data signal line BL1.
  • the data read and write cycle t also includes: a standby phase (i.e., Stand by phase) before the pre-charging phase tW1 and/or before the data reading phase tR.
  • a standby phase i.e., Stand by phase
  • the data read/write cycle t also includes: a data holding phase tW3 after the data writing phase tW2.
  • a standby phase includes: a first standby phase tD1 before the pre-charging phase tW1, and a second standby phase tD2 after the data holding phase tW3 and before the data reading phase tR.
  • the data reading and writing method provided by the embodiment of the present disclosure also includes the following steps.
  • the first transistor T1 and the second transistor T2 are in the off state, the data signal line BL1 provides the first reference voltage V1 to the first transistor T1, and the auxiliary signal line BL2 provides the first reference voltage V1 to the first transistor T1 and the second transistor T2 at the same time.
  • the embodiment of the present disclosure can use the data signal line BL1 to provide the first reference voltage V1 to the first electrode of the first transistor T1, and use the auxiliary signal line BL2 to provide the first reference voltage V1 to the second electrode of the first transistor T2, thereby ensuring that there is no large voltage difference between the first electrode and the second electrode of the first transistor T1, so as to effectively reduce the risk of leakage current generation, especially when the first reference voltage V1 is a high-level voltage.
  • first standby stage tD1 and the second standby stage tD2 mentioned in some of the above embodiments are the standby stages mentioned in the aforementioned data read and write circuit.
  • first standby stage tD1 can be independent of the write cycle tw
  • second standby stage tD2 can be independent of the read cycle tR.
  • the first standby stage tD1 and the second standby stage tD2 can also be regarded as the same standby stage, so as to enter different read and write cycles in response to different received commands. For example, when a write command is received, a write cycle is entered, or when a read command is received, a read cycle is entered.
  • the first control signal line WL applies the second write control voltage VCW2 to the second electrode B of the capacitor C; the second control signal line WWL applies the fourth write control voltage VCW4 to the second gate G2 of the second transistor T2.
  • the second write control voltage VCW2 and the fourth write control voltage VCW4 are the same.
  • the first transistor T1 and the second transistor T2 are both N-type transistors.
  • the second write control voltage VCW2 and the fourth write control voltage VCW4 are both low-level voltages.
  • the storage unit U is configured to store data, including a capacitor C and a first transistor T1 and a second transistor T2 connected to a first electrode A of the capacitor C.
  • a data signal line BL2 is connected to the first transistor T1 in the storage unit U, and an auxiliary signal line BL2 is connected to the first transistor T1 in the storage unit U.
  • the first transistor T1 and the second transistor T2 are connected, and in the pre-charging stage tW1, after the data signal line BL1 provides the first reference voltage V1 to the first transistor T1, the auxiliary signal line BL2 provides the first reference voltage V1 to the first transistor T1 and the second transistor T2 at the same time, and the first control signal line WL provides the first write control voltage VCW1 to the second electrode B of the capacitor C, and the second transistor T2 is turned on, the storage node SN is pre-charged.
  • the auxiliary signal line BL2 floats and the data signal line BL1 provides the data voltage Vdata to the first transistor T1, then the first transistor T1 is turned on, and the storage node SN can be naturally discharged to a stable state to write the data data corresponding to the aforementioned data voltage Vdata.
  • the voltage of the storage node SN after pre-charging is greater than the reference voltage, for example, greater than (Vdata1+Vth), that is, the voltage of the storage node SN is not only greater than the data voltage Vdata provided by the data signal line BL1, but the difference between the voltage of the storage node SN and the aforementioned data voltage Vdata is also greater than the threshold voltage Vth of the first transistor T1.
  • some embodiments of the present disclosure may turn off the first transistor T1 and the second transistor T2 (see the relevant description of the data holding stage tW3 for details).
  • the data signal line BL1 and the auxiliary signal line BL2 may be used to provide the first reference voltage V1 to the first transistor T1, respectively, and the auxiliary signal line BL2 may be used to provide the first reference voltage V1 to the second transistor T2.
  • the first transistor T1 and the second transistor T2 are both in the off state, and the voltage of the storage node SN can be kept stable.
  • a read control voltage VCR may be provided to the second electrode B of the capacitor C, and a second reference voltage V2 may be provided to the first transistor T1 and the second transistor T2 simultaneously through the auxiliary signal line BL2.
  • the voltage of the storage node SN may affect the conduction between the first electrode S/D11 and the second electrode S/D12 of the first transistor T1, so that the data signal line BL1 reads data in response to whether the first transistor T1 is turned on.
  • the data read by the data signal line BL1 in response to whether the first transistor T1 is turned on may not be affected by the threshold voltage Vth of the first transistor T1, so as to ensure the accuracy of the reading of the stored data data, thereby further improving the memory performance.
  • Some embodiments of the present disclosure also provide a memory on the other hand.
  • it includes at least one storage unit U, and a first bit line BL1, a second bit line BL2, a first word line WL and a second word line WWL connected to the storage unit U.
  • the storage unit U includes: a capacitor C, a first transistor T1 and a second transistor T2.
  • the capacitor C includes a first electrode A and a second electrode B that are insulated.
  • the first transistor T1 and the second transistor T2 both include a gate and a first electrode and a second electrode.
  • the first electrode A, the gate G1 of the first transistor T1 and the first electrode S/D21 of the second transistor T2 are connected, and the connection intersection of the three is a storage node SN.
  • the first word line WL is connected to the second electrode B, and the second word line WWL is connected to the gate G2 of the second transistor T2.
  • the first bit line BL1 is connected to the first electrode S/D11 of the first transistor T1, and the second bit line BL2 is simultaneously connected to the second electrode S/D12 of the first transistor T1 and the second electrode S/D22 of the second transistor T2.
  • the first bit line BL1 is configured to provide a data voltage for data to be written in a data writing phase, and read the data written into the storage node in response to whether the first transistor T1 is turned on in a data reading phase.
  • the transmission direction of the matching current is such that, in the first electrode S/D11 and the second electrode S/D12 of the first transistor T1, one may be a source electrode and the other may be a drain electrode. In the first electrode S/D21 and the second electrode S/D22 of the second transistor T2, one may be a source electrode and the other may be a drain electrode.
  • FIG. 2 takes the first transistor T1 and the second transistor T2 as n-type transistors as an example for description, and the type of the transistor is not limited in practical applications.
  • the function of the first bit line BL1 in the memory is equivalent to the function of the aforementioned data signal line
  • the function of the second bit line BL2 is equivalent to the function of the aforementioned auxiliary signal line
  • the function of the first word line WL is equivalent to the function of the aforementioned first control signal line
  • the function of the second word line WWL is equivalent to the function of the aforementioned second control signal line.
  • Some embodiments of the present disclosure also provide a method for driving a memory, which is used to drive the memory as described above. Referring to FIG. 2 and FIG. 5 , FIG. 6 , and FIG. 7 , the method includes the following steps.
  • the first bit line BL1 provides the first reference voltage V1 to the first electrode S/D11 of the first transistor T1.
  • the second bit line BL2 provides the first reference voltage V1 to the second electrode S/D12 of the first transistor T1 and the second electrode S/D22 of the second transistor T1 at the same time.
  • the first word line WL applies the first write control voltage VCW1 to the second electrode B.
  • the second word line WWL applies the third write control voltage VCW3 to the gate G2 of the second transistor T2 to control the second transistor T2 to turn on, so as to precharge the storage node SN.
  • the first reference voltage V1 is greater than the sum of the maximum data voltage to be written to the storage unit U and the threshold voltage VTH of the first transistor T1.
  • the second bit line BL2 floats, and the first bit line BL1 provides the data voltage Vdata to the first electrode S/D11 of the first transistor T1.
  • the first transistor T1 is turned on, the storage node SN is discharged to a stable state, and the data data corresponding to the data voltage is written.
  • the second word line WWL applies the fourth write control voltage VCW3 to the gate G2 of the second transistor T2, and the second transistor T2 is in the off state.
  • the first word line WL applies the read control voltage VCR to the second electrode B.
  • the second bit line BL2 simultaneously provides the second reference voltage V2 to the second electrode S/D12 of the first transistor T1 and the second electrode S/D22 of the second transistor T2.
  • the first bit line BL1 reads the data written in the storage node SN in response to whether the first transistor T1 is turned on.
  • the method further includes: in the data holding stage tW3 , pulling up the voltage of the first bit line BL1 to the first reference voltage V1 , and after the voltage of the first bit line BL1 reaches the first reference voltage, first turning off the second transistor T2 , and then pulling up the voltage of the second bit line BL2 to the first reference voltage V1 .
  • the method further includes: the first word line WL applies a second write control voltage VCW2 to the second electrode B of the capacitor C, and the second write control voltage VCW2 is less than the first write control voltage VCW1. Moreover, the difference between the second write control voltage VCW2 and the first write control voltage VCW1 can be reasonably set according to needs.
  • the method further includes: in the data holding stage tW3 , the first word line WL first applies a second write control voltage VCW2 to the second electrode B of the capacitor C, and pulls up the voltage of the first bit line BL1 to the first reference voltage V1; and then turns off the second transistor T2, and pulls up the voltage of the second bit line BL2 to the first reference voltage V1.
  • the second write control voltage VCW2 is less than the first write control voltage VCW1.
  • the turn-off of the second transistor T2 can be achieved by controlling the turn-off control voltage (ie, the fourth write control voltage VCW4 ) applied by the second word line WWL to the gate G2 thereof.
  • the turn-off control voltage ie, the fourth write control voltage VCW4
  • the method also includes: in a first standby stage tD1 before the pre-charging stage tW1, and a second standby stage tD2 after the data holding stage tW3 and before the data reading stage tR, the first word line WL applies a second write control voltage VCW2 to the second electrode B of the capacitor C, the second word line WWL applies a fourth write control voltage VCW4 to the gate G2 of the second transistor T2, the first bit line BL1 provides a first reference voltage V1 to the first electrode S/D11 of the first transistor T1, and the second bit line BL2 provides a first reference voltage V1 to the second electrode S/D12 of the first transistor T1 and the second electrode S/D22 of the second transistor T2 at the same time.
  • Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other devices with data storage functions.
  • the electronic device may include a housing, a circuit board disposed in the housing, and a memory or a data read-write circuit integrated on the circuit board.
  • the structure of the memory or the data read-write circuit can refer to the relevant description in some of the above embodiments.
  • the electronic device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.
  • the memory may be coupled to an external control device such as a processor or an actuator.
  • the processor is coupled to the memory, and the processor can control the read and write operations of the memory.
  • the memory is a three-dimensional dynamic random access memory.

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Abstract

本公开涉及一种数据读写电路及其方法、存储器及其驱动方法、电子设备，涉及存储技术领域，用于提高数据读取的准确度。该数据读写方法包括：在预充电阶段，数据信号线(BL1)向第一晶体管(T1)提供第一参考电压(v1)，辅助信号线(BL2)向第一晶体管(T1)和第二晶体管(T2)同时提供第一参考电压(v1)，电容器(C)的第二电极(B)施加第一写控制电压(VCW1)，第二晶体管(T2)导通，对存储节点(SN)进行预充电；其中，数据对应的最大数据电压与第一晶体管(T1)的阈值电压之和为基准电压，第一参考电压(v1)大于基准电压。在数据写入阶段，响应于写命令，辅助信号线(BL2)浮置，数据信号线(BL1)向第一晶体管(T1)提供数据电压，第一晶体管(T1)导通；存储节点(SN)放电至稳定状态，写入数据电压对应的数据。

Description

数据读写电路及其方法、存储器及其驱动方法、电子设备
相关申请的交叉引用
本公开要求于2023年04月28日提交中国专利局、申请号为2023104805526、发明名称为“数据读写电路及其方法、存储器及其驱动方法、电子设备”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及存储技术领域，特别是涉及一种数据读写电路及其方法、存储器及其驱动方法、电子设备。
背景技术
随着通讯技术和数字技术的发展，人们持续追求功耗更低、重量更轻和性能更佳的产品。存储器易于具有更高的集成密度以及更大的存储容量，逐渐成为了目前存储领域的重要研究方向之一。比如，在三维动态随机存取存储器中，相较于存储单元采用1T1C架构，存储单元采用2T架构，可以有效解决存储单元采用1T1C架构时因关键尺寸缩小带来的电容制备工艺难的问题。
发明内容
根据一些实施例，本公开一方面提供了一种数据读写方法，应用于存储单元。存储单元被配置为存储数据，包括电容器及与电容器的第一电极相连接的第一晶体管和第二晶体管。电容器的第一电极、第一晶体管和第二晶体管三者相连接的交点为存储节点。电容器还包括与第一电极相对设置的第二电极。存储单元的数据读写周期包括：预充电阶段和数据写入阶段。数据读写方法包括以下步骤。
在预充电阶段，数据信号线向第一晶体管提供第一参考电压，辅助信号线向第一晶体管和第二晶体管同时提供第一参考电压；电容器的第二电极施加第一写控制电压，第二晶体管导通，对存储节点进行预充电；其中，数据对应的最大数据电压与第一晶体管的阈值电压之和为基准电压，第一参考电压大于基准电压。
在数据写入阶段，响应于写命令，辅助信号线浮置，数据信号线向第一晶体管提供数据电压，第一晶体管导通；存储节点放电至稳定状态，写入所述数据电压对应的数据。
根据一些实施例，数据读写周期还包括：位于数据写入阶段之后的数据保持阶段。所述数据读写方法还包括：在数据保持阶段，上拉数据信号线的电压至第一参考电压，并于数据信号线的电压为第一参考电压之后先关断第二晶体管，再上拉辅助信号线的电压至第一参考电压；其中，在关断第二晶体管之后，向电容器的第二电极施加第二写控制电压；第二写控制电压小于第一写控制电压。
根据另一些实施例，数据读写周期还包括：位于数据写入阶段之后的数据保持阶段。所述数据读写方法还包括：在数据保持阶段，先向电容器的第二电极施加第二写控制电压，上拉数据信号线的电压至第一参考电压；再关断第二晶体管，上拉辅助信号线的电压至第一参考电压；其中，第二写控制电压小于第一写控制电压。
根据一些实施例，数据读写周期还包括数据读取阶段。所述数据读写方法还包括：在数据读取阶段，响应于读命令，向电容器的第二电极施加读控制电压，并通过辅助信号线向第一晶体管和第二晶体管同时提供第二参考电压；其中，数据信号线响应于第一晶体管是否导通读取数据。
根据一些实施例，存储节点写入的数据包括“1”或“0”。在数据读取阶段，存储节点写入的数据为“1”时，第一晶体管处于导通状态。存储节点写入的数据为“0”时，第一晶体管处于关断状态。
根据一些实施例，数据读写周期还包括：位于预充电阶段之前和/或位于数据读取阶段之前的待机阶段。数据读写方法还包括：在待机阶段，第一晶体管和第二晶体管处于关断状态，数据信号线向第一晶体管提供第一参考电压，辅助信号线向第一晶体管和第二晶体管同时提供第一参考电压。
根据一些实施例，数据读写周期还包括：位于数据写入阶段之后的数据保持阶段。数据读取阶段位于数据保持阶段之后。待机阶段包括：位于预充电阶段之前的第一待机阶段，以及位于数据保持阶段之后且位于数据读取阶段之前的第二待机阶段。
根据一些实施例，本公开又一方面还提供了一种数据读写电路，包括存储单元、数据信号线和辅助信号线。存储单元被配置为存储数据，包括电容器及与电容器的第一电极相连接的第一晶体管和第二晶体管。电容器还包括与第一电极相对设置的第二电极。数据信号线与第一晶体管相连接，被配置为于待机阶段和预充电阶段向第一晶体管提供第一参考电压，于数据写入阶段向第一晶体管提供数据电压，于数据读取阶段响应于所述第一晶体管是否导通读取数据。辅助信号线与第一晶体管、第二晶体管相连接，被配置为于待机阶段和预充电阶段向第一晶体管提供第一参考电压，于数据写入阶段浮置，于数据读取阶段向第一晶体管和第二晶体管同时提供第二参考电压。其中，数据对应的最大数据电压与第一晶体管的阈值电压之和为基准电压；第一参考电压大于基准电压。
根据一些实施例，数据读写电路还包括第一控制信号线和第二控制信号线。第一控制信号线与电容器的第二电极相连接，被配置为：于预充电阶段和数据写入阶段向电容器的第二电极施加第一写控制电压，于数据读取阶段向电容器的第二电极施加读控制电压。第二控制信号线与第二晶体管相连接，被配置为于待机阶段和数据读取阶段控制第二晶体管关断，于预充电阶段和数据写入阶段控制第二晶体管导通。
根据一些实施例，数据信号线还被配置为：于数据保持阶段，向第一晶体管提供第一参考电压。第二控制信号线还被配置为：于数据保持阶段，在数据信号线的电压为第一参考电压之后，控制第二晶体管关断。辅助信号线还被配置为：于数据保持阶段，在关断第二晶体管之后，向第一晶体管和第二晶体管同时提供第一参考电压。
此外，第一控制信号线还被配置为：于数据保持阶段，在关断第二晶体管之后，向电容器的第二电极施加第二写控制电压；其中，第二写控制电压小于第一写控制电压。
根据另一些实施例，第一控制信号线还被配置为：于数据保持阶段，向电容器的第二电极施加第二写控制电压；其中，第二写控制电压小于第一写控制电压。数据信号线还被配置为：于数据保持阶段，在第二电极的电压为第二写控制电压之后向第一晶体管提供第一参考电压。第二控制信号线还被配置为：于数据保持阶段，在数据信号线提供第一参考电压之后，控制第二晶体管关断。辅助信号线还被配置为：于数据保持阶段，在关断第二晶体管之后向第一晶体管和第二晶体管同时提供第一参考电压。
根据一些实施例，第一晶体管包括第一栅极、第一极和第二极。第二晶体管包括第二栅极、第一极和第二极。其中，第一栅极和第二晶体管的第一极均与电容器的第一电极相连接。电容器的第二电极与第一控制信号线相连接。第二栅极与第二控制信号线相连接。第一晶体管的第一极与数据信号线相连接。第一晶体管的第二极和第二晶体管的第二极分别与辅助信号线相连接。
根据一些实施例，存储单元的数量为多个。多个存储单元沿第一方向排布呈行，沿第二方向排布呈列；第一方向和第二方向相交。其中，一行存储单元共用一条第一控制信号线和一条第二控制信号线。一列存储单元共用一条数据信号线和一条辅助信号线。
根据一些实施例，数据读写电路还包括第一参考电压端和第二参考电压端。
第一参考电压端通过第一选通电路与数据信号线对应连接，通过第二选通电路与辅助信号线对应连接。其中，第一参考电压端被配置为提供第一参考电压。第一选通电路被配置为：于待机阶段和预充电阶段，选择连通第一参考电压端和数据信号线。第二选通电路 被配置为：于待机阶段和预充电阶段，选择连通第一参考电压端和辅助信号线。
第二参考电压端通过第三选通电路与辅助信号线对应连接。其中，第二参考电压端被配置为提供第二参考电压。第三选通电路被配置为：于数据读取阶段选择连通第二参考电压端和辅助信号线。
根据一些实施例，本公开又一方面还提供了一种存储器，包括至少一个存储单元，以及与存储单元对应连接的第一位线、第二位线、第一字线和第二字线；其中，存储单元包括：电容器、第一晶体管和第二晶体管。电容器包括绝缘设置的第一电极和第二电极。第一晶体管和第二晶体管均包括栅极和第一极、第二极。第一电极、第一晶体管的栅极和第二晶体管的第一极相连接，且三者的连接交点为存储节点。第一字线与第二电极相连接，第二字线与第二晶体管的栅极相连接。第一位线与第一晶体管的第一极相连接，第二位线与第一晶体管的第二极、第二晶体管的第二极同时连接。第一位线被配置为：于数据写入阶段提供待写入数据的数据电压，于数据读取阶段响应于第一晶体管是否导通读取存储节点已写入的数据。
根据一些实施例，本公开又一方面还提供了一种存储器的驱动方法，应用于如上所述的存储器。所述方法包括步骤如下。
在预充电阶段，第一位线向第一晶体管的第一极提供第一参考电压。第二位线向第一晶体管的第二极和第二晶体管的第二极同时提供第一参考电压。第一字线向第二电极施加第一写控制电压。第二字线向第二晶体管的栅极施加第三写控制电压，控制第二晶体管导通，以对存储节点进行预充电。其中，第一参考电压大于存储单元待写入的最大数据电压和第一晶体管的阈值电压之和。
在数据写入阶段，第二位线浮置，第一位线向第一晶体管的第一极提供数据电压。第一晶体管导通，存储节点放电至稳定状态，写入所述数据电压对应的数据。
在数据读取阶段，第二字线向第二晶体管的栅极施加第四写控制电压，第二晶体管处于关断状态。第一字线向第二电极施加读控制电压。第二位线向第一晶体管的第二极和第二晶体管的第二极同时提供第二参考电压。第一位线响应于第一晶体管是否导通读取存储节点已写入的数据。
根据一些实施例，本公开又一方面还提供了一种电子设备，包括：如上一些实施例中所述的数据读写电路；或如上一些实施例中所述的存储器。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为相关技术中提供的一种2T0C架构存储单元的电路示意图；
图2为本公开一些实施例中提供的一种数据读写电路或存储器的电路示意图；
图3为本公开一些实施例中提供的另一种数据读写电路或存储器的结构框图；
图4为图3所示数据读写电路或存储器的一种等效电路图；
图5为本公开一些实施例中提供的一种数据读写方法或一种存储器的驱动方法的时序图；
图6为本公开一些实施例中提供的另一种数据读写方法或另一种存储器的驱动方法的时序图；
图7为本公开一些实施例中提供的又一种数据读写方法或另一种存储器的驱动方法 的时序图；
图8为本公开一些实施例中提供的一种数据读取阶段施加不同读控制电压时第一晶体管的电流-电压特性变化的曲线图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本公开的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
可以理解，本申请所使用的术语“第一”、“第二”、“第三”、“第四”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将第一个元件与另一个元件区分。举例来说，在不脱离本申请的范围的情况下，可以将第一晶体管称为第二晶体管，且类似地，可将第二晶体管称为第一晶体管。第一晶体管和第二晶体管两者都是晶体管，但其不是同一晶体管。
可以理解，以下实施例中的“连接”，如果被连接的电路、模块、单元等相互之间具有电信号或数据的传递，则应理解为“电连接”、“通信连接”等。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中使用的术语“和/或”包括相关所列项目的任何及所有组合。
目前，在三维动态随机存取存储器中，各存储单元可以采用1T1C架构、2T0C架构及2T1C架构等。然而，存储单元采用2T1C架构时也容易面对更多新的挑战。
示例地，如图1中所示，采用2T1C架构的存储单元包括：读晶体管T_r、写晶体管T_w以及第一电极与读晶体管T_r的第二极、写晶体管T_w的第二极同时连接的电容器C；其中，电容器C的第二电极连接接地电压端。读晶体管T_r的栅极连接读字线Read-WL，第一极连接读位线Read-BL。写晶体管T_w的栅极连接写字线Write-WL，第一极连接写位线Write-BL。
本公开一些实施例提供的一种新的存储单元电路设计，驱动方法，其中，存储单元具有2T以及1C，2T同时参与预充电，2T同时参加写数据，实现在写入阶段对读晶体管Vth的补偿。
本公开实施例中，存储单元的读晶体管T_r和写晶体管T_w在实现数据写入及数据读取时的工作相对独立，即：依赖于导通的写晶体管T_w将数据写入至电容器C，同时保持读晶体管T_r处于关断状态；依赖于读晶体管T_r是否导通从电容器C读取数据，同时保持写晶体管T_w处于关断状态。然而，受限于生产工艺及晶体管的使用时长，容易使得各晶体管(尤其是读晶体管T_r)的阈值电压产生较大变化，从而不可避免地会对数据的读取产生不良影响，导致影响数据读取的准确度。
本申请至少部分实施例中，读晶体管在数据写入阶段同时参与预充电和写入数据，在读阶段用于读数据。
本公开一些实施例提供了一种数据读写电路及其方法、存储器及其驱动方法、电子设 备，可以利用数据信号线(或第一位线)和辅助信号线(或第二位线)在数据读写周期的不同阶段分别向存储单元内的第一晶体管和第二晶体管提供不同的电信号，并结合对存储单元内电容器和第二晶体管二者控制电压的控制，于数据写入阶段在存储节点写入数据的同时将第一晶体管的阈值补偿电压保留于存储节点。从而方便后续于数据读取阶段可以通过数据信号线读取不受第一晶体管阈值电压影响的数据，进而确保存储数据读取的准确度，以进一步提升电子设备的性能。其中，数据信号线(或第一位线)不仅可以在数据写入阶段提供待写入数据的数据电压，还可以在数据读取阶段响应于第一晶体管是否导通读取已写入的数据。
可以理解，存储器通常包含多个存储单元，各存储单元可以二维单层分布或三维多层分布。为了方便描述以及理解，以下一些实施例中的数据读写电路及数据读写方法，以一个存储单元及其对应的驱动为例进行了介绍。并且，在介绍本公开实施例提供的方案时，本公开实施例提及的数据读写电路主要指存储单元阵列内的电路，不包含外围电路(例如行选址驱动电路、列选址驱动电路等)。该数据读写电路包含至少一个存储单元的元器件及与该存储单元相连接的驱动引线。
请参阅图2，在本公开一些实施例提供的数据读写电路，包括：存储单元U、数据信号线BL1和辅助信号线BL2。
存储单元U被配置为存储数据，包括第一晶体管T1、第二晶体管T2以及电容器C；
如图2，电容器C包含相互绝缘的两个电极，其中一个为第一电极A，其与第一晶体管T1的第一栅极G1连接，同时与第二晶体管T2的第一极S/D21连接。电容器C还包括与第一电极A相对设置的第二电极B，第二电极B与第一控制信号线WL连接。电容器C的第一电极A、第一晶体管T1的第一栅极G1和第二晶体管T2的第一极S/D21三者相连接的交点为存储节点SN。
存储单元U的数据读写时序包括：数据写入阶段、数据读取阶段、以及数据写入或读取之前的待机阶段(可以理解为stand by阶段)；其中，本申请实施例中在数据写入阶段之前还包括预充电阶段，在数据写入阶段之后还包括数据保持阶段。
数据信号线BL1与第一晶体管T1相连接，被配置为于待命阶段和预充电阶段向第一晶体管T1提供第一参考电压，于数据写入阶段向第一晶体管T1提供数据电压，于数据读取阶段响应于第一晶体管T1是否导通读取数据。此处，在数据写入阶段向第一晶体管T1提供数据电压后，可以存储该数据电压的数据。
辅助信号线BL2与第一晶体管T1、第二晶体管T2相连接，被配置为于待命阶段和预充电阶段向第一晶体管T1提供第一参考电压，于数据写入阶段浮置，于数据读取阶段向第一晶体管T1和第二晶体管T2同时提供第二参考电压。
本公开实施例中，存储单元U可存储数据对应的最大数据电压与第一晶体管T1的阈值电压之和为基准电压，数据信号线BL1和辅助信号线BL2提供的第一参考电压大于所述基准电压。
此处，存储单元U可存储数据对应的最大数据电压，是指：在存储单元U可存储的各数据中，例如数据“1”或数据“0”中，对应数据电压绝对值最大的电压。例如，存储单元U可存储的数据包括数据“0”和数据“1”，其中，数据“1”对应的数据电压Vdata1和数据“0”对应的数据电压Vdata0可以同为正性电压或者同为负性电压。并且，数据“1”对应的数据电压Vdata1的绝对值大于数据“0”对应的数据电压Vdata0的绝对值。基于此，数据“1”对应的数据电压即可以为存储单元U可存储数据的最大数据电压。反之亦然。
可以理解，在以数据“1”对应的数据电压Vdata1为存储单元U可存储数据的最大数据电压时，该最大数据电压与第一晶体管T1的阈值电压Vth之和为基准电压，即基准电压为Vdata1+Vth。此处，基准电压是为了方便描述，给予的最大数据电压与第一晶体管 T1的阈值电压Vth之和的定义，其仅是用于示意以基准电压为参照标准时第一参考电压的取值范围。例如，第一参考电压大于基准电压(即大于Vdata1+Vth)。并且，第一参考电压和基准电压的差值可以根据需求合理设定。
示例地，第二参考电压小于第一参考电压。以第一晶体管T1和第二晶体管T2均为N型晶体管示例，第一参考电压可以由第一参考电压端提供，第一参考电压端例如为可以提供额定高电平电压的电源电压端；第二参考电压可以由第二参考电压端提供，第二参考电压端例如为可以提供额定低电平电压的公共电压端。
示例地，第二参考电压大于存储单元U可存储数据的最小数据电压，且小于存储单元U可存储数据的最大数据电压。例如，Vdata1＞第二参考电压＞Vdata0。
此处，可以理解，在数据读写电路的实际应用中，考虑到电容器C、数据信号线BL1和辅助信号线BL2之间的耦合效应，第二参考电压V2可以大于最小数据电压和因耦合效应带来的电压变量(矢量)之和，以及小于最大数据电压和因耦合效应带来的电压变量(矢量)之和，以便于在数据读取阶段明显区分数据“1”和数据“0”所带来的电压变化或电流变化。并且，因不同时序和/或不同控制电压给数据读写电路带来的耦合效应不同，前述的电压变量(矢量)可结合实际情况具体确定。
在一些实施例中，请参阅图2，数据读写电路还包括第一控制信号线WL和第二控制信号线WWL。电容器C包括第一电极A和第二电极B。第一晶体管T1包括第一栅极G1、第一极S/D11和第二极S/D12。第二晶体管T2包括第二栅极G2、第一极S/D21和第二极S/D22。其中，第一栅极G1和第二晶体管T2的第一极S/D21均与第一电极A相连接，且第一栅极G1、第二晶体管T2的第一极S/D21和第一电极A三者相连接的交点为存储节点SN。第二电极B与第一控制信号线WL相连接。第二栅极G2与第二控制信号线WWL相连接。第一晶体管T1的第一极S/D11与数据信号线BL1相连接。第一晶体管T1的第二极S/D12和第二晶体管T2的第二极S/D22分别与辅助信号线BL2相连接。
此处，匹配电流的传输方向，在第一晶体管T1的第一极S/D11和第二极S/D12中，一者可以为源极，另一者可以为漏极。在第二晶体管T2的第一极S/D21和第二极S/D22中，一者可以为源极，另一者可以为漏极。
图2中，上述两个晶体管均为n型晶体管，实际应用中不限制晶体管的类型。
本公开实施例中，存储单元U包括电容器C及与电容器C的第一电极A相连接的第一晶体管T1和第二晶体管T2，通过设置数据信号线BL1与存储单元U内的第一晶体管T1相连接，辅助信号线BL2与存储单元U内的第一晶体管T1、第二晶体管T2相连接，可以利用数据信号线BL1和辅助信号线BL2在数据读写周期的不同阶段分别向第一晶体管T1和第二晶体管T2提供不同的电信号，并结合对电容器C第二电极B和第二晶体管T2二者控制电压的控制，于数据写入阶段在存储节点SN写入数据的同时将第一晶体管T1的阈值补偿电压保留于存储节点SN。从而方便后续于数据读取阶段可以通过数据信号线BL1读取不受第一晶体管T1阈值电压Vth影响的数据，进而确保存储数据读取的准确度，以进一步提升存储器性能。此外，在本公开实施例提供的数据读写电路中，无需在存储单元U内设置接地端，还有利于进一步实现存储单元U的高密度集成。
需要补充的是，在一些实施例中，第一控制信号线WL与电容器C的第二电极B相连接，被配置为：于预充电阶段和数据写入阶段向电容器C的第二电极B施加第一写控制电压。此处，第一控制信号线WL还可以视需求被配置为向电容器C的第二电极B施加第二写控制电压。
在一些实施例中，第二控制信号线WWL与第二晶体管T2的第二栅极G2相连接，被配置为于待机阶段和数据读取阶段控制第二晶体管T2关断，于预充电阶段和数据写入阶段控制第二晶体管T2导通。其中，第二控制信号线WWL控制第二晶体管T2导通的控制电压为第三写控制电压。并且，第二晶体管T2的关断可以通过第二控制信号线WWL向第二栅 极G2施加的关断控制电压(例如第四写控制电压)控制实现。
示例地，第一晶体管T1和第二晶体管T2均为N型晶体管。相应地，第一写控制电压和第三写控制电压均为高电平电压。第二写控制电压和第四写控制电压均为低电平电压。进一步地，第一写控制电压可以小于第三控制电压，第一写控制电压可以根据需求合理设置。第二写控制电压和第四写控制电压可以相同，例如均为接地电压。
在一些实施例，写周期还包括位于数据写入阶段之后的数据保持阶段。
在一些示例中，数据信号线BL1还被配置为：于数据保持阶段，向第一晶体管T1提供第一参考电压。第二控制信号线WWL还被配置为：于数据保持阶段，在数据信号线BL1的电压为第一参考电压之后，控制第二晶体管T2关断。辅助信号线BL2还被配置为：于数据保持阶段，在关断第二晶体管T2之后，向第一晶体管T1和第二晶体管T2同时提供第一参考电压。
此外，第一控制信号线WL还被配置为：于数据保持阶段，在关断第二晶体管T2之后，向电容器C的第二电极B施加第二写控制电压。其中，第二写控制电压小于第一写控制电压。并且，第二写控制电压和第一写控制电压的差值，可以视需求合理设定。
本公开实施例中，在写入数据data至存储节点SN之后的数据保持阶段，上拉数据信号线BL1的电压至第一参考电压V1，可以通过第一晶体管T1第一极S/D11和存储节点SN之间的电压差使得第一晶体管T1呈关断状态。此时，连接存储节点SN和辅助信号线BL2的第二晶体管T2呈导通状态，基于电容器C、数据信号线BL1和辅助信号线BL2之间的耦合效应，可以保持存储节点SN电压的稳定。之后，先关断第二晶体管T2，再通过辅助信号线BL2向第一晶体管T1和第二晶体管T2同时提供第一参考电压，可以避免第二晶体管T2产生漏电流，从而将数据data保持于存储节点SN。
可以理解，在数据读取阶段，数据信号线BL1响应于第一晶体管T1是否导通而读取数据data，可以表现为通过数据信号线BL1所传输电流或电压的变化读取数据data。因此，在数据保持阶段，在关断第二晶体管T2之后，还可以利用第一控制信号线WL向电容器C的第二电极B施加第二写控制电压。第二写控制电压小于第一写控制电压，可以拉低存储节点SN的电压。如此，不仅可以进一步确保第一晶体管T1的关断状态，避免第一晶体管T1产生漏电流，还方便于后续通过第一控制信号线WL向电容器C的第二电极B施加读控制电压，进而实现数据data的读取扫描控制。
在另一些示例中，第一控制信号线WL还被配置为：于数据保持阶段，向电容器C的第二电极B提供第二写控制电压，第二写控制电压小于第一写控制电压。数据信号线BL1还被配置为：于数据保持阶段，在第二电极B的电压为第二写控制电压之后向第一晶体管T1提供第一参考电压。第二控制信号线WWL还被配置为：于数据保持阶段，在数据信号线BL1提供第一参考电压之后，控制第二晶体管T2关断。辅助信号线BL2还被配置为：于数据保持阶段，在关断第二晶体管T2之后，向第一晶体管T1和第二晶体管T2同时提供第一参考电压。
本公开实施例中，在写入数据data至存储节点SN之后，先向电容器C的第二电极B提供第二写控制电压。第二写控制电压小于第一写控制电压，可以拉低存储节点SN的电压，以控制第一晶体管T1处于关断状态。之后，上拉数据信号线BL1的电压至第一参考电压V1。由于此时连接存储节点SN和辅助信号线BL2的第二晶体管T2保持导通状态，存储节点SN的电压保持稳定。最后，关断第二晶体管T2，再通过辅助信号线BL2向第一晶体管T1和第二晶体管T2同时提供第一参考电压，可以避免第二晶体管T2产生漏电流，并将数据data稳定于存储节点SN。
需要说明的是，上述第一控制信号线WL对电容器C第二电极B上电压的控制，以及第二控制信号线WWL对第二晶体管T2中第二栅极G2电压的控制，可以详见后文中的数据读写方法中。此处仅对第一控制信号线WL和第二控制信号线WWL的连接关系及基本功能 进行了介绍。
在一些实施例中，第一控制信号线WL和第二控制信号线WWL提供的各写控制电压为脉冲电压。
在一些实施例中，第一控制信号线WL在写周期内提供的第一写控制电压和其在读周期内提供的读控制电压可以相同，也可以不同。
示例地，第一写控制电压和读控制电压相同。以第一晶体管T1和第二晶体管T2均为N型晶体管示例，第一写控制电压和读控制电压可以均为高电平电压。以第一晶体管T1和第二晶体管T2均为P型晶体管示例，第一写控制电压和读控制电压可以均为低电平电压。
示例地，第一写控制电压小于读控制电压。例如，第一写控制电压的电压绝对值小于读控制电压的电压绝对值。
以上为本申请实施例提供的存储单元，存储单元的驱动方法，以下将介绍该存储单元的存储阵列。
在一些实施例中，请参阅图3和图4，存储单元U的数量为多个。多个存储单元U沿第一方向排布呈行，沿第二方向排布呈列；图中示意性地给出m×n个存储单元。第一方向和第二方向相交。此处，第一方向为行方向，也为第一控制信号线WL和/或第二控制信号线WWL的延伸方向。第二方向为列方向，也为数据信号线BL1和/或辅助信号线BL2的延伸方向。第一方向和第二方向例如正交。
示例地，如图3和图4中所示，一行存储单元U共用一条第一控制信号线WL，共用一条第二控制信号线WWL。一列存储单元U共用一条数据信号线BL1，共用一条辅助信号线BL2。图中各存储单元中的晶体管以N型晶体管为例。
示例地，数据信号线BL1与存储节点SN之间的耦合电容小于第一目标阈值。辅助信号线BL2与存储节点SN之间的耦合电容小于第二目标阈值。此处，第一目标阈值和第二目标阈值相同或不同，均可。
进一步，第一目标阈值和第二目标阈值均可以采用一较小值。
示例地，数据信号线BL1与存储节点SN之间的耦合电容为第一耦合电容。数据信号线BL1与电容器C、辅助信号线BL2之间的总耦合电容为第二耦合电容。第一耦合电容和第二耦合电容的比值小于目标值。并且，目标值越小越好。
在一些实施例中，请继续参阅图3和图4，数据读写电路还包括第一参考电压端v1和第二参考电压端v2。
第一参考电压端v1通过第一选通电路10与数据信号线BL1对应连接，通过第二选通电路20与辅助信号线BL2对应连接。第一参考电压端v1被配置为提供第一参考电压。第一选通电路10被配置为：于待机阶段和预充电阶段，选择连通第一参考电压端v1和数据信号线BL1；第二选通电路20被配置为：于待机阶段和预充电阶段，选择连通第一参考电压端v1和辅助信号线BL2。
第二参考电压端v2通过第三选通电路30与辅助信号线BL2对应连接。第二参考电压端v2被配置为提供第二参考电压。第三选通电路30被配置为：于数据读取阶段选择连通第二参考电压端v2和辅助信号线BL2。
示例地，连接数据信号线BL1的第一参考电压端v1和连接辅助信号线BL2的第一参考电压端v1可以为同一电压端，也可以为提供相同电压的不同电压端。
进一步地，连接数据信号线BL1的第一参考电压端v1和连接辅助信号线BL2的第一参考电压端v1为提供相同电压的不同电压端，且该不同电压端可以分区域设置，例如分别设置于存储单元U阵列相对的两侧。
在一些实施例中，如图4中所示，第一选通电路10包括与各数据信号线BL1一一对应地相连的第一选择晶体管TC1；其中，各第一选择晶体管TC1的栅极均与第一选通信号 线CTL1连接；各第一选择晶体管TC1的第一极分别与对应的数据信号线BL1连接；各第一选择晶体管TC1的第二极均与第一参考电压端v1连接。
第二选通电路20包括与各辅助信号线BL2一一对应地相连的第二选择晶体管TC2；其中，各第二选择晶体管TC2的栅极均与第二选通信号线CTL2连接；各第二选择晶体管TC2的第一极分别与对应的辅助信号线BL2连接；各第二选择晶体管TC2的第二极均与第一参考电压端v1连接。
第三选通电路30包括与各辅助信号线BL2一一对应地相连的第三选择晶体管TC3；其中，各第三选择晶体管TC3的栅极均与读取选通信号线CTL-R连接；各第三选择晶体管TC3的第一极分别与对应的辅助信号线BL2连接；各第三选择晶体管TC3的第二极均与第二参考电压端v2连接。
在上述一些实施例提及的各选择晶体管的第一极和第二极中，其中一者可以为源极，另一者可以为漏极。并且，各选择晶体管可以响应于对应选通信号线提及的选通信号择一导通，以实现对各存储单元U的读写控制。
在一些实施例中，请继续参阅图3和图4，数据读写电路还可以包括一个或多个感测放大电路40。例如，数据读写电路包括与数据信号线BL1一一对应地多个感测放大电路40。并且，各数据信号线BL1远离第一参考电压端v1的一端分别与对应的感测放大电路40连接，以读取数据。
此处，匹配数据读写电路读取数据的方式，感测放大电路40可以采用电流感测放大电路或电压感测放大电路。
示例地，感测放大电路40为电流感测放大电路。如此，在数据读取阶段，数据信号线BL1持续提供第一参考电压，响应于第一晶体管T1是否导通，感测放大电路40可以通过感测数据信号线BL1所传输电流的变化读取数据。
示例地，感测放大电路40为电压感测放大电路。在数据读取阶段，响应于第一晶体管T1是否导通，数据信号线BL1预提供的第一参考电压可以变化或不变化，以使得感测放大电路40可以通过感测数据信号线BL1所传输电压的变化读取数据。
此外，本公开实施例对感测放大电路40的电路结构不作限定。例如，感测放大电路40为电压感测放大电路，例如为比较放大电路，感测放大电路40可以与第三参考电压端v3连接，以通过比较第三参考电压端v3提供的第三参考电压和数据信号线BL所传输电压的差值，读取数据。
需要补充的是，上述一些实施例中，请结合图3和图4理解，第一控制信号线WL提供的第一写控制电压及第二控制信号线WWL提供的第三写控制电压，均是针对该存储单元U在执行数据写入时提供的控制电压。基于此，可以理解，对于存储单元U阵列，在向执行数据写入的存储单元U所在行提供前述的第一写控制电压和第三写控制电压之外，其他行存储单元U对应的第一控制信号线WL提供第二写控制电压，其他行存储单元U对应的第二控制信号线WWL提供第四写控制电压即可，以实现存储单元U阵列的行扫描写入。
本公开一些实施例还提供了一种数据读写方法，以实现上述数据读写电路的数据读写过程。该数据读写方法可以应用于任一存储单元U，存储单元U被配置为存储数据，其结构可以参见前述一些实施例中的相关描述。上述数据读写电路所具有的技术优势，该数据读写方法也均具备。
请结合图2、图5、图6和图7理解，在本公开一些实施例提供的数据读写方法中，存储单元U的数据读写周期t包括写周期tW、读周期tR及待机阶段(例如第一待机阶段tD1和第二待机阶段tD2)。
在一些实施例中，如图5中所示，写周期tW包括预充电阶段tW1和数据写入阶段tW2。所述数据读写方法包括步骤S100和S200。
S100，在预充电阶段tW1，数据信号线BL1向第一晶体管T1提供第一参考电压V1， 辅助信号线BL2向第一晶体管T1和第二晶体管T2同时提供第一参考电压V1；电容器C的第二电极B施加第一写控制电压VCW1，第二晶体管T2导通，对存储节点SN进行预充电；其中，数据对应的最大数据电压与第一晶体管T1的阈值电压Vth之和为基准电压，第一参考电压V1大于基准电压。
此处，在完成存储节点SN的预充电之后，存储节点SN的电压为第一参考电压V1。
示例地，存储单元U可存储的数据包括数据“0”和数据“1”，其中，数据“1”对应的数据电压Vdata1大于数据“0”对应的数据电压Vdata0。基于此，数据“1”对应的数据电压Vdata1即可以为存储单元U可存储数据的最大数据电压。反之亦然。
基于此，在以数据“1”对应的数据电压Vdata1为存储单元U可存储数据的最大数据电压时，基准电压为Vdata1+Vth，第一参考电压大于Vdata1+Vth。并且，第一参考电压和基准电压的差值可以根据需求合理设定。
此处，基准电压是为了方便描述，给予的最大数据电压与第一晶体管T1的阈值电压Vth之和的定义，其仅是用于示意以基准电压为参照标准时第一参考电压的取值范围。
示例地，第一晶体管T1和第二晶体管T2采用N型晶体管或P型晶体管，也均是允许的。为方便描述，以下一些实施例中均是以第一晶体管T1和第二晶体管T2为N型晶体管作为示例进行了表述。
在一些实施例中，请继续参阅图2、图5、图6和图7，在预充电阶段tW1，第一控制信号线WL向电容器C施加第一写控制电压VCW1。第二控制信号线WWL向第二晶体管T2的第二栅极G2提供第三写控制电压VCW3。此时，数据信号线BL1向第一晶体管T1的第一极S/D11提供第一参考电压V1，辅助信号线BL2向第一晶体管T1的第二极S/D12提供第一参考电压V1，第一晶体管T1处于非导通状态。示例地，第一写控制电压VCW1和第三写控制电压VCW3均为高电平电压。
示例地，第一写控制电压VCW1小于第三写控制电压VCW3，第一写控制电压VCW1可以根据需求合理设置。
S200，在数据写入阶段tW2，响应于写命令，辅助信号线BL2浮置，数据信号线BL1向第一晶体管T1提供数据电压Vdata，第一晶体管T1导通。存储节点SN放电至稳定状态，写入数据电压Vdata对应的数据data。
此处，存储节点SN放电至稳定状态，是指：存储节点SN的电压变化趋于0。在存储节点SN放电至稳定状态之后，存储节点SN的电压为Vdata+Vth(包括近似等于)。
并且，如图5、图6和图7中所示，在数据写入阶段tW2，第一控制信号线WL向电容器C的第二电极B持续施加第一写控制电压VCW1。第二控制信号线WWL向第二晶体管T2的第二栅极G2持续提供第三写控制电压VCW3。此时，数据信号线BL1向第一晶体管T1的第一极S/D11提供数据电压Vdata，辅助信号线BL2浮置。
此外，数据信号线BL1提供的数据电压Vdata与待写入的数据相关。例如，待写入数据为数据“1”，数据信号线BL1在数据写入阶段tW2提供的数据电压为Vdata1。或者，还例如，待写入数据为数据“0”，数据信号线BL1在数据写入阶段tW2提供的数据电压为Vdata0。
在一些实施例中，如图3和图4中所示，辅助信号线BL2通过第二选通电路20与第一参考电压端v1相连，并通过第三选通电路30与第二参考电压端v2相连。辅助信号线BL2浮置，是指：与该辅助信号线BL2相连的第二选通电路20和第三选通电路30均呈关断状态，辅助信号线BL2连接第二选通电路20和第三选通电路30的端部无信号输入。
在一些实施例中，写周期tW还包括：位于数据写入阶段tW2之后的数据保持阶段tW3。
在一些示例中，请参阅图6，所述数据读写方法还包括步骤S300。
S300，在数据保持阶段tW3，上拉数据信号线BL1的电压至第一参考电压V1，并于数据信号线BL1的电压为第一参考电压之后先关断第二晶体管T2，再上拉辅助信号线BL2 的电压至第一参考电压V1。
此外，请继续参阅图6，在关断第二晶体管T2之后，所述数据读写方法还包括：向电容器C的第二电极B施加第二写控制电压VCW2，第二写控制电压VCW2小于第一写控制电压VCW1。并且，第二写控制电压和第一写控制电压的差值，可以视需求合理设定。
本公开实施例中，在写入数据data至存储节点SN之后的数据保持阶段tW3，可以上拉数据信号线BL1的电压至第一参考电压V1，并通过第一晶体管T1第一极S/D11和存储节点SN之间的电压差使得第一晶体管T1呈关断状态。此时，连接存储节点SN和辅助信号线BL2的第二晶体管T2呈导通状态，基于电容器C、数据信号线BL1和辅助信号线BL2之间的耦合效应，可以保持存储节点SN电压的稳定(例如保持于Vdata+Vth)。之后，先关断第二晶体管T2，再通过辅助信号线BL2向第一晶体管T1和第二晶体管T2同时提供第一参考电压V1，可以将数据data保留于存储节点SN(存储节点SN的电压包含Vdata+Vth)。
可以理解，在数据读取阶段tR，数据信号线BL1响应于第一晶体管T1是否导通而读取数据data，可以表现为通过数据信号线BL1所传输电流或电压的变化读取数据data。因此，在数据保持阶段tW3，在关断第二晶体管T2之后，还可以利用第一控制信号线WL向电容器C的第二电极B施加第二写控制电压VCW2。第二写控制电压VCW2小于第一写控制电压VCW1，可以拉低存储节点SN的电压。如此，不仅可以进一步确保第一晶体管T1的关断状态，避免第一晶体管T1产生漏电流，还方便于后续通过第一控制信号线WL向电容器C的第二电极B施加读控制电压VCR，进而实现数据data的读取扫描控制。
此处，请参阅图6，在数据保持阶段tW3，在关断第二晶体管T2之后，先上拉辅助信号线BL2的电压至第一参考电压V1，或者先通过第一控制信号线WL向电容器C的第二电极B施加第二写控制电压VCW2，或者二者同时进行，也均是允许的。
并且，在关断第二晶体管T2之后，第一控制信号线WL向电容器C的第二电极B施加第二写控制电压VCW2时，存储节点SN的电压会随之变化。例如，第二写控制电压VCW2为低电平电压，若存储节点SN写入的数据为数据“1”，则存储节点SN的电压可以对应变化为：Vdata1+Vth-△V；若存储节点SN写入的数据为数据“0”，则存储节点SN的电压可以对应变化为：Vdata0+Vth-△V。
相应地，在后续的数据读取阶段tR，第一控制信号线WL向电容器C的第二电极B施加读控制电压VCR时，存储节点SN的电压会随之变化。例如，读控制电压VCR为高电平电压，若存储节点SN写入的数据为数据“1”，则存储节点SN的电压可以对应变化为：Vdata1+Vth-△V+△V'；若存储节点SN写入的数据为数据“0”，则存储节点SN的电压可以对应变化为：Vdata0+Vth-△V+△V'。
本公开实施例中，存储节点SN的电压在第一控制信号线WL向电容器C的第二电极B施加第二写控制电压VCW2或读控制电压VCR之后虽然发生了变化，但存储节点SN的电压始终包括写入数据对应的数据电压Vdata和第一晶体管T1的阈值电压Vth，并且对应于不同的数据电压(例如Vdata1和Vdata0)，存储节点SN的电压变化是相同的，不影响数据读取阶段tR准确读取数据。
在另一些示例中，请参阅图7，所述数据读写方法还包括步骤S300'。
S300'，在数据保持阶段tW3，先向电容器C的第二电极B施加第二写控制电压VCW2，上拉数据信号线BL1的电压至第一参考电压V1；再关断第二晶体管T2，上拉辅助信号线BL2的电压至第一参考电压V1。其中，第二写控制电压VCW2小于第一写控制电压VCW1。
此处，可以理解，第二晶体管T2的关断可以通过第二控制信号线WWL向第二栅极G2施加的关断控制电压(即第四写控制电压VCW4)控制实现。
示例地，第二写控制电压VCW2和第四写控制电压VCW4相同。
示例地，第一晶体管T1和第二晶体管T2均为N型晶体管。相应地，第二写控制电压 VCW2和第四写控制电压VCW4均为低电平电压。
本公开实施例中，在写入数据data至存储节点SN之后，先向电容器C的第二电极B施加第二写控制电压VCW2。第二写控制电压VCW2小于第一写控制电压VCW1，可以拉低存储节点SN的电压，以控制第一晶体管T1处于关断状态。之后，上拉数据信号线BL1的电压至第一参考电压V1。由于此时连接存储节点SN和辅助信号线BL2的第二晶体管T2保持导通状态，存储节点SN的电压保持稳定(例如保持于Vdata+Vth)。最后，关断第二晶体管T2，再通过辅助信号线BL2向第一晶体管T1和第二晶体管T2同时提供第一参考电压V1，可以避免第二晶体管T2产生漏电流，并将数据data稳定于存储节点SN(例如存储节点SN的电压为Vdata+Vth)。
在一些实施例中，如图5、图6和图7中所示，读周期tR包括：数据读取阶段tR。所述数据读写方法还包括步骤S400。
S400，在数据读取阶段tR，响应于读命令，向电容器C的第二电极B施加读控制电压VCR，并通过辅助信号线BL2向第一晶体管T1和第二晶体管T2同时提供第二参考电压V2；其中，数据信号线BL1还被配置为：响应于第一晶体管T1是否导通读取数据。
示例地，第二参考电压V2小于第一参考电压V1。
示例地，第二参考电压V2大于存储单元U可存储数据的最小数据电压，且小于存储单元U可存储数据的最大数据电压。例如，Vdata1＞V2＞Vdata0。
此处，可以理解，在数据读写电路的实际应用中，考虑到电容器C、数据信号线BL1和辅助信号线BL2之间的耦合效应，第二参考电压V2可以大于最小数据电压和因耦合效应带来的电压变量(矢量)之和，以及小于最大数据电压和因耦合效应带来的电压变量(矢量)之和。
在一些实施例中，第一控制信号线WL在写周期tW内提供的第一写控制电压VCW1和其在读周期tR内提供的读控制电压VCR可以相同，也可以不同。
示例地，第一写控制电压VCW1和读控制电压VCR相同。
示例地，第一写控制电压VCW1小于读控制电压VCR。
此处，响应于读命令向电容器C第二电极B施加的读控制电压VCR，是指：通过第一控制信号线WL所施加的合适电压，能够确保第一晶体管T1在存储节点SN存储不同数据时对应处于不同的状态。
图8中的(a)图和(b)图分别示出了在向电容器C的第二电极B施加两种不同的读控制电压VCR时，第一晶体管T1的电流-电压特性曲线图；其中，(a)图对应的读控制电压VCR小于(b)图对应的读控制电压VCR。通过比对图8中的(a)图和(b)图可知，合理选择读控制电压VCR的大小，可以在存储节点SN存储数据“0”或数据“1”时，确保第一晶体管T1能够存在明显的导通或关断状态，以利于读取数据。
在一些实施例中，请结合图5、图6、图7和图8理解，存储节点SN写入的数据包括“1”或“0”。在数据读取阶段tR，向电容器C的第二电极B施加读控制电压VCR之后：
若存储节点SN存储的数据为“1”时，则第一晶体管T1的栅源电压VGS(即第一栅极G1与其第二极S/D12之间的电压差)较大，并大于第一晶体管T1的阈值电压Vth，第一晶体管T1处于导通状态。
若存储节点SN存储的数据为“0”时，则第一晶体管T1的栅源电压VGS(即第一栅极G1与其第二极S/D12之间的电压差)较小，并小于第一晶体管T1的阈值电压Vth，第一晶体管T1处于关断状态。
为了更清楚的说明数据读取阶段tR的数据读取过程，以下以图5和图7所示的数据读取方法进行了示例，图6所示的数据读取方法可以适应性理解。
在数据读取阶段tR，若第一晶体管T1中第一栅极G1的电压为存储节点SN写入数据“1”后的电压，即＝Vdata1+Vth。第一晶体管T1中第二极S/D12的电压为辅助信号线BL2 提供的第二参考电压V2。第一晶体管T1的栅源电压VGS＝Vdata1+Vth-V2。由于V2小于Vdata1，因此第一晶体管T1栅源电压VGS大于Vth。
在数据读取阶段tR，若第一晶体管T1中第一栅极G1的电压为存储节点SN写入数据“0”后的电压，即＝Vdata0+Vth。第一晶体管T1中第二极S/D12的电压为辅助信号线BL2提供的第二参考电压V2。第一晶体管T1的栅源电压VGS＝Vdata0+Vth-V2。由于V2大于Vdata0，因此第一晶体管T1的栅源电压VGS小于Vth。
此外，请结合图3、图4、图5、图6及图7理解，匹配数据读写电路读取数据的方式，数据信号线BL1响应于第一晶体管T1是否导通读取数据的方式可以表现为：电流感测读取或电压感测读取。
示例地，在数据读取阶段tR，数据信号线BL1持续提供第一参考电压V1，响应于第一晶体管T1是否导通，数据信号线BL1连接的感测放大电路40可以通过感测数据信号线BL1所传输电流的变化读取数据。
示例地，在数据读取阶段tR，响应于第一晶体管T1是否导通，数据信号线BL1预提供的第一参考电压V1可以变化或不变化，以使得感测放大电路40可以通过感测数据信号线BL1所传输电压的变化读取数据。
值得一提的是，在一些实施例中，请参阅图5、图6和图7，数据读写周期t还包括：位于预充电阶段tW1之前和/或位于数据读取阶段tR之前的待机阶段(即Stand by阶段)。
示例地，如图6和图7中所示，数据读写周期t还包括：位于数据写入阶段tW2之后的数据保持阶段tW3。数据读取阶段tR位于数据保持阶段tW3之后。待机阶段，包括：位于预充电阶段tW1之前的第一待机阶段tD1，以及位于数据保持阶段tW3之后且位于数据读取阶段tR之前的第二待机阶段tD2。
相应地，本公开实施例提供的数据读写方法还包括如下步骤。
在待机阶段(包括第一待机阶段tD1和第二待机阶段tD2)，第一晶体管T1和第二晶体管T2处于关断状态，数据信号线BL1向第一晶体管T1提供第一参考电压V1，辅助信号线BL2向第一晶体管T1和第二晶体管T2同时提供第一参考电压V1。
本公开实施例在待机阶段，可以利用数据信号线BL1向第一晶体管T1的第一极提供第一参考电压V1，利用辅助信号线BL2向第一晶体管T2的第二极提供第一参考电压V1，从而确保第一晶体管T1的第一极和第二极之间无较大压差，以有效降低漏电流产生的风险。尤其是在第一参考电压V1为高电平电压的情况下。
此外，可以理解，上述一些实施例中提及的第一待机阶段tD1和第二待机阶段tD2，即为前述数据读写电路中提及的待机阶段。结合前述记载，第一待机阶段tD1可以独立于写周期tw之外，第二待机阶段tD2可以独立于读周期tR之外。并且，基于第一待机阶段tD1和第二待机阶段tD2时，数据信号线BL1、辅助信号线BL2、第一控制信号线WL和第二控制信号线WWL所提供的电压信号相同，第一待机阶段tD1和第二待机阶段tD2也可以视为是同一待机阶段，以响应于接收命令的不同而进入不同的读写周期。例如，在接收到写命令时对应进入写周期，或在接收到读命令时对应进入读周期。
可以理解，在第一待机阶段tD1和第二待机阶段tD2，第一控制信号线WL向电容器C的第二电极B施加第二写控制电压VCW2；第二控制信号线WWL向第二晶体管T2的第二栅极G2施加第四写控制电压VCW4。
示例地，第二写控制电压VCW2和第四写控制电压VCW4相同。
示例地，第一晶体管T1和第二晶体管T2均为N型晶体管。第二写控制电压VCW2和第四写控制电压VCW4均为低电平电压。
本公开实施例中，存储单元U被配置为存储数据，包括电容器C及与电容器C的第一电极A相连接的第一晶体管T1和第二晶体管T2。本公开实施例通过设置数据信号线BL2与存储单元U内的第一晶体管T1连接，设置辅助信号线BL2与存储单元U内的第一晶体 管T1、第二晶体管T2相连接，可以于预充电阶段tW1，在数据信号线BL1向第一晶体管T1提供第一参考电压V1，辅助信号线BL2向第一晶体管T1和第二晶体管T2同时提供第一参考电压V1，以及第一控制信号线WL向电容器C的第二电极B提供第一写控制电压VCW1，并导通第二晶体管T2之后，对存储节点SN进行预充电。基于第一参考电压V1大于基准电压(即存储单元U可存储数据对应的最大数据电压与第一晶体管T1的阈值电压之和，例如为Vdata1+Vth)，也即V1＞(Vdata1+Vth)，这样在对存储节点SN进行预充电之后，该存储节点SN的电压(＝或≈V1)可以大于基准电压，例如大于(Vdata1+Vth)。如此，在数据写入阶段tW2，响应于写命令，使得辅助信号线BL2浮置且数据信号线BL1向第一晶体管T1提供数据电压Vdata之后，导通第一晶体管T1，存储节点SN可以自然放电至稳定状态，以写入前述数据电压Vdata对应的数据data。
本公开实施例中，由于存储节点SN预充电之后的电压大于基准电压，例如大于(Vdata1+Vth)，即：该存储节点SN的电压不仅大于数据信号线BL1提供的数据电压Vdata，且该存储节点SN的电压和前述数据电压Vdata的差值还大于第一晶体管T1的阈值电压Vth，因此在存储节点SN放电至稳定状态之后，存储节点SN的电压对应为前述数据电压Vdata和第一晶体管T1的阈值电压Vth之和(即＝或≈Vdata+Vth)，从而可以在写入数据data的同时将第一晶体管T1的阈值补偿电压(＝或≈Vth)保留于存储节点SN。
在此基础上，在写入数据data之后，本公开一些实施例可以关断第一晶体管T1和第二晶体管T2(详见数据保持阶段tW3的相关描述)。并且，可以在第二待机阶段tD2，利用数据信号线BL1和辅助信号线BL2分别向第一晶体管T1提供第一参考电压V1，以及利用辅助信号线BL2向第二晶体管T2提供第一参考电压V1。此时，第一晶体管T1和第二晶体管T2均处于关断状态，可以保持存储节点SN的电压稳定。
之后，在数据读取阶段tR，响应于读命令，可以向电容器C的第二电极B提供读控制电压VCR，并通过辅助信号线BL2向第一晶体管T1和第二晶体管T2同时提供第二参考电压V2。在数据信号线BL1提供第一参考电压V1，辅助信号线BL2提供第二参考电压V2，且向电容器C的第二电极B提供读控制电压VCR之后，存储节点SN的电压大小可以影响第一晶体管T1第一极S/D11和第二极S/D12之间的导通与否，以使得数据信号线BL1响应于第一晶体管T1是否导通来读取数据。由于存储节点SN的电压包含第一晶体管T1的阈值补偿电压(＝或≈Vth)，因此数据信号线BL1响应于第一晶体管T1是否导通而读取的数据可以不受第一晶体管T1阈值电压Vth的影响，以确保存储数据data读取的准确度，从而进一步提升存储器性能。
本公开一些实施例又一方面还提供了一种存储器。请结合图2、图3和图4理解，包括至少一个存储单元U，以及与存储单元U对应连接的第一位线BL1、第二位线BL2、第一字线WL和第二字线WWL。其中，存储单元U包括：电容器C、第一晶体管T1和第二晶体管T2。电容器C包括绝缘设置的第一电极A和第二电极B。第一晶体管T1和第二晶体管T2均包括栅极和第一极、第二极。第一电极A、第一晶体管T1的栅极G1和第二晶体管T2的第一极S/D21相连接，且三者的连接交点为存储节点SN。第一字线WL与第二电极B相连接，第二字线WWL与第二晶体管T2的栅极G2相连接。第一位线BL1与第一晶体管T1的第一极S/D11相连接，第二位线BL2与第一晶体管T1的第二极S/D12、第二晶体管T2的第二极S/D22同时连接。第一位线BL1被配置为：于数据写入阶段提供待写入数据的数据电压，于数据读取阶段响应于第一晶体管T1是否导通读取存储节点已写入的数据。
此处，匹配电流的传输方向，在第一晶体管T1的第一极S/D11和第二极S/D12中，一者可以为源极，另一者可以为漏极。在第二晶体管T2的第一极S/D21和第二极S/D22中，一者可以为源极，另一者可以为漏极。并且，图2中以第一晶体管T1和第二晶体管T2均为n型晶体管为例进行了介绍，实际应用中并不限制该晶体管的类型。
此外，结合前述一些实施例中数据读写电路的相关描述，该存储器中第一位线BL1的功能与前述的数据信号线功能等同，第二位线BL2的功能与前述的辅助信号线功能等同，第一字线WL的功能与前述的第一控制信号线功能等同，第二字线WWL的功能与前述的第二控制信号线功能等同。该存储器中第一位线BL1、第二位线BL2、第一字线WL及第二字线WWL的结构设置及使用均可以对应参考前述实施例中数据读写电路进行，此处不再详述。
本公开一些实施例还提供了一种存储器的驱动方法，用于驱动如上所述的存储器。请结合图2及图5、图6、图7，所述方法包括步骤如下。
在预充电阶段tW1，第一位线BL1向第一晶体管T1的第一极S/D11提供第一参考电压V1。第二位线BL2向第一晶体管T1的第二极S/D12和第二晶体管T1的第二极S/D22同时提供第一参考电压V1。第一字线WL向第二电极B施加第一写控制电压VCW1。第二字线WWL向第二晶体管T2的栅极G2施加第三写控制电压VCW3，控制第二晶体管T2导通，以对存储节点SN进行预充电。其中，第一参考电压V1大于存储单元U待写入的最大数据电压和第一晶体管T1的阈值电压VTH之和。
在数据写入阶段tW2，第二位线BL2浮置，第一位线BL1向第一晶体管T1的第一极S/D11提供数据电压Vdata。第一晶体管T1导通，存储节点SN放电至稳定状态，写入所述数据电压对应的数据data。
在数据读取阶段tR，第二字线WWL向第二晶体管T2的栅极G2施加第四写控制电压VCW3，第二晶体管T2处于关断状态。第一字线WL向第二电极B施加读控制电压VCR。第二位线BL2向第一晶体管T1的第二极S/D12和第二晶体管T2的第二极S/D22同时提供第二参考电压V2。第一位线BL1响应于第一晶体管T1是否导通读取存储节点SN已写入的数据。
在一些实施例中，请参阅图6，所述方法还包括：在数据保持阶段tW3，上拉第一位线BL1的电压至第一参考电压V1，并于第一位线BL1的电压为第一参考电压之后先关断第二晶体管T2，再上拉第二位线BL2的电压至第一参考电压V1。
此外，请继续参阅图6，在关断第二晶体管T2之后，所述方法还包括：第一字线WL向电容器C的第二电极B施加第二写控制电压VCW2，第二写控制电压VCW2小于第一写控制电压VCW1。并且，第二写控制电压VCW2和第一写控制电压VCW1的差值，可以视需求合理设定。
在一些示例中，请继续参阅图6，在数据保持阶段tW3，在关断第二晶体管T2之后，先上拉第二位线BL2的电压至第一参考电压V1，或者先通过第一字线WL向电容器C的第二电极B施加第二写控制电压VCW2，或者二者同时进行，也均是允许的。
在另一些实施例中，请参阅图7，所述方法还包括：在数据保持阶段tW3，第一字线WL先向电容器C的第二电极B施加第二写控制电压VCW2，上拉第一位线BL1的电压至第一参考电压V1；再关断第二晶体管T2，上拉第二位线BL2的电压至第一参考电压V1。其中，第二写控制电压VCW2小于第一写控制电压VCW1。
此处，可以理解，第二晶体管T2的关断可以通过第二字线WWL向其栅极G2施加的关断控制电压(即第四写控制电压VCW4)控制实现。
值得一提的是，在一些实施例中，请参阅图5、图6和图7，所述方法还包括：在预充电阶段tW1之前的第一待机阶段tD1，以及位于数据保持阶段tW3之后且位于数据读取阶段tR之前的第二待机阶段tD2，第一字线WL向电容器C的第二电极B施加第二写控制电压VCW2，第二字线WWL向第二晶体管T2的栅极G2施加第四写控制电压VCW4，第一位线BL1向第一晶体管T1的第一极S/D11提供第一参考电压V1，第二位线BL2向第一晶体管T1的第二极S/D12和第二晶体管T2的第二极S/D22同时提供第一参考电压V1。
上述一些实施例提及的驱动方法的技术原理，可对应参照前述数据读写方法中的技术 原理适应性理解，此处不再详述。
本公开一些实施例还提供了一种电子设备，例如数据存储设备、影印机、网络设备、家用电器、仪器仪表、手机、电脑等具备数据存储功能的设备。该电子设备可以包括壳体以及设置在壳体内的电路板、集成在电路板上的存储器或数据读写电路。存储器或数据读写电路的结构可以参阅上述一些实施例中的相关描述。电子设备中还可以包括其他必要的元件或部件，本公开实施例对此不作限定。
在一些实施例中，存储器可以耦接处理器或执行器等外部控制器件。处理器与存储器耦接，处理器能够控制存储器的读写操作。
在一些实施例中，存储器为三维动态随机存取存储器。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种数据读写方法，应用于存储单元；所述存储单元被配置为存储数据，包括电容器及与所述电容器的第一电极相连接的第一晶体管和第二晶体管；所述第一电极、所述第一晶体管和所述第二晶体管三者相连接的交点为所述存储单元的存储节点；所述电容器还包括与所述第一电极相对设置的第二电极；所述存储单元的数据读写周期包括：预充电阶段和数据写入阶段；所述数据读写方法包括：
    在所述预充电阶段，数据信号线向所述第一晶体管提供第一参考电压，辅助信号线向所述第一晶体管和所述第二晶体管同时提供所述第一参考电压；所述电容器的第二电极施加第一写控制电压，所述第二晶体管导通，对所述存储节点进行预充电；其中，所述数据对应的最大数据电压与所述第一晶体管的阈值电压之和为基准电压，所述第一参考电压大于所述基准电压；
    在所述数据写入阶段，响应于写命令，所述辅助信号线浮置，所述数据信号线向所述第一晶体管提供数据电压，所述第一晶体管导通；所述存储节点放电至稳定状态，写入所述数据电压对应的数据。
  2. 如权利要求1所述的数据读写方法，其中，所述数据读写周期还包括：位于所述数据写入阶段之后的数据保持阶段；所述数据读写方法还包括：
    在所述数据保持阶段，上拉所述数据信号线的电压至所述第一参考电压，并于所述数据信号线的电压为所述第一参考电压之后先关断所述第二晶体管，再上拉所述辅助信号线的电压至所述第一参考电压；
    其中，在关断所述第二晶体管之后，所述数据读写方法还包括：向所述电容器的第二电极施加第二写控制电压；所述第二写控制电压小于所述第一写控制电压。
  3. 如权利要求1或2所述的数据读写方法，其中，所述数据读写周期还包括：位于所述数据写入阶段之后的数据保持阶段；所述数据读写方法还包括：
    在所述数据保持阶段，先向所述电容器的第二电极施加第二写控制电压，上拉所述数据信号线的电压至所述第一参考电压；再关断所述第二晶体管，上拉所述辅助信号线的电压至所述第一参考电压；其中，所述第二写控制电压小于所述第一写控制电压。
  4. 如权利要求1～3中任一项所述的数据读写方法，其中，所述数据读写周期还包括：数据读取阶段；所述数据读写方法还包括：
    在所述数据读取阶段，响应于读命令，向所述电容器的第二电极施加读控制电压，并通过所述辅助信号线向所述第一晶体管和第二晶体管同时提供第二参考电压；其中，所述数据信号线响应于所述第一晶体管是否导通读取数据。
  5. 如权利要求1～4中任一项所述的数据读写方法，其中，所述存储节点写入的所述数据包括“1”或“0”；在所述数据读取阶段，所述存储节点写入的所述数据为“1”时，所述第一晶体管处于导通状态；所述存储节点写入的所述数据为“0”时，所述第一晶体管处于关断状态。
  6. 如权利要求1～5中任一项所述的数据读写方法，其中，所述数据读写周期还包括：位于所述预充电阶段之前和/或位于所述数据读取阶段之前的待机阶段；所述数据读写方法还包括：
    在所述待机阶段，所述第一晶体管和所述第二晶体管处于关断状态，所述数据信号线向所述第一晶体管提供所述第一参考电压，所述辅助信号线向所述第一晶体管和所述第二晶体管同时提供所述第一参考电压。
  7. 如权利要求6所述的数据读写方法，其中，所述数据读写周期还包括：位于所述数据写入阶段之后的数据保持阶段；所述数据读取阶段位于所述数据保持阶段之后；
    所述待机阶段，包括：位于所述预充电阶段之前的第一待机阶段，以及位于所述数据 保持阶段之后且位于所述数据读取阶段之前的第二待机阶段。
  8. 一种数据读写电路，包括：
    存储单元，被配置为存储数据，包括电容器及与所述电容器的第一电极相连接的第一晶体管和第二晶体管；所述电容器还包括与所述第一电极相对设置的第二电极；所述第一电极、所述第一晶体管和所述第二晶体管三者相连接的交点为所述存储单元的存储节点；
    数据信号线，与所述第一晶体管相连接，被配置为：于待机阶段和预充电阶段向所述第一晶体管提供第一参考电压，于数据写入阶段向所述第一晶体管提供数据电压，于数据读取阶段响应于所述第一晶体管是否导通读取数据；
    辅助信号线，与所述第一晶体管、所述第二晶体管相连接，被配置为：于所述待机阶段和所述预充电阶段向所述第一晶体管提供所述第一参考电压，于所述数据写入阶段浮置，于所述数据读取阶段向所述第一晶体管和所述第二晶体管同时提供第二参考电压；
    其中，所述数据对应的最大数据电压与所述第一晶体管的阈值电压之和为基准电压；所述第一参考电压大于所述基准电压。
  9. 如权利要求8所述的数据读写电路，其中，还包括：
    第一控制信号线，与所述电容器的第二电极相连接，被配置为：于所述预充电阶段和所述数据写入阶段向所述第二电极施加第一写控制电压，于所述数据读取阶段向所述第二电极施加读控制电压；
    第二控制信号线，与所述第二晶体管相连接，被配置为：于所述待机阶段和所述数据读取阶段控制所述第二晶体管关断，于所述预充电阶段和所述数据写入阶段控制所述第二晶体管导通。
  10. 如权利要求9所述的数据读写电路，其中，
    所述数据信号线还被配置为：于数据保持阶段，向所述第一晶体管提供所述第一参考电压；
    所述第二控制信号线还被配置为：于所述数据保持阶段，在所述数据信号线的电压为所述第一参考电压之后，控制所述第二晶体管关断；
    所述辅助信号线还被配置为：于所述数据保持阶段，在关断所述第二晶体管之后，向所述第一晶体管和第二晶体管同时提供所述第一参考电压；
    其中，所述第一控制信号线还被配置为：于所述数据保持阶段，在关断所述第二晶体管之后，向所述第二电极施加第二写控制电压；其中，所述第二写控制电压小于所述第一写控制电压。
  11. 如权利要求9或10所述的数据读写电路，其中，
    所述第一控制信号线还被配置为：于数据保持阶段，向所述第二电极施加第二写控制电压；其中，所述第二写控制电压小于所述第一写控制电压；
    所述数据信号线还被配置为：于所述数据保持阶段，在所述第二电极的电压为所述第二写控制电压之后向所述第一晶体管提供所述第一参考电压；
    所述第二控制信号线还被配置为：于所述数据保持阶段，在所述数据信号线提供所述第一参考电压之后，控制所述第二晶体管关断；
    所述辅助信号线还被配置为：于所述数据保持阶段，在关断所述第二晶体管之后，向所述第一晶体管和第二晶体管同时提供所述第一参考电压。
  12. 如权利要求9～11中任一项所述的数据读写电路，其中，所述第一晶体管包括：第一栅极、第一极和第二极；所述第二晶体管包括第二栅极、第一极和第二极；其中，
    所述第一栅极和所述第二晶体管的第一极均与所述第一电极相连接；
    所述第二电极与所述第一控制信号线相连接；
    所述第二栅极与所述第二控制信号线相连接；
    所述第一晶体管的第一极与所述数据信号线相连接；
    所述第一晶体管的第二极和所述第二晶体管的第二极分别与所述辅助信号线相连接。
  13. 如权利要求9～12中任一项所述的数据读写电路，其中，所述存储单元的数量为多个；多个所述存储单元沿第一方向排布呈行，沿第二方向排布呈列；所述第一方向和所述第二方向相交；
    其中，一行所述存储单元共用一条所述第一控制信号线和一条所述第二控制信号线；
    一列所述存储单元共用一条所述数据信号线和一条所述辅助信号线。
  14. 如权利要求8～13中任一项所述的数据读写电路，其中，还包括：
    第一参考电压端，通过第一选通电路与所述数据信号线对应连接，通过第二选通电路与所述辅助信号线对应连接；其中，所述第一参考电压端被配置为提供所述第一参考电压；所述第一选通电路被配置为：于所述待机阶段和所述预充电阶段，选择连通所述第一参考电压端和所述数据信号线；所述第二选通电路被配置为：于所述待机阶段和所述预充电阶段，选择连通所述第一参考电压端和所述辅助信号线；
    第二参考电压端，通过第三选通电路与所述辅助信号线对应连接；其中，所述第二参考电压端被配置为提供所述第二参考电压；所述第三选通电路被配置为：于所述数据读取阶段选择连通所述第二参考电压端和所述辅助信号线。
  15. 一种存储器，包括：至少一个存储单元，以及与所述存储单元对应连接的第一位线、第二位线、第一字线和第二字线；
    其中，所述存储单元包括：电容器、第一晶体管和第二晶体管；所述电容器包括绝缘设置的第一电极和第二电极；所述第一晶体管和所述第二晶体管均包括栅极和第一极、第二极；
    所述第一电极、所述第一晶体管的栅极和所述第二晶体管的第一极相连接，且三者的连接交点为存储节点；
    所述第一字线与所述第二电极相连接，所述第二字线与所述第二晶体管的栅极相连接；
    所述第一位线与所述第一晶体管的第一极相连接，所述第二位线与所述第一晶体管的第二极、所述第二晶体管的第二极同时连接；
    其中，所述第一位线被配置为：于预充电阶段向所述第一晶体管的第一极提供第一参考电压，于数据写入阶段向所述第一晶体管提供待写入数据的数据电压，于数据读取阶段响应于所述第一晶体管是否导通读取所述存储节点已写入的数据；
    所述第二位线被配置为：于所述预充电阶段向所述第一晶体管的第二极和所述第二晶体管的第二极同时提供所述第一参考电压，于所述数据写入阶段浮置，于所述数据读取阶段向所述第一晶体管和第二晶体管同时提供第二参考电压；
    其中，所述第一参考电压大于所述存储单元待写入的最大数据电压和所述第一晶体管的阈值电压之和。
  16. 一种存储器的驱动方法，应用于如权利要求15所述的存储器；所述方法包括：
    在预充电阶段，所述第一位线向所述第一晶体管的第一极提供第一参考电压，所述第二位线向所述第一晶体管的第二极和所述第二晶体管的第二极同时提供所述第一参考电压；所述第一字线向所述第二电极施加第一写控制电压，所述第二字线向所述第二晶体管的栅极施加第三写控制电压，控制所述第二晶体管导通，以对所述存储节点进行预充电；
    在数据写入阶段，所述第二位线浮置，所述第一位线向所述第一晶体管的第一极提供数据电压；所述第一晶体管导通，所述存储节点放电至稳定状态，写入所述数据电压对应的数据；
    在数据读取阶段，所述第二字线向所述第二晶体管的栅极施加第四写控制电压，所述第二晶体管处于关断状态；所述第一字线向所述第二电极施加读控制电压；所述第二位线向所述第一晶体管的第二极和所述第二晶体管的第二极同时提供第二参考电压；所述数据 信号线响应于所述第一晶体管是否导通读取所述存储节点已写入的所述数据；
    其中，所述第一参考电压大于所述存储单元待写入的最大数据电压和所述第一晶体管的阈值电压之和。
  17. 一种电子设备，包括：如权利要求8～14中任一项所述的数据读写电路；或如权利要求15所述的存储器。
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