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WO2024221622A1 - 一种前照式图像传感器实现方法及前照式图像传感器 - Google Patents

一种前照式图像传感器实现方法及前照式图像传感器 Download PDF

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Publication number
WO2024221622A1
WO2024221622A1 PCT/CN2023/108183 CN2023108183W WO2024221622A1 WO 2024221622 A1 WO2024221622 A1 WO 2024221622A1 CN 2023108183 W CN2023108183 W CN 2023108183W WO 2024221622 A1 WO2024221622 A1 WO 2024221622A1
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Prior art keywords
image sensor
illuminated image
deep trench
semiconductor substrate
layer
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PCT/CN2023/108183
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English (en)
French (fr)
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陈丹科
赵立新
黄琨
付文
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格科微电子（上海）有限公司
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Publication of WO2024221622A1 publication Critical patent/WO2024221622A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a front-illuminated image sensor implementation method and the front-illuminated image sensor.
  • CMOS image sensors have been increasingly widely used in many fields, such as consumer electronics, automotive electronics, security, biomedicine, industrial monitoring, etc., due to their low power consumption, low cost, and CMOS process compatibility.
  • the photodiode of a single pixel unit has a certain upper limit for generating or accumulating charge, namely the full well capacity.
  • the photodiode of a single pixel unit receives strong incident light, the photodiode can easily reach the full well capacity.
  • overflow drain structures in pixel units to guide Excess photoelectrons overflow to the overflow drain instead of migrating to the adjacent photodiode, thereby improving the floating phenomenon.
  • an additional transistor similar to a transfer transistor (TX) is added around the photodiode, and a high-voltage drain is added as an overflow channel, but this design scheme is difficult to apply to small-size pixel designs.
  • the structure of the pixel unit of a common CMOS image sensor can be divided into two types: a 3T structure and a 4T structure. In the 4T structure, the floating diffusion area can usually be designed as an overflow drain.
  • the barrier height of the overflow potential from the floating diffusion area to the photodiode can be adjusted.
  • the floating diffusion area is at a high potential, and the excess photoelectrons generated by the photodiode under high brightness conditions can migrate to the floating diffusion area with a lower overflow barrier height, thereby improving the floating problem.
  • this method uses the floating diffusion area as an overflow drain, which has problems such as a small overflow channel range, poor control capability, and large process deviation.
  • the design of the floating diffusion area as an overflow drain is difficult to apply to the 3T structure.
  • the floating diffusion area of the integration row is at a low potential, and it is difficult to extract the excess charge generated by the photodiode. Therefore, the floating diffusion area in the 3T structure is difficult to realize the function of the overflow drain, which makes the excess charge generated by the photodiode easily overflow to other photodiodes, causing the image quality to deteriorate.
  • the conventional 3T structure therefore has a more serious floating problem. Therefore, the overflow drain of the 3T structure is often designed as a vertical overflow drain, that is, a layer of N-type area is added to the bottom of the photodiode to form an overflow channel.
  • the conventional vertical overflow drain process usually requires deep N-type or P-type injection of the photodiode to achieve the adjustment of the overflow barrier, but due to the high injection energy, severe tailing, and difficult to control the injection width, it is difficult to make a thin and easy-to-control vertical overflow drain overflow barrier layer.
  • the depth of the photodiode in order to increase the sensitivity of the pixel unit to red light or infrared light, it is usually necessary to increase the depth of the photodiode, so the depth of the vertical overflow drain is also required. Large (such as more than 5 microns).
  • the N-well of the vertical overflow drain is implanted too deeply, which has high requirements on the implantation energy, photoresist thickness or cross-sectional shape, high implantation cost and difficulty, and has great limitations.
  • the object of the present invention is to provide a method for realizing a front-illuminated image sensor, comprising:
  • An isolation structure between the image sensor pixel units is formed in the first deep trench.
  • the method further comprises:
  • a first doping layer is provided at the lower part of the semiconductor substrate, wherein the doping type of the first doping layer is the same as the doping type of the photogenerated carrier collection region of the front-illuminated image sensor, and a second doping layer of opposite doping type to the first doping layer is formed on the first doping layer to form a potential barrier blocking layer for noise in the semiconductor substrate, thereby improving the performance of the image sensor.
  • the method further includes:
  • a photogenerated carrier collection region of the front-illuminated image sensor is formed on the upper portion of the second doping layer, and the photogenerated carrier collection region and the doping layer of the first doping layer are Same type;
  • the first deep trench of the semiconductor substrate is etched to a certain depth to improve the electrical isolation and optical isolation performance between the photogenerated carrier collection regions of the semiconductor island structure.
  • the method further comprises:
  • Ion implantation of a doping type opposite to that of the first doping layer is performed at the bottom of the first deep trench and the implanted ions are laterally diffused to form the second doping layer.
  • the second doping layer at least partially covers the first doping layer.
  • a cantilever connection structure is formed, so that at least part of the upper portions of the semiconductor island structures are connected to each other through the cantilever connection structure.
  • the semiconductor substrate is formed on the surface of the first doping layer, and when etching the semiconductor substrate to form a first deep trench, etching stops in the semiconductor substrate, and the distance between the bottom of the first deep trench and the surface of the first doping layer is between 0 and 2 microns.
  • the step of causing the ion implantation region to perform lateral diffusion comprises:
  • a high-temperature annealing process is used to cause the ion implantation area to diffuse laterally, so that the ion implantation areas around the semiconductor island structure are connected, thereby achieving electrical isolation between the semiconductor island structures and between the semiconductor island structure and the first doping layer, while maintaining electrical connection between the semiconductor substrate and the first doping layer in the peripheral area.
  • the isolation structure formed between the image sensor pixel units in the first deep trench includes:
  • a polycrystalline semiconductor material is filled on the surface of the first dielectric layer to form the isolation structure.
  • forming the cantilever beam connection structure includes:
  • the first deep trench and the cantilever beam connection structure are formed by lateral etching.
  • a transistor structure is formed at the cantilever beam connection structure.
  • the present invention also provides a front-illuminated image sensor, which is formed by using the above-mentioned implementation method of the front-illuminated image sensor.
  • the present invention proposes a new method for forming a front-illuminated image sensor, which can realize the electrical connection of the deep vertical overflow drain without being limited by the depth of the photodiode.
  • the present invention adds a layer of N-type epitaxial layer so that it can serve as the deep N-type injection area of the photodiode in the pixel area and can also play a connecting role in the peripheral vertical overflow drain.
  • the P-type injection of the vertical overflow drain does not require a photolithography mask.
  • the present invention can omit the photodiode deep injection photolithography mask and the vertical overflow drain N-well injection photolithography mask, thereby reducing the process cost.
  • the process flow adopted by the present invention has low injection energy, so it can effectively reduce the doping distribution caused by injection, so that a thin overflow barrier layer with clear boundaries can be obtained, and the deviation between different pixels can be effectively controlled.
  • FIG. 8 is a schematic diagram of the cross-sectional structure of a peripheral region, and the others are schematic diagrams of the cross-sectional structure of a pixel region.
  • the object of the present invention is to provide a method for implementing a front-illuminated image sensor, specifically comprising the following steps:
  • Step S1 before forming the gate, etching the semiconductor substrate 100 to form a first deep trench 110 and a semiconductor island structure 120 separated by the first deep trench 110, as shown in FIG1 ;
  • Step S2 forming an isolation structure 111 between the image sensor pixel units in the first deep trench 110 , as shown in FIG. 2 .
  • step S2 may be implemented by the following steps:
  • Step S21 forming a first dielectric layer 112 (not shown in the figure) on the surface of the first deep trench 110;
  • Step S22 filling a polycrystalline semiconductor material on the surface of the first dielectric layer 112 to form the isolation structure 111 .
  • a cantilever connection structure 121 when etching the semiconductor substrate 100 in step S1 to form the first deep trench 110 and the semiconductor island structure 120 separated by the first deep trench 110, a cantilever connection structure 121 may be formed, and the cantilever connection structure 121 connects at least part of the upper part of the semiconductor island structure 120 to each other through the connection structure, so as to reduce process defects generated in subsequent epitaxial steps and improve the performance of the image sensor.
  • a transistor structure may be formed at the cantilever connection structure 121.
  • the cantilever beam connection structure 121 may be formed by the following steps:
  • Step S31 etching the semiconductor substrate 100 to form a second trench 130, as shown in FIG. 3;
  • Step S32 forming a second dielectric layer 131 (not shown in the figure) on the surface of the second trench 130;
  • Step S33 etching the bottom of the second dielectric layer 131 and the semiconductor substrate 100 to form a third deep trench 140, as shown in FIG. 4;
  • Step S34 forming the first deep trench 110 and the cantilever beam connection structure 121 by lateral etching, as shown in FIG. 5 .
  • the method before etching the semiconductor substrate 100 in step S1, the method further includes:
  • a first doping layer 200 is provided at the bottom of the semiconductor substrate 100, wherein the doping type of the first doping layer 200 is the same as the photogenerated current of the front-illuminated image sensor.
  • the sub-collection regions have the same doping type, as shown in FIG1 . For example, they may all be N-type doped.
  • a second doping layer 300 having a doping type opposite to that of the first doping layer 200 may be formed on the first doping layer 200.
  • the second doping layer 300 is P-type doped to form a potential barrier blocking layer for noise in the semiconductor substrate 100, so as to improve the performance of the image sensor.
  • the present invention can form the second doping layer 300 on the surface of the first doping layer 200 by an epitaxial process
  • a photogenerated carrier collection region of the front-illuminated image sensor may be formed on the second doping layer.
  • the photogenerated carrier collection region has the same doping type as the first doping layer 200.
  • the etching may be performed to a certain depth to improve the electrical isolation and optical isolation performance between the photogenerated carrier collection regions of the semiconductor island structure.
  • the second doping layer 300 can be formed by implanting ions with doping types opposite to those of the first doping layer 200 at the bottom of the first deep trench 110 and laterally diffusing the implanted ions, as shown in FIGS. 6 and 7 .
  • a high temperature annealing process can be used to perform lateral diffusion on the ion implantation area, so that the ion implantation area around the semiconductor island structure 120 is connected, as shown in FIG. 7, so that the semiconductor island structures 120 and the semiconductor island structures 120 are connected to each other.
  • the electrical isolation between the doped layers 200 is achieved while maintaining the electrical connection between the semiconductor substrate 100 and the first doped layer 200 in the peripheral region, as shown in FIG. 8 .
  • an N-type first doping layer 200 is provided, and the N-type first doping layer 200 preferably adopts N+ type doping with a high doping concentration to serve as a vertical overflow drain.
  • the concentration of the high-concentration N-type doping in the vertical overflow drain is too low, the potential will drop too much, causing the overflow barrier of the photodiode to rise and the floating to deteriorate; and if the doping concentration is too high, diffusion is likely to occur during the subsequent heat treatment process, affecting the photodiode and easily causing variation.
  • the N-type doping concentration of the first doping layer is between 10 17 and 10 21 , and the thickness can be 0.5 to 5 microns.
  • a semiconductor substrate 100 may be formed on the first doped layer 200 by epitaxy, and N-type doping may be used to form a photo-generated carrier collection region of a photodiode in a subsequent process, and to provide a partial full well capacity, and at the same time, to be electrically connected to the first doped layer 200 in the peripheral region.
  • the doping concentration range of the semiconductor substrate 100 may be selected between 10 14 and 10 18 , and the thickness may be 2 to 10 microns.
  • a P-type doping epitaxy may be further performed on the N-type doped semiconductor substrate 100 to provide a P-type substrate for transistors in the pixel region and the peripheral region.
  • step S1 is performed to form a first deep trench 110 and a semiconductor island.
  • Structure 120 at this time, a cantilever connection structure 121 can be formed according to the process of steps S31 to S34.
  • shallow ion implantation is performed, as shown in FIG6.
  • the doping type of this ion implantation is opposite to that of the first doping layer 200, that is, P-type doping, such as boron implantation, is used in this embodiment.
  • P-type doping such as boron implantation
  • the overflow barrier in the pixel area can be regulated by regulating the P-type implantation energy, dose, annealing time, and annealing temperature.
  • the distance between the first deep trenches 110 can be increased so that the P-type implantation does not affect the electrical connection between the N-type doped semiconductor substrate 100 and the high-concentration N-type doped first doping layer 200, as shown in FIG8.
  • the P-type implantation energy can be selected between 5 and 50 k
  • the implantation dose concentration can be selected between 10 12 and 10 15
  • the annealing temperature can be selected between 800 and 1200° C.
  • the annealing time is preferably not more than 6 hours.
  • the second doping layer 300 needs to at least partially cover the first doping layer 200.
  • the semiconductor substrate 100 can be directly formed on the surface of the first doping layer 200, and when the semiconductor substrate 100 is etched to form the first deep trench 110 in step S1, the etching stops in the semiconductor substrate 100, wherein the distance between the bottom of the first deep trench 110 and the surface of the first doping layer 200 can be controlled to be between 0 and 2 microns.
  • step S2 can be performed to form an isolation region, as shown in FIG. 2 , and then subsequent conventional steps of the image sensor are performed, such as active region etching, photodiode formation, transistor formation, source and drain implantation, metal connection, etc.
  • the process flow of the vertical overflow drain adopted in this embodiment can realize the electrical connection of the deep vertical overflow drain without being limited by the depth of the photodiode.
  • it can serve as the deep N-type injection area of the photodiode in the pixel area, and can also realize the connection of the peripheral vertical overflow drain; at the same time, the P-type injection of the vertical overflow drain does not require a photolithography mask, so compared with the process flow of the conventional vertical overflow drain formation, the photodiode deep injection photolithography mask and the vertical overflow drain N-well injection photolithography mask can be omitted, thereby reducing the process cost.
  • the overflow barrier adjustment of the vertical overflow drain is formed by shallow P-type injection, and the injection energy is low, so the doping distribution caused by the injection can be effectively reduced, so that a thin thickness and clear boundary overflow barrier layer can be obtained, and the deviation between different pixels can be effectively controlled.
  • the present invention also provides a front-illuminated image sensor, which is formed by using the aforementioned implementation method of the front-illuminated image sensor.

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Abstract

本发明提供一种前照式图像传感器的实现方法，包括：在栅极形成之前，刻蚀半导体衬底形成第一深沟槽，及由所述第一深沟槽间隔的半导体岛状结构；于所述第一深沟槽中形成所述图像传感器像素单元之间的隔离结构。本发明可以不受到光电二极管深度的限制实现深层纵向溢出漏的电学连接。优选地，相较于常规的工艺流程，以省略光电二极管深层注入光刻掩膜和纵向溢出漏N阱注入光刻掩膜，从而降低工艺成本。本发明采用的工艺流程注入能量低，因此可以有效减少注入导致的掺杂分布，从而可以得到厚度薄、边界清晰的溢出势垒层，有效控制不同像素之间的偏差。

Description

一种前照式图像传感器实现方法及前照式图像传感器
本申请要求于2023年4月26日提交中国专利局、申请号为202310471699.9、发明名称为“一种前照式图像传感器实现方法及前照式图像传感器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，特别涉及一种前照式图像传感器实现方法及前照式图像传感器。
背景技术
近年来，CMOS图像传感器因具备低功耗、低成本、CMOS工艺兼容等特点，逐渐在多个领域得到越来越广泛的应用，如消费电子、汽车电子、安防、生物医疗、工业监控等。在CMOS图像传感器中，单个像素单元的光电二极管具备一定的产生或积累电荷的上限，即满阱容量，当单个像素单元的光电二极管接收强的入射光时，该光电二极管就很容易达到满阱容量，当积累的光电子过多时，就容易产生该像素单元的光电子向周围邻近像素单元的光电二极管迁移的浮散过程，使得邻近像素的光电子数增加，导致图像质量下降。因此，从设计和工艺上改善浮散现象是CMOS图像传感器设计和制备的重点。
当前，业界主要通过在像素单元中设计溢出漏结构，引导 多余光电子向溢出漏溢出，而不向邻近的光电二极管迁移，以此来改善浮散现象。如在光电二极管的周边额外新增一个类似转移晶体管(TX)的晶体管，并增加一个高压漏极作为溢出通道，但这种设计方案难以适用于小尺寸像素设计。常见CMOS图像传感器的像素单元的结构可以分为3T结构、4T结构两种。在4T结构中，通常可以把浮置扩散区设计成溢出漏。通过对转移晶体管沟道的注入条件的调节，可以调节浮置扩散区到光电二极管的溢出电势的势垒高度。在积分行光电二极管积分的过程中，浮置扩散区处于高电位，高亮条件下光电二极管产生的多余光电子可以向溢出势垒高度更低的浮置扩散区迁移，从而改善浮散问题。但此种方法将浮置扩散区作为溢出漏，存在溢出通道范围较小、控制能力差且工艺偏差大等问题。此外，浮置扩散区作为溢出漏的设计难以适用于3T结构。
在3T结构中，积分时，积分行的浮置扩散区处于低电位，难以将光电二极管产生的多余电荷抽走，因此3T结构中的浮置扩散区难以实现溢出漏的功能，这使得光电二极管产生的多余电荷容易向其他光电二极管溢出，使得图像质量下降，常规的3T结构因而具备更严重的浮散问题。因此，3T结构的溢出漏常被设计成纵向溢出漏，即在光电二极管底部增加一层N型区域，形成一个溢出通道。但是，常规的纵向溢出漏工艺流程通常需要通过光电二极管的深层N型注入或P型注入实现溢出势垒的调节，但由于注入能量较高，拖尾严重，注入宽度难以控制，因此难以做出厚度薄且易控制的纵向溢出漏溢出势垒层。此外，为了提高像素单元的红光或红外光的敏感度，通常需要增加光电二极管的深度，因此也要求纵向溢出漏的深度 较大(如5微米以上)。而纵向溢出漏的N阱进行过深的离子注入，对注入能量、光刻胶厚度或截面形状要求较高，注入成本高、注入难度大，存在较大的局限性。
发明内容
本发明的目的在于提供一种前照式图像传感器的实现方法，包括：
在栅极形成之前，刻蚀半导体衬底形成第一深沟槽，及由所述第一深沟槽间隔的半导体岛状结构；
于所述第一深沟槽中形成所述图像传感器像素单元之间的隔离结构。
进一步地，所述刻蚀半导体衬底之前，还包括：
提供位于所述半导体衬底下部的第一掺杂层，所述第一掺杂层的掺杂类型与所述前照式图像传感器光生载流子收集区的掺杂类型相同，于所述第一掺杂层上形成与所述第一掺杂层掺杂类型相反的第二掺杂层，以形成所述半导体衬底中噪声的势垒阻挡层，提高图像传感器的性能。
进一步地，通过外延工艺于所述第一掺杂层表面形成所述第二掺杂层；
形成所述第二掺杂层之后，还包括：
于所述第二掺杂层上部形成所述前照式图像传感器的光生载流子收集区，所述光生载流子收集区与所述第一掺杂层的掺杂 类型相同；；
刻蚀半导体衬底所述第一深沟槽至一定深度，以提高所述半导体岛状结构的光生载流子收集区之间电学隔离和光学隔离性能。
进一步地，形成所述第一深沟槽后，还包括：
于所述第一深沟槽底部进行与第一掺杂层类型相反的掺杂的离子注入并对离子注入进行侧向扩散，形成所述第二掺杂层。
进一步地，所述第二掺杂层至少部分覆盖所述第一掺杂层。
进一步地，所述刻蚀半导体衬底形成第一深沟槽及由所述第一深沟槽间隔的半导体岛状结构时，形成悬梁连接结构，使至少部分所述半导体岛状结构上部之间通过所述悬梁连接结构相互连接。
进一步地，所述半导体衬底形成于所述第一掺杂层表面，所述刻蚀半导体衬底形成第一深沟槽时，刻蚀停止在所述半导体衬底中，所述第一深沟槽的底部与所述第一掺杂层表面的距离在0～2微米之间。
进一步地，所述使所述离子注入区进行侧向扩散包括：
采用高温退火工艺，使所述离子注入区进行侧向扩散，使所述半导体岛状结构周围的所述离子注入区相连，实现所述半导体岛状结构之间、以及所述半导体岛状结构与所述第一掺杂层的电学隔离，同时保持外围区域的所述半导体衬底和所述第一掺杂层的电性连接。
进一步地，所述于所述第一深沟槽中形成所述图像传感器像素单元之间的隔离结构包括：
于所述第一深沟槽表面形成第一介质层；
于所述第一介质层表面填充多晶半导体材料，形成所述隔离结构。
进一步地，所述形成悬梁连接结构包括：
刻蚀所述半导体衬底，形成第二沟槽；
于所述第二沟槽表面形成第二介质层；
刻蚀所述第二介质层底部及所述半导体衬底，形成第三深沟槽；
通过侧向刻蚀，形成所述第一深沟槽及所述悬梁连接结构。
进一步地，于所述悬梁连接结构处形成晶体管结构。
本发明还提供了一种前照式图像传感器，采用前述的前照式图像传感器的实现方法形成
本发明通过上述方案，提出了一种新的前照式图像传感器的形成方法，可以实现深层纵向溢出漏的电学连接，而不受到光电二极管深度的限制。在可选的实施方式中，本发明通过新增一层N型外延层，使其既充当像素区域光电二极管的深层N型注入区，也能起到外围纵向溢出漏的连接作用，同时纵向溢出漏的P型注入不需要光刻掩膜，因此相较于常规的工艺流程，本发明可以省略光电二极管深层注入光刻掩膜和纵向溢出漏N阱注入光刻掩膜，从而降低工艺成本。本发明采用的工艺流程注入能量低，因此可以有效减少注入导致的掺杂分布，从而可以得到厚度薄、边界清晰的溢出势垒层，有效控制不同像素之间的偏差。
附图说明
通过参照附图阅读以下所作的对非限制性实施例的详细描述，本发明的其它特征、目的和优点将会变得更明显。
图1～图8为本发明不同实施例中前照式图像传感器形成过程中的结构示意图，其中图8为外围区域的截面结构示意图，其余为像素区域的截面示意图。
在图中，贯穿不同的示图，相同或类似的附图标记表示相同或相似的装置(模块)或步骤。
具体实施方式
本发明的目的在于提供一种前照式图像传感器的实现方法，具体地，包括以下步骤：
步骤S1：在栅极形成之前，刻蚀半导体衬底100形成第一深沟槽110，及由所述第一深沟槽110间隔的半导体岛状结构120，如图1所示；
步骤S2：于所述第一深沟槽110中形成所述图像传感器像素单元之间的隔离结构111，如图2所示。
在一种实施方式中，如图2所示，步骤S2可以通过以下步骤实现：
步骤S21：于所述第一深沟槽110表面形成第一介质层112(图中未示出)；
步骤S22：于所述第一介质层112表面填充多晶半导体材料，形成所述隔离结构111。
在可选的实施方式中，步骤S1中刻蚀半导体衬底100形成第一深沟槽110及由所述第一深沟槽110间隔的半导体岛状结构120时，可形成悬梁连接结构121，悬梁连接结构121使至少部分所述半导体岛状结构120的上部之间通过该连接结构相互连接，以减少后续外延步骤时产生的工艺缺陷，提高图像传感器的性能。优选地，可于该悬梁连接结构121处形成晶体管结构。
具体地，在可选的实施方式中，可以采用以下步骤形成悬梁连接结构121：
步骤S31：刻蚀所述半导体衬底100，形成第二沟槽130，如图3所示；
步骤S32：于所述第二沟槽130表面形成第二介质层131(图中未示出)；
步骤S33：刻蚀所述第二介质层131底部及所述半导体衬底100，形成第三深沟槽140，如图4所示；
步骤S34：通过侧向刻蚀，形成所述第一深沟槽110及所述悬梁连接结构121，如图5所示。
在一种可选的实施方式中，在步骤S1刻蚀半导体衬底100之前，还包括：
提供位于所述半导体衬底100下部的第一掺杂层200，所述第一掺杂层200的掺杂类型与所述前照式图像传感器光生载流 子收集区的掺杂类型相同，如图1所示。例如，可以均为N型掺杂。之后，可以于所述第一掺杂层200上形成与所述第一掺杂层200掺杂类型相反的第二掺杂层300，例如，若第一掺杂层200选择N型掺杂，则第二掺杂层300则选择P型掺杂，以形成所述半导体衬底100中噪声的势垒阻挡层，以提高图像传感器的性能。
具体地，在一种可选的实施方式中，本发明可以通过外延工艺于所述第一掺杂层200表面形成所述第二掺杂层300；
在形成所述第二掺杂层300之后，可以继续于所述第二掺杂层上部形成所述前照式图像传感器的光生载流子收集区，在此种实施方式中，所述光生载流子收集区与所述第一掺杂层200的掺杂类型相同。进而，在步骤S1刻蚀半导体衬底100形成第一深沟槽110时，可以刻蚀至一定深度，以提高所述半导体岛状结构的光生载流子收集区之间电学隔离和光学隔离性能。
在另一种可选的实施方式中，也可以在步骤S1刻蚀形成第一深沟槽110之后，通过于所述第一深沟槽110底部进行与第一掺杂层200类型相反的掺杂的离子注入、并对离子注入进行侧向扩散的方式，来形成所述第二掺杂层300，如图6、图7所示。
优选地，在对离子注入进行侧向扩散时，可以采用高温退火工艺使所述离子注入区进行侧向扩散，使得所述半导体岛状结构120周围的所述离子注入区相连，如图7所示，实现所述半导体岛状结构120之间、以及所述半导体岛状结构120与所述第一掺 杂层200之间的电学隔离，同时保持外围区域的所述半导体衬底100和所述第一掺杂层200的电性连接，如图8所示。
例如，在一具体的实施例中，如图1所示，提供N型的第一掺杂层200，该N型第一掺杂层200优选的采用高掺杂浓度的N+型掺杂，以作为纵向溢出漏。在实际操作中，若纵向溢出漏中高浓度N型掺杂的浓度过低，会使得电势过多下降，使得光电二极管的溢出势垒上升，浮散变差；而若掺杂浓度过高，后续的热处理过程中也容易发生扩散，对光电二极管产生影响，也容易产生变异。在本实施例中，优选地，第一掺杂层的N型掺杂浓度为1017～1021之间，厚度可采用0.5～5微米。
之后，在第一掺杂层200上方可通过外延的方式形成半导体衬底100，采用N型掺杂，以便在后续工艺中形成光电二极管的光生载流子收集区，并提供部分满阱容量，同时，也能够在外围区域与第一掺杂层200电性连接。在实际操作中，若半导体衬底100中的N型掺杂浓度过低，会使得纵向溢出漏的外围链接电阻增加，反之则会引起光电二极管耗尽电势的增加，使得读出困难，产生残影。优选地，在本实施例中，半导体衬底100的掺杂浓度范围可以选择在1014～1018之间，厚度可以为2～10微米。
进一步地，还可在N型掺杂的半导体衬底100上继续进行一次P型掺杂的外延，为像素区域及外围区域的晶体管提供P型衬底。
之后，进行步骤S1，刻蚀形成第一深沟槽110和半导体岛状 结构120，此时可依据步骤S31～步骤S34的过程形成悬梁连接结构121。在深沟槽刻蚀完成后，进行浅层离子注入，如图6所示，此次离子注入的掺杂类型与第一掺杂层200相反，即在本实施例中采用P型掺杂，如硼注入。进一步通过高温退火工艺，实现P型注入的横向及纵向扩散，形成P阱，如图7所示。在实际操作过程中，通过对P型注入能量、剂量以及退火时间、退火温度的调控，可以实现像素区域内溢出势垒的调控。在外围纵向溢出漏的连接区域，可以通过增加第一深沟槽110之间的距离，使得该P型注入不影响N型掺杂的半导体衬底100与高浓度N型掺杂的第一掺杂层200之间的电性连接，如图8所示。优选地，该P型注入能量可以选择在5～50k之间，注入的剂量浓度可以选择在1012～1015之间，退火温度可以选择在800～1200℃，退火时间最好不超过6小时。
优选地，在此种实施例中，所述第二掺杂层300需至少部分覆盖所述第一掺杂层200。进一步可选地，所述半导体衬底100可直接形成于所述第一掺杂层200表面，在步骤S1中刻蚀半导体衬底100形成第一深沟槽110时，刻蚀停止在所述半导体衬底100中，其中所述第一深沟槽110的底部与所述第一掺杂层200表面的距离可控制在0～2微米之间。
之后，即可进行步骤S2，形成隔离区域，如图2所示，再进行图像传感器的后续常规步骤，比如有源区刻蚀、形成光电二极管、形成晶体管、源漏注入、金属连接等等。
在这种实施例中所采用的纵向溢出漏的工艺流程，可以实现深层纵向溢出漏的电学连接，而不受到光电二极管深度的限制。在工艺流程中，通过新增一层N型外延层，既可以充当像素区域的光电二极管的深层N型注入区域，也可以实现外围纵向溢出漏的连接；同时纵向溢出漏的P型注入不需要光刻掩膜，因此相较于常规纵向溢出漏形成的工艺流程而言，可以省略光电二极管深层注入光刻掩膜、纵向溢出漏N阱注入光刻掩膜，从而降低工艺成本。此种实施例中采用的工艺流程，纵向溢出漏的溢出势垒调节通过浅层P型注入形成，注入能量低，因此可以有效减少注入导致的掺杂分布，从而可以得到厚度薄、边界清晰的溢出势垒层，有效控制不同像素之间的偏差。
本发明还提供了一种前照式图像传感器，采用前述的前照式图像传感器的实现方法形成。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论如何来看，均应将实施例看作是示范性的，而且是非限制性的。此外，明显的，“包括”一词不排除其他元素和步骤，并且措辞“一个”不排除复数。装置权利要求中陈述的多个元件也可以由一个元件来实现。第一、第二等词语用来表示名称，而并不表示任何特定的顺序。

Claims (12)

  1. 一种前照式图像传感器的实现方法，其特征在于，包括：
    在栅极形成之前，刻蚀半导体衬底形成第一深沟槽，及由所述第一深沟槽间隔的半导体岛状结构；
    于所述第一深沟槽中形成所述图像传感器像素单元之间的隔离结构。
  2. 如权利要求1所述的前照式图像传感器的实现方法，其特征在于，所述刻蚀半导体衬底之前，还包括：
    提供位于所述半导体衬底下部的第一掺杂层，所述第一掺杂层的掺杂类型与所述前照式图像传感器光生载流子收集区的掺杂类型相同，于所述第一掺杂层上形成与所述第一掺杂层掺杂类型相反的第二掺杂层，以形成所述半导体衬底中噪声的势垒阻挡层，提高图像传感器的性能。
  3. 如权利要求2所述的前照式图像传感器的实现方法，其特征在于，通过外延工艺于所述第一掺杂层表面形成所述第二掺杂层；
    形成所述第二掺杂层之后，还包括：
    于所述第二掺杂层上部形成所述前照式图像传感器的光生载流子收集区，所述光生载流子收集区与所述第一掺杂层的掺杂类型相同；
    刻蚀半导体衬底所述第一深沟槽至一定深度，以提高所述 半导体岛状结构的光生载流子收集区之间电学隔离和光学隔离性能。
  4. 如权利要求2所述的前照式图像传感器的实现方法，其特征在于，形成所述第一深沟槽后，还包括：
    于所述第一深沟槽底部进行与第一掺杂层类型相反的掺杂的离子注入并对离子注入进行侧向扩散，形成所述第二掺杂层。
  5. 如权利要求4所述的前照式图像传感器的实现方法，其特征在于，所述第二掺杂层至少部分覆盖所述第一掺杂层。
  6. 如权利要求1所述的前照式图像传感器的实现方法，其特征在于，所述刻蚀半导体衬底形成第一深沟槽及由所述第一深沟槽间隔的半导体岛状结构时，形成悬梁连接结构，使至少部分所述半导体岛状结构上部之间通过所述悬梁连接结构相互连接。
  7. 如权利要求4所述的前照式图像传感器的实现方法，其特征在于，所述半导体衬底形成于所述第一掺杂层表面，所述刻蚀半导体衬底形成第一深沟槽时，刻蚀停止在所述半导体衬底中，所述第一深沟槽的底部与所述第一掺杂层表面的距离在0～2微米之间。
  8. 如权利要求4所述的前照式图像传感器的实现方法，其特征在于，所述使所述离子注入区进行侧向扩散包括：
    采用高温退火工艺，使所述离子注入区进行侧向扩散，使 所述半导体岛状结构周围的所述离子注入区相连，实现所述半导体岛状结构之间、以及所述半导体岛状结构与所述第一掺杂层的电学隔离，同时保持外围区域的所述半导体衬底和所述第一掺杂层的电性连接。
  9. 如权利要求1所述的前照式图像传感器的实现方法，其特征在于，所述于所述第一深沟槽中形成所述图像传感器像素单元之间的隔离结构包括：
    于所述第一深沟槽表面形成第一介质层；
    于所述第一介质层表面填充多晶半导体材料，形成所述隔离结构。
  10. 如权利要求6所述的前照式图像传感器的实现方法，其特征在于，所述形成悬梁连接结构包括：
    刻蚀所述半导体衬底，形成第二沟槽；
    于所述第二沟槽表面形成第二介质层；
    刻蚀所述第二介质层底部及所述半导体衬底，形成第三深沟槽；
    通过侧向刻蚀，形成所述第一深沟槽及所述悬梁连接结构。
  11. 如权利要求6所述的前照式图像传感器的实现方法，其特征在于，于所述悬梁连接结构处形成晶体管结构。
  12. 一种前照式图像传感器，其特征在于，采用如权利要求1～11所述的前照式图像传感器的实现方法形成。
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KR20040058691A (ko) * 2002-12-27 2004-07-05 주식회사 하이닉스반도체 누화현상을 감소시킨 시모스 이미지센서 및 그 제조방법
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