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WO2024221464A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2024221464A1
WO2024221464A1 PCT/CN2023/091855 CN2023091855W WO2024221464A1 WO 2024221464 A1 WO2024221464 A1 WO 2024221464A1 CN 2023091855 W CN2023091855 W CN 2023091855W WO 2024221464 A1 WO2024221464 A1 WO 2024221464A1
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WO
WIPO (PCT)
Prior art keywords
conductive layer
signal line
substrate
pixel driving
transistor
Prior art date
Application number
PCT/CN2023/091855
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English (en)
French (fr)
Other versions
WO2024221464A9 (zh
Inventor
曾超
邱远游
张手强
温为舒
朱磊
汪锐
Original Assignee
京东方科技集团股份有限公司
重庆京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 重庆京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202380008942.1A priority Critical patent/CN119234311A/zh
Priority to PCT/CN2023/091855 priority patent/WO2024221464A1/zh
Publication of WO2024221464A1 publication Critical patent/WO2024221464A1/zh
Publication of WO2024221464A9 publication Critical patent/WO2024221464A9/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device.
  • OLED display panels have gradually become one of the mainstreams in the display field due to their excellent performance such as low power consumption, high color saturation, wide viewing angle, thin thickness, and flexibility.
  • an array substrate comprising: a substrate, and a plurality of pixel driving circuit groups disposed on the substrate, wherein the plurality of pixel driving circuit groups are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect.
  • Each of the plurality of pixel driving circuit groups comprises: two pixel driving circuits disposed along the first direction.
  • the array substrate further includes: a first conductive layer disposed on the substrate, and a second conductive layer and a power signal line disposed on a side of the first conductive layer away from the substrate.
  • the pixel driving circuit includes: a driving transistor and a capacitor, and the capacitor includes: a first electrode plate and a second electrode plate, the first electrode plate is connected to the gate of the driving transistor, and the second electrode plate is connected to the power signal line; wherein the first electrode plate is located in the first conductive layer, and the second electrode plate is located in the second conductive layer; a first connection pattern is connected between the second electrodes of the two pixel driving circuits in the pixel driving circuit group, and the first connection pattern is located in the second conductive layer. wherein the size of the first connection pattern in the second direction is smaller than the size of the second electrode plate in the second direction.
  • a ratio of a size of the first connection pattern in the second direction to a size of the second electrode plate in the second direction is in a range of 10% to 50%.
  • a size of the first connection pattern in the second direction ranges from 2.0 ⁇ m to 5.5 ⁇ m.
  • the array substrate further includes: a shielding layer disposed between the substrate and the first conductive layer.
  • the shielding layer includes a plurality of shielding patterns; along the first direction, between at least two adjacent pixel driving circuit groups, a second connection pattern is connected between the shielding patterns of two adjacent pixel driving circuits, and the second connection pattern is located in the shielding layer.
  • the array substrate further includes: a second semiconductor layer, the second semiconductor layer is located on a side of the second conductive layer away from the substrate. The orthographic projection of the second connection pattern on the substrate overlaps with the orthographic projection of the second semiconductor layer on the substrate.
  • a third gate dielectric layer and a third insulating layer are provided on a side of the second semiconductor layer away from the substrate.
  • the third gate dielectric layer and the third insulating layer are provided with: at least one first via hole, the at least one first via hole penetrates the third gate dielectric layer and the third insulating layer to the second semiconductor layer, and the orthographic projection of the at least one first via hole on the substrate overlaps with the orthographic projection of the second connection pattern on the substrate.
  • the array substrate further comprises: a shielding layer disposed between the substrate and the first conductive layer.
  • the shielding layer comprises a plurality of shielding patterns; in the pixel driving circuit group, a third connection pattern is connected between the shielding patterns of two pixel driving circuits, and the third connection pattern is located in the shielding layer.
  • the orthographic projection of the first connection pattern on the substrate overlaps with the orthographic projection of the third connection pattern on the substrate by more than 70%.
  • the array substrate further comprises: a fourth conductive layer disposed on a side of the second conductive layer away from the substrate, and a first initialization signal line and a second initialization signal line located on the fourth conductive layer.
  • the orthographic projections of the first initialization signal line and the second initialization signal line on the substrate overlap with the orthographic projection of the first conductive layer on the substrate.
  • an overlapping area between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the first conductive layer on the substrate is greater than an overlapping area between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the first conductive layer on the substrate.
  • a ratio of an overlapping area between an orthographic projection of the first initialization signal line on the substrate and an orthographic projection of the first conductive layer on the substrate to an overlapping area between an orthographic projection of the second initialization signal line on the substrate and an orthographic projection of the first conductive layer on the substrate is greater than 1.5.
  • the array substrate includes: a reset signal line, the reset signal line is located in the first conductive layer, and the first initialization signal line, the second initialization signal line and the orthographic projection of the reset signal line on the substrate overlap.
  • the array substrate includes: the shielding layer disposed on one side of the substrate, and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer and a fourth conductive layer sequentially disposed in a direction away from the shielding layer.
  • the material of the first semiconductor layer includes low-temperature polysilicon
  • the material of the second semiconductor layer includes indium gallium zinc oxide.
  • the array substrate further includes: a shielding layer disposed between the substrate and the first conductive layer, the shielding layer including a plurality of shielding patterns; along the first direction, between at least two adjacent pixel driving circuit groups, a second connection pattern is connected between the shielding patterns of two adjacent pixel driving circuits, and the second connection pattern is located in the shielding layer.
  • the array substrate further includes: a light emitting control signal line.
  • the pixel driving circuit further includes: a second light-emitting control transistor, a gate of the second light-emitting control transistor is connected to a light-emitting control signal line, and a first electrode of the second light-emitting control transistor is connected to a second electrode of the driving transistor.
  • a region between two adjacent pixel driving circuit groups, between the first electrodes of two adjacent second light-emitting control transistors, and between the second connection pattern and the light-emitting control signal line is a first light-transmitting region, and an area of the first light-transmitting region is greater than 10 ⁇ m 2 .
  • the array substrate further includes: a first initialization signal line and a light emitting control signal line.
  • the pixel driving circuit further includes: a first reset transistor, a second light emitting control transistor and a second reset transistor, wherein the first electrode of the first reset transistor is connected to the first initialization signal line, and the second electrode of the first reset transistor is connected to the first light emitting control transistor.
  • the first electrodes of the second light emitting control transistors are connected, the second electrodes of the second light emitting control transistors are connected to the second electrodes of the second reset transistors, the first electrodes of the second light emitting control transistors are connected to the second electrodes of the driving transistors, and the gate of the second light emitting control transistors are connected to the light emitting control signal line.
  • the area between two adjacent pixel driving circuit groups, between the second electrodes of two adjacent second emission control transistors and between the first initialization signal line and the emission control signal line is a second light-transmitting area, and the area of the second light-transmitting area is greater than 10 ⁇ m 2 .
  • an array substrate comprising: a substrate, and a plurality of pixel driving circuit groups arranged on the substrate, wherein the plurality of pixel driving circuit groups are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect; wherein each pixel driving circuit group comprises: two pixel driving circuits arranged along the first direction.
  • the array substrate further comprises: a first conductive layer arranged on the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, and a fifth conductive layer.
  • the pixel driving circuit comprises: a driving transistor and a capacitor, wherein the capacitor comprises: a first plate and a second plate, wherein the first plate is connected to the gate of the driving transistor, and the second plate is connected to the fifth conductive layer.
  • the first electrode is located in the first conductive layer, and the second electrode is located in the second conductive layer; a first connection pattern is connected between the second electrodes of two pixel driving circuits in the pixel driving circuit group, and the first connection pattern is located in the second conductive layer; wherein the size of the first connection pattern in the second direction is smaller than the size of the second electrode in the second direction.
  • the array substrate also includes: a second scanning signal line
  • the pixel driving circuit also includes: a compensation transistor, the first electrode of the compensation transistor is connected to the gate of the driving transistor, the second electrode of the compensation transistor is connected to the second electrode of the driving transistor through a first pattern, and the gate of the compensation transistor is connected to the second scanning signal line.
  • the array substrate further includes: the shielding layer disposed on the substrate, and a first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer and the fourth conductive layer sequentially disposed in a direction away from the shielding layer.
  • the active layer of the driving transistor is located in the first semiconductor layer; the second scanning signal line is at least partially located in the third conductive layer; the active layer of the compensation transistor is located in the second semiconductor layer; and the first pattern is located in the fourth conductive layer.
  • the first pattern is connected to the second electrode of the driving transistor through a third via
  • the first conductive pattern is also connected to the second electrode of the compensation transistor through a first via
  • the first connection pattern does not overlap with the first via and the third via.
  • the shielding layer includes multiple shielding patterns; along the first direction, between at least two adjacent pixel driving circuit groups, a second connection pattern is connected between the shielding patterns of two adjacent pixel driving circuits, and the second connection pattern is located in the shielding layer; the second connection pattern does not overlap with the third via.
  • the shielding pattern and the second connection pattern are used to receive a constant voltage signal.
  • a display panel comprising: an array substrate as described in any of the above embodiments, the display panel also comprising a plurality of light-emitting devices, which are arranged on a plurality of pixel driving circuits of the array substrate, and the array substrate is used to drive the plurality of light-emitting devices to emit light.
  • a display device comprising: a display panel as described in any of the above embodiments, and further comprising a driving chip for driving the display panel to display.
  • FIG1 is a structural diagram of a mobile phone provided according to some embodiments of the present disclosure.
  • FIG2 is a structural diagram of a display panel provided according to some embodiments of the present disclosure.
  • FIG3A is an equivalent circuit diagram of a pixel driving circuit provided according to some embodiments of the present disclosure.
  • FIG3B is a timing diagram of a pixel driving circuit provided according to some embodiments of the present disclosure.
  • FIG4 is a structural diagram of a first conductive layer, a second conductive layer, and a second semiconductor layer after being superimposed according to some embodiments of the present disclosure
  • FIG. 5 is a structural diagram of a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, and a second semiconductor layer after being superimposed according to some embodiments of the present disclosure
  • FIG. 6 is a structural diagram of the shielding layer, the first conductive layer, the second conductive layer and the second semiconductor layer provided at CC of the array substrate provided in FIG. 5 after being superimposed;
  • FIG7A is a structural diagram of a shielding layer provided according to some embodiments of the present disclosure.
  • FIG. 7B is a structural diagram of a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer and a third conductive layer after being superimposed according to some embodiments of the present disclosure
  • 7C is another structural diagram of the shielding layer, the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer and the third conductive layer provided by some embodiments of the present disclosure after being superimposed;
  • 7D is another structural diagram of the shielding layer, the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer and the third conductive layer provided by some embodiments of the present disclosure after being superimposed;
  • 7E is another structural diagram of the shielding layer, the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer and the third conductive layer provided by some embodiments of the present disclosure after being superimposed;
  • FIG8 is a structural diagram of a third conductive layer provided according to some embodiments of the present disclosure.
  • FIG9 is a structural diagram of a fourth conductive layer provided according to some embodiments of the present disclosure.
  • FIG. 10 is a diagram of a shielding layer, a first semiconductor layer, a first conductive layer, A structural diagram after the second conductive layer, the second semiconductor layer, the third conductive layer and the fourth conductive layer are superimposed;
  • FIG11 is a structural diagram of a shielding layer, a first conductive layer, and a fourth conductive layer after being superimposed according to some embodiments of the present disclosure
  • FIG. 12 is a structural diagram of the superposition of a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer provided in accordance with some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • coupled indicates, for example, that two or more components are in direct physical or electrical contact.
  • coupled or “communicatively coupled” may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°;
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of the layers and the area of the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.
  • some embodiments of the present disclosure provide a display device.
  • the display device provided by the embodiments of the present disclosure may be any device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images.
  • the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and/or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.
  • PDAs personal data assistants
  • handheld or portable computers GPS receivers/navigators
  • cameras MP4 video players
  • video cameras game consoles
  • game consoles e.g., watches, clocks, calculators
  • television monitors flat panel displays
  • computer monitors e.g., flat panel displays, computer
  • a display device is exemplified as a mobile phone 1000 .
  • the mobile phone 1000 includes: a display panel 100 , and the mobile phone 1000 also includes: a frame, a circuit board, a driver chip and other electronic accessories.
  • the display panel 100 is arranged in the frame, and the driver chip is used to drive the display panel 100 for display.
  • the display panel 100 includes: an array substrate 1 and a light-emitting device stack 2.
  • the array substrate 1 includes: a base 101 and a pixel circuit stack 30, and the pixel circuit stack 30 is disposed on the base 101.
  • the material of the substrate 101 may include any one of glass, metal or flexible material.
  • the pixel circuit stack 30 is formed with multiple pixel driving circuits 10.
  • the pixel circuit stack 30 includes: a blocking layer 11, a first semiconductor layer 13, a first conductive layer 15, a second conductive layer 17, a second semiconductor layer 61, a third conductive layer 62, a fourth conductive layer 19 and a fifth conductive layer 21 stacked in sequence.
  • the material of the first semiconductor layer 13 includes low temperature polysilicon.
  • the material of the second semiconductor layer 61 includes indium gallium zinc oxide.
  • the functional film layers include: a shielding layer 11, a first semiconductor layer 13, a first conductive layer 15, a second conductive layer 17, a second semiconductor layer 61, a third conductive layer 62, a fourth conductive layer 19 and a fifth conductive layer 21.
  • the insulating layer includes: a first insulating layer 102 , a first gate dielectric layer 103 , a second gate dielectric layer 104 , a second insulating layer 105 , a third gate dielectric layer 106 , a third insulating layer 107 , a passivation layer 108 , a first planarization layer 109 and a second planarization layer 110 .
  • the pixel circuit stack 30 includes a blocking layer 11, a first insulating layer 102, a first semiconductor layer 13, a first gate dielectric layer 103, a first conductive layer 15, a second gate dielectric layer 104, a second conductive layer 17, a second insulating layer 105, a second semiconductor layer 61, a third gate dielectric layer 106, a third conductive layer 62, a third insulating layer 107, a fourth conductive layer 19, a passivation layer 108, a first planarization layer 109, a fifth conductive layer 21 and a second planarization layer 110 which are stacked in sequence.
  • the material of the first planarization layer 109 and the second planarization layer 110 includes polyimide, and the material of the first insulating layer 102 , the second insulating layer 105 , and the third insulating layer 107 includes any one of silicon nitride and silicon oxide.
  • the pixel driving circuit 10 in some embodiments of the present disclosure can be a 7T1C, 8T1C or 9T1C circuit, wherein T represents a transistor, and the number before T represents the number of transistors, and C represents a capacitor, and the number before C represents the number of capacitors.
  • 7T1C represents 7 transistors and 1 capacitor.
  • the structure of the pixel driving circuit 10 shown in FIG3A is introduced, and the pixel driving circuit 10 is a 7T1C pixel driving circuit.
  • the pixel driving circuit 10 includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a second reset transistor T7.
  • the first reset transistor T1 includes: a gate, a first electrode and a second electrode T12, the gate of the first reset transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1, and the second electrode T12 of the first reset transistor T1 is electrically connected to the third node N3.
  • the first reset transistor T1 is configured to: reset the gate of the driving transistor T3 in response to the reset signal received at the first reset signal line Reset1.
  • the compensation transistor T2 includes: a gate, a first electrode T21 and a second electrode T22, the gate of the compensation transistor T2 is electrically connected to the second scanning signal line Gate2, the first electrode T21 of the compensation transistor T2 is electrically connected to the first scanning signal line The node N1 is electrically connected, and the second electrode T22 of the compensation transistor T2 is electrically connected to the third node N3.
  • the compensation transistor T2 is configured to reset or threshold-compensate the driving transistor T3 in response to the scan signal received at the second scan signal line Gate2.
  • the driving transistor T3 includes: a gate T33, a first electrode and a second electrode T32, the gate T33 of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to the second node N2, and the second electrode T32 of the driving transistor T3 is electrically connected to the third node N3.
  • the driving transistor T3 is configured to generate a driving current signal.
  • the data writing transistor T4 includes: a gate, a first electrode, and a second electrode, the gate of the data writing transistor T4 is electrically connected to the first scanning signal line Gate1, the first electrode of the data writing transistor T4 is electrically connected to the data signal line Data, and the second electrode of the data writing transistor T4 is electrically connected to the second node N2.
  • the data writing transistor T4 is configured to: in response to the scanning signal received at the first scanning signal line Gate1, transmit the data signal received at the data signal line Data to the driving transistor T3.
  • the first light emission control transistor T5 includes: a gate, a first electrode, and a second electrode.
  • the gate of the first light emission control transistor T5 is electrically connected to the light emission control signal line EM
  • the first electrode of the first light emission control transistor T5 is electrically connected to the power signal line ELVDD
  • the second electrode of the first light emission control transistor T5 is electrically connected to the second node N2.
  • the first light emission control transistor T5 is configured to: in response to the light emission control signal received at the light emission control signal line EM, transmit the power signal received at the power signal line ELVDD to the driving transistor T3.
  • the second light emission control transistor T6 includes: a gate, a first electrode, and a second electrode.
  • the gate of the second light emission control transistor T6 is electrically connected to the light emission control signal line EM
  • the first electrode of the second light emission control transistor T6 is electrically connected to the third node N3
  • the second electrode of the second light emission control transistor T6 is electrically connected to the fourth node N4.
  • the second light emission control transistor T6 is configured to: in response to the light emission control signal received at the light emission control signal line EM, transmit the driving current signal to the light emitting device L, so as to drive the light emitting device L to emit light.
  • the second reset transistor T7 includes: a gate, a first electrode, and a second electrode, the gate of the second reset transistor T7 is electrically connected to the second reset signal line Reset2, the first electrode of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and the second electrode of the second reset transistor T7 is electrically connected to the fourth node N4.
  • the second reset transistor T7 is configured to: in response to the reset signal received at the second reset signal line Reset2, transmit the initialization signal received at the second initialization signal line Vinit2 to the light emitting device L to reset the light emitting device L.
  • the anode of the light emitting device L is electrically connected to the fourth node N4, and the cathode of the light emitting device L is electrically connected to the reference voltage line ELVSS.
  • the first electrode of the transistor of the present disclosure is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure can be structurally indistinguishable.
  • the first electrode of the transistor is The first electrode is the source, and the second electrode is the drain; illustratively, when the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.
  • the nodes do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the junction points of related electrical connections in the circuit diagram being equivalent.
  • the plurality of pixel driving circuit groups 12 are arranged in a plurality of rows along the second direction Y, and the first reset signal line Reset1 connected to the gate of the first reset transistor T1 of the current row may be the same reset signal line Reset as the second reset signal line Reset2 connected to the gate of the second reset transistor T7 of the previous row (as shown in FIG. 4 ). That is, when a reset signal line Reset is turned on, the reset signal line Reset transmits a reset signal to the first reset transistor T1 of the current row and the second reset transistor T7 of the previous row simultaneously.
  • the pixel driving circuit 10 further includes: a capacitor Cst, the capacitor Cst includes: a first plate Cst1 and a second plate Cst2, the first plate Cst1 of the capacitor Cst is electrically connected to the first node N1, and the second plate Cst2 of the capacitor Cst is electrically connected to the power signal line ELVDD.
  • the pixel driving circuit 10 adopts an LTPO (Low Temperature Polycrystalline Oxide) circuit, that is, a pixel driving circuit 10 includes both a low-temperature polycrystalline silicon (Low Temperature Poly-Silicon, abbreviated as LTPS) thin film transistor and an oxide (Oxide) thin film transistor.
  • LTPS Low Temperature Poly-Silicon
  • Oxide oxide
  • the low-temperature polycrystalline silicon thin film transistor has a strong load capacity
  • the oxide (Oxide) thin film transistor has a small off-state current and a stronger charge retention ability than the low-temperature polycrystalline silicon thin film transistor. In this way, the pixel driving circuit 10 can achieve higher charge mobility and better stability.
  • the compensation transistor T2 can be an oxide thin film transistor, and it is an N-type transistor, that is, it is turned on at a high level.
  • the first reset transistor T1, the drive transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6 and the second reset transistor T7 are all P-type transistors of low temperature polysilicon thin film transistors (Low Temperature Poly-silicon Thin Film Transistor), and are turned on at a low level.
  • the setting of using an oxide thin film transistor for the compensation transistor T2 can effectively prevent the leakage of the first node N1.
  • the first semiconductor layer 13, the first conductive layer 15, and the second conductive layer 17 form a first reset transistor T1, a drive transistor T3, a data write transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7, and a capacitor Cst in the LTPO circuit.
  • the second semiconductor layer 61 and the third conductive layer 62 form a compensation transistor T2.
  • the above examples of the first reset transistor T1 , the compensation transistor T2 , the drive transistor T3 , the data writing transistor T4 , the first light emission control transistor T5 , the second light emission control transistor T6 and the second reset transistor T7 do not constitute a limitation on the transistor type.
  • the timing diagram of the pixel driving circuit 10 is shown in Fig. 3B.
  • the timing diagram includes three phases, an initialization phase t1, a data writing and Vth compensation phase t2, and an emission phase t3.
  • Initialization stage t1 the first reset signal line Reset1 is at a low level, the light emitting control signal line EM and the second scanning signal line
  • the signal line Gate2 is at a high level, the first reset transistor T1 and the compensation transistor T2 are turned on, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off, and the voltage of the first initialization signal line Vinit1 is written into the N1 power saving through the first reset transistor T1 and the compensation transistor T2 to initialize it.
  • the first reset signal line Reset1 is at a high level, and the signal transmitted by the first initialization signal line Vinit1 is turned off.
  • the first scanning signal line Gate1 is at a low level, and the data signal at the data signal line Data is written into the N1 node through the data writing transistor T4, the driving transistor T3 and the compensation transistor T2, and the Vth of the driving transistor T3 is compensated.
  • the second scanning signal line Gate2 is at a low level
  • the light emission control signal line EM is at a low level
  • the compensation transistor T2 is turned off
  • the first light emission control transistor T5 and the second light emission control transistor T6 are turned on to enter the light emission phase.
  • the light emitting device stack 2 is formed with a plurality of light emitting devices L, and the plurality of light emitting devices L are arranged on a plurality of pixel driving circuits 10 of the array substrate 1, and the array substrate 1 is used to drive the plurality of light emitting devices L to emit light.
  • the light emitting device stack 2 includes: an anode layer 202, a pixel defining layer 201, a light emitting function layer 203, and a cathode layer 204 stacked sequentially on a side of the pixel circuit stack 30 away from the substrate 101.
  • the mobile phone 1000 also includes components such as a camera, various sensors, and a speaker.
  • the photosensitive component is, for example, a camera, and accordingly, this technology is the under-screen camera technology; the photosensitive component is, for example, a fingerprint sensor, and accordingly, this technology is the under-screen fingerprint recognition technology.
  • the under-screen camera technology and the under-screen fingerprint recognition technology there are certain requirements for the light transmittance of the display screen.
  • the setting of each film layer used to form the pixel driving circuit 10 affects the light transmittance of the screen, thereby affecting the shooting effect and fingerprint recognition effect of the display screen.
  • an array substrate 1 which includes: a substrate 101 and a plurality of pixel driving circuit groups 12 disposed on the substrate 101, wherein the plurality of pixel driving circuit groups 12 are arranged in an array along a first direction X and a second direction Y.
  • Each of the plurality of pixel driving circuit groups 12 includes: two pixel driving circuits 10 disposed along the first direction X.
  • the first direction X and the second direction Y intersect, and the first direction X and the second direction Y are parallel to the upper surface of the substrate 101.
  • the first direction X and the second direction Y are perpendicular to each other
  • the first direction X is the row direction in which the plurality of pixel driving circuit groups 12 are arranged
  • the second direction Y is the column direction in which the plurality of pixel driving circuit groups 12 are arranged.
  • two pixel driving circuits 10 are set as a pixel driving circuit group 12, and two data signal lines Data in one pixel driving circuit group 12 can be arranged adjacent to each other in the first direction X, and two power signal lines ELVDD of the pixel driving circuit group 12 are arranged on both sides of the two data signal lines Data, that is, in one pixel driving circuit group 12, the power signal line ELVDD, the data signal line Data, the data signal line Data and the power signal line ELVDD are arranged in sequence along the first direction X. Based on this arrangement, in two adjacent pixel driving circuit groups 12, two adjacent power signal lines ELVDD can be connected to reduce the voltage of the power signal line ELVDD. drop.
  • the array substrate 1 provided in the embodiment of the present disclosure further includes: a first conductive layer 15 disposed on one side of the substrate 101 (as shown in FIG. 2 ), and a second conductive layer 17 disposed on a side of the first conductive layer 15 away from the substrate 101.
  • the array substrate 1 further includes: a power signal line ELVDD (as shown in FIG. 12 ).
  • the pixel driving circuit 10 includes: a driving transistor T3 and a capacitor Cst, the capacitor Cst includes: a first plate Cst1 and a second plate Cst2, the first plate Cst1 is connected to the gate of the driving transistor T3, and the second plate Cst2 is connected to the power signal line ELVDD.
  • the first plate Cst1 is located on the first conductive layer 15, and the second plate Cst2 is located on the second conductive layer 17.
  • the first electrode plate Cst1 and the gate of the driving transistor T3 are an integrated structure.
  • the second plate Cst2 of the capacitor Cst of each pixel driving circuit 10 needs to be connected to the power signal line ELVDD, multiple second plates Cst2 of multiple capacitors Cst can be connected to reduce the voltage drop of the power signal provided by the power signal line ELVDD during transmission.
  • a first connection pattern M1 is connected between the second plates Cst2 of two pixel driving circuits 10 in the pixel driving circuit group 12, and the first connection pattern M1 is located on the second conductive layer 17. That is, two adjacent second plates Cst are connected by the first connection pattern M1.
  • the dimension d1 of the first connection pattern M1 in the second direction Y is smaller than the dimension d2 of the second electrode plate Cst2 in the second direction Y.
  • the dimension d1 of the first connection pattern M1 in the second direction Y refers to the maximum dimension of the first connection pattern M1 in the second direction Y
  • the dimension d2 of the second electrode plate Cst2 in the second direction Y refers to the maximum dimension of the second electrode plate Cst2 in the second direction Y.
  • the first connection pattern M1 is connected to the second electrode plate Cst2 of the two pixel driving circuits 10 in the pixel driving circuit group 12.
  • the first connection pattern M1 and the second electrode plate Cst2 of the two pixel driving circuits 10 in the pixel driving circuit group 12 are an integrated structure, which can simplify the structure and preparation process of the array substrate 1.
  • the first connection pattern M1 connects the second plates Cst2 of two pixel driving circuits 10, and the two pixel driving circuits 10 can receive the same power signal. Since the first connection pattern M1 plays the role of transmitting the power signal in a pixel driving circuit group 12, the setting of the size d1 of the first connection pattern M1 in the second direction Y being smaller than the size d2 of the second plate Cst2 in the second direction Y does not affect the transmission of the power signal. Therefore, the size d1 of the first connection pattern M1 in the second direction Y can be set to be smaller than the size d2 of the second plate Cst2 in the second direction Y. This setting can increase the light transmittance of the area S1 between the two second plates Cst2 in a pixel driving circuit group 12.
  • the embodiment of the present disclosure increases the transmittance of the area S1 between two second plates Cst2 in a pixel driving circuit group 12 by setting the dimension d1 of the first connection pattern M1 in the second direction Y to be smaller than the dimension d2 of the second plate Cst2 in the second direction Y, thereby achieving the purpose of improving the light transmittance of the array substrate 1.
  • a ratio of a dimension d1 of the first connection pattern M1 in the second direction Y to a dimension d2 of the second electrode plate Cst2 in the second direction Y is in a range of 10% to 50%.
  • the ratio of the dimension d1 of the first connection pattern M1 in the second direction Y to the dimension d2 of the second electrode plate Cst2 in the second direction Y is 10%, 15%, 25%, 30%, 40% or 50%, etc., which is not limited here.
  • the ratio of the dimension d1 of the first connection pattern M1 in the second direction Y to the dimension d2 of the second electrode plate Cst2 in the second direction Y is set to be in the range of 10% to 50%.
  • the first connection pattern M1 can not only connect the second electrodes Cst2 of two pixel driving circuits 10 in a pixel driving circuit group 12 to transmit power signals, but also improve the light transmittance of the array substrate 1.
  • a dimension d1 of the first connection pattern M1 in the second direction Y ranges from 2.0 ⁇ m to 5.5 ⁇ m.
  • a dimension d1 of the first connection pattern M1 in the second direction Y is 2.0 ⁇ m, 3.5 ⁇ m, 4.0 ⁇ m, 5.0 ⁇ m or 5.5 ⁇ m, etc., which is not limited here.
  • the area of the second conductive layer 17 is reduced by about 26.9 ⁇ m 2.
  • the arrangement of the structure of the region S1 increases the light transmittance of the array substrate 1 by about 1.5%.
  • the array substrate 1 includes: a shielding layer 11 disposed between the base 101 and the first conductive layer 15. As shown in Figures 6 and 7A to 7E, the shielding layer 11 includes a plurality of shielding patterns 111.
  • the shielding layer 11 is provided to prevent the light on the side of the substrate 101 away from the shielding layer 11 from affecting the pixel driving circuit 10.
  • the pixel driving circuit includes shielding patterns 111, each shielding pattern 111 overlaps with the first plate Cst1 and the second plate Cst2 of the capacitor Cst, and the first plate Cst1 and the gate of the driving transistor T3 are an integral structure, that is, the shielding pattern 111 overlaps with the gate of the driving transistor T3, and the shielding pattern 111 can prevent the light on the side of the substrate 101 away from the shielding pattern 111 from affecting the pixel driving circuit 10 (for example, the driving transistor T3).
  • the shielding pattern 111 of each pixel driving circuit 10 is connected in the first direction X and the second direction Y to form a network structure, and the shielding pattern 111 is electrically connected to the reference voltage line ELVSS.
  • the cathode layer 204 is used to transmit a reference voltage signal. Electrically connecting the shielding pattern 111 to the reference voltage line ELVSS means connecting the shielding pattern 111 to the cathode layer 204, which can reduce the resistance of the cathode layer 204, thereby reducing the voltage drop of the reference voltage line ELVSS.
  • the shielding patterns 111 of the circuit 10 are connected with the second connection pattern M2, and the second connection pattern M2 is located on the shielding layer 11.
  • the second connection pattern M2 and the shielding pattern 111 are an integrated structure, which can simplify the structure and preparation process of the array substrate 1.
  • the array substrate 1 further includes: a second semiconductor layer 61, which is located on a side of the second conductive layer 17 away from the substrate 101.
  • the orthographic projection of the second connection pattern M2 on the substrate 101 overlaps with the orthographic projection of the second semiconductor layer 61 on the substrate 101.
  • the second semiconductor layer 61 includes an active layer pattern of the compensation transistor T2.
  • the pixel driving circuit group 12 located on the left is called the first pixel driving circuit group 121
  • the pixel driving circuit group 12 located on the right is called the second pixel driving circuit group 122
  • the portion of the shielding layer 11 connected between the first pixel driving circuit group 121 and the second pixel driving circuit group 122 is a second connection pattern M2, which is used to transmit a fixed voltage signal, for example, the fixed voltage signal is a reference voltage signal.
  • the orthographic projection of the second connection pattern M2 on the substrate 101 overlaps with the orthographic projection of the second semiconductor layer 61 on the substrate 101, that is, the second connection pattern M2 is arranged between the second semiconductor layer 61 and the substrate 101, so that the light blocking area of the second semiconductor layer 61 and the light blocking area of the second connection pattern M2 partially overlap, thereby reducing the light blocking of the second connection pattern M2 and improving the light transmittance of the array substrate 1.
  • an overlapping area S2 of an orthographic projection of the second connection pattern M2 on the substrate 101 and an orthographic projection of the second semiconductor layer 61 on the substrate 101 is 20 ⁇ m 2 to 30 ⁇ m 2 .
  • the overlapping area of the orthographic projection of the second connection pattern M2 on the substrate 101 and the orthographic projection of the second semiconductor layer 61 on the substrate 101 is represented as area S21.
  • an overlapping area S2 of an orthographic projection of the second connection pattern M2 on the substrate 101 and an orthographic projection of the second semiconductor layer 61 on the substrate 101 is 20 ⁇ m 2 , 21 ⁇ m 2 , 23 ⁇ m 2 , 25 ⁇ m 2 , 27 ⁇ m 2 , 29 ⁇ m 2 or 30 ⁇ m 2 , etc., which is not limited here.
  • the light transmittance of the array substrate 1 is increased by about 0.57%.
  • the shielding pattern 111 in the first direction X and the second direction Y
  • the light transmittance of the array substrate 1 can be improved.
  • a plurality of shielding patterns 111 are connected in the first direction X and the second direction Y to form a network structure.
  • the connection pattern (referred to as a transverse connection pattern) of the adjacent shielding patterns 111 in the first direction X includes one or more of the second connection pattern M21, M22, M23 and the fourth connection pattern F1.
  • the transverse connection patterns are all drawn in one figure in FIG7A .
  • the connection pattern of the adjacent shielding patterns 111 in the second direction is referred to as a longitudinal connection pattern F4.
  • the longitudinal connection pattern F4 is in the shape of a strip and extends in the second direction as a whole, and is used to connect the two shielding patterns 111 located at both ends thereof.
  • the lateral connection pattern includes a first second connection pattern M21, and the orthographic projection of the first second connection pattern M21 on the substrate 101 overlaps with the orthographic projection of the second semiconductor layer 61 on the substrate 101. Specifically, the orthographic projection of the first second connection pattern M21 on the substrate 101 overlaps with the end of the active layer of the compensation transistor T2.
  • the transverse connection pattern includes a second second connection pattern M22, and the orthographic projection of the second second connection pattern M22 on the substrate 101 overlaps with the orthographic projection of the second semiconductor layer 61 on the substrate 101.
  • the orthographic projection of the second second connection pattern M22 on the substrate 101 overlaps with the middle of the active layer of the compensation transistor T2.
  • the orthographic projection of the second second connection pattern M22 on the substrate 101 overlaps with the orthographic projection of the second scanning signal line Gate2 on the substrate 101.
  • the second scanning signal line Gate2 includes a first sub-scanning signal line 2G2 located in the second conductive layer 17 and a second sub-scanning signal line 3G2 located in the third conductive layer 62.
  • the first sub-scanning signal line 2G2 and the second sub-scanning signal line 3G2 are connected to form the second scanning signal line Gate2.
  • the transverse connection pattern includes a third second connection pattern M23, and the orthographic projection of the third second connection pattern M23 on the substrate 101 overlaps with the orthographic projection of the second semiconductor layer 61 on the substrate 101.
  • the orthographic projection of the third second connection pattern M23 on the substrate 101 overlaps with the other end of the active layer of the compensation transistor T2.
  • the orthographic projection of the third second connection pattern M23 on the substrate 101 also overlaps with the orthographic projection of the first scan signal line Gate1 on the substrate 101.
  • the first scan signal line Gate1 is located in the first conductive layer 15.
  • the lateral connection pattern includes a fourth connection pattern F1, and the orthographic projection of the fourth connection pattern F1 on the substrate 101 overlaps with the orthographic projection of the first semiconductor layer 13 on the substrate 101 and the orthographic projection of the light emitting control signal line EM on the substrate 101.
  • the light emitting control signal line EM is located in the first conductive layer 15.
  • the longitudinal connection pattern F4 overlaps with the first semiconductor layer 13 .
  • a portion of the longitudinal connection pattern F4 overlaps with the active layer of the second reset transistor T7 in the first semiconductor layer 13 .
  • the horizontal connection pattern and the vertical connection pattern in the shielding layer 11 are connected to the horizontal connection pattern in the other film layers.
  • the patterns overlap, so that the transverse connection patterns and the longitudinal connection patterns do not need to occupy additional space, which can improve the light transmittance of the array substrate 1.
  • a third gate dielectric layer 106 and a third insulating layer 107 are disposed on a side of the second semiconductor layer 61 away from the substrate 101 .
  • the third gate dielectric layer 106 and the third insulating layer 107 include at least one first via hole K1 .
  • the function of the first via K1 is to realize the connection between the compensation transistor T2 and the first reset transistor T1 and the driving transistor T3.
  • the array substrate 1 has a fourth conductive layer 19, and the fourth conductive layer 19 includes a first pattern H1 and a second pattern H2.
  • two first vias K1 are included, which are represented as via No. 1 K11 and via No. 2 K12.
  • one end of the first pattern H1 is connected to the second pole T12 of the first reset transistor T1
  • the other end of the first pattern H1 is connected to the second pole T32 of the driving transistor T3 and the second pole T22 of the compensation transistor T2 through the via No. 2 K12
  • one end of the second pattern H2 is connected to the first pole T21 of the compensation transistor T2 through the via No. 1 K11
  • the other end of the second pattern H2 is connected to the gate T33 of the driving transistor T3.
  • At least one first via hole penetrates the third gate dielectric layer 106 (as shown in FIG. 2 ) and the third insulating layer 107 (as shown in FIG. 2 ) to the second semiconductor layer 61 , and an orthographic projection of at least one first via hole K1 on the substrate 101 overlaps with an orthographic projection of the second connection pattern M2 on the substrate 101 .
  • a size d3 of the first via hole K1 is greater than 2.5 ⁇ m and less than or equal to 3 ⁇ m.
  • the third gate dielectric layer 106 and the third insulating layer 107 are not shown in FIG. 7B and FIG. 8 .
  • the arrangement of the third gate dielectric layer 106 and the third insulating layer 107 can refer to FIG. 2 .
  • the first via hole K1 is square, and the size d3 of the first via hole K1 may be the width of the first via hole K1.
  • the first via hole K1 is circular, and the size d3 of the first via hole K1 may be the diameter of the first via hole K1.
  • the size d3 of the first via hole K1 is 2.6 ⁇ m, 2.7 ⁇ m, 2.8 ⁇ m, 2.9 ⁇ m, or 3 ⁇ m, etc., which is not limited here.
  • the surface of the area where the third insulating layer 107 covers the second semiconductor layer 61 is relatively high, that is, the surface of this area is relatively far away from the substrate 101, and when making a via hole penetrating the third gate dielectric layer 106 and the third insulating layer 107, the first via hole K1 formed in this area can be made relatively large.
  • the via hole penetrating the third insulating layer 107 also includes a plurality of second via holes K2, and the orthographic projection of the second via hole K2 on the substrate 101 does not overlap with the orthographic projection of the second semiconductor layer 61 on the substrate 101, and the size of the second via hole K2 is generally less than or equal to 2.5 ⁇ m.
  • the first via hole K1 (the first via hole K11 and the second via hole K12) is relatively large in size, which can increase The contact area of the two conductive patterns connected by the first via hole K1 is increased, thereby reducing the contact resistance.
  • the array substrate 1 includes: a shielding layer 11 disposed between the base 101 and the first conductive layer 15 .
  • the provision of the shielding layer 11 can prevent the light on the side of the substrate 101 away from the shielding layer 11 from affecting the pixel driving circuit 10 and can reduce the voltage drop of the signal line. Please refer to the above content for details and will not be repeated here.
  • each pixel driving circuit 10 is connected in the first direction X and the second direction Y to form a network structure.
  • the shielding patterns 111 of each pixel driving circuit 10 are connected in the first direction X and the second direction Y to form a network structure.
  • two pixel driving circuits 10 are symmetrically arranged along the second direction Y.
  • the transistors including: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a second reset transistor T7 of the two pixel driving circuits 10 on both sides of the center line L1 are arranged symmetrically relative to the center line L1.
  • the array substrate 1 includes a fifth conductive layer 21, and the fifth conductive layer 21 is provided with a power signal line ELVDD and a data signal line Data. Between two adjacent pixel driving circuit groups 12 in the first direction X, the power signal line ELVDD of the two adjacent pixel driving circuits 10 can be shared.
  • the shielding patterns 111 of the two adjacent pixel driving circuits 10 are connected, and this pattern is called the second connection pattern M2.
  • the shielding patterns 111 between the two pixel driving circuits 10 are connected, and this pattern is called the third connection pattern M3.
  • a third connection pattern M3 is connected between the shielding patterns 111 of two pixel driving circuits 10 , and the third connection pattern M3 is located on the shielding layer 11 .
  • the orthographic projection of the second conductive layer 17 on the substrate 101 covers the orthographic projection of the third connection pattern M3 on the substrate 101 .
  • the third connection pattern M3 and the shielding pattern 111 are an integrated structure, which can simplify the structure and manufacturing process of the array substrate 1 .
  • the third connection pattern M3 is used to transmit a fixed voltage signal, for example, the fixed voltage signal is a reference voltage signal.
  • the orthographic projection of the first connection pattern M1 on the substrate 101 overlaps with the orthographic projection of the third connection pattern M3 on the substrate 101 by more than 70%.
  • the first connection pattern M1 connects the second plates Cst2 of the two pixel driving circuits 10, and a shielding pattern 111 of the shielding layer 11 is provided on the side of the second plate Cst2 close to the substrate 101.
  • the shielding pattern 111 can be connected to a fixed voltage signal, such as a reference voltage signal. The influence of the surrounding stray charges on the driving transistor T3 can be shielded.
  • the third connection pattern M3 is used to connect the shielding patterns 111 of the two pixel driving circuits 10, so that the positive projection of the first connection pattern M1 connecting the two second plates Cst2 on the substrate 101 can be set, and the overlapping area with the positive projection of the third connection pattern M3 on the substrate 101 is greater than 70%.
  • the overlapping area of the orthographic projection of the first connection pattern M1 on the substrate 101 and the orthographic projection of the third connection pattern M3 on the substrate 101 is 75%, 80%, 90% or 100%, etc., which is not limited here.
  • an overlapping area S3 of an orthographic projection of the first connection pattern M1 on the substrate 101 and an orthographic projection of the third connection pattern M3 on the substrate 101 is 4 ⁇ m 2 -10 ⁇ m 2 .
  • an overlapping area S3 of an orthographic projection of the first connection pattern M1 on the substrate 101 and an orthographic projection of the third connection pattern M3 on the substrate 101 is 4 ⁇ m 2 , 5 ⁇ m 2 , 6 ⁇ m 2 , 7 ⁇ m 2 , 8 ⁇ m 2 , 9 ⁇ m 2 or 10 ⁇ m 2 , etc., which is not limited here.
  • the above embodiment of the present disclosure reduces the influence of the third connection pattern M3 on the light transmittance by setting the orthographic projection of the first connection pattern M1 on the substrate 101 to cover the orthographic projection of the third connection pattern M3 on the substrate 101.
  • this setting increases the light transmittance of the array substrate 1 by about 0.19%.
  • the array substrate 1 includes a fourth conductive layer 19 disposed on a side of the first conductive layer 15 away from the substrate 101, and a first initialization signal line Vinit1 and a second initialization signal line Vinit2 located on the fourth conductive layer 19.
  • the first initialization signal line Vinit1 and the second initialization signal line Vinit2 are arranged on the fourth conductive layer 19, and the orthographic projections of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate 101 are arranged to overlap with the orthographic projections of the first conductive layer 15 on the substrate 101, thereby reducing the influence of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the light transmittance.
  • an overlapping area S41 between an orthographic projection of the first initialization signal line Vinit1 on the substrate 101 and an orthographic projection of the first conductive layer 15 on the substrate 101 is greater than an overlapping area S42 between an orthographic projection of the second initialization signal line Vinit2 on the substrate 101 and an orthographic projection of the first conductive layer 15 on the substrate 101.
  • an overlapping area S4 of an orthographic projection of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate 101 and an orthographic projection of the first conductive layer 15 on the substrate 101 ranges from 15 ⁇ m 2 to 20 ⁇ m 2 .
  • the overlap area of the orthographic projection of the first initialization signal line Vinit1 on the substrate 101 and the orthographic projection of the first conductive layer 15 on the substrate 101 is represented as area S41
  • the overlap area of the orthographic projection of the second initialization signal line Vinit1 on the substrate 101 is represented as area S41
  • an overlapping area S4 of an orthographic projection of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate 101 and an orthographic projection of the first conductive layer 15 on the substrate 101 is 15 ⁇ m 2 , 16 ⁇ m 2 , 17 ⁇ m 2 , 18 ⁇ m 2 , 19 ⁇ m 2 or 20 ⁇ m 2 , etc. , which is not limited here.
  • a ratio of an overlapping area S41 of an orthographic projection of the first initialization signal line Vinit1 on the substrate 101 and an orthographic projection of the first conductive layer 15 on the substrate 101 to an overlapping area S42 of an orthographic projection of the second initialization signal line Vinit2 on the substrate 101 and an orthographic projection of the first conductive layer 15 on the substrate 101 is greater than 1.5.
  • an overlap area S41 of an orthographic projection of the first initialization signal line Vinit1 on the substrate 101 and an overlap area S42 of an orthographic projection of the first conductive layer 15 on the substrate 101 ranges from 12 ⁇ m 2 to 19 ⁇ m 2 .
  • An overlap area S42 of an orthographic projection of the second initialization signal line Vinit2 on the substrate 101 and an overlap area S42 of an orthographic projection of the first conductive layer 15 on the substrate 101 ranges from 1 ⁇ m 2 to 3 ⁇ m 2 .
  • an overlapping area S41 of an orthographic projection of the first initialization signal line Vinit1 on the substrate 101 and an orthographic projection of the first conductive layer 15 on the substrate 101 is 12 ⁇ m 2 , 13 ⁇ m 2 , 14 ⁇ m 2 , 15 ⁇ m 2 , 16 ⁇ m 2 , 17 ⁇ m 2 or 19 ⁇ m 2 , etc. , which is not limited here.
  • an overlapping area S42 of an orthographic projection of the second initialization signal line Vinit2 on the substrate 101 and an orthographic projection of the first conductive layer 15 on the substrate 101 is 1 ⁇ m 2 , 2 ⁇ m 2 or 3 ⁇ m 2 , etc., which is not limited here.
  • the orthographic projections of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate 101 are overlapped with the orthographic projections of the first conductive layer 15 on the substrate 101, thereby reducing the influence of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the light transmittance.
  • this arrangement increases the light transmittance of the array substrate 1 by about 0.94%.
  • the array substrate 1 includes a reset signal line Reset, the reset signal line Reset is located in the first conductive layer 15 , and the first initialization signal line Vinit1 , the second initialization signal line Vinit2 and the reset signal line Reset overlap in their orthographic projections on the substrate 101 .
  • the reset signal line Reset since the reset signal line Reset is set in the first conductive layer 15, the first initialization signal line Vinit1 and the second initialization signal line Vinit2 are located in the fourth conductive layer 19, compared with setting the first initialization signal line Vinit1 and the second initialization signal line Vinit2 in the second conductive layer 17, the reset signal line Reset and the first initialization signal line Vinit1, the second initialization signal line Vinit2 are farther apart in the direction perpendicular to the plane where the substrate 101 is located.
  • the reset signal line Reset overlaps with the first initialization signal line Vinit1, the second initialization signal line Vinit2 in their orthographic projections on the substrate 101, the problem of electrostatic breakdown caused by the overlapping of the signal lines can be effectively prevented, and the light transmittance of the array substrate 1 can be improved.
  • the first semiconductor layer 13 includes an active layer pattern of a first reset transistor T1, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a second reset transistor T7, wherein the active layer pattern of each transistor includes a transistor source and a drain, and a channel region therebetween.
  • the second semiconductor layer includes an active layer pattern of a compensation transistor T2.
  • the first conductive layer 15 includes a first reset transistor T1, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a gate of a second reset transistor T7, and a first plate Cst1 of a capacitor Cst.
  • the gates of the above transistors overlap with the channel region to form the above transistors.
  • the first conductive layer also includes a first scanning signal line Gate1, a light emission control signal line EM, and a reset signal line Reset.
  • the second conductive layer 17 includes: a first sub-scanning signal line 2G2, and the third conductive layer 62 includes: a second sub-scanning signal line 3G2.
  • the first sub-scanning signal line 2G2 and the second sub-scanning signal line 3G2 are connected to form a second scanning signal line Gate2.
  • the fourth conductive layer 19 includes a first initialization signal line Vinit1 and a second initialization signal line Vinit2 .
  • the fifth conductive layer 21 includes a data signal line Data and a power signal line ELVDD.
  • connection relationship between the signal line and the transistor can be referred to the above introduction and will not be repeated here.
  • the array substrate 1 further includes: a shielding layer 11 disposed between the substrate 101 and the first conductive layer 15. Along the first direction X, between at least two adjacent pixel driving circuit groups 12, and between shielding patterns 111 of two adjacent pixel driving circuits 10, a second connection pattern M2 is connected, and the second connection pattern M2 is located on the shielding layer 11.
  • the array substrate 1 further includes: a light emitting control signal line EM.
  • the pixel driving circuit 10 further includes: a second light emitting control transistor T6 , a gate of which is connected to the light emitting control signal line EM, and a first electrode of which is connected to the second electrode T32 of the driving transistor T3 .
  • the gate of the second light emitting control transistor T6 is an integrated structure with the light emitting control signal line EM.
  • the area between two adjacent pixel driving circuit groups 12, between the first electrodes of two adjacent second light emission control transistors T6 and between the second connection pattern M2 and the light emission control signal line EM is a first light transmission area W1, and the area of the first light transmission area W1 is greater than 10 ⁇ m 2 .
  • the area of the first light-transmitting region W1 is 15 ⁇ m 2 , 20 ⁇ m 2 , 25 ⁇ m 2 or 30 ⁇ m 2 , etc., which is not limited here.
  • conductive film layers such as the shielding layer 11, the first semiconductor layer 13, the first conductive layer 15, the second conductive layer 17, the second semiconductor layer 61, the third conductive layer 62, the fourth conductive layer 19 and the fifth conductive layer 21 are all opaque film layers.
  • the first conductive layer 15, the second conductive layer 17, the third conductive layer 62, the fourth conductive layer 19 and the fifth conductive layer 21 are usually made of opaque metal layers.
  • the light-transmitting area can be the area between the anode and the substrate, excluding the conductive layer pattern and the semiconductor layer pattern. If the conductive layer is made of a transparent conductive layer, such as indium tin oxide ITO, this area can also be considered as a light-transmitting area.
  • the array substrate 1 further includes: a first initialization signal line Vinit1 and a light emission control signal line EM.
  • the pixel driving circuit 10 further includes: a first reset transistor T1, a second light emission control transistor T6, and a second reset transistor T7, wherein a first electrode of the first reset transistor T1 is connected to the first initialization signal line Vinit1, a second electrode T12 of the first reset transistor T1 is connected to a first electrode of the second light emission control transistor T6, and a second electrode of the second light emission control transistor T6 is connected to a second electrode of the second reset transistor T7.
  • a first electrode of the second light emission control transistor T6 is connected to a second electrode T32 of the driving transistor T3, and a gate of the second light emission control transistor T6 is connected to the light emission control signal line EM.
  • the area between two adjacent pixel driving circuit groups 12, between the second electrodes of two adjacent second emission control transistors T6 and between the first initialization signal line Vinit1 and the emission control signal line EM is a second light-transmitting area W2, and the area of the second light-transmitting area W2 is greater than 10 ⁇ m 2 .
  • the area of the second light-transmitting region W2 is 15 ⁇ m 2 , 20 ⁇ m 2 , 25 ⁇ m 2 or 30 ⁇ m 2 , etc., which is not limited here.
  • the light transmittance of the array substrate 1 can be improved.
  • the array substrate 1 includes: a substrate 101, and a plurality of pixel driving circuit groups 12 arranged on the substrate 101, wherein the plurality of pixel driving circuit groups 12 are arranged in an array along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect; wherein each pixel driving circuit group 10 includes: two pixel driving circuits 10 arranged along the first direction X.
  • the array substrate 1 also includes: a first conductive layer 15 arranged on the substrate 101, a second conductive layer 17 arranged on the side of the first conductive layer 15 away from the substrate 101, and a fifth conductive layer 21; illustratively, the fifth conductive layer 21 is provided with a power signal line ELVDD and a data signal line Data.
  • the pixel driving circuit 10 includes: a driving transistor T3 and a capacitor Cst, and the capacitor Cst includes: a first plate Cst1 and a second plate Cst2, and the first plate Cst1 is connected to the gate T33 of the driving transistor T3.
  • the first plate Cst1 is located in the first conductive layer 15, and the second plate Cst2 is located in the second conductive layer 17; as shown in FIG. 12 , the second plate Cst2 is connected to the fifth conductive layer 21; illustratively, the second plate Cst2 of the capacitor Cst is electrically connected to the power signal line ELVDD in the fifth conductive layer 21.
  • a first connection pattern M1 is connected between the second plates Cst2 of two pixel driving circuits 10 in the pixel driving circuit group 12, and the first connection pattern M1 is located in the second conductive layer 17.
  • the size d1 of the first connection pattern M1 in the second direction is smaller than the size d2 of the second plate Cst2 in the second direction Y.
  • the dimension d1 of the first connection pattern M1 in the second direction Y refers to the dimension d2 of the first connection pattern M1.
  • the maximum dimension in the second direction Y, the dimension d2 of the second electrode plate Cst2 in the second direction Y refers to the maximum dimension of the second electrode plate Cst2 in the second direction Y.
  • the first connection pattern M1 is connected to the second electrode plate Cst2 of the two pixel driving circuits 10 in the pixel driving circuit group 12.
  • the first connection pattern M1 and the second electrode plate Cst2 of the two pixel driving circuits 10 in the pixel driving circuit group 12 are an integrated structure, which can simplify the structure and preparation process of the array substrate 1.
  • the first connection pattern M1 connects the second plates Cst2 of two pixel driving circuits 10, and the two pixel driving circuits 10 can receive the same power signal. Since the first connection pattern M1 plays the role of transmitting the power signal in a pixel driving circuit group 12, the setting of the size d1 of the first connection pattern M1 in the second direction Y being smaller than the size d2 of the second plate Cst2 in the second direction Y does not affect the transmission of the power signal. Therefore, the size d1 of the first connection pattern M1 in the second direction Y can be set to be smaller than the size d2 of the second plate Cst2 in the second direction Y. This setting can increase the light transmittance of the area S1 between the two second plates Cst2 in a pixel driving circuit group 12.
  • the array substrate further includes: a second scanning signal line Gate2 .
  • the pixel driving circuit further includes: a compensation transistor T2, a first electrode of the compensation transistor T2 is connected to the gate of the driving transistor T3, a second electrode of the compensation transistor T2 is connected to the second electrode of the driving transistor T3, and a gate of the compensation transistor T2 is connected to the second scanning signal line Gate2.
  • the array substrate 1 also includes: a blocking layer 11 arranged on the substrate 101, and a first semiconductor layer 13, the first conductive layer 15, the second conductive layer 17, the second semiconductor layer 61, the third conductive layer 62 and the fourth conductive layer 19 arranged in sequence along the direction away from the blocking layer 11; the fifth conductive layer 21 is located on the side of the fourth conductive layer 19 away from the substrate 101.
  • the active layer of the driving transistor T3 is located in the first semiconductor layer 13 .
  • the second scanning signal line is at least partially located in the third conductive layer 62; wherein the second scanning signal line Gate2 includes a first sub-scanning signal line 2G2 located in the second conductive layer 17 and a second sub-scanning signal line 3G2 located in the third conductive layer 62, and the first sub-scanning signal line 2G2 and the second sub-scanning signal line 3G2 are connected to form the second scanning signal line Gate2.
  • the active layer of the compensation transistor T2 is located in the second semiconductor layer 61; the portion of the second sub-scanning signal line 3G2 passing through the active layer of the compensation transistor T2 serves as the gate of the compensation transistor T2.
  • the second electrode of the compensation transistor T2 is connected to the second electrode of the driving transistor T3 through the first pattern H1 , and the first pattern H1 is located in the fourth conductive layer 19 .
  • the first pattern H1 is connected to the second electrode T32 of the driving transistor T3 through the third via K3, and the first pattern H1 is also connected to the second electrode T32 of the compensation transistor T2 through the first via K1.
  • two first vias K1 are included, which are represented as via K11 and via K12. As shown in FIG. 10 , one end of the first pattern H1 is connected to the second electrode T12 of the first reset transistor T1 through the via, and the other end of the first pattern H1 is connected to the first electrode T12 of the compensation transistor T2 through the second via K12.
  • the second via hole K12 in the first via hole K1Z passes through the third insulating layer 107, the third gate dielectric layer 106, the second insulating layer 105, the second gate dielectric layer 104, and the first gate dielectric layer 103 from the fourth conductive layer 19 in sequence to reach the first semiconductor layer 13, so that the first pattern H1 is connected to the second electrode T32 of the driving transistor T3 through the third via hole K3.
  • the second via hole K12 in the first via hole K1Z passes through the third insulating layer 107 and the third gate dielectric layer 106 from the fourth conductive layer 19 in sequence to reach the second semiconductor layer 61, so that the first pattern H1 is also connected to the second electrode of the compensation transistor T2 through the first via hole K1.
  • the first connection pattern M1 does not overlap with the first via hole K1 and the third via hole K3 .
  • the blocking layer 11 includes a plurality of blocking patterns 111 .
  • a second connection pattern M2 is connected between the shielding patterns of two adjacent pixel driving circuits, and the second connection pattern M2 is located on the shielding layer 11; for the specific description of the second connection pattern M2, please refer to the previous description, which will not be repeated.
  • the second connection pattern M2 does not overlap with the third via K3.
  • the parasitic capacitance coupling between the second electrode of the driving transistor and the constant voltage line can be reduced during the operation of the pixel driving circuit in the data writing and Vth compensation stage t2, thereby avoiding affecting the compensation effect and further avoiding affecting the light-emitting effect of the light-emitting device.
  • the shielding pattern 111 and the second connection pattern M2 are used to receive a constant voltage signal.
  • the shielding layer 11 can be connected to a constant voltage signal, such as a power signal VDD, a reference voltage signal VSS, an initialization signal Vinit, etc. These constant voltage signals can be connected to the shielding layer 11 in the display area in the peripheral area of the array substrate.

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Abstract

一种阵列基板，包括：基底以及设置于基底上的多个像素驱动电路组，多个像素驱动电路组沿第一方向和第二方向阵列排布。其中，多个像素驱动电路组中的每个像素驱动电路组包括：沿第一方向设置的两个像素驱动电路。阵列基板还包括：第一导电层和第二导电层，像素驱动电路包括：电容器，电容器包括：第一极板和第二极板，第一极板位于第一导电层，第二极板位于第二导电层；像素驱动电路组中的两个像素驱动电路的第二极板之间连接有第一连接图案，第一连接图案位于第二导电层。其中，第一连接图案在第二方向上的尺寸，小于第二极板在第二方向上的尺寸。

Description

阵列基板、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
有机电致发光二极管(Organic Light-Emitting Diode，简称OLED)显示面板板凭借其低功耗、高色饱和度、广视角、薄厚度、能实现柔性化等优异性能，逐渐成为显示领域的主流之一。
发明内容
一方面，提供一种阵列基板，阵列基板包括：基底，以及设置于所述基底上的多个像素驱动电路组，所述多个像素驱动电路组沿第一方向和第二方向阵列排布，所述第一方向和所述第二方向相交。其中，所述多个像素驱动电路组中的每个像素驱动电路组包括：沿所述第一方向设置的两个像素驱动电路。
阵列基板还包括：设置于所述基底上的第一导电层，以及设置于所述第一导电层远离所述基底一侧的第二导电层以及电源信号线。所述像素驱动电路包括：驱动晶体管和电容器，所述电容器包括：第一极板和第二极板，所述第一极板与所述驱动晶体管的栅极连接，所述第二极板与所述电源信号线连接；其中，所述第一极板位于所述第一导电层，所述第二极板位于所述第二导电层；所述像素驱动电路组中的两个像素驱动电路的第二极板之间连接有第一连接图案，所述第一连接图案位于所述第二导电层。其中，所述第一连接图案在所述第二方向上的尺寸，小于所述第二极板在所述第二方向上的尺寸。
在一些实施例中，所述第一连接图案在所述第二方向上的尺寸，与所述第二极板在所述第二方向上的尺寸的比值范围为10％～50％。
在一些实施例中，所述第一连接图案在所述第二方向上的尺寸范围为2.0μm～5.5μm。
在一些实施例中，阵列基板还包括：设置于所述基底和所述第一导电层之间的遮挡层。所述遮挡层包括多个遮挡图案；沿所述第一方向，相邻的至少两个所述像素驱动电路组之间，相邻的两个像素驱动电路的遮挡图案之间连接有第二连接图案，所述第二连接图案位于所述遮挡层。阵列基板还包括：第二半导体层，所述第二半导体层位于所述第二导电层远离所述基底的一侧。所述第二连接图案在所述基底上的正投影，与所述第二半导体层在所述基底上的正投影有交叠。
在一些实施例中，在所述第二半导体层远离所述基底的一侧设置有第三栅介质层和第三绝缘层。所述第三栅介质层和所述第三绝缘层设置有：至少一个第一过孔，所述至少一个第一过孔贯穿所述第三栅介质层和所述第三绝缘层至所述第二半导体层，所述至少一个第一过孔在基底上的正投影，与所述第二连接图案在基底上的正投影有交叠。
在一些实施例中，阵列基板还包括：设置于所述基底和所述第一导电层之间的遮挡层。所述遮挡层包括多个遮挡图案；在所述像素驱动电路组中，两个像素驱动电路的遮挡图案之间连接有第三连接图案，所述第三连接图案位于所述遮挡层。所述第一连接图案在所述基底上的正投影，与所述第三连接图案在所述基底上的正投影的交叠面积大于70％。
在一些实施例中，阵列基板还包括：设置于所述第二导电层远离所述基底一侧的第四导电层，以及位于所述第四导电层的第一初始化信号线和第二初始化信号线。所述第一初始化信号线和所述第二初始化信号线在所述基底上的正投影，与所述第一导电层在所述基底上的正投影有交叠。
在一些实施例中，在每个所述像素驱动电路中，所述第一初始化信号线在所述基底上的正投影与所述第一导电层在所述基底上的正投影的交叠面积，大于所述第二初始化信号线在基底上的正投影与所述第一导电层在所述基底上的正投影的交叠面积。
在一些实施例中，在每个所述像素驱动电路中，所述第一初始化信号线在所述基底上的正投影与所述第一导电层在所述基底上的正投影的交叠面积，与所述第二初始化信号线在基底上的正投影与所述第一导电层在所述基底上的正投影的交叠面积的比值，大于1.5。
在一些实施例中，阵列基板包括：复位信号线，所述复位信号线位于所述第一导电层，所述第一初始化信号线、所述第二初始化信号线与所述复位信号线在所述基底上的正投影有交叠。
在一些实施例中，阵列基板包括：设置于所述基底一侧的所述遮挡层，并沿远离所述遮挡层的方向依次设置的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层和第四导电层。所述第一半导体层的材料包括低温多晶硅，所述第二半导体层的材料包括：氧化铟镓锌。
在一些实施例中，阵列基板还包括：设置于所述基底和所述第一导电层之间的遮挡层，所述遮挡层包括多个遮挡图案；沿所述第一方向，相邻的至少两个所述像素驱动电路组之间，相邻的两个像素驱动电路的遮挡图案之间连接有第二连接图案，所述第二连接图案位于所述遮挡层。阵列基板还包括：发光控制信号线。
所述像素驱动电路还包括：第二发光控制晶体管，所述第二发光控制晶体管的栅极与发光控制信号线连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极连接。在相邻的两个所述像素驱动电路组之间，相邻的两个所述第二发光控制晶体管的第一极之间以及第二连接图案和发光控制信号线之间的区域为第一透光区，所述第一透光区的面积大于10μm2。
在一些实施例中，阵列基板还包括：第一初始化信号线和发光控制信号线。所述像素驱动电路还包括：第一复位晶体管、第二发光控制晶体管和第二复位晶体管，所述第一复位晶体管的第一极与所述第一初始化信号线连接，所述第一复位晶体管的第二极与所述第 二发光控制晶体管的第一极连接，所述第二发光控制晶体管的第二极与所述第二复位晶体管的第二极连接。所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极连接，第二发光控制晶体管的栅极与发光控制信号线连接。
在相邻的两个所述像素驱动电路组之间，相邻的两个所述第二发光控制晶体管的第二极之间以及所述第一初始化信号线和所述发光控制信号线之间的区域为第二透光区，所述第二透光区的面积大于10μm2。
另一方面，提供一种阵列基板，包括：基底，以及设置于所述基底上的多个像素驱动电路组，所述多个像素驱动电路组沿第一方向和第二方向阵列排布，所述第一方向和所述第二方向相交；其中，每个像素驱动电路组包括：沿所述第一方向设置的两个像素驱动电路。阵列基板还包括：设置于所述基底上的第一导电层，设置于所述第一导电层远离所述基底一侧的第二导电层，以及第五导电层。所述像素驱动电路包括：驱动晶体管和电容器，所述电容器包括：第一极板和第二极板，所述第一极板与所述驱动晶体管的栅极连接，所述第二极板与所述第五导电层连接。
其中，所述第一极板位于所述第一导电层，所述第二极板位于所述第二导电层；所述像素驱动电路组中的两个像素驱动电路的第二极板之间连接有第一连接图案，所述第一连接图案位于所述第二导电层；其中，所述第一连接图案在所述第二方向上的尺寸，小于所述第二极板在所述第二方向上的尺寸。
在一些实施例中，阵列基板还包括：第二扫描信号线，所述像素驱动电路还包括：补偿晶体管，所述补偿晶体管的第一极与驱动晶体管的栅极连接，所述补偿晶体管的第二极通过第一图案与所述驱动晶体管的第二极连接，所述补偿晶体管的栅极与所述第二扫描信号线连接。
阵列基板还包括：设置于所述基底上的所述遮挡层，并沿远离所述遮挡层的方向依次设置的第一半导体层、所述第一导电层、所述第二导电层、第二半导体层、第三导电层和第四导电层。所述驱动晶体管的有源层位于第一半导体层；所述第二扫描信号线至少部分位于所述第三导电层；所述补偿晶体管的有源层位于第二半导体层；所述第一图案位于所述第四导电层。
在一些实施例中，所述第一图案通过第三过孔与所述驱动晶体管的第二极连接，所述第一导电图案还通过第一过孔与所述补偿晶体管的第二极连接，所述第一连接图案与所述第一过孔以及所述第三过孔均不交叠。
在一些实施例中，所述遮挡层包括多个遮挡图案；沿所述第一方向，相邻的至少两个所述像素驱动电路组之间，相邻的两个像素驱动电路的遮挡图案之间连接有第二连接图案，所述第二连接图案位于所述遮挡层；所述第二连接图案与所述第三过孔不交叠。
在一些实施例中，所述遮挡图案和所述第二连接图案用于接收恒压信号。
另一方面，提供一种显示面板，显示面板包括：如上任一实施例所述的阵列基板，显示面板还包括多个发光器件，设置于所述阵列基板的多个像素驱动电路上，所述阵列基板用于驱动所述多个发光器件发光。
又一方面，提供一种显示装置，显示装置包括：如上任一实施例所述的显示面板，显示装置还包括驱动芯片，用于驱动所述显示面板进行显示。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开一些实施例所提供的手机的结构图；
图2为根据本公开一些实施例所提供的显示面板的结构图；
图3A为根据本公开一些实施例所提供的像素驱动电路的等效电路图；
图3B为根据本公开一些实施例所提供的像素驱动电路的时序图；
图4为根据本公开一些实施例所提供的第一导电层、第二导电层和第二半导体层叠加后的结构图；
图5为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一导电层、第二导电层和第二半导体层叠加后的结构图；
图6为基于图5所提供的阵列基板的CC处所提供的遮挡层、第一导电层、第二导电层和第二半导体层叠加后的结构图；
图7A为根据本公开一些实施例所提供的遮挡层的结构图；
图7B为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一导电层、第二导电层、第二半导体层和第三导电层叠加后的一种结构图；
图7C为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一导电层、第二导电层、第二半导体层和第三导电层叠加后的另一种结构图；
图7D为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一导电层、第二导电层、第二半导体层和第三导电层叠加后的又一种结构图；
图7E为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一导电层、第二导电层、第二半导体层和第三导电层叠加后的又一种结构图；
图8为根据本公开一些实施例所提供的第三导电层的结构图；
图9为根据本公开一些实施例所提供的第四导电层的结构图；
图10为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一导电层、 第二导电层、第二半导体层、第三导电层和第四导电层叠加后的结构图；
图11为根据本公开一些实施例所提供的遮挡层、第一导电层和第四导电层叠加后的结构图；
图12为根据本公开一些实施例所提供的遮挡层、第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层、第四导电层和第五导电层叠加后的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。术语“耦接”例如表明两个或两个以上部件有直接物理接触或电接触。术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接 受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层的厚度和区域的面积。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
如图1所示，本公开的一些实施例提供一种显示装置。本公开实施例所提供的显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
如图1所示，本公开实施例中以显示装置为手机1000进行示例性说明。
如图2所示，手机1000包括：显示面板100，手机1000还包括：框架、电路板、驱动芯片以及其他电子配件等，显示面板100设置于框架内，驱动芯片用于驱动显示面板100进行显示。
示例性的，如图2所示，以该显示面板100为OLED(Organic Light-Emitting Diode，有机电致发光二极管)显示面板为例，显示面板100包括：阵列基板1和发光器件叠层2。阵列基板1包括：基底101和像素电路叠层30，像素电路叠层30设置于基底101上。
示例性的，基底101的材料可以包括玻璃、金属或者柔性材料中的任一种。
像素电路叠层30形成有多个像素驱动电路10，例如，像素电路叠层30包括：依次层叠设置的遮挡层11、第一半导体层13、第一导电层15、第二导电层17、第二半导体层61、第三导电层62、第四导电层19和第五导电层21。
示例性的，第一半导体层13的材料包括低温多晶硅。第二半导体层61的材料包括：氧化铟镓锌。
需要说明的是，阵列基板1的各功能膜层之间还设置有绝缘层。功能膜层包括：遮挡层11、第一半导体层13、第一导电层15、第二导电层17、第二半导体层61、第三导电层62、第四导电层19和第五导电层21。
示例性的，如图2所示，绝缘层包括：第一绝缘层102、第一栅介质层103、第二栅介质层104、第二绝缘层105、第三栅介质层106、第三绝缘层107、钝化层108、第一平坦化层109和第二平坦化层110。
例如，像素电路叠层30包括依次层叠设置的遮挡层11、第一绝缘层102、第一半导体层13、第一栅介质层103、第一导电层15、第二栅介质层104、第二导电层17、第二绝缘层105、第二半导体层61、第三栅介质层106、第三导电层62、第三绝缘层107、第四导电层19、钝化层108、第一平坦化层109、第五导电层21和第二平坦化层110。
示例性的，第一平坦化层109和第二平坦化层110的材料包括聚酰亚胺，第一绝缘层102、第二绝缘层105和第三绝缘层107的材料包括氮化硅和氧化硅中的任一种。
在一些实施例中，本公开的一些实施例中的像素驱动电路10可以为7T1C、8T1C或者9T1C的电路，其中T代表晶体管，位于T前面的数字表示为晶体管的个数，C代表电容器，位于C前面的数字表示为电容器的个数，示例性的，7T1C表示7个晶体管和1个电容器。
在一些实施例中，介绍基于图3A所示的像素驱动电路10的结构，该像素驱动电路10为7T1C的像素驱动电路。该像素驱动电路10包括：第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7。
示例性的，如图3A所示，第一复位晶体管T1包括：栅极、第一极和第二极T12，第一复位晶体管T1的栅极与第一复位信号线Reset1电连接，第一复位晶体管T1的第一极与第一初始化信号线Vinit1电连接，第一复位晶体管T1的第二极T12与第三节点N3电连接。第一复位晶体管T1被配置为：响应于在第一复位信号线Reset1处接收的复位信号，对驱动晶体管T3的栅极进行复位。
示例性的，如图3A所示，补偿晶体管T2包括：栅极、第一极T21和第二极T22，补偿晶体管T2的栅极与第二扫描信号线Gate2电连接，补偿晶体管T2的第一极T21与第一 节点N1电连接，补偿晶体管T2的第二极T22与第三节点N3电连接。补偿晶体管T2被配置为：响应于第二扫描信号线Gate2处接收的扫描信号，对驱动晶体管T3进行复位或阈值补偿。
示例性的，如图3A所示，驱动晶体管T3包括：栅极T33、第一极和第二极T32，驱动晶体管T3的栅极T33与第一节点N1电连接，驱动晶体管T3的第一极与第二节点N2电连接，驱动晶体管T3的第二极T32与第三节点N3电连接。驱动晶体管T3被配置为产生驱动电流信号。
示例性的，如图3A所示，数据写入晶体管T4包括：栅极、第一极和第二极，数据写入晶体管T4的栅极与第一扫描信号线Gate1电连接，数据写入晶体管T4的第一极与数据信号线Data电连接，数据写入晶体管T4的第二极与第二节点N2电连接。数据写入晶体管T4被配置为：响应于在第一扫描信号线Gate1处接收的扫描信号，将在数据信号线Data处接收的数据信号传输至驱动晶体管T3。
示例性的，如图3A所示，第一发光控制晶体管T5包括：栅极、第一极和第二极，第一发光控制晶体管T5的栅极与发光控制信号线EM电连接，第一发光控制晶体管T5的第一极与电源信号线ELVDD电连接，第一发光控制晶体管T5的第二极与第二节点N2电连接。第一发光控制晶体管T5被配置为：响应于在发光控制信号线EM处接收的发光控制信号，将在电源信号线ELVDD处接收的电源信号传输至驱动晶体管T3。
示例性的，如图3A所示，第二发光控制晶体管T6包括：栅极、第一极和第二极，第二发光控制晶体管T6的栅极与发光控制信号线EM电连接，第二发光控制晶体管T6的第一极与第三节点N3电连接，第二发光控制晶体管T6的第二极与第四节点N4电连接。第二发光控制晶体管T6被配置为：响应于在发光控制信号线EM处接收的发光控制信号，将驱动电流信号传输至发光器件L，用于驱动发光器件L发光。
示例性的，如图3A示，第二复位晶体管T7包括：栅极、第一极和第二极，第二复位晶体管T7的栅极与第二复位信号线Reset2电连接，第二复位晶体管T7的第一极与第二初始化信号线Vinit2电连接，第二复位晶体管T7的第二极与第四节点N4电连接。第二复位晶体管T7被配置为：响应于在第二复位信号线Reset2处接收的复位信号，将第二初始化信号线Vinit2处接收的初始信号传输至发光器件L，以对发光器件L进行复位。
示例性的，发光器件L的阳极与第四节点N4电连接，发光器件L的阴极与参考电压线ELVSS电连接。
需要说明的是，本公开晶体管的第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第 一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开实施例提供的电路中，节点并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
需要说明的是，多个像素驱动电路组12沿第二方向Y设置有多行，本行的第一复位晶体管T1的栅极连接的第一复位信号线Reset1，可以与上一行的第二复位晶体管T7的栅极连接的第二复位信号线Reset2为同一条复位信号线Reset(如图4所示)。即当一条复位信号线Reset导通时，该复位信号线Reset向本行的第一复位晶体管T1和上一行的第二复位晶体管T7同时传输复位信号。
示例性的，如图3A所示，像素驱动电路10还包括：电容器Cst，电容器Cst包括：第一极板Cst1和第二极板Cst2，电容器Cst的第一极板Cst1与第一节点N1电连接，电容器Cst的第二极板Cst2与电源信号线ELVDD电连接。
在一些实施例中，像素驱动电路10采用LTPO(Low Temperature Polycrystalline Oxide，低温多晶氧化物)电路，即一个像素驱动电路10同时包括低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)薄膜晶体管和氧化物(Oxide)薄膜晶体管，低温多晶硅薄膜晶体管的载荷能力较强，氧化物(Oxide)薄膜晶体管的关态电流小，电荷保持能力强于低温多晶硅薄膜晶体管，这样可以实现像素驱动电路10较高的电荷迁移率和较好的稳定性。
例如，补偿晶体管T2可以采用氧化物薄膜晶体管，且为N型晶体管，即高电平导通。第一复位晶体管T1、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7均为低温多晶硅薄膜晶体管(Low Temperature Poly-silicon Thin Film Transistor)的P型晶体管，低电平导通。将补偿晶体管T2采用氧化物薄膜晶体管的设置，可以有效的防止第一节点N1漏电。
示例性的，第一半导体层13、第一导电层15、第二导电层17形成了LTPO电路中的第一复位晶体管T1、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7和电容器Cst。第二半导体层61和第三导电层62形成了补偿晶体管T2。
需要说明的是，上述第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7的示例并不构成对晶体管类型的限制。
示例性的，像素驱动电路10的时序图如图3B所示。该时序包括三个阶段，初始化阶段t1、数据写入以及Vth补偿阶段t2和发射阶段t3。
初始化阶段t1：第一复位信号线Reset1为低电平，发光控制信号线EM和第二扫描信 号线Gate2为高电平，第一复位晶体管T1和补偿晶体管T2打开，第一发光控制晶体管T5和第二发光控制晶体管T6关闭，第一初始化信号线Vinit1的电压通过第一复位晶体管T1和补偿晶体管T2写入N1节电，使其初始化。
数据写入以及Vth补偿阶段t2，第一复位信号线Reset1为高电平，第一初始化信号线Vinit1传输的信号关闭。第一扫描信号线Gate1低电平，数据信号线Data处的数据信号通过数据写入晶体管T4，驱动晶体管T3和补偿晶体管T2写入N1节点，补偿驱动晶体管T3的Vth。
发射阶段t3，第二扫描信号线Gate2为低电平，发光控制信号线EM为低电平，补偿晶体管T2关闭，第一发光控制晶体管T5和第二发光控制晶体管T6打开进入发光阶段。
如图2所示，发光器件叠层2形成有多个发光器件L，多个发光器件L设置于阵列基板1的多个像素驱动电路10上，阵列基板1用于驱动多个发光器件L发光。发光器件叠层2包括：依次层叠设置在像素电路叠层30远离基底101一侧的阳极层202、像素界定层201、发光功能层203以及阴极层204。
在一些实施例中，手机1000还包括摄像头、各种传感器、扬声器等部件。
为了实现全面屏显示，需要将感光部件集成在显示面板100下方，感光部件从显示面板100的正面采光。感光部件例如为摄像头，相应的，这种技术为屏下摄像头技术；感光部件例如为指纹传感器，相应的，这种技术为屏下指纹识别技术。实现屏下摄像头技术和屏下指纹识别技术，对显示屏的光线透过率有一定的要求。然而，在显示屏中，用于形成像素驱动电路10的各膜层的设置，影响了屏幕的光线透过率，从而影响了显示屏的拍摄效果和指纹识别效果。
基于上述问题，如图2和图4所示，本公开的一些实施例提供一种阵列基板1，阵列基板1包括：基底101以及设置于基底101上的多个像素驱动电路组12，多个像素驱动电路组12沿第一方向X和第二方向Y阵列排布。其中，多个像素驱动电路组12中的每个像素驱动电路组12包括：沿第一方向X设置的两个像素驱动电路10。
其中，第一方向X和第二方向Y相交，且第一方向X和第二方向Y均平行于基底101的上表面。示例性的，第一方向X和第二方向Y相垂直，第一方向X为多个像素驱动电路组12排布的行方向，第二方向Y为多个像素驱动电路组12排布的列方向。
示例性的，如图12所示，将两个像素驱动电路10设置为一个像素驱动电路组12，可以将一个像素驱动电路组12中的两条数据信号线Data在第一方向X上相邻设置，将该像素驱动电路组12的两条电源信号线ELVDD设置于两条数据信号线Data的两侧，即在一个像素驱动电路组12中，电源信号线ELVDD、数据信号线Data、数据信号线Data和电源信号线ELVDD沿第一方向X依次设置。基于这种设置，在相邻的两个像素驱动电路组12中，相邻设置的两条电源信号线ELVDD可以相连接，以减小电源信号线ELVDD的压 降。
如图2和图4所示，本公开实施例所提供的阵列基板1还包括：设置于基底101(如图2所示)一侧的第一导电层15，以及设置于第一导电层15远离基底101一侧的第二导电层17。阵列基板1还包括：电源信号线ELVDD(如图12所示)。
如图4所示，像素驱动电路10包括：驱动晶体管T3和电容器Cst，电容器Cst包括：第一极板Cst1和第二极板Cst2，第一极板Cst1与驱动晶体管T3的栅极连接，第二极板Cst2与电源信号线ELVDD连接。其中，如图4所示，第一极板Cst1位于第一导电层15，第二极板Cst2位于第二导电层17。
示例性的，第一极板Cst1与驱动晶体管T3的栅极为一体结构。
由于每个像素驱动电路10的电容器Cst的第二极板Cst2均需要与电源信号线ELVDD连接，因此可以将多个电容器Cst的多个第二极板Cst2连接起来，以降低电源信号线ELVDD所提供的电源信号在传输过程中的压降。
基于此，像素驱动电路组12中的两个像素驱动电路10的第二极板Cst2之间连接有第一连接图案M1，第一连接图案M1位于第二导电层17。即通过第一连接图案M1将相邻的两个第二极板Cst连接起来。
其中，第一连接图案M1在第二方向Y上的尺寸d1，小于第二极板Cst2在第二方向Y上的尺寸d2。
需要说明的是，第一连接图案M1在第二方向Y上的尺寸d1是指第一连接图案M1在第二方向Y上的最大尺寸，第二极板Cst2在第二方向Y上的尺寸d2是指第二极板Cst2在第二方向Y上的最大尺寸。
例如，第一连接图案M1与像素驱动电路组12中的两个像素驱动电路10的第二极板Cst2相连，具体为，第一连接图案M1与像素驱动电路组12中的两个像素驱动电路10的第二极板Cst2为一体结构，可以简化阵列基板1的结构和制备工艺。
示例性的，如图4所示，在一个像素驱动电路组12中，第一连接图案M1连接两个像素驱动电路10的第二极板Cst2，两个像素驱动电路10可以接收同一个电源信号。由于第一连接图案M1在一个像素驱动电路组12中起传输电源信号的作用，第一连接图案M1在第二方向Y上的尺寸d1小于第二极板Cst2在第二方向Y上的尺寸d2的设置，并不影响电源信号的传输。因此，可以设置第一连接图案M1在第二方向Y上的尺寸d1，小于第二极板Cst2在第二方向Y上的尺寸d2。该设置可以增加一个像素驱动电路组12中的两个第二极板Cst2之间的区域S1的光线透过率。
本公开的实施例通过设置第一连接图案M1在第二方向Y上的尺寸d1，小于第二极板Cst2在第二方向Y上的尺寸d2，可以增加一个像素驱动电路组12中的两个第二极板Cst2之间区域S1的透过率，实现提高阵列基板1光线透过率的目的。
在一些实施例中，如图4所示，第一连接图案M1在第二方向Y上的尺寸d1，与第二极板Cst2在第二方向Y上的尺寸d2的比值范围为10％～50％。
示例性的，第一连接图案M1在第二方向Y上的尺寸d1，与第二极板Cst2在第二方向Y上的尺寸d2的比值为10％、15％、25％、30％、40％或50％等，此处并不设限。
将第一连接图案M1在第二方向Y上的尺寸d1，与第二极板Cst2在第二方向Y上的尺寸d2的比值范围为10％～50％的设置，第一连接图案M1既可以满足连接一个像素驱动电路组12中两个像素驱动电路10的第二极板Cst2以传输电源信号的作用，又可以提高阵列基板1光线透过率。
在一些示例中，如图4所示，第一连接图案M1在第二方向Y上的尺寸d1范围为2.0μm～5.5μm。
示例性的，如图4所示，第一连接图案M1在第二方向Y上的尺寸d1为2.0μm、3.5μm、4.0μm、5.0μm或5.5μm等，此处并不设限。
示例性的，图4所示的第一连接图案M1在第二方向Y上的尺寸d1，小于第二极板Cst2在第二方向Y上的尺寸d2，例如，d1＝5.5μm，d2＝13.5μm。在另一些示例中，第一连接图案M1在第二方向Y上的尺寸d1和第二极板Cst2第二方向Y上的尺寸d2相等，例如，d1＝d2＝13.5μm。两者相比，在一个像素驱动电路10的布图设计中，在区域S1，第二导电层17的面积减小约26.9μm2。在阵列基板1中，该区域S1结构的设置，阵列基板1的光线透过率提高了1.5％左右。
在一些实施例中，如图2和图5、图7A～图7E所示，阵列基板1包括：设置于基底101和第一导电层15之间的遮挡层11。如图6、图7A～图7E所示，遮挡层11包括多个遮挡图案111。
遮挡层11的设置可以避免基底101远离遮挡层11一侧的光线对像素驱动电路10的影响。如图6所示，像素驱动电路包括遮挡图案111，每个遮挡图案111与电容器Cst的第一极板Cst1和第二极板Cst2均有交叠，第一极板Cst1与驱动晶体管T3的栅极为一体结构，即遮挡图案111与驱动晶体管T3的栅极有交叠，遮挡图案111能够避免基底101远离遮挡图案111一侧的光线对像素驱动电路10(例如驱动晶体管T3)的影响。
示例性的，每个像素驱动电路10的遮挡图案111在第一方向X和第二方向Y上相连接，形成网络结构，并将遮挡图案111与参考电压线ELVSS电连接，如图2所示，阴极层204用于传输参考电压信号，将遮挡图案111与参考电压线ELVSS电连接，即为将遮挡图案111与阴极层204相连接，可以减小阴极层204的电阻，从而减少参考电压线ELVSS的压降。
沿第一方向X，相邻的至少两个像素驱动电路组12之间，相邻的两个像素驱动 电路10的遮挡图案111之间连接有第二连接图案M2，第二连接图案M2位于遮挡层11。例如，第二连接图案M2与遮挡图案111为一体结构，这样可以简化阵列基板1的结构和制备工艺。
如图2、图4、图5和图6所示，阵列基板1还包括：第二半导体层61，第二半导体层61位于第二导电层17远离基底101的一侧。第二连接图案M2在基底101上的正投影，与第二半导体层61在基底101上的正投影有交叠。第二半导体层61包括补偿晶体管T2的有源层图案。
在一些示例中，如图6所示，沿第一方向X，位于左侧的像素驱动电路组12称为第一像素驱动电路组121，位于右侧的像素驱动电路组12称为第二像素驱动电路组122，第一像素驱动电路组121和第二像素驱动电路组122之间的相连接的遮挡层11部分为第二连接图案M2，用于传输固定电压信号，例如，该固定电压信号为参考电压信号。
第二连接图案M2在基底101上的正投影，与第二半导体层61在基底101上的正投影有交叠，即将第二连接图案M2设置于第二半导体层61和基底101之间，使得第二半导体层61对光线的遮挡区域与第二连接图案M2对光线的遮挡区域部分重合，减少第二连接图案M2对光线的遮挡，提高阵列基板1的光线透过率。
在一些实施例中，如图6所示，沿第一方向X，在相邻的两个像素驱动电路组12之间，第二连接图案M2在基底101上的正投影，与第二半导体层61在基底101上的正投影的交叠面积S2为20μm2～30μm2。
示例性的，如图2和图6所示，在第一像素驱动电路组121的像素驱动电路10中，第二连接图案M2在基底101上的正投影，与第二半导体层61在基底101上的正投影的交叠面积表示为面积S21。在第二像素驱动电路组122的像素驱动电路10中，第二连接图案M2在基底101上的正投影，与第二半导体层61在基底101上的正投影的交叠面积表示为面积S22，交叠面积S2为面积S21和面积S22之和，即S2＝S21+S22。
示例性的，沿第一方向X，在相邻的两个像素驱动电路组12之间，第二连接图案M2在基底101上的正投影，与第二半导体层61在基底101上的正投影的交叠面积S2为20μm2、21μm2、23μm2、25μm2、27μm2、29μm2或30μm2等，此处并不设限。
示例性的，如图6所示，通过设置第二连接图案M2在基底101上的正投影，与第二半导体层61在基底101上的正投影有交叠，使得阵列基板1的光线透过率提高了0.57％左右。
在一些实施例中，通过设置遮挡图案111在第一方向X和第二方向Y上的连 接方式的不同，可以实现提高阵列基板1的光线透过率。
如图7A所示，多个遮挡图案111在第一方向X和第二方向Y上相连接，形成网络结构，在相邻的两个像素驱动电路组12之间，相邻遮挡图案111在第一方向X上的连接图案(称为横向连接图案)包括第二连接图案M21、M22、M23和第四连接图案F1中的一种或多种，为方便示意，图7A中将横向连接图案均画在一个图中。相邻遮挡图案111在第二方向上的连接图案称为纵向连接图案F4，纵向连接图案F4呈条状，且整体沿第二方向延伸，用于连接位于其两端的两个遮挡图案111。
示例性的，如图7A和图7B所示，横向连接图案包括第一种第二连接图案M21，第一种第二连接图案M21在基底101上的正投影，与第二半导体层61在基底101上的正投影有交叠，具体地，第一种第二连接图案M21在基底101上的正投影，与补偿晶体管T2的有源层的端部有交叠。
示例性的，如图7A和图7C所示，横向连接图案包括第二种第二连接图案M22，第二种第二连接图案M22在基底101上的正投影，与第二半导体层61在基底101上的正投影有交叠，具体地，第二种第二连接图案M22在基底101上的正投影，与补偿晶体管T2的有源层的中部有交叠。同时，第二种第二连接图案M22在基底101上的正投影，与第二扫描信号线Gate2在基底101上的正投影相交叠。其中，第二扫描信号线Gate2包括位于第二导电层17的第一子扫描信号线2G2和位于第三导电层62包括的第二子扫描信号线3G2，第一子扫描信号线2G2和第二子扫描信号线3G2相连接形成为第二扫描信号线Gate2。
示例性的，如图7A和图7D所示，横向连接图案包括第三种第二连接图案M23，第三种第二连接图案M23在基底101上的正投影，与第二半导体层61在基底101上的正投影有交叠，具体地，第三种第二连接图案M23在基底101上的正投影，与补偿晶体管T2的有源层的另一端部有交叠。同时，第三种第二连接图案M23在基底101上的正投影，还与第一扫描信号线Gate1在基底101上的正投影相交叠。其中，第一扫描信号线Gate1位于第一导电层15。
示例性地，如图7A和图7E所示，横向连接图案包括第四连接图案F1，第四连接图案F1在基底101上的正投影，与第一半导体层13在基底101上的正投影及发光控制信号线EM在基底101上的正投影相交叠。其中，发光控制信号线EM位于第一导电层15。
示例性的，如图7A和图7B所示，纵向连接图案F4与第一半导体层13有交叠，具体的，可参见图7B中箭头处，纵向连接图案F4的一部分与第一半导体层13中第二复位晶体管T7的有源层相交叠。
通过上述设置，使得遮挡层11中的横向连接图案和纵向连接图案与其他膜层中的 图案有交叠，从而横向连接图案和纵向连接图案无需另外占据空间，可以提高阵列基板1的光线透过率。
在一些实施例中，如图2所示，在第二半导体层61远离基底101的一侧设置有第三栅介质层106和第三绝缘层107。
如图7B所示，第三栅介质层106和第三绝缘层107包括：至少一个第一过孔K1。
示例性的，如图7B所示，第一过孔K1的作用是为了实现补偿晶体管T2与第一复位晶体管T1及驱动晶体管T3的连接。示例性的，如图9和图10所示，阵列基板1具有第四导电层19，第四导电层19包括第一图案H1和第二图案H2。在一个像素驱动电路10中，包括两个第一过孔K1，表示为一号过孔K11和二号过孔K12。如图10所示，第一图案H1的一端与第一复位晶体管T1的第二极T12连接，第一图案H1的另一端通过二号过孔K12与驱动晶体管T3的第二极T32以及补偿晶体管T2的第二极T22连接，第二图案H2的一端通过一号过孔K11与补偿晶体管T2的第一极T21连接，第二图案H2的另一端与驱动晶体管T3的栅极T33连接。
示例性的，至少一个第一过孔贯穿第三栅介质层106(如图2所示)和第三绝缘层107(如图2所示)至第二半导体层61，至少一个第一过孔K1在基底101上的正投影，与第二连接图案M2在基底101上的正投影有交叠。
示例性的，如图8所示，第一过孔K1的尺寸d3大于2.5μm，且小于或等于3μm。
需要说明的是，为了更清楚的展示第一过孔K1的位置，在图7B和图8中未显示第三栅介质层106和第三绝缘层107，第三栅介质层106和第三绝缘层107的设置可以参照图2。
示例性的，如图8所示，第一过孔K1为方形，第一过孔K1的尺寸d3可以为第一过孔K1的宽度。或，第一过孔K1为圆形，第一过孔K1的尺寸d3可以为第一过孔K1的直径。例如，第一过孔K1的尺寸d3为2.6μm、2.7μm、2.8μm、2.9μm或3μm等，此处并不设限。
如图7B所示，由于第二半导体层61和第二连接图案M2交叠设置，第三绝缘层107覆盖第二半导体层61所在区域的表面相对较高，即该区域的表面相对远离基底101，在制作贯穿第三栅介质层106和第三绝缘层107的过孔时，在该区域形成的第一过孔K1可以做的相对较大。例如，如图9所示，贯穿第三绝缘层107的过孔还包括多个第二过孔K2，第二过孔K2在基底101上的正投影，与第二半导体层61在基底101上的正投影无交叠，第二过孔K2的尺寸一般小于或等于2.5μm。
第一过孔K1(一号过孔K11和二号过孔K12)尺寸相对较大的设置，可以增 大通过第一过孔K1相连接的两个导电图案的接触面积，从而减小了接触电阻。
在一些实施例中，如图2、图5和图6所示，阵列基板1包括：设置于基底101和第一导电层15之间的遮挡层11。
示例性的，遮挡层11的设置可以避免基底101远离遮挡层11一侧的光线对像素驱动电路10的影响，以及可以降低信号线的压降，具体参照上述内容介绍，此处不再赘述。
由上述内容可知，每个像素驱动电路10的遮挡图案111在第一方向X和第二方向Y上相连接，形成网络结构。如图12所示，在像素驱动电路组12中，两个像素驱动电路10沿第二方向Y对称设置。
示例性的，如图12所示，在像素驱动电路组12中，具有沿第二方向Y的中线L1，中线L1两侧的两个像素驱动电路10的晶体管(包括：第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7)相对中线L1对称布置。阵列基板1包括第五导电层21，第五导电层21设置有电源信号线ELVDD和数据信号线Data，在第一方向X上相邻的两个像素驱动电路组12之间，相邻的两个像素驱动电路10的电源信号线ELVDD可以共用。
基于上述对称设置，在每相邻的两个像素驱动电路组12之间，相邻的两个像素驱动电路10的遮挡图案111相连接，该图案称为第二连接图案M2。在像素驱动电路组12中，两个像素驱动电路10之间的遮挡图案111相连接，该图案称为第三连接图案M3。
示例性的，如图5所示，在像素驱动电路组12中，两个像素驱动电路10的遮挡图案111之间连接有第三连接图案M3，第三连接图案M3位于遮挡层11。
示例性的，第二导电层17在基底101上的正投影，覆盖第三连接图案M3在基底101上的正投影。
例如，第三连接图案M3与遮挡图案111为一体结构，这样可以简化阵列基板1的结构和制备工艺。
示例性的，第三连接图案M3用于传输固定电压信号，例如，该固定电压信号为参考电压信号。
在一些实施例中，如图5所示，在第二导电层17包括第一连接图案M1的情况下，第一连接图案M1在基底101上的正投影，与第三连接图案M3在基底101上的正投影的交叠面积大于70％。
示例性的，如图5所示，在一个像素驱动电路组12中，第一连接图案M1连接两个像素驱动电路10的第二极板Cst2，在第二极板Cst2靠近基底101的一侧设置有遮挡层11的遮挡图案111，遮挡图案111可以接入固定电压信号，例如参考电压信号。遮挡图案111 可以屏蔽周边杂散电荷对驱动晶体管T3的影响。可以理解的是，在一个像素驱动电路组12中，第三连接图案M3用于连接两个像素驱动电路10的遮挡图案111，从而可以设置连接两个第二极板Cst2第一连接图案M1在基底101上的正投影，与第三连接图案M3在基底101上的正投影的交叠面积大于70％。
示例性的，第一连接图案M1在基底101上的正投影，与第三连接图案M3在基底101上的正投影的交叠面积为75％、80％、90％或100％等，此处并不设限。
在一些实施例中，如图5所示，在每个像素驱动电路组12中，第一连接图案M1在基底101上的正投影，与第三连接图案M3在基底101上的正投影的交叠面积S3为4μm2～10μm2。
示例性的，在每个像素驱动电路组12中，第一连接图案M1在基底101上的正投影，与第三连接图案M3在基底101上的正投影的交叠面积S3为4μm2、5μm2、6μm2、7μm2、8μm2、9μm2或10μm2等，此处并不设限。
本公开的上述实施例通过设置第一连接图案M1在基底101上的正投影，覆盖第三连接图案M3在基底101上的正投影，减小了第三连接图案M3对光线透过率的影响，示例性的，该设置使得阵列基板1的光线透过率提高了0.19％左右。
在一些实施例中，如图2、图10和图11所示，阵列基板1包括设置于第一导电层15远离基底101一侧的第四导电层19，以及位于第四导电层19的第一初始化信号线Vinit1和第二初始化信号线Vinit2。第一初始化信号线Vinit1和第二初始化信号线Vinit2在基底101上的正投影，与第一导电层15在基底101上的正投影有交叠。
将第一初始化信号线Vinit1和第二初始化信号线Vinit2设置于第四导电层19，且将第一初始化信号线Vinit1和第二初始化信号线Vinit2在基底101上的正投影，与第一导电层15在基底101上的正投影有交叠的设置，可以减少第一初始化信号线Vinit1和第二初始化信号线Vinit2对光线透过率的影响。
在一些示例中，如图11所示，在每个像素驱动电路10中，在每个像素驱动电路12中，第一初始化信号线Vinit1在基底101上的正投影与第一导电层15在基底101上的正投影的交叠面积S41，大于第二初始化信号线Vinit2在基底101上的正投影与第一导电层15在基底101上的正投影的交叠面积S42。
示例性的，第一初始化信号线Vinit1和第二初始化信号线Vinit2在基底101上的正投影，与第一导电层15在基底101上的正投影的交叠面积S4的范围为15μm2～20μm2。
示例性的，如图11所示，第一初始化信号线Vinit1在基底101上的正投影，与第一导电层15在基底101上的正投影的交叠面积表示为面积S41，第二初始化信号 线Vinit2在基底101上的正投影，与第一导电层15在基底101上的正投影的交叠面积表示为面积S42，可以理解的是，S4＝S41+S42。
示例性的，第一初始化信号线Vinit1和第二初始化信号线Vinit2在基底101上的正投影，与第一导电层15在基底101上的正投影的交叠面积S4为15μm2、16μm2、17μm2、18μm2、19μm2或20μm2等，此处并不设限。
示例性的，在每个所述像素驱动电路12中，第一初始化信号线Vinit1在基底101上的正投影与第一导电层15在基底101上的正投影的交叠面积S41，与第二初始化信号线Vinit2在基底101上的正投影与第一导电层15在基底101上的正投影的交叠面积S42的比值，大于1.5。
在一些示例中，如图11所示，在每个像素驱动电路10中，第一初始化信号线Vinit1在基底101上的正投影，与第一导电层15在基底101上的正投影的交叠面积S41的范围为12μm2～19μm2。第二初始化信号线Vinit2在基底101上的正投影，与第一导电层15在基底101上的正投影的交叠面积S42的范围为1μm2～3μm2。
示例性的，在每个像素驱动电路10中，第一初始化信号线Vinit1在基底101上的正投影，与第一导电层15在基底101上的正投影的交叠面积S41为12μm2、13μm2、14μm2、15μm2、16μm2、17μm2或19μm2等，此处并不设限。
示例性的，在每个像素驱动电路10中，第二初始化信号线Vinit2在基底101上的正投影，与第一导电层15在基底101上的正投影的交叠面积S42为1μm2、2μm2或3μm2等，此处并不设限。
本公开的实施例通过第一初始化信号线Vinit1和第二初始化信号线Vinit2在基底101上的正投影，与第一导电层15在基底101上的正投影有交叠的设置，减少了第一初始化信号线Vinit1和第二初始化信号线Vinit2对光线透过率的影响，示例性的，该设置使得阵列基板1的光线透过率提高了0.94％左右。
在一些示例中，如图10和图11所示，阵列基板1包括：复位信号线Reset，复位信号线Reset位于第一导电层15，第一初始化信号线Vinit1、第二初始化信号线Vinit2与复位信号线Reset在基底101上的正投影有交叠。
示例性的，如图11所示，由于复位信号线Reset设置于第一导电层15，第一初始化信号线Vinit1和第二初始化信号线Vinit2位于第四导电层19，相比于将第一初始化信号线Vinit1和第二初始化信号线Vinit2设置于第二导电层17，复位信号线Reset和第一初始化信号线Vinit1、第二初始化信号线Vinit2在垂直基底101所在平面的方向上的距离相隔较远，在复位信号线Reset与第一初始化信号线Vinit1、第二初始化信号线Vinit2在基底101上的正投影有交叠的情况下，可以有效的防止信号线的交叠产生静电击穿的问题，并且可以提高阵列基板1的光线透过率的目的。
在一些实施例中，如图12所示，第一半导体层13包括第一复位晶体管T1、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7的有源层图案，上述各晶体管的有源层图案包括晶体管源极和漏极，及二者之间的沟道区。第二半导体层包括补偿晶体管T2的有源层图案。
第一导电层15包括第一复位晶体管T1、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7的栅极，以及电容器Cst的第一极板Cst1。上述各晶体管的栅极与沟道区重叠，从而形成上述各晶体管。第一导电层还包括第一扫描信号线Gate1、发光控制信号线EM和复位信号线Reset。
第二导电层17包括：第一子扫描信号线2G2，第三导电层62包括：第二子扫描信号线3G2，第一子扫描信号线2G2和第二子扫描信号线3G2相连接形成为第二扫描信号线Gate2。
第四导电层19包括：第一初始化信号线Vinit1和第二初始化信号线Vinit2。
第五导电层21包括：数据信号线Data和电源信号线ELVDD。
关于信号线和晶体管的连接关系可以参照上述内容介绍，此处不再赘述。
在一些实施例中，如图12所示，阵列基板1还包括：设置于基底101和第一导电层15之间的遮挡层11。沿第一方向X，相邻的至少两个像素驱动电路组12之间，相邻的两个像素驱动电路10的遮挡图案111之间连接有第二连接图案M2，第二连接图案M2位于遮挡层11。阵列基板1还包括：发光控制信号线EM。
像素驱动电路10还包括：第二发光控制晶体管T6，第二发光控制晶体管T6的栅极与发光控制信号线EM连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极T32连接。
示例性的，第二发光控制晶体管T6的栅极与发光控制信号线EM为一体结构。
在相邻的两个像素驱动电路组12之间，相邻的两个第二发光控制晶体管T6的第一极之间以及第二连接图案M2和发光控制信号线EM之间的区域为第一透光区W1，第一透光区W1的面积大于10μm2。
示例性的，第一透光区W1的面积为15μm2、20μm2、25μm2或30μm2等，此处并不设限。
需要说明的是，在本申请一些实施例提供的阵列基板中，诸如遮挡层11、第一半导体层13、第一导电层15、第二导电层17、第二半导体层61、第三导电层62、第四导电层19和第五导电层21等导电膜层均为不透光膜层，例如第一导电层15、第二导电层17、第三导电层62、第四导电层19和第五导电层21通常采用不透光的金属层制作，透光区可以是阳极与基底之间，不包括导电层图案以及半导体层图案的区域。若导电层采用透明导电层制作，例如氧化铟锡ITO，则该区域也可以算为透光区。
在一些实施例中，如图12所示，阵列基板1还包括：第一初始化信号线Vinit1和发光控制信号线EM。像素驱动电路10还包括：第一复位晶体管T1、第二发光控制晶体管T6和第二复位晶体管T7，第一复位晶体管T1的第一极与第一初始化信号线Vinit1连接，第一复位晶体管T1的第二极T12与第二发光控制晶体管T6的第一极连接，第二发光控制晶体管T6的第二极与第二复位晶体管T7的第二极连接。第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极T32连接，第二发光控制晶体管T6的栅极与发光控制信号线EM连接。
在相邻的两个像素驱动电路组12之间，相邻的两个第二发光控制晶体管T6的第二极之间以及第一初始化信号线Vinit1和发光控制信号线EM之间的区域为第二透光区W2，第二透光区W2的面积大于10μm2。
示例性的，第二透光区W2的面积为15μm2、20μm2、25μm2或30μm2等，此处并不设限。
通过设置第一透光区W1的面积大于10μm2和第二透光区W2的面积大于10μm2，可以提高阵列基板1的光线透过率。
在本公开的一些实施例中，如图2和图4所示，阵列基板1包括：基底101，以及设置于基底101上多个像素驱动电路组12，所述多个像素驱动电路组12沿第一方向X和第二方向Y阵列排布，第一方向X和第二方向Y相交；其中，每个像素驱动电路组10包括：沿第一方向X设置的两个像素驱动电路10。
如图2和图12所示，阵列基板1还包括：设置于所述基底101上的第一导电层15，设置于所述第一导电层15远离基底101一侧的第二导电层17，以及第五导电层21；示例性地，第五导电层21设置有电源信号线ELVDD和数据信号线Data。
以像素驱动电路10为7T1C为例，如图3A～图5所示，像素驱动电路10包括：驱动晶体管T3和电容器Cst，电容器Cst包括：第一极板Cst1和第二极板Cst2，所述第一极板Cst1与驱动晶体管T3的栅极T33连接。第一极板Cst1位于第一导电层15，第二极板Cst2位于第二导电层17；如图12所示，所述第二极板Cst2与第五导电层21连接；示例性地，电容器Cst的第二极板Cst2与第五导电层21中的电源信号线ELVDD电连接。
由于每个像素驱动电路10的电容器Cst的第二极板Cst2均需要与电源信号线ELVDD连接，因此可以将多个电容器Cst的多个第二极板Cst2连接起来，以降低电源信号线ELVDD所提供的电源信号在传输过程中的压降。基于此，如图4所示，像素驱动电路组12中的两个像素驱动电路10的第二极板Cst2之间连接有第一连接图案M1，所述第一连接图案M1位于所述第二导电层17。其中，第一连接图案M1在第二方向上的尺寸d1，小于第二极板Cst2在第二方向Y上的尺寸d2。
需要说明的是，第一连接图案M1在第二方向Y上的尺寸d1是指第一连接图案M1 在第二方向Y上的最大尺寸，第二极板Cst2在第二方向Y上的尺寸d2是指第二极板Cst2在第二方向Y上的最大尺寸。
例如，第一连接图案M1与像素驱动电路组12中的两个像素驱动电路10的第二极板Cst2相连，具体为，第一连接图案M1与像素驱动电路组12中的两个像素驱动电路10的第二极板Cst2为一体结构，可以简化阵列基板1的结构和制备工艺。
示例性的，如图4所示，在一个像素驱动电路组12中，第一连接图案M1连接两个像素驱动电路10的第二极板Cst2，两个像素驱动电路10可以接收同一个电源信号。由于第一连接图案M1在一个像素驱动电路组12中起传输电源信号的作用，第一连接图案M1在第二方向Y上的尺寸d1小于第二极板Cst2在第二方向Y上的尺寸d2的设置，并不影响电源信号的传输。因此，可以设置第一连接图案M1在第二方向Y上的尺寸d1，小于第二极板Cst2在第二方向Y上的尺寸d2。该设置可以增加一个像素驱动电路组12中的两个第二极板Cst2之间的区域S1的光线透过率。
在一些实施例中，如图3A和图4所示，阵列基板还包括：第二扫描信号线Gate2。
像素驱动电路还包括：补偿晶体管T2，补偿晶体管T2的第一极与驱动晶体管T3的栅极连接，补偿晶体管T2的第二极与所述驱动晶体管T3的第二极连接，补偿晶体管T2的栅极与所述第二扫描信号线Gate2连接。
如图2所示，阵列基板1还包括：设置于基底101上的遮挡层11，并沿远离遮挡层11的方向依次设置的第一半导体层13、所述第一导电层15、所述第二导电层17、第二半导体层61、第三导电层62和第四导电层19；第五导电层21位于第四导电层19远离基底101一侧。
如图10所示，驱动晶体管T3的有源层位于第一半导体层13。
第二扫描信号线至少部分位于第三导电层62；其中，第二扫描信号线Gate2包括位于第二导电层17的第一子扫描信号线2G2和位于第三导电层62包括的第二子扫描信号线3G2，第一子扫描信号线2G2和第二子扫描信号线3G2相连接形成为第二扫描信号线Gate2。补偿晶体管T2的有源层位于第二半导体层61；第二子扫描信号线3G2的经过补偿晶体管T2的有源层的部分作为补偿晶体管T2的栅极。
如图9和图10所示，补偿晶体管T2的第二极通过第一图案H1与所述驱动晶体管T3的第二极连接，第一图案H1位于第四导电层19。
在一些示例中，继续参见图9和图10，所述第一图案H1通过第三过孔K3与所述驱动晶体管T3的第二极T32连接，所述第一图案H1还通过第一过孔K1与所述补偿晶体管T2的第二极连接，在一个像素驱动电路10中，包括两个第一过孔K1，表示为一号过孔K11和二号过孔K12。如图10所示，第一图案H1的一端通过过孔与第一复位晶体管T1的第二极T12连接，第一图案H1的另一端通过二号过孔K12与补偿晶体管T2的第 二极T22连接。其中，第三过孔K3由第四导电层19依次贯穿第三绝缘层107、第三栅介质层106、第二绝缘层105、第二栅介质层104、第一栅介质层103，到达第一半导体层13，使得第一图案H1通过第三过孔K3与所述驱动晶体管T3的第二极T32连接。第一过孔K1Z中的二号过孔K12由第四导电层19依次贯穿第三绝缘层107、第三栅介质层106，到达第二半导体层61，使得第一图案H1还通过该第一过孔K1与所述补偿晶体管T2的第二极连接。
在一些实施例中，第一连接图案M1与所述第一过孔K1以及第三过孔K3均不交叠。
在一些实施例中，如图7A和图7B所示，所述遮挡层11包括多个遮挡图案111。
沿第一方向X，相邻的至少两个所述像素驱动电路组12之间，相邻的两个像素驱动电路的遮挡图案之间连接有第二连接图案M2，所述第二连接图案M2位于所述遮挡层11；对于第二连接图案M2的具体描述可参见前边的描述，不再赘述。第二连接图案M2与第三过孔K3不交叠。
通过将设置第一连接图案M1、第二连接图案M2与第三过孔K3不交叠，能够在像素驱动电路的工作过程中，在数据写入以及Vth补偿阶段t2，减小驱动晶体管的第二极与恒压线的寄生电容耦合，避免影响补偿效果，进而避免发光器件的发光效果受到影响。
在一些实施例中，遮挡图案111和第二连接图案M2用于接收恒压信号。示例性地，遮挡层11可以接入恒压信号，例如电源信号VDD、参考电压信号VSS，初始化信号Vinit等，这些恒压信号可以在阵列基板的周边区接入显示区的遮挡层11中。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板，包括：基底，以及设置于所述基底上的多个像素驱动电路组，所述多个像素驱动电路组沿第一方向和第二方向阵列排布，所述第一方向和所述第二方向相交；其中，每个像素驱动电路组包括：沿所述第一方向设置的两个像素驱动电路；
    还包括：设置于所述基底上的第一导电层，设置于所述第一导电层远离所述基底一侧的第二导电层，以及电源信号线；
    所述像素驱动电路包括：驱动晶体管和电容器，所述电容器包括：第一极板和第二极板，所述第一极板与所述驱动晶体管的栅极连接，所述第二极板与所述电源信号线连接；
    其中，所述第一极板位于所述第一导电层，所述第二极板位于所述第二导电层；所述像素驱动电路组中的两个像素驱动电路的第二极板之间连接有第一连接图案，所述第一连接图案位于所述第二导电层；
    其中，所述第一连接图案在所述第二方向上的尺寸，小于所述第二极板在所述第二方向上的尺寸。
  2. 根据权利要求1所述的阵列基板，其中，所述第一连接图案在所述第二方向上的尺寸，与所述第二极板在所述第二方向上的尺寸的比值范围为10％～50％。
  3. 根据权利要求1或2所述的阵列基板，其中，所述第一连接图案在所述第二方向上的尺寸范围为2.0μm～5.5μm。
  4. 根据权利要求1～3任一项所述的阵列基板，还包括：设置于所述基底和所述第一导电层之间的遮挡层；所述遮挡层包括多个遮挡图案；
    沿所述第一方向，相邻的至少两个所述像素驱动电路组之间，相邻的两个像素驱动电路的遮挡图案之间连接有第二连接图案，所述第二连接图案位于所述遮挡层；
    还包括：第二半导体层，所述第二半导体层位于所述第二导电层远离所述基底的一侧；
    所述第二连接图案在所述基底上的正投影，与所述第二半导体层在所述基底上的正投影有交叠。
  5. 根据权利要求4所述的阵列基板，其中，在所述第二半导体层远离所述基底的一侧设置有第三栅介质层和第三绝缘层；
    所述第三栅介质层和所述第三绝缘层设置有：至少一个第一过孔，所述至少一个第一过孔贯穿所述第三栅介质层和所述第三绝缘层中的至少一者至所述第二半导体层，所述至少一个第一过孔在基底上的正投影，与所述第二连接图案在基底上的正投影有交叠。
  6. 根据权利要求1～5任一项所述的阵列基板，还包括：设置于所述基底和所述第一导电层之间的遮挡层；所述遮挡层包括多个遮挡图案；
    在所述像素驱动电路组中，两个像素驱动电路的遮挡图案之间连接有第三连接图案，所述第三连接图案位于所述遮挡层；
    所述第一连接图案在所述基底上的正投影，与所述第三连接图案在所述基底上的正投 影的交叠面积大于70％。
  7. 根据权利要求1～6任一项所述的阵列基板，还包括设置于所述第二导电层远离所述基底一侧的第四导电层，以及位于所述第四导电层的第一初始化信号线和第二初始化信号线；
    所述第一初始化信号线和所述第二初始化信号线在所述基底上的正投影，与所述第一导电层在所述基底上的正投影有交叠。
  8. 根据权利要求7所述的阵列基板，其中，在每个所述像素驱动电路中，所述第一初始化信号线在所述基底上的正投影与所述第一导电层在所述基底上的正投影的交叠面积，大于所述第二初始化信号线在基底上的正投影与所述第一导电层在所述基底上的正投影的交叠面积。
  9. 根据权利要求7或8所述的阵列基板，其中，在每个所述像素驱动电路中，所述第一初始化信号线在所述基底上的正投影与所述第一导电层在所述基底上的正投影的交叠面积，与所述第二初始化信号线在基底上的正投影与所述第一导电层在所述基底上的正投影的交叠面积的比值，大于1.5。
  10. 根据权利要求7～9任一项所述的阵列基板，还包括：复位信号线，所述复位信号线位于所述第一导电层，所述第一初始化信号线、所述第二初始化信号线与所述复位信号线在所述基底上的正投影有交叠。
  11. 根据权利要求1～10任一项所述的阵列基板，还包括：设置于所述基底上的所述遮挡层，并沿远离所述遮挡层的方向依次设置的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层和第四导电层；
    所述第一半导体层的材料包括低温多晶硅；
    所述第二半导体层的材料包括氧化铟镓锌。
  12. 根据权利要求1～11任一项所述的阵列基板，还包括：设置于所述基底和所述第一导电层之间的遮挡层，所述遮挡层包括多个遮挡图案；沿所述第一方向，相邻的至少两个所述像素驱动电路组之间，相邻的两个像素驱动电路的遮挡图案之间连接有第二连接图案，所述第二连接图案位于所述遮挡层；
    还包括：发光控制信号线；
    所述像素驱动电路还包括：第二发光控制晶体管，所述第二发光控制晶体管的栅极与发光控制信号线连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极连接；
    在相邻的两个所述像素驱动电路组之间，相邻的两个所述第二发光控制晶体管的第一极之间以及第二连接图案和发光控制信号线之间的区域为第一透光区，所述第一透光区的面积大于5μm2。
  13. 根据权利要求1～12任一项所述的阵列基板，还包括：第一初始化信号线和发光控 制信号线和第二扫描信号线；
    所述像素驱动电路还包括：第一复位晶体管、第二发光控制晶体管、第二复位晶体管，和补偿晶体管，所述第一复位晶体管的第一极与所述第一初始化信号线连接，所述第一复位晶体管的第二极与补偿晶体管的第一极连接，所述第二发光控制晶体管的第二极与所述第二复位晶体管的第二极连接；所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极连接，第二发光控制晶体管的栅极与发光控制信号线连接，所述补偿晶体管的栅极与第二扫描信号线连接；
    在相邻的两个所述像素驱动电路组之间，相邻的两个所述第二发光控制晶体管的第二极之间以及所述第一初始化信号线和所述发光控制信号线之间的区域为第二透光区，所述第二透光区的面积大于10μm2。
  14. 一种阵列基板，包括：基底，以及设置于所述基底上的多个像素驱动电路组，所述多个像素驱动电路组沿第一方向和第二方向阵列排布，所述第一方向和所述第二方向相交；其中，每个像素驱动电路组包括：沿所述第一方向设置的两个像素驱动电路；
    还包括：设置于所述基底上的第一导电层，设置于所述第一导电层远离所述基底一侧的第二导电层，以及第五导电层；
    所述像素驱动电路包括：驱动晶体管和电容器，所述电容器包括：第一极板和第二极板，所述第一极板与所述驱动晶体管的栅极连接，所述第二极板与所述第五导电层连接；
    其中，所述第一极板位于所述第一导电层，所述第二极板位于所述第二导电层；所述像素驱动电路组中的两个像素驱动电路的第二极板之间连接有第一连接图案，所述第一连接图案位于所述第二导电层；
    其中，所述第一连接图案在所述第二方向上的尺寸，小于所述第二极板在所述第二方向上的尺寸。
  15. 根据权利要求14所述的阵列基板，还包括：第二扫描信号线，
    所述像素驱动电路还包括：补偿晶体管，所述补偿晶体管的第一极与驱动晶体管的栅极连接，所述补偿晶体管的第二极通过第一图案与所述驱动晶体管的第二极连接，所述补偿晶体管的栅极与所述第二扫描信号线连接；
    还包括：设置于所述基底上的所述遮挡层，并沿远离所述遮挡层的方向依次设置的第一半导体层、所述第一导电层、所述第二导电层、第二半导体层、第三导电层和第四导电层；
    所述驱动晶体管的有源层位于第一半导体层；
    所述第二扫描信号线至少部分位于所述第三导电层；
    所述补偿晶体管的有源层位于第二半导体层；
    所述第一图案位于所述第四导电层。
  16. 根据权利要求15所述的阵列基板，其中，所述第一图案通过第三过孔与所述驱动晶体管的第二极连接，所述第一导电图案还通过第一过孔与所述补偿晶体管的第二极连接，所述第一连接图案与所述第一过孔以及所述第三过孔均不交叠。
  17. 根据权利要求16所述的阵列基板，其中，所述遮挡层包括多个遮挡图案；
    沿所述第一方向，相邻的至少两个所述像素驱动电路组之间，相邻的两个像素驱动电路的遮挡图案之间连接有第二连接图案，所述第二连接图案位于所述遮挡层；所述第二连接图案与所述第三过孔不交叠。
  18. 根据权利要求17所述的阵列基板，其中，所述遮挡图案和所述第二连接图案用于接收恒压信号。
  19. 一种显示面板，包括：
    如权利要求1～13、14～18中任一项所述的阵列基板；
    多个发光器件，设置于所述阵列基板的多个像素驱动电路上；所述阵列基板用于驱动所述多个发光器件发光。
  20. 一种显示装置，包括：
    如权利要求19所述的显示面板；
    驱动芯片，用于驱动所述显示面板进行显示。
PCT/CN2023/091855 2023-04-28 2023-04-28 阵列基板、显示面板及显示装置 WO2024221464A1 (zh)

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