WO2024198326A1 - 3d stacked semiconductor device and manufacturing method therefor, and electronic device - Google Patents

Abstract

A 3D stacked semiconductor device and a manufacturing method therefor, and an electronic device. The 3D stacked semiconductor device comprises: a plurality of transistors, which are distributed in different layers and stacked in a direction perpendicular to a substrate (1); and a word line (40), which penetrates the transistors in different layers. The transistor comprises a first electrode (51), a second electrode (52), a semiconductor layer (23) surrounding a side wall of the word line (40), a gate insulating layer (24) arranged between the side wall of the word line (40) and the semiconductor layer (23), a first contact layer (61) arranged between the first electrode (51) and the semiconductor layer (23), and a second contact layer (62) arranged between the second electrode (52) and the semiconductor layer (23); a plurality of first contact layers (61) of the plurality of transistors are arranged at intervals in a direction in which the word line (40) extends; and a plurality of second contact layers (62) of the plurality of transistors are arranged at intervals in the direction in which the word line (40) extends.

Description

3D stacked semiconductor device and manufacturing method thereof, and electronic device

This application claims the priority of the Chinese patent application filed with the China Patent Office on March 28, 2023, with application number 202310316367.3 and invention name “A 3D stacked semiconductor device, its manufacturing method, and electronic device”, the content of which should be understood as incorporated into this application by reference.

Technical Field

The embodiments of the present disclosure relate to, but are not limited to, the field of device design and manufacturing of semiconductor technology, and in particular to a 3D stacked semiconductor device and a manufacturing method thereof, and an electronic device.

Background Art

With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products.

Summary of the invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The present disclosure provides a 3D stacked semiconductor device, including:

Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate;

A word line, passing through the transistors of different layers;

The transistor includes a first electrode, a second electrode, and a semiconductor layer surrounding the side wall of the word line; a first contact layer arranged between the first electrode and the semiconductor layer and connected to the first electrode and the semiconductor layer, and a second contact layer arranged between the second electrode and the semiconductor layer and connected to the second electrode and the semiconductor layer; the multiple first contact layers of the multiple transistors are arranged at intervals in the direction in which the word line extends, and the multiple second contact layers of the multiple transistors are arranged at intervals in the direction in which the word line extends.

In some embodiments, the plurality of semiconductor layers of the plurality of transistors are spaced apart in an extension direction of the word line.

In some embodiments, the semiconductor device further comprises:

A first insulating layer and a conductive layer are alternately distributed from bottom to top in a direction vertical to the substrate;

a through hole penetrating the first insulating layer and the conductive layer, wherein the word line, the gate insulating layer surrounding the sidewall of the word line, the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer, and the plurality of first contact layers and the plurality of second contact layers arranged in different regions of the sidewalls of the plurality of semiconductor layers are sequentially distributed in the through hole from inside to outside;

The plurality of semiconductor layers extend in a direction vertical to the substrate and are disconnected at the sidewall of the first insulating layer;

The conductive layer includes the first electrode and the second electrode spaced apart from each other.

In some embodiments, the diameter of the through hole corresponding to the first area of the conductive layer is larger than the diameter of the through hole corresponding to the second area of the first insulating layer;

The conductive layer only exposes the side wall in the through hole, and the first insulating layer exposes the side wall and the upper and lower sides in the through hole. a portion of a surface;

The first contact layer is at least distributed on the side wall of the conductive layer, and the second contact layer is at least distributed on the side wall of the conductive layer.

In some embodiments, the first contact layer is also distributed in partial areas of the upper and lower surfaces of the first insulating layer exposed in the through hole and is not distributed on the side walls of the first insulating layer; the second contact layer is also distributed in partial areas of the upper and lower surfaces of the first insulating layer exposed in the through hole and is not distributed on the side walls of the first insulating layer.

In some embodiments, the semiconductor layer is distributed on a surface of the first contact layer and a surface of the second contact layer and is not distributed on a sidewall of the first insulating layer.

In some embodiments, the semiconductor layer is also distributed in partial regions of upper and lower surfaces of the first insulating layer exposed in the through hole.

In some embodiments, the gate insulating layer is distributed on the surface of each of the semiconductor layers and is not distributed on the sidewall of the first insulating layer, and the gate insulating layers on the surfaces of the semiconductor layers of different layers are spaced apart from each other.

In some embodiments, the contact area between the conductive layer and the first insulating layer is laterally etched to form a recessed area along a direction parallel to the substrate, and the recessed area is provided with a fourth insulating layer, and the fourth insulating layer isolates the word line and the first contact layer, the second contact layer, and the semiconductor layer.

In some embodiments, the 3D stacked semiconductor device further includes: a protective layer arranged on the side wall of the conductive layer; the protective layer arranged on the side wall of the first electrode is disconnected from the protective layer arranged on the side wall of the second electrode; the protective layers on the side walls on the same side of the first electrodes of transistors in different layers are connected to form an integrated structure; the protective layers on the side walls on the same side of the second electrodes of transistors in different layers are connected to form an integrated structure.

An embodiment of the present disclosure provides an electronic device, comprising the 3D stacked semiconductor device described in any of the above embodiments.

The present disclosure provides a method for manufacturing a 3D stacked semiconductor device, comprising:

Providing a substrate, depositing a first insulating film and a conductive film alternately on the substrate in sequence, and patterning to form a stacked structure, wherein the stacked structure comprises a stack of alternately arranged first insulating layers and conductive layers, wherein the conductive layers comprise conductive portions extending along a first direction;

Etching the sidewall of the conductive layer to a preset thickness in a direction parallel to the substrate to form a protective layer covering the sidewall of the conductive layer;

A through hole is formed penetrating the stacked structure in a direction perpendicular to the substrate, and the conductive layer is etched in a direction away from the through hole, so that on a plane parallel to the substrate, along the first direction, the orthographic projection of the region of the through hole located in the first insulating layer falls within the orthographic projection of the region of the through hole located in the conductive layer, and the through hole enables the conductive portion to form a first electrode and a second electrode separated from each other; and the sidewall of the through hole exposes each of the conductive layer and the protective layer;

Depositing a contact film in the through hole to form a contact layer, etching and removing the contact layer covering the side wall of the protection layer, and disconnecting the contact layers covering the side walls of different conductive layers from each other, and disconnecting the contact layer covering the side wall of the first electrode and the contact layer covering the side wall of the second electrode from each other;

Etching the protection layer in a direction away from the through hole so that, on a plane parallel to the substrate, an orthographic projection of the through hole located in the first insulating layer falls within an orthographic projection of the through hole located in the conductive layer;

A word line extending in a direction perpendicular to the substrate is formed in the through hole, a gate insulating layer surrounding the word line, and a semiconductor layer surrounding the gate insulating layer, wherein the semiconductor layer is connected to the contact layer.

In some embodiments, etching the protection layer in a direction away from the through hole comprises: etching the protection layer in a direction away from the through hole The protective layer is etched in a direction so that the protective layer arranged on the side wall of the first electrode is disconnected from the protective layer arranged on the side wall of the second electrode.

In some embodiments, the word line extending in a direction perpendicular to the substrate is formed in the through hole, and the gate insulating layer surrounding the word line and the semiconductor layer surrounding the gate insulating layer include:

Depositing a semiconductor film, a gate insulating film and a sacrificial layer film in the through hole in sequence to form the semiconductor layer, the gate insulating layer and the sacrificial layer;

Etching a portion of the sacrificial layer in the through hole so that the sidewall of the through hole located in the first insulating layer exposes the first insulating layer, and the sidewall of the through hole located in the conductive layer exposes the sacrificial layer; etching and removing the semiconductor layer and the gate insulating layer in the through hole of the first insulating layer;

Depositing a fourth insulating film in the through hole to form a fourth insulating layer, and etching the fourth insulating layer covering a side of the sacrificial layer facing the through hole;

A gate electrode film is deposited in the through hole, and the gate electrode film fills the through hole to form the word line.

Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. The objects and advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description and the drawings.

Other aspects will be apparent upon reading and understanding the drawings and detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation on the technical solution.

FIG. 1A is a schematic plan view of a semiconductor device provided by an exemplary embodiment;

FIG1B is a schematic cross-sectional view along the aa' direction in FIG1A ;

FIG1C is a schematic cross-sectional view along the cc' direction in FIG1A ;

FIG2 is a schematic cross-sectional view of a stacked structure formed along a direction perpendicular to a substrate provided by an exemplary embodiment;

3A is a cross-sectional view along a direction parallel to the substrate after a conductive layer is formed, provided by an exemplary embodiment (a cross-sectional view of a film layer where the conductive layer is located);

FIG3B is a cross-sectional view along the cc' direction in FIG3A;

4A is a cross-sectional view along a direction parallel to the substrate after the capacitor region is opened provided by an exemplary embodiment (a cross-sectional view of the film layer where the conductive layer is located);

Fig. 4B is a cross-sectional view along the aa' direction in Fig. 4A;

Fig. 4C is a cross-sectional view along the dd' direction in Fig. 4A;

FIG5A is a schematic plan view of an exemplary embodiment after forming a second capacitor electrode;

Fig. 5B is a cross-sectional view along the aa' direction in Fig. 5A;

FIG5C is a cross-sectional view along the dd' direction in FIG5A;

FIG6A is a schematic plan view of an exemplary embodiment after exposing the sidewall of a conductive layer;

FIG6B is a cross-sectional view along the cc' direction in FIG6A;

FIG7A is a schematic plan view of an exemplary embodiment after etching a conductive layer;

FIG7B is a cross-sectional view along the cc' direction in FIG7A;

FIG8A is a schematic plan view of an exemplary embodiment after forming a protective layer and a third insulating layer;

FIG8B is a cross-sectional view along the cc' direction in FIG8A;

FIG9A is a schematic plan view of an exemplary embodiment after forming a second through hole;

FIG9B is a cross-sectional view along the aa' direction in FIG9A;

FIG10A is a schematic plan view of an exemplary embodiment after etching a second through hole;

Fig. 10B is a cross-sectional view along the aa' direction in Fig. 10A;

FIG10C is a cross-sectional view along the cc' direction in FIG10A;

FIG11A is a schematic plan view of an exemplary embodiment after forming a contact layer;

FIG11B is a cross-sectional view along the aa' direction in FIG11A;

FIG11C is a cross-sectional view along the cc' direction in FIG11A;

FIG12A is a schematic plan view of an exemplary embodiment after etching a contact layer;

FIG12B is a cross-sectional view along the aa' direction in FIG12A;

FIG12C is a cross-sectional view along the cc' direction in FIG12A;

FIG13A is a schematic plan view of an exemplary embodiment after etching a protective layer;

FIG13B is a cross-sectional view along the cc' direction in FIG13A;

FIG14A is a schematic plan view of an exemplary embodiment after forming a semiconductor layer, a gate insulating layer and a sacrificial layer;

FIG14B is a cross-sectional view along the aa' direction in FIG14A;

FIG14C is a cross-sectional view along the cc' direction in FIG14A;

FIG15A is a cross-sectional view along the aa′ direction after etching a sacrificial layer provided by an exemplary embodiment;

FIG15B is a cross-sectional view along the aa′ direction after etching the semiconductor layer and the gate insulating layer provided by an exemplary embodiment;

FIG15C is a cross-sectional view along the cc' direction after etching the semiconductor layer and the gate insulating layer provided by an exemplary embodiment;

FIG16A is a cross-sectional view along the aa′ direction after forming a gate electrode provided by an exemplary embodiment;

FIG16B is a cross-sectional view along the cc' direction after forming a gate electrode provided by an exemplary embodiment;

FIG. 17 is a flow chart of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment.

Description of reference numerals:
1-substrate; 2-stop layer; 3-protective layer; 6-contact layer; 9-first insulating layer; 10-first insulating film; 11-first conductive film; 12-conductive layer; 13-dielectric layer; 14-second insulating layer; 15-third insulating layer; 16-fourth insulating layer; 23-semiconductor layer; 24-gate insulating layer; 25-sacrificial layer; 26-gate electrode; 30-bit line; 40-word line; 41-first capacitor electrode; 42-second capacitor electrode; 51-first electrode; 52-second electrode; 61-first contact layer; 62-second contact layer; 100-capacitor region; K1-first through hole; K2-second through hole.

Details

The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by one of ordinary skill in the art to which the present invention belongs.

The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a physical connection, or an electrical signal connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

The "A and B are arranged in the same layer" mentioned in the present disclosure includes film layers formed of the same material or different materials located on the same film layer. Exemplarily, A and B are formed by forming the same film layer with the same material and then undergoing the same patterning process or different patterning processes. A and B arranged in the same layer may be located on the same horizontal plane but not necessarily on the same film layer, or located in different regions of the same film layer but not necessarily on the same horizontal plane.

“The orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

Figure 1A is a plan view schematic diagram of a 3D stacked semiconductor device provided by an exemplary embodiment, Figure 1B is a cross-sectional schematic diagram along the aa’ direction in Figure 1A, and Figure 1C is a cross-sectional schematic diagram along the cc’ direction in Figure 1A.

The semiconductor device may be a transistor, or a memory cell including a transistor, or a memory cell array including a memory cell, or a 3D stacked structure including a memory cell array, or a memory including a transistor or a memory cell array, etc.

As shown in FIG. 1A , FIG. 1B and FIG. 1C , an embodiment of the present disclosure provides a 3D stacked semiconductor device, which may include:

A plurality of transistors are distributed in different layers and stacked along a direction perpendicular to the substrate 1;

A word line 40, passing through the transistors of different layers;

The transistor includes a first electrode 51, a second electrode 52, a semiconductor layer 23 surrounding the side wall of the word line 40, and a gate insulating layer 24 arranged between the side wall of the word line 40 and the semiconductor layer 23; a first contact layer 61 arranged between the first electrode 51 and the semiconductor layer 23 and connected to the first electrode 51 and the semiconductor layer 23, and a second contact layer 62 arranged between the second electrode 52 and the semiconductor layer 23 and connected to the second electrode 52 and the semiconductor layer 23; the multiple first contact layers 61 of the multiple transistors are arranged at intervals in the direction in which the word line 40 extends, and the multiple second contact layers 62 of the multiple transistors are arranged at intervals in the direction in which the word line 40 extends.

The contact performance between the first contact layer 61 and the first electrode 51 is better than the contact performance between the semiconductor layer 23 and the first electrode 51, and the contact performance between the second contact layer 62 and the second electrode 52 is better than the contact performance between the semiconductor layer 23 and the second electrode 52, that is, compared with the direct contact between the first electrode 51 and the semiconductor layer 23, the first contact layer 61 can reduce the contact resistance between the first electrode 51 and the semiconductor layer 23, and compared with the direct contact between the second electrode 52 and the semiconductor layer 23, the second contact layer 62 can reduce the contact resistance between the second electrode 52 and the semiconductor layer 23.

In the solution provided in this embodiment, the first electrode 51 is connected to the semiconductor layer 23 via the first contact layer 61 , and the second electrode 52 is connected to the semiconductor layer 23 via the second contact layer 62 , which can reduce contact resistance and improve device performance.

In some embodiments, the semiconductor layers 23 of the transistors are spaced apart in the extension direction of the word line 40, such as physically disconnected. The solution provided in this embodiment can remove parasitic transistors between transistors to prevent leakage.

In some embodiments, the cross section of the semiconductor layer 23 in a direction parallel to the substrate 1 may be in a square ring shape, but is not limited thereto and may be other shapes.

In some embodiments, the semiconductor layer 23 extends on the sidewall of the word line 40 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate 1. The semiconductor layer 23 may extend only in a direction perpendicular to the substrate 1, or the main body may extend in a direction perpendicular to the substrate 1, and a horizontal portion may extend in a horizontal direction and toward the word line 40 at the end.

The word line 40 may be partially or completely surrounded by the surrounding semiconductor layer 23. In some embodiments, the surrounding may be completely surrounded as a whole, and the cross section of the semiconductor layer 23 after the surrounding is a closed ring. The cross section is intercepted in a direction parallel to the substrate. In some embodiments, the surrounding may be partially surrounded, and the cross section after the surrounding is not closed, but presents a ring shape. For example, a ring with an opening.

In some embodiments, the material components of different regions of the word line 40 extending in a direction perpendicular to the substrate 1 are the same, which can be understood as being formed using the same film manufacturing process. The same material components can be understood as the same main elements tested in the material.

In some embodiments, the semiconductor device may further include:

A first insulating layer 9 and a conductive layer 12 are alternately distributed from bottom to top along a direction vertical to the substrate 1;

A second through hole K2 penetrating the first insulating layer 9 and the conductive layer 12, wherein the word line 40, the gate insulating layer 24 surrounding the side wall of the word line 40, the plurality of semiconductor layers 23 surrounding different regions of the side wall of the gate insulating layer 24, and the plurality of first contact layers 61 and the plurality of second contact layers 62 arranged in different regions of the side wall of the plurality of semiconductor layers 23 are sequentially distributed in the second through hole K2 from inside to outside;

The plurality of semiconductor layers 23 extend in a direction vertical to the substrate 1 and are disconnected at the sidewall of the first insulating layer 9;

The conductive layer 12 includes the first electrode 51 and the second electrode 52 which are spaced apart from each other.

In some embodiments, the diameter of the first area of the conductive layer 12 corresponding to the second through hole K2 is larger than the diameter of the second area of the first insulating layer 9; that is, the orthographic projection of the second area of the first insulating layer 9 corresponding to the second through hole K2 on the substrate 1 falls into the orthographic projection of the first area of the conductive layer 12 corresponding to the second through hole K2 on the substrate 1.

The conductive layer 9 only exposes the side wall in the second through hole K2, and the first insulating layer 9 exposes the side wall and partial areas of the upper and lower surfaces in the second through hole K2;

The first contact layer 61 is at least distributed on the side wall of the conductive layer 9 , and the second contact layer 62 is at least distributed on the side wall of the conductive layer 9 .

In some embodiments, the first contact layer 61 is also distributed on partial areas of the upper and lower surfaces of the first insulating layer 9 exposed in the second through hole K2 and is not distributed on the side walls of the first insulating layer 9; the second contact layer 62 is also distributed on partial areas of the upper and lower surfaces of the first insulating layer 9 exposed in the second through hole K2 and is not distributed on the side walls of the first insulating layer 9.

In some embodiments, the semiconductor layer 23 is distributed on the surface of the first contact layer 61 and the surface of the second contact layer 62 and is not distributed on the sidewall of the first insulating layer 9 .

In some embodiments, as shown in FIG. 1C , the semiconductor layer 23 is also distributed in partial regions of the upper and lower surfaces of the first insulating layer 9 exposed in the second through hole K2 .

In some embodiments, the gate insulating layer 24 is distributed on the surface of each semiconductor layer 23 and is not distributed on the sidewall of the first insulating layer 9, and the gate insulating layers 24 on the surfaces of the semiconductor layers 23 of different layers may be spaced apart from each other. However, the disclosed embodiments are not limited thereto, and transistors of different layers may share a ring-shaped gate insulating layer 24 extending in a direction perpendicular to the substrate 1.

In some embodiments, the contact area between the conductive layer 12 and the first insulating layer 9 is laterally etched to form a recessed area along a direction parallel to the substrate 1, and the recessed area may be provided with a fourth insulating layer 16, and the fourth insulating layer 16 isolates the word line 40 and the first contact layer 61, the second contact layer 62, and the semiconductor layer 23.

In some embodiments, the 3D stacked semiconductor device may further include: a protective layer 3 arranged on the side wall of the conductive layer 12; the protective layer 3 arranged on the side wall of the first electrode 51 is disconnected from the protective layer 3 arranged on the side wall of the second electrode 52; the protective layers 3 on the side walls on the same side of the first electrodes 51 of transistors in different layers are connected to form an integrated structure; the protective layers 3 on the side walls on the same side of the second electrodes 52 of transistors in different layers are connected to form an integrated structure.

In some embodiments, along a direction perpendicular to the substrate, the first electrode 51 and the second electrode 52 of the same transistor may be located at the same horizontal plane, such as located on the same supporting layer, and the supporting layer is partially or entirely parallel to the substrate, and the supporting layer may be an isolation layer between storage units. The first electrode and the second electrode are located at the same horizontal plane, and the conductive materials may be the same or different.

In some embodiments, the first electrode 51 and the second electrode 52 of the same transistor may be located in the same conductive film layer. It can be understood that the first electrode 51 and the second electrode 52 are formed by patterning the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate 1, or may not be parallel, and the first electrode 51 and the second electrode 52 may be located in the same horizontal plane, or different horizontal planes, but are formed by patterning the same conductive film layer, that is, the first electrode 51 and the second electrode 52 are different regions of the same conductive film layer and are independent of each other. The first electrode 51 and the second electrode 52 may be arranged in the same layer. That is, the first electrode 51 and the second electrode 52 may be formed simultaneously by the same patterning process, but the embodiments of the present disclosure are not limited thereto, and the first electrode 51 and the second electrode 52 may be manufactured separately by different patterning processes.

In some embodiments, the transistor may include a gate electrode 26 , and the gate electrodes 26 of transistors in different layers are part of the word line 40 . The semiconductor layers 23 disposed at intervals are disconnected, and the word line 40 is exposed in the disconnected area.

In some embodiments, the word line 40 may extend in a straight line in a direction perpendicular to the substrate 1. In some embodiments, the orthographic projection of each transistor gate electrode 26 on a plane perpendicular to the substrate 1 may be at the same position, and the gate electrodes 26 of each transistor in different layers are connected to form a straight word line 40.

In some embodiments, the 3D stacked semiconductor device may further include: a plurality of bit lines 30 distributed in different layers and extending in a direction parallel to the substrate 1, wherein the bit lines 30 are connected to the second electrodes 52 of the transistors in the same layer as the bit lines 30 to form an integrated structure. The second electrodes 52 of the transistors may be a part of the bit lines 30 connected to the second electrodes 52. For example, the bit lines 30 are straight lines, and the sidewalls of the straight lines are connected to the semiconductor layer 23, or the bit lines 30 have branches of an integrated design, and the branches are connected to the semiconductor layer 23, wherein the extension direction of the branches intersects with the extension direction of the bit lines 30, such as being approximately perpendicular.

The branches may be a plurality of branches on one side wall of the bit line 30 , or a plurality of branches on both side walls at the same time, and each branch may form a transistor or a memory cell accordingly.

In some embodiments, the bit line 30 may extend along the second direction Y, and the first electrode 51 may extend along the first direction X. The first direction X may be perpendicular to the second direction Y, but is not limited thereto. The first direction X may intersect the second direction Y.

In some embodiments, on a plane parallel to the substrate 1, the orthographic projections of the semiconductor layer 23 or the gate insulating layer 24 or the gate electrode 26 of the transistors of different layers may overlap. The orthographic projections of the semiconductor layer 23 or the gate insulating layer 24 or the gate electrode 26 overlap, which can make the 3D stacked semiconductor device compact.

In some embodiments, on a plane parallel to the substrate 1, the orthographic projections of the first electrode 51 or the second electrode 52 of the transistors of different layers may overlap. In the solution provided in this embodiment, in the process, a multi-layer stacked first electrode and second electrode may be formed by stacking a conductive layer and an insulating layer and then by a mask, so that the process is simple. In addition, the structure of the 3D memory may be made more compact.

The stacked transistor can be applied in multiple memory scenarios, such as the traditional 1T structure, 2T structure, structure with capacitor or structure without capacitor in DRAM scenario, or can be applied to 4T or 6T memory cell scenario in SRAM.

In some embodiments, the 3D stacked semiconductor device may further include a data storage element.

In some embodiments, the data storage element is, for example, a capacitor, that is, a 1T1C storage structure is formed. However, the embodiments of the present disclosure are not limited thereto, and other transistors may be combined to form a 2T0C storage structure, and so on.

In some embodiments, the capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42 , and the first capacitor electrode 41 is connected to the first electrode 51 .

In some embodiments, the first capacitor electrode 41 and the first electrode 51 may be connected to form an integrated structure, or the two may share one electrode, which may be a wire extending laterally in a direction parallel to the substrate.

In some embodiments, the second capacitor electrode 42 may include a first sublayer 421 and a second sublayer 422 disposed on a side of the first sublayer 421 away from the first capacitor electrode 41 , wherein the first sublayer 421 is, for example, titanium nitride (TiN), and the second sublayer 422 is, for example, polysilicon.

In some embodiments, the second capacitor electrodes 42 of the capacitors of transistors in different layers can be connected as an integrated structure. The main surface of the second capacitor electrode 42 of the capacitors in the first column of different layers extends in a direction perpendicular to the substrate 1 to form a plate shape, and extends to the end surface and side surface of the first electrode 51 in the thickness direction of the film layer (i.e., parallel to the substrate 1) to form a capacitor with the first electrode 51.

In some embodiments, the capacitor may further include a dielectric layer 13 disposed between the first capacitor electrode 41 and the second capacitor electrode 42 .

In some embodiments, the dielectric layers 13 of the capacitors of transistors of different layers may be connected into an integrated structure. The capacitors of different layers share the same dielectric layer 13 .

In some embodiments, a plurality of the 3D stacked semiconductor devices may form a 3D stacked semiconductor device array, for example, three 3D stacked semiconductor devices may form a 3D stacked semiconductor device array, and the three 3D stacked semiconductor devices may be distributed along a direction parallel to the substrate 1 , for example, along the second direction Y. The second electrodes 52 of transistors in the same layer may be connected to the same bit line 30 .

The technical solution of this embodiment is further explained below through the manufacturing process of the 3D stacked semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layers, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

In an exemplary embodiment, a manufacturing process of a 3D stacked semiconductor device may include:

1) A first insulating film 10 and a first conductive film 11 are alternately deposited on a substrate 1 to form a stacked structure, as shown in FIG2 . FIG2 is a schematic cross-sectional view along a direction perpendicular to the substrate 1 after the stacked structure is formed.

In some embodiments, the first insulating film 10 and the first conductive film 11 may be deposited by chemical vapor deposition.

As used herein, the term "substrate" means and includes a base material or structure on which a material such as a vertical field effect transistor is formed. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

In some embodiments, the substrate 1 may be a semiconductor substrate, such as a silicon substrate.

In some embodiments, the first insulating film 10 may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

In some embodiments, the first conductive film 11 may be one or more of the following different types of materials:

For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

Alternatively, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, conductive metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

Alternatively, it may be polysilicon, silicon, germanium, silicon germanium, etc. which are conductive after being doped.

The stacked structure shown in FIG2 includes four layers of first insulating films 10 and three layers of first conductive films 11, which is only an example. In other embodiments, the stacked structure may include more or fewer layers of first insulating films 10 and first conductive films 11 that are alternately arranged. A conductive film 11.

2) forming a stop layer 2 and a conductive layer 12;

The forming of the stop layer 2 and the conductive layer 12 may include:

Depositing a stop layer thin film on the substrate 1 formed with the aforementioned pattern to form a stop layer 2;

The first insulating film 10 and the first conductive film 11 are patterned to form a first insulating layer 9 and a conductive layer 12, wherein the conductive layer 12 may include a bit line 30 and a plurality of conductive portions 21, wherein the conductive portion 21 may extend along a first direction X, and the bit line 30 may extend along a second direction Y, and the conductive portion 21 may subsequently form a first electrode 51 and a second electrode 52 of a transistor, as shown in FIG3A and FIG3B, wherein FIG3A is a cross-sectional view parallel to the direction of the substrate 1 after the conductive layer 12 is formed (a cross-sectional view of the film layer where the conductive layer 12 is located), and FIG3B is a cross-sectional view along the cc' direction in FIG3A. The cc' direction may be parallel to the extension direction of the bit line 30.

In some embodiments, the stacked structure may be etched by dry etching, and after patterning to form the conductive layer 12, the etched area may be filled with a first insulating film and polished to isolate different devices.

In some embodiments, the stop layer film includes but is not limited to a material having a higher etching selectivity ratio with the first insulating film 10, such as silicon nitride (SiN).

3) Opening the capacitor region 100;

The open capacitance region 100 may include:

The first insulating film located in the capacitor region 100 is etched and removed to expose one end of the conductive portion 21 away from the bit line 30 (including an end face of the conductive portion 21 away from the bit line 30 and a side wall whose distance from the end face is less than or equal to a preset distance), as shown in Figures 4A, 4B and 4C, wherein Figure 4A is a cross-sectional view parallel to the direction of the substrate 1 after the capacitor region is formed (a cross-sectional view of the film layer where the conductive layer 12 is located), Figure 4B is a cross-sectional view along the aa' direction in Figure 4A, and Figure 4C is a cross-sectional view along the dd' direction in Figure 4A. The aa' direction can be parallel to the extension direction of the conductive portion 21, the aa' direction can be perpendicular to the cc' direction, and the dd' direction can be parallel to the cc' direction.

In some embodiments, wet etching may be used to laterally etch the first insulating film of the stacked structure.

4) forming a dielectric layer 13 and a second capacitor electrode 42;

The forming and manufacturing of the second capacitor electrode 42 may include:

Dielectric material and conductor material are sequentially deposited on the substrate 1 on which the aforementioned pattern is formed, to form a dielectric layer 13 and a second capacitor electrode 42 respectively, wherein the dielectric layer 13 covers the exposed area of the conductive portion 21, that is, the dielectric layer 13 covers the end surface of the conductive portion 21 away from the bit line 30 and the side wall whose distance from the end surface is less than or equal to a preset distance; the second capacitor electrode 42 wraps the exposed area of the conductive portion 21 and is insulated from the conductive portion 21 by the dielectric layer 13.

The dielectric material and the conductor material outside the capacitor region 100 are etched away, and a second insulating film is deposited to form a second insulating layer 14, as shown in FIGS. 5A , 5B and 5C , wherein FIG. 5A is a plan view after the second capacitor electrode 42 is formed (wherein the capacitor region 100 is a top view, and the region outside the capacitor region 100 is a cross-sectional view of the film layer where the conductive layer 12 is located), FIG. 5B is a cross-sectional view along the aa’ direction in FIG. 5A , and FIG. 5C is a cross-sectional view along the dd’ direction in FIG. 5A .

The dielectric layer 13 serves as a medium between the capacitor plates, the second capacitor electrode 42 serves as one electrode of the capacitor, and part of the conductive portion 21 serves as another electrode of the capacitor, namely, the first capacitor electrode 41 .

In some embodiments, the dielectric material and the conductor material can be deposited by atomic layer deposition (ALD).

In some embodiments, the dielectric material may be a Low-K material, such as silicon oxide, or a High-K The dielectric material is a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO ₂ ) and other high-K materials. In some embodiments, the conductor material includes but is not limited to at least one of the following:

Metals or alloys, for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., and metal alloys containing the aforementioned metals;

Alternatively, it can be a conductive metal oxide, metal nitride, metal silicide, metal carbide, polysilicon, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other conductive metal nitride materials.

In some implementations, the depositing of the conductor material may include: depositing a first conductor material to form a first sublayer 421; depositing a second conductor material to form a second sublayer 422, wherein the first sublayer 421 and the second sublayer 422 constitute the second capacitor electrode 42. The first conductor material is, for example, TiN, and the second conductor material is, for example, polysilicon. The first sublayer 421 may extend along the surface of the dielectric layer 13.

In some embodiments, the second insulating film includes but is not limited to SiO2.

In some embodiments, before depositing the dielectric material, TiN or the like may be deposited in the capacitor region 100, and together with a portion of the conductive portion 21, serve as the first capacitor electrode 41 of the capacitor. That is, an adhesive film layer such as TiN is provided between the first electrode 51 and the dielectric layer 13 to enhance the adhesion between the first electrode 51 and the dielectric layer 13. The adhesive film layer covers the exposed area of the first electrode 51, and the adhesive film layers attached to the first electrodes 51 of different layers are disconnected, that is, after depositing the adhesive film layer, before depositing the dielectric material, the adhesive film layer may be etched to disconnect the adhesive film layers attached to the first electrodes 51 of different layers.

5) Etching the first insulating film in a direction perpendicular to the substrate 1 to expose the side walls of the conductive layer 12, that is, to expose the side walls of the conductive portion 21 and the side walls of the bit line 30, as shown in FIG6A and FIG6B, wherein FIG6A is a plan view after exposing the side walls of the conductive layer 12 (wherein the capacitor region 100 is a top view, and the area outside the capacitor region 100 is a top view of the film layer where the conductive layer 12 is located), and FIG6B is a cross-sectional view along the cc' direction in FIG6A. It can be seen that at this time, a plurality of first through holes K1 penetrating the stacked structure in a direction perpendicular to the substrate 1 are formed, and the first insulating film on the side walls of the conductive portion 21 and the side walls of the bit line 30 have been etched away, which facilitates the subsequent etching of the side walls of the conductive portion 21 and the side walls of the bit line 30.

In some embodiments, the first insulating film may be etched along a direction perpendicular to the substrate 1 by dry etching.

6) Laterally etch the conductive layer 12 so that the orthographic projection of the conductive layer 12 falls within the orthographic projection of the adjacent first insulating layer 9, as shown in FIG7A and FIG7B, wherein FIG7A is a plan view after etching the conductive layer 12 (wherein the capacitor region 100 is a top view, and the area outside the capacitor region 100 is a top view of the film layer where the conductive layer 12 is located and the adjacent first insulating layer 9), and FIG7B is a cross-sectional view along the cc' direction in FIG7A. It can be seen that along the direction parallel to the substrate 1, a portion of each side wall of the conductive layer 12 is laterally etched away, and the orthographic projection of the first sub-hole K11 of the first through hole K1 located in the first insulating layer 9 falls within the orthographic projection of the second sub-hole K12 of the first through hole K1 located in the conductive layer 12.

In some embodiments, wet etching may be performed using an SC1 solution having a high etching selectivity ratio for the first insulating layer 9 and the conductive layer 12 , and the conductive layer 12 may be etched to a preset width in a direction parallel to the substrate 1 and away from the first through hole K1 .

7) forming a protective layer 3 and a third insulating layer 15;

The forming of the protection layer 3 and the third insulating layer 15 may include: depositing protection layers in the first through hole K1 in sequence A layer of film and a third insulating film are filled to form the protective layer 3 and the third insulating layer 15; as shown in Figures 8A and 8B, wherein Figure 8A is a plan view after the protective layer 3 and the third insulating layer 15 are formed (wherein the capacitor region 100 is a top view, and the area outside the capacitor region 100 is a top view of the film layer where the conductive layer 12 is located and the adjacent first insulating layer 9), and Figure 8B is a cross-sectional view along the cc' direction in Figure 8A. It can be seen that the side walls of the conductive layer 12 are all covered with the protective layer 3.

In some embodiments, the protection layer film and the third insulating film may be deposited by ALD.

In some embodiments, the protective layer film includes but is not limited to SiN. The protective layer film is made of different materials from the first insulating film 10 and the third insulating film and has a certain etching selectivity ratio, so that the first insulating film 10 and the third insulating film are not affected when the protective layer film is subsequently etched.

In some embodiments, the third insulating film includes but is not limited to SiO ₂ .

8) forming a plurality of second through holes K2;

The forming of the plurality of second through holes K2 may include: etching the stacked structure by dry etching to form a plurality of second through holes K2 penetrating the plurality of conductive layers 12, the sidewalls of the second through holes K2 exposing the conductive layer 12 (or, the conductive portion 21) and the protective layer 3, and the aperture sizes of the second through holes K2 in different layers are substantially consistent, as shown in FIG9A and FIG9B, wherein FIG9A is a plan view after the second through holes K2 are formed (wherein the capacitor region 100 is a top view, and the region outside the capacitor region 100 is a top view of the film layer where the conductive layer 12 is located), and FIG9B is a cross-sectional view along the aa' direction in FIG9A, and the second through holes K2 may extend in a direction perpendicular to the substrate 1. The second through holes K2 may expose or not expose the substrate 1. The conductive portion 21 is divided into two independent parts by the second through holes K2, which serve as the first electrode 51 and the second electrode 52, respectively.

In some embodiments, when the stacked structure is dry-etched, a high aspect ratio etching (HAR ET) method can be used for etching. In some embodiments, the aspect ratio (Aspect ratio) is greater than 6:1.

In some embodiments, the orthographic projection of the second through hole K2 on a plane parallel to the substrate 1 may be a square or the like.

9) Laterally etching the conductive layer 12 to a preset thickness in a direction away from the second through hole K2, so that the area of the second through hole K2 located in the conductive layer 12 expands in a direction away from the second through hole K2, as shown in Figures 10A, 10B and 10C, wherein Figure 10A is a plan view after etching the second through hole K2 (wherein the capacitor area 100 is a top view, and the area outside the capacitor area 100 is a top view of the film layer where the conductive layer 12 is located), Figure 10B is a cross-sectional view along the aa' direction in Figure 10A, and Figure 10C is a cross-sectional view along the cc' direction in Figure 10A. It can be seen that in the aa' direction, the diameter of the area K21 of the second through hole K2 located in the first insulating layer 9 is smaller than the diameter of the area K22 of the second through hole K2 located in the conductive layer 12, and it can be seen that in the aa' direction, the side wall of the second through hole K2 exposes the conductive layer 12, and in the cc' direction, the side wall of the second through hole K2 exposes the protective layer 3.

In some embodiments, an acid solution having a high etching selectivity ratio between the first insulating layer 9 and the conductive layer 12 may be used to perform lateral wet etching on the conductive layer 12 in a direction away from the second through hole K2 .

10) forming a contact layer 6;

The forming of the contact layer 6 may include: depositing a contact film in the second through hole K2 to form a contact layer 6, and the contact layer 6 is distributed on the bottom wall and side wall of the second through hole K2, as shown in Figures 11A, 11B and 11C, wherein Figure 11A is a plan schematic diagram after the contact layer 6 is formed (wherein the capacitor area 100 is a top view, and the area outside the capacitor area 100 is a top view of the film layer where the conductive layer 12 is located), Figure 11B is a cross-sectional view along the aa' direction in Figure 11A, and Figure 11C is a cross-sectional view along the cc' direction in Figure 11A.

In some embodiments, the material of the contact film may be a material having good metal contact properties and forming a low contact resistance, such as at least one of titanium (Ti) and TiN.

In some embodiments, the contact film may be deposited by ALD.

11) etching a portion of the contact layer 6 to form a first contact layer 61 and a second contact layer 62;

The etching of a portion of the contact layer 6 to form the first contact layer 61 and the second contact layer 62 may include:

The contact layer 6 covering the side walls of the protection layer 3 and the side walls of the first insulating layer 9 is etched away to form a first contact layer 61 and a second contact layer 62 separated from each other; the first contact layer 61 is arranged on the side wall of the first electrode 51, and the second contact layer 62 is arranged on the side wall of the second electrode 52, and the first contact layers 61 arranged on the first electrodes 51 of different transistors are disconnected from each other, and the second contact layers 62 arranged on the second electrodes 52 of different transistors are disconnected from each other;

The contact layer 6 is laterally etched in a direction parallel to the substrate 1, and the thickness of the contact layer 6 covering the side wall of the conductive layer 12 is reduced (i.e., the thickness of the first contact layer 61 and the second contact layer 62 is reduced), and space is reserved for the subsequent formation of the semiconductor layer, the gate insulating layer and the gate electrode, as shown in Figures 12A, 12B and 12C, wherein Figure 12A is a plan view after etching the contact layer 6 (wherein the capacitor region 100 is a top view, and the area outside the capacitor region 100 is a top view of the film layer where the conductive layer 12 is located), Figure 12B is a cross-sectional view along the aa' direction in Figure 12A, and Figure 12C is a cross-sectional view along the cc' direction in Figure 12A. It can be seen that the side wall of the protective layer 3 is not covered with the contact layer 6, and the thickness of the contact layer 6 covering the side wall of the conductive layer 12 is reduced in a direction parallel to the substrate 1.

In some embodiments, dry etching or wet etching may be used to remove the contact layer 6 covering the sidewalls of the protection layer 3 and the sidewalls of the first insulating layer 9 .

In some embodiments, wet etching may be used to reduce the thickness of the contact layer 6 .

12) The protective layer 3 is laterally etched to a preset thickness in a direction away from the second through hole K2, so that the caliber of the area where the second through hole K2 is located in the conductive layer 12 is larger than the caliber of the area where the second through hole K2 is located in the first insulating layer 9, as shown in Figures 13A and 13B, wherein Figure 13A is a plan view after etching the protective layer 3 (wherein the capacitor area 100 is a top view, and the area outside the capacitor area 100 is a top view of the film layer where the conductive layer 12 is located), and Figure 13B is a cross-sectional view along the cc' direction in Figure 13A. It can be seen that in the cc' direction, the caliber of the area K21 where the second through hole K2 is located in the first insulating layer 9 is smaller than the caliber of the area K22 where the second through hole K2 is located in the conductive layer 12, so as to facilitate the subsequent deposition of the sacrificial layer film to retain part of the sacrificial layer film to protect the semiconductor layer and the gate insulating layer. When the protective layer 3 is laterally etched, the etching can be performed to expose the third insulating layer 15.

In some embodiments, phosphoric acid or the like may be used to etch the protective layer 3 .

13) A semiconductor layer 23 , a gate insulating layer 24 and a sacrificial layer 25 are formed.

The forming of the semiconductor layer 23, the gate insulating layer 24 and the sacrificial layer 25 may include:

A semiconductor film and a gate insulating film are sequentially deposited on the side wall of the second through hole K2 to form a semiconductor layer 23 and a gate insulating layer 24;

A sacrificial layer thin film is deposited in the second through hole K2 to form a sacrificial layer 25 . The sacrificial layer 25 can fill the second through hole K2, or only fill the area where the orthographic projection of the second through hole K2 in the area K22 of the conductive layer 12 is located outside the orthographic projection of the area K21 of the second through hole K2 in the first insulating layer 9. The sacrificial layer 25 located in the area K22 of the second through hole K2 in the conductive layer 12 is thicker, so as to protect the semiconductor layer 23 located in the area of the second through hole K2 in the conductive layer 12 when the conductor layer 23 and the gate insulating layer 24 located in the area of the second through hole K2 in the first insulating layer 9 are subsequently removed, as shown in Figures 14A, 14B and 14C, wherein Figure 14A is a plan schematic diagram after the semiconductor layer 23, the gate insulating layer 24 and the sacrificial layer 25 are formed (wherein the capacitor area 100 is a top view, and the area outside the capacitor area 100 is a top view of the film layer where the conductive layer 12 is located), Figure 14B is a cross-sectional view along the aa' direction in Figure 14A, and Figure 14C is a cross-sectional view along the cc' direction in Figure 14A.

In some embodiments, the material of the sacrificial layer film can be a conductive material, for example, the same as the material of the subsequent gate electrode film, so that after etching away the semiconductor layer 23 and the gate insulating layer 24 located in the region of the second through hole K2 in the first insulating layer 9, the sacrificial layer 25 does not need to be removed before depositing the gate electrode film, and the gate electrode can be directly deposited. The sacrificial layer 25 and the subsequently deposited gate electrode film together serve as the gate electrode of the final device. However, the disclosed embodiment is not limited thereto, and the material of the sacrificial layer film may be different from that of the gate electrode film. After the semiconductor layer 23 and the gate insulating layer 24 located in the region of the second through hole K2 in the first insulating layer 9 are removed by etching, the sacrificial layer 25 may be removed before the gate electrode film is deposited.

In some embodiments, the semiconductor film, the gate insulating film and the sacrificial layer film may be deposited by ALD.

In an exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap less than 1.65 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide does not exclude compounds containing other elements, such as N, Si, etc., nor does it exclude the presence of other small amounts of doping elements.

In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

These materials have a wider band gap and a lower leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 ^-15 A, thereby improving the operating performance of the dynamic memory.

The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

In an exemplary embodiment of the present disclosure, the material of the gate insulating layer 24 may include one or more layers of High-K dielectric material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO ₂ ) and other high-K materials.

In some embodiments, the sacrificial layer film includes but is not limited to at least one of the following:

For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

Alternatively, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO) and other conductive metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other conductive metal nitride materials;

Alternatively, it may be polysilicon, silicon, germanium, silicon germanium, etc. which are conductive after being doped.

14) removing the semiconductor layer 23 and the gate insulating layer 24 located in the region K21 of the second through hole K2 in the first insulating layer 9;

The semiconductor layer 23 and the gate insulating layer 24 located in the region K21 of the second through hole K2 on the first insulating layer 9 are removed. 24 can include:

The sacrificial layer 25 located on the side wall of the second through hole K2 is etched along a direction perpendicular to the substrate 1 to expose the gate insulating layer 24 located in the region K21 of the second through hole K2 in the first insulating layer 9, but the gate insulating layer 24 located in the region K22 of the second through hole K2 in the conductive layer 12 is not exposed, that is, the sacrificial layer 25 located in the region K22 of the second through hole K2 in the conductive layer 12 is not completely etched away, and the gate insulating layer 24 located in the region K22 of the second through hole K2 in the conductive layer 12 is protected, as shown in FIG. 15A , which is a cross-sectional view along the aa′ direction after etching the sacrificial layer 25; in some embodiments, the sacrificial layer 25 may be etched by dry etching or wet etching;

By utilizing wet etching, a solution having a slow etching rate for the sacrificial layer 25 and a fast etching rate (greater than the etching rate for the sacrificial layer 25) for the semiconductor layer 23 and the gate insulating layer 24 is used for etching, that is, a solution having a high etching selectivity ratio for the semiconductor layer 23 and the gate insulating layer 24 and the sacrificial layer 25 is selected for etching, so that the semiconductor layer 23 and the gate insulating layer 24 located in the area K21 of the first insulating layer 9 where the second through hole K2 is located can be completely etched away, as shown in FIGS. 15B and 15C , wherein FIG. 15B is a cross-sectional view along the aa’ direction after etching the semiconductor layer 23 and the gate insulating layer 24, and FIG. 15C is a cross-sectional view along the cc’ direction after etching the semiconductor layer 23 and the gate insulating layer 24.

For example, when the sacrificial layer is ITO, the semiconductor layer 23 is IGZO, and the gate insulating layer 24 is Al ₂ O ₃ , a dilute hydrochloric acid (HCl) solution with a high etching selectivity (the solution can also be a strong acid such as acetic acid, perchloric acid, etc.) can be used for etching. Dilute hydrochloric acid can react with Al ₂ O ₃ , so Al ₂ O ₃ can be removed first, and then react with the IGZO film to etch away the IGZO. Under room temperature conditions, the etching rate of HCl in the range of 1% to 20% by mass for the ITO film is very slow, and the etching rate for the IGZO film is particularly fast. The etching selectivity of HCl for IGZO/ITO can reach 100:1 to 1000:1, and the IGZO/Al ₂ O ₃ film located in the area K21 of the second through hole K2 in the first insulating layer 9 is completely etched away.

The solution provided in this embodiment can prevent the formation of a parasitic transistor in the semiconductor layer located in the area K21 of the first insulating layer 9 where the second through hole K2 is located, thereby avoiding leakage caused by the parasitic transistor.

15) forming a fourth insulating layer 16 and a gate electrode 26;

The forming of the fourth insulating layer 16 and the gate electrode 26 may include:

Depositing a fourth insulating film on the side wall of the second through hole K2 to form a fourth insulating layer 16;

Etching and removing the fourth insulating layer 16 covering the side of the sacrificial layer 25 facing the second through hole K2 and the fourth insulating layer 16 located in the region of the second through hole K2 in the first insulating layer 9;

A gate electrode film is deposited in the second through hole K2 to form a gate electrode 26 filling the second through hole K2, as shown in FIG16A and FIG16B , wherein FIG16A is a schematic cross-sectional view along the aa' direction after the gate electrode 26 is formed, and FIG16B is a schematic cross-sectional view along the cc' direction after the gate electrode 26 is formed. The gate electrodes 26 of the transistors in the same column are connected to form a word line 40.

In some embodiments, the fourth insulating film may be deposited by ALD.

In some embodiments, the fourth insulating layer 16 may be removed by dry etching.

In some embodiments, the fourth insulating film includes but is not limited to SiO2.

In some embodiments, the fourth insulating film may be made of the same material as the gate insulating film.

In some embodiments, the gate electrode film may include but is not limited to at least one of the following: for example, containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

Alternatively, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO) and other conductive metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other conductive metal nitride materials;

Alternatively, it may be polysilicon, silicon, germanium, silicon germanium, etc. which are conductive after being doped.

In order to prevent the semiconductor layer 23 and the gate insulating layer 24 located in the area 22 of the second through hole K2 in the conductive layer 12 from being over-etched during wet etching, thereby exposing the conductive layer 12 and causing a short circuit between the gate electrode 26 and the conductive layer 12 (for example, a short circuit between the gate electrode 26 and the bit line 30) when the gate electrode 26 is directly deposited subsequently, in the present embodiment, a fourth insulating layer 16 is used for isolation to avoid the risk of short circuit.

The solution provided in this embodiment can effectively remove the parasitic transistor and prevent leakage by providing a contact layer between the semiconductor layer and the first electrode and the second electrode, and by removing the semiconductor layer located on the side wall of the first insulating layer. In addition, by providing a fourth insulating layer, short circuits between capacitors, word lines, and bit lines can be avoided, thereby improving yield.

The above manufacturing process is only an example, but the embodiments of the present disclosure are not limited thereto and can be manufactured in other ways. For example, in step 14), the sacrificial layer 25 can be first etched by dry etching, and then the thickness of the sacrificial layer 25 along the direction perpendicular to the substrate 1 can be thinned by wet etching, and then the conductor layer 23 and the gate insulating layer 24 located in the area K21 of the second through hole K2 in the first insulating layer 9 can be removed by dry etching. At this time, the fourth insulating layer 16 may not be formed.

The present disclosure also provides an electronic device, including the 3D stacked semiconductor device of the above embodiment. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

FIG17 is a flow chart of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment. As shown in FIG17 , the present disclosure provides a method for manufacturing a 3D stacked semiconductor device, including:

Step 1701, providing a substrate, and alternately depositing a first insulating film and a conductive film on the substrate in sequence, and patterning to form a stacked structure, wherein the stacked structure includes a stack of alternately arranged first insulating layers and conductive layers, and the conductive layer includes a conductive portion extending along a first direction;

Step 1702, etching the sidewalls of the conductive layer to a preset thickness along a direction parallel to the substrate to form a protection layer covering the sidewalls of the conductive layer;

Step 1703, forming a through hole penetrating the stacked structure in a direction perpendicular to the substrate, and etching the conductive layer in a direction away from the through hole, so that on a plane parallel to the substrate, along the first direction, the orthographic projection of a region of the through hole located in the first insulating layer falls within the orthographic projection of a region of the through hole located in the conductive layer, and the through hole enables the conductive portion to form a first electrode and a second electrode separated from each other; and the sidewalls of the through hole expose each of the conductive layer and the protective layer;

Step 1704, depositing a contact film in the through hole to form a contact layer, etching and removing the contact layer covering the side wall of the protection layer, and disconnecting the contact layers covering the side walls of different conductive layers from each other, and disconnecting the contact layer covering the side wall of the first electrode and the contact layer covering the side wall of the second electrode from each other;

Step 1705, etching the protection layer in a direction away from the through hole, so that on a plane parallel to the substrate, the orthographic projection of the through hole located in the first insulating layer falls within the orthographic projection of the through hole located in the conductive layer;

Step 1706: forming a word line extending in a direction perpendicular to the substrate in the through hole, a gate insulating layer surrounding the word line, and a semiconductor layer surrounding the gate insulating layer, wherein the semiconductor layer is in contact with the contact layer.

In this embodiment, the structure, materials, related parameters and detailed manufacturing process of each film layer have been described in detail in the previous embodiments and will not be repeated here.

The method for manufacturing a 3D stacked semiconductor device provided in this embodiment forms a contact layer, thereby reducing the contact resistance between the semiconductor layer and the first electrode and the second electrode, thereby improving the device performance.

In some embodiments, etching the protection layer in a direction away from the through hole comprises: etching the protection layer in a direction away from the through hole The protective layer is etched in a direction so that the protective layer arranged on the side wall of the first electrode is disconnected from the protective layer arranged on the side wall of the second electrode.

In some embodiments, the word line extending in a direction perpendicular to the substrate is formed in the through hole, and the gate insulating layer surrounding the word line and the semiconductor layer surrounding the gate insulating layer may include:

Depositing a semiconductor film, a gate insulating film and a sacrificial layer film in the through hole in sequence to form the semiconductor layer, the gate insulating layer and the sacrificial layer;

Etching a portion of the sacrificial layer in the through hole so that the sidewall of the through hole located in the first insulating layer exposes the first insulating layer, and the sidewall of the through hole located in the conductive layer exposes the sacrificial layer; etching and removing the semiconductor layer and the gate insulating layer in the through hole of the first insulating layer;

Depositing a fourth insulating film in the through hole to form a fourth insulating layer, and etching the fourth insulating layer covering a side of the sacrificial layer facing the through hole;

A gate electrode film is deposited in the through hole, and the gate electrode film fills the through hole to form the word line.

The solution provided in this embodiment can remove the semiconductor layer between transistors, eliminate parasitic transistors, and avoid leakage and failure between devices.

Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims (14)

A 3D stacked semiconductor device, comprising: Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate; A word line, passing through the transistors of different layers; The transistor includes a first electrode, a second electrode, and a semiconductor layer surrounding the side wall of the word line; a first contact layer arranged between the first electrode and the semiconductor layer and connected to the first electrode and the semiconductor layer, and a second contact layer arranged between the second electrode and the semiconductor layer and connected to the second electrode and the semiconductor layer; the multiple first contact layers of the multiple transistors are arranged at intervals in the direction in which the word line extends, and the multiple second contact layers of the multiple transistors are arranged at intervals in the direction in which the word line extends. The 3D stacked semiconductor device according to claim 1, wherein the plurality of semiconductor layers of the plurality of transistors are spaced apart in an extending direction of the word line. The 3D stacked semiconductor device according to claim 2, wherein the semiconductor device further comprises: A first insulating layer and a conductive layer are alternately distributed from bottom to top in a direction vertical to the substrate; a through hole penetrating the first insulating layer and the conductive layer, wherein the word line, the gate insulating layer surrounding the sidewall of the word line, the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer, and the plurality of first contact layers and the plurality of second contact layers arranged in different regions of the sidewalls of the plurality of semiconductor layers are sequentially distributed in the through hole from inside to outside; The plurality of semiconductor layers extend in a direction vertical to the substrate and are disconnected at the sidewall of the first insulating layer; The conductive layer includes the first electrode and the second electrode spaced apart from each other. The 3D stacked semiconductor device according to claim 3, wherein the diameter of the through hole corresponding to the first region of the conductive layer is larger than the diameter of the through hole corresponding to the second region of the first insulating layer; The conductive layer only exposes the side wall in the through hole, and the first insulating layer exposes the side wall and partial areas of the upper and lower surfaces in the through hole; The first contact layer is at least distributed on the side wall of the conductive layer, and the second contact layer is at least distributed on the side wall of the conductive layer. The 3D stacked semiconductor device according to claim 4, wherein the first contact layer is also distributed in partial areas of the upper and lower surfaces of the first insulating layer exposed in the through hole and is not distributed on the side walls of the first insulating layer; the second contact layer is also distributed in partial areas of the upper and lower surfaces of the first insulating layer exposed in the through hole and is not distributed on the side walls of the first insulating layer. The 3D stacked semiconductor device according to claim 4, wherein the semiconductor layer is distributed on a surface of the first contact layer and a surface of the second contact layer and is not distributed on a side wall of the first insulating layer. The 3D stacked semiconductor device according to claim 6, wherein the semiconductor layer is also distributed in partial areas of upper and lower surfaces of the first insulating layer exposed in the through hole. The 3D stacked semiconductor device according to claim 4, wherein the gate insulating layer is distributed on the surface of each of the semiconductor layers and is not distributed on the sidewalls of the first insulating layer, and the gate insulating layers on the surfaces of the semiconductor layers of different layers are spaced apart from each other. The 3D stacked semiconductor device according to claim 4, wherein the contact area between the conductive layer and the first insulating layer is laterally etched to form a recessed area along a direction parallel to the substrate, and the recessed area is provided with a fourth insulating layer, and the fourth insulating layer isolates the word line and the first contact layer, the second contact layer, and the semiconductor layer. According to any one of claims 3 to 9, the 3D stacked semiconductor device further comprises: a protective layer arranged on the side wall of the conductive layer; the protective layer arranged on the side wall of the first electrode is disconnected from the protective layer arranged on the side wall of the second electrode; the protective layers on the side walls on the same side of the first electrodes of transistors in different layers are connected to form an integrated structure; the protective layers on the side walls on the same side of the second electrodes of transistors in different layers are connected to form an integrated structure. An electronic device comprising the 3D stacked semiconductor device according to any one of claims 1 to 10. A method for manufacturing a 3D stacked semiconductor device, comprising: Providing a substrate, depositing a first insulating film and a conductive film alternately on the substrate in sequence, and patterning to form a stacked structure, wherein the stacked structure comprises a stack of alternately arranged first insulating layers and conductive layers, wherein the conductive layers comprise conductive portions extending along a first direction; Etching the sidewall of the conductive layer to a preset thickness in a direction parallel to the substrate to form a protective layer covering the sidewall of the conductive layer; A through hole is formed penetrating the stacked structure in a direction perpendicular to the substrate, and the conductive layer is etched in a direction away from the through hole, so that on a plane parallel to the substrate, along the first direction, the orthographic projection of a region of the through hole located in the first insulating layer falls within the orthographic projection of a region of the through hole located in the conductive layer, and the through hole enables the conductive portion to form a first electrode and a second electrode separated from each other; and the sidewall of the through hole exposes each of the conductive layer and the protective layer; Depositing a contact film in the through hole to form a contact layer, etching and removing the contact layer covering the side wall of the protection layer, and disconnecting the contact layers covering the side walls of different conductive layers from each other, and disconnecting the contact layer covering the side wall of the first electrode and the contact layer covering the side wall of the second electrode from each other; Etching the protection layer in a direction away from the through hole so that, on a plane parallel to the substrate, an orthographic projection of the through hole located in the first insulating layer falls within an orthographic projection of the through hole located in the conductive layer; A word line extending in a direction perpendicular to the substrate is formed in the through hole, a gate insulating layer surrounding the word line, and a semiconductor layer surrounding the gate insulating layer, wherein the semiconductor layer is connected to the contact layer. The method for manufacturing a semiconductor device according to claim 12, wherein etching the protective layer in a direction away from the through hole comprises: etching the protective layer in a direction away from the through hole so that the protective layer arranged on the side wall of the first electrode is disconnected from the protective layer arranged on the side wall of the second electrode. The method for manufacturing a semiconductor device according to claim 12, wherein the word line extending in a direction perpendicular to the substrate is formed in the through hole, and the gate insulating layer surrounding the word line and the semiconductor layer surrounding the gate insulating layer include: Depositing a semiconductor film, a gate insulating film and a sacrificial layer film in the through hole in sequence to form the semiconductor layer, the gate insulating layer and the sacrificial layer; Etching a portion of the sacrificial layer in the through hole so that the sidewall of the through hole located in the first insulating layer exposes the first insulating layer, and the sidewall of the through hole located in the conductive layer exposes the sacrificial layer; etching and removing the semiconductor layer and the gate insulating layer in the through hole of the first insulating layer; Depositing a fourth insulating film in the through hole to form a fourth insulating layer, and etching the fourth insulating layer covering a side of the sacrificial layer facing the through hole; A gate electrode film is deposited in the through hole, and the gate electrode film fills the through hole to form the word line.