WO2024183912A1

WO2024183912A1 - Monolithically integrated schottky barrier diode semiconductor device

Info

Publication number: WO2024183912A1
Application number: PCT/EP2023/055978
Authority: WO
Inventors: Tomasz SLEDZIEWSKI; Samir Mouhoubi
Original assignee: Huawei Digital Power Technologies Co., Ltd.
Priority date: 2023-03-09
Filing date: 2023-03-09
Publication date: 2024-09-12

Abstract

The disclosure relates to a monolithically Schottky barrier diode integrated semiconductor device comprising at least one semiconductor cell (100). The at least one semiconductor cell (100) comprises: a substrate (1); a Schottky section (4, 7) comprising a layer stack of a current spreading layer (4) and a mesa Schottky contact region (7); a trench (111) formed next to the Schottky section (4, 7) along a first direction (104); a planar channel section (4, 5, 6) formed below the trench (111) on both sides of the Schottky section (4, 7); a body contact region (8) formed in the Schottky section (4, 7) and the planar channel section (4, 5, 6) along a second direction (107). The body contact region (8) is electrically connecting the trench body region (5) of the planar channel section (5, 6). Two or more planar carrier channels (114a, 114b) are formed in each planar channel section (4, 5, 6) and two or more Schottky barrier diodes (116a, 116b) are formed in the Schottky section (4, 7).

Description

MONOLITH ICALLY INTEGRATED SCHOTTKY BARRIER DIODE SEMICONDUCTOR DEVICE

TECHNICAL FIELD

The disclosure relates to the field of power semiconductor devices, in particular trench-gate semiconductor devices and elementary cells of such devices as well as methods for their production. In particular, the disclosure relates to a monolithically Schottky barrier diode integrated semiconductor device and method for manufacturing thereof. For example, the disclosure also relates to a silicon carbide MOS device with split gate and integrated Schottky diode.

BACKGROUND

A feature of the power MOSFET is the presence of a pn-junction, so-called body diode, which can be used for current conduction (freewheeling) when the polarity of the drain-source voltage is reversed compared to the blocking state, which may happen for example in inductively switching circuits. In this particular case, MOSFET, which in its nature is a unipolar device, enters into a bipolar conduction mode. Usage of the parasitic body diode enables elimination of external freewheeling diodes from a circuit and decreases a total application cost, which is especially important in case of a costly silicon carbide (SiC) technology. However, in case of SiC, utilization of the body diode for freewheeling may lead to serious device reliability issues. The presence of minority carriers (bipolar conduction) at concentrations above a certain threshold concentration level results in so-called bipolar degradation. Electron-hole recombination induces Shockley stacking faults (SSF) from basal plane dislocations (BPD) under forward bipolar operation. The SSFs expand further with higher currents or stress and cause degradation of threshold voltage, on-state resistance and current gain of a device.

SUMMARY

This disclosure provides a silicon carbide power device with improved reliability without the problems described above.

Furthermore, an improved MOS device is provided, for example based on SiC technology. Reliability of the device is improved by suppression of freewheeling current conduction through a body diode. The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

The devices and methods will be exemplarily described hereinafter for the SiC MOSFET, but it may also be applicable to other materials, e.g., silicon (Si), gallium nitride (GaN), gallium oxide (Ga2O3) and others, and to other devices, e.g., IGBT.

The described devices and methods are applicable to any power conversion system or architecture using semiconductor power devices. It is applicable when high blocking voltage, high current density and high switching frequency are required. It is applicable to all power electronic systems targeting energy loss, application size and total application cost reduction.

Related products described hereinafter can be power electronics products, particularly DC and AC converters used in photovoltaics, electric vehicles, chargers and on-board chargers, data centers, railway and others.

The following terms, abbreviations and notations will be used:

MOS Metal Oxide Semiconductor

FET Field Effect Transistor

MOSFET Metal Oxide Semiconductor Field Effect Transistor

S Source

D Drain

G Gate

SiC Silicon Carbide

IGBT Insulated Gate Bipolar Junction Transistor

JFET Junction Field Effect Transistor

CSL Current Spreading Layer

SBD Schottky Barrier Diode

SSF Shockley Stacking Faults

BPD Basal Plane Dislocations

Device active area - area which conducts a forward electric current; it is smaller than a device total area; Device total area - can be understood as a chip (die) area; consists of the active area and all peripheries, e.g. an edge termination, scribe lines (dicing streets), contact pads (e.g. a gate electrodegate contact) and others;

Forward electric current - a main electric current flowing through a device during its on-state;

Edge termination - a region extending outside of the active area having the effect to reduce an electric field in outer part of a device;

Source - a region in MOSFET which injects majority carriers during the on-state;

Drain - a region in MOSFET which collects majority carriers during the on-state;

Emitter - a region in IGBT which injects majority carriers during the on-state;

Collector - a region in IGBT which collects majority carriers and injects minority carriers during the on-state;

Majority carriers - electric carriers (electrons or holes) which dominate in the forward electric current conduction; their density is much bigger than the density of minority carriers;

Minority carriers - electric carriers (electrons or holes) whose density is much lower than the density of the majority carriers;

Gate - a voltage-controlled region in MOSFET or IGBT which switches a device between the on-state and the off-state;

Drift layer - a region in MOSFET or IGBT which conducts the electric current in the on-state and sustains the biggest portion of an applied voltage (blocking voltage) in the off-state (blocking state);

Channel - a region in a body region of MOSFET or in a base region of IGBT to which the electric carriers are injected from the source or from the emitter, respectively, and whose conduction is controlled by the gate; Body region - a region in MOSFET of an opposite doping type to the doping type of the source and drift layer, which contains the channel and which creates a pn-junction with the drift layer;

Base region - a region in IGBT of an opposite doping type to the doping type of the source and drift layer, which contains the channel and which creates a pn-junction with the drift layer;

JFET region - a region between the body regions or base regions or MOSFET or IGBT, respectively; and

CSL - a region below the JFET region having the effect to spread the electric current in order to reduce an on-state resistance.

Herein, power MOSFETs and Schottky diodes are described. The power MOSFET is a key semiconductor power device, in which an electrical current flow is forced by a voltage applied between a drain electrode and a source electrode, and, which is controlled by a voltage applied between a gate electrode and the source electrode.

As described above, a feature of the power MOSFET is the presence of a pn-junction, so- called body diode, which can be used for current conduction (freewheeling) when the polarity of the drain-source voltage is reversed compared to the blocking state, which may happen for example in inductively switching circuits. In this particular case, MOSFET, which in its nature is a unipolar device, enters into a bipolar conduction mode. Usage of the parasitic body diode enables elimination of external freewheeling diodes from a circuit and decreases a total application cost, which can be an issue in case of a costly silicon carbide (SiC) technology.

Due to the bipolar degradation, the body diode of SiC MOSFET is often not recommended for use. Instead, Schottky barrier diode (SBD) can be monolithically integrated with SiC MOSFET, which is less expensive than using an external SiC SBD for freewheeling. In such devices, in order to suppress the operation of the body diode, the SBD has to be made preferential for the current conduction, which is achieved by design and process optimization, particularly by increase of current density and decrease of resistance in the SBD-part of the device. Such solutions are described in this disclosure hereinafter.

The Schottky diode, also known as Schottky barrier diode (SBD), is a semiconductor diode formed by the junction of a semiconductor with a metal. It has a low forward voltage drop and a very fast switching action. When sufficient forward voltage is applied, current flows in the forward direction.

According to a first aspect, the disclosure relates to a monolithically integrated Schottky barrier diode semiconductor device comprising at least one semiconductor cell, the at least one semiconductor cell comprising: a substrate being arranged at a bottom surface of the at least one semiconductor cell; a Schottky section placed above the substrate, the Schottky section comprising a layer stack of a current spreading layer and a mesa Schottky contact region; a trench formed next to the Schottky section and above the substrate along a first direction parallel to the bottom surface, the trench formed on both sides of the Schottky section, the trench comprising a trench bottom and at least one trench side wall; a planar channel section formed above the substrate and below the trench on both sides of the Schottky section, the planar channel section comprising a layer stack of the current spreading layer, a trench body region and a trench source region; wherein the trench body region forms a shield below the trench, the shield covering the trench bottom for protection against high electric fields; a body contact region formed in the Schottky section and the planar channel section along a second direction parallel to the bottom surface, the body contact region electrically connecting the trench body region of the planar channel section; wherein two or more planar carrier channels are formed in each planar channel section and two or more Schottky barrier diodes are formed in the Schottky section.

The above semiconductor device describes how to monolithically integrate a planar-gate MOSFET with SBD. The device is robust against degradation of threshold voltage, on-state resistance and current gain, due to suppression of the body diode operation.

The trench body region can be formed by several subregions of the same type, for example. Each of implanted regions described above can be produced by one or more than one ion implantation shot.

The second direction can be orthogonal to the first direction or can be within an angle between 0 and 90 degrees, for example.

In an exemplary implementation of the semiconductor device, the at least one semiconductor cell comprises: a buffer layer placed on top of the substrate; and a drift layer placed on top of the buffer layer; wherein the Schottky section is placed on top of the drift layer. The buffer layer provides design flexibility. The buffer layer may be a first deposited layer and the drift layer a second deposited layer. The semiconductor cell is not limited to these two layers, it understands that even more layers can be deposited. For example, the drift layer can be decomposed into a plurality of layers which have different characteristics/effects, or different parameters but the same characteristics/effects. In other words, there are basically two layers, the buffer layer and the drift layer, but the number of layers is not limited to 2. There may be other layers having another characteristic or effect than the drift layer and the buffer layer. This provides a high degree of design flexibility when designing the semiconductor cells and the trench-gate planar-gate semiconductor device.

In an exemplary implementation of the semiconductor device, the substrate, the buffer layer, the drift layer, the current spreading layer, the trench source region and the mesa Schottky contact region are of a first semiconductor doping type; and the trench body region and the body contact region are of a second semiconductor doping type.

In an exemplary implementation of the semiconductor device, the trench source region is implanted and self-aligned on the trench body region. This allows implementation for smaller pitch of the device and for reduction of the number of process steps. The trench source region may be directly implanted into the trench body region through a spacer mask, for example.

In an exemplary implementation of the semiconductor device, the current spreading layer is shallower than the trench body region in the planar channel section. Accordingly, the shallower current spreading layer allows higher blocking voltage of the device due to lower electric field at the trench body and/or in the gate oxide.

The term “shallower” means here that the current spreading layer is smaller or thinner than the trench body region in the planar channel section. That means, a thickness of the current spreading layer is less than a thickness of the layer represented by the trench body region. “Shallower” means smaller absolute value at y-axis. For example, when CSL is placed at a depth of 2 urn and the shield reaches the depth of 3 urn, CSL is shallower than the shield.

In an exemplary implementation of the semiconductor device, a first planar carrier channel in each planar channel section is formed between the trench source region and the current spreading layer of a first part of the planar channel section and a second planar carrier channel in each planar channel section is formed between the trench source region and the current spreading layer of a second part of the planar channel section; wherein a Schottky contact is formed on top of the mesa Schottky contact region; and wherein a first Schottky barrier diode is formed by a first part of the Schottky contact and the mesa Schottky contact region of a first part of the Schottky section and a second Schottky barrier diode is formed by a second part of the Schottky contact and the mesa Schottky contact region of a second part of the Schottky section.

A highly integrated semiconductor device where multiple carrier channels and Schottky barrier diodes can be monolithically integrated in one semiconductor cell.

The Schottky contact defines a metal contact; the mesa Schottky contact region defines a semiconductor region. The Schottky barrier diodes are formed by the metal and the semiconductor.

In one exemplary implementation, the semiconductor device can be a Silicon Carbide device, for example.

Such SiC device provides enabling higher switching frequencies and a reduced application size, as compared to silicon. Such SiC device enables lower switching losses and/or lower conduction losses compared to silicon devices rated at a same blocking voltage.

The body contact region may extend in the second direction from the mesa Schottky contact region to the trench body region.

In an exemplary implementation of the semiconductor device, e.g., as described below with respect to Figure 4a, the body contact region is placed in the trench body region between two parts of the trench source region. This provides design flexibility for implementing the body contact region.

In an exemplary implementation of the semiconductor device, e.g., as described below with respect to Figure 4b, the body contact region extends to the at least one trench side wall. This also provides design flexibility for implementing the body contact region.

In an exemplary implementation of the semiconductor device, the body contact region and the trench source region are arranged staggered along the first direction with respect to each other. This also provides design flexibility for implementing the body contact region. In an exemplary implementation of the semiconductor device, e.g., as described below with respect to Figures 5a and 5b, the body contact region forms a stripe-shaped region extending next to and in parallel to the trench source region; and/or the body contact region forms a patterned-shaped region with the trench source region. The shape of the body contacts is drawn as rectangles for exemplary purpose. It has to be understood that any geometrical shape can be used: circles, ovals, hexagons, etc. This also provides design flexibility for implementing the body contact region.

In an exemplary implementation of the semiconductor device, the at least one semiconductor cell comprises: a gate electrode formed in the trench above the planar carrier channels, the gate electrode having an overlay with the trench source region; a first ohmic contact formed in the trench above the trench source region and the body contact region, the first ohmic contact providing a first part of a source contact; and a first Schottky contact formed above the mesa Schottky contact region of a first part of the Schottky section; a second Schottky contact formed above the mesa Schottky contact region of a second part of the Schottky section; a second ohmic contact formed above the body contact region between the first Schottky contact and the second Schottky contact, the second ohmic contact providing a second part of the source contact; and an interlayer dielectric layer electrically separating the gate electrode from the first and second ohmic contacts. This provides monolithically integrated Schottky barrier diodes.

In an exemplary implementation of the semiconductor device, e.g., as described below with respect to Figure 2a, the interlayer dielectric layer is formed in the trench and overlays the mesa Schottky contact region and the body contact region on top of the Schottky section. Such interlayer dielectric layer separates the gate electrode from the ohmic contacts in the planar channel section.

In an exemplary implementation of the semiconductor device, e.g., as described below with respect to Figures 2b and 2c, the interlayer dielectric layer is formed in the trench without overlaying the mesa Schottky contact region and the body contact region on top of the Schottky section. The mesa Schottky contact region and the body contact region on top of the Schottky section have a larger contact area when not being overlayed by the interlayer dielectric layer.

In an exemplary implementation of the semiconductor device, an oxide thickness between the trench source region and the gate is increased over an oxide thickness between the planar carrier channels and the gate. The increased oxide thickness provides smaller gate-source capacitance.

In an exemplary implementation of the semiconductor device, e.g., as described below with respect to Figure 2c, the second ohmic contact is extending onto a portion of the at least one trench side wall of the trench; or the second ohmic contact and the Schottky contact are extending onto a portion of the at least one trench side wall of the trench. Thus, the mesa source region and the mesa Schottky contact region have a larger contact area.

In an exemplary implementation of the semiconductor device, the at least one semiconductor cell is forming a SBD-integrated MOSFET structure; or a doping type of the substrate is of opposite doping type to the doping type of the drift layer, and the at least one semiconductor cell is forming a SBD-integrated IGBT structure. Therefore, from its principle of operation, IGBT offers lower static (conduction) power losses than MOSFET. IGBT enables higher current densities than MOSFET or alternatively higher blocking voltages at the same current densities as MOSFET.

In an exemplary implementation of the semiconductor device, the first semiconductor doping type is an n-type doping and the second semiconductor doping type is a p-type doping; or the first semiconductor doping type is a p-type doping and the second semiconductor doping type is an n-type doping. This offers design flexibility, in particular for implementing CMOS logic components.

According to a second aspect, the disclosure relates to a method for producing at least one semiconductor cell of a monolithically Schottky barrier diode integrated semiconductor device, the method comprising: providing a substrate arranged at a bottom surface of the at least one semiconductor cell; placing a buffer layer on top of the substrate; placing a drift layer on top of the buffer layer; forming a Schottky section above the substrate, the Schottky section comprising a layer stack of a current spreading layer and a mesa Schottky contact region; forming a trench next to the Schottky section and above the substrate along a first direction parallel to the bottom surface, the trench on both sides of the Schottky section, the trench comprising a trench bottom and at least one trench side wall; forming a planar channel section above the substrate and below the trench on both sides of the Schottky section, the planar channel section comprising a layer stack of the current spreading layer, a trench body region and a trench source region; forming a body contact region in the Schottky section and the planar channel section along a second direction parallel to the bottom surface, the body contact region electrically connecting the trench body region of the planar channel section; and forming two or more planar carrier channels in each planar channel section and forming two or more Schottky barrier diodes in the Schottky section.

Such method allows producing a reliable semiconductor device because it is prevented from bipolar degradation by using SBD.

One way of producing body contact region can be to etch trench I re-grow semiconductor I planarize, but the preferred solution is just to implant the body contact region, which does not require any trench etching.

In an exemplary implementation of the method, the trench source region is formed self-aligned on the trench body region by using a spacer process. Due to the self-aligned processing, the number of process steps and thus the manufacturing complexity can be reduced.

In an exemplary implementation of the method, the method comprises: forming a gate electrode in the trench above the planar carrier channels, the gate electrode having an overlay with the trench source region; forming a first ohmic contact in the trench above the trench source region and the body contact region, the first ohmic contact providing a first part of a source contact; forming a second ohmic contact above the body contact region, the second ohmic contact providing a second part of the source contact; and forming an interlayer dielectric layer electrically separating the gate electrode from the first and second ohmic contacts.

Such method allows to separate the gate electrode from the ohmic contacts in the planar channel section.

In an exemplary implementation of the method, the gate electrode is formed self-aligned in the trench by using a spacer process; wherein the interlayer dielectric layer is formed self-aligned by using a thermal oxidation process; and wherein the first ohmic contact and the second ohmic contact are formed self-aligned by using a selective silicidation process. The number of process steps can be reduced and that the cell pitch can be also reduced. BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the disclosure will be described with respect to the following figures, in which:

Fig. 1 shows a 3D structure of a semiconductor cell 100 of a monolithically Schottky barrier diode integrated semiconductor device according to the disclosure;

Fig. 2a shows a 3D structure of the semiconductor cell 100 with an interlayer dielectric layer (ILD) according to a first example;

Fig. 2b shows a 3D structure of the semiconductor cell 100 with an interlayer dielectric layer (ILD) according to a second example;

Fig. 2c shows a 3D structure of the semiconductor cell 100 with an interlayer dielectric layer (ILD) according to a third example;

Fig. 3 shows a 3D structure of a first embodiment of the semiconductor cell 100;

Fig. 4a shows a 3D structure of a second embodiment of the semiconductor cell 100;

Fig. 4b shows a 3D structure of a third embodiment of the semiconductor cell 100;

Fig. 5a shows a 3D structure of a fourth embodiment of the semiconductor cell 100; and

Fig. 5b shows a 3D structure of a fifth embodiment of the semiconductor cell 100.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims. It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

The semiconductor devices described herein may be implemented in various applications, e.g., in power conversion devices for automotive and industrial applications. The described semiconductor devices may be applied in integrated circuits and/or modules and power applications and may be manufactured according to various technologies. For example, the semiconductor devices may be utilized in logic integrated circuits, power modules, analog integrated circuits, mixed signal integrated circuits, optical circuits, memory circuits and/or integrated passives.

In the following Figures reference signs are either illustrated by arrows pointing to the respective parts or regions of the device or within parentheses at the respective regions of the device. This representation of reference signs has been chosen for a better illustration of the devices, in order to avoid long arrows pointing through large parts of the pictures.

Fig. 1 shows a 3D structure of a semiconductor cell 100 of a monolithically Schottky barrier diode integrated semiconductor device according to the disclosure.

The monolithically Schottky barrier diode integrated semiconductor device comprises at least one semiconductor cell 100 as shown in Figure 1.

The semiconductor cell 100 comprises a substrate 1 being arranged at a bottom surface 101 of the at least one semiconductor cell 100.

The semiconductor cell 100 comprises a Schottky section 4, 7 placed above the substrate 1. The Schottky section 4, 7 comprises a layer stack of a current spreading layer 4 and a mesa Schottky contact region 7.

The semiconductor cell 100 comprises a trench 111 formed next to the Schottky section 4, 7 and above the substrate 1 along a first direction 104 parallel to the bottom surface 101. The trench 111 is formed on both sides of the Schottky section 4, 7. The trench 111 comprises a trench bottom 111a and at least one trench side wall 111b.

The semiconductor cell 100 comprises a planar channel section 4, 5, 6 formed above the substrate 1 and below the trench 111 on both sides of the Schottky section 4, 7. The planar channel section 4, 5, 6 comprises a layer stack of the current spreading layer 4, a trench body region 5 and a trench source region 6. The trench body region 5 forms a shield below the trench 111. This shield is covering the trench bottom 111a for protection against high electric fields.

The semiconductor cell 100 comprises a body contact region 8 formed in the Schottky section 4, 7 and the planar channel section 4, 5, 6 along a second direction 107 parallel to the bottom surface 101. The body contact region 8 is electrically connecting the trench body region 5 of the planar channel section 4, 5, 6.

As can be seen from Figure 1 , multiple planar carrier channels 114a, 114b are formed in each planar channel section 4, 5, 6 and multiple Schottky barrier diodes 116a, 116b are formed in the Schottky section 4, 7.

The semiconductor cells 100 as shown in Figure 1 can be placed side-by-side with each other (in the second (x) direction 107 and/or in the first (z) direction 104) to form the monolithically Schottky barrier diode integrated semiconductor device. Depending on the illustration, the trench 111 can be formed at the sides of each semiconductor cell 100 as shown in Figure 1 or the trench 111 can be formed in the middle section of each semiconductor cell 100 (not shown in Figure 1).

The trench body region 5 can be formed by several subregions of the same type, for example. Each of implanted regions described above can be produced by one or more than one ion implantation shot. The second direction 107 can be orthogonal to the first direction 104 as shown in the example of Figure 1 or it can be within an angle between 0 and 90 degrees.

The semiconductor cell 100 comprises a buffer layer 2 placed on top of the substrate 1 ; and a drift layer 3 placed on top of the buffer layer 2. The Schottky section 4, 7 can be placed on top of the drift layer 3 as shown in Figure 1. The substrate 1 , the buffer layer 2, the drift layer 3, the current spreading layer 4, the trench source region 6, and the mesa Schottky contact region 7 can be of a first semiconductor doping type, e.g., an n-doping type as shown in Figure 1. The trench body region 5 and the body contact region 8 can be of a second semiconductor doping type, e.g., a p-doping type as shown in Figure 1. In Figure 1 and the other Figures the reference signs of the respective layers are put in parentheses after the first or second semiconductor doping type.

The trench source region 6 can be implanted into the trench body region 5 as shown in Figure 1 . The trench source region 6 may be directly implanted into the trench body region 5 through a spacer mask, for example.

As shown in Figure 1 , the current spreading layer 4 may be deeper than the trench body region 5 in the planar channel section 4, 5, 6.

The term “deeper” means here that the current spreading layer 4 is larger or thicker than the trench body region 5. That means, a thickness of the current spreading layer 4 is greater than a thickness of the layer represented by the trench body region 5, as can be seen from Figure 1.

A first planar carrier channel 114a in each planar channel section 4, 5, 6 may be formed between the trench source region 6 and the current spreading layer 4 of a first part of each planar channel section 4, 5, 6 and a second planar carrier channel 114b in each planar channel section 4, 5, 6 may be formed between the trench source region 6 and the current spreading layer 4 of a second part of each planar channel section 4, 5, 6 as can be seen from Figure 1.

Schottky contacts 201 , 202 may be formed on top of the mesa Schottky contact region 7.

A first Schottky barrier diode 116a may be formed by a first part of the Schottky contact 201 and the mesa Schottky contact region 7 of a first part of the Schottky section 4, 7. A second Schottky barrier diode 116b may be formed by a second part of the Schottky contact 202 and the mesa Schottky contact region 7 of a second part of the Schottky section 4, 7.

The Schottky contacts 201 , 202 define metal contacts; the mesa Schottky contact region 7 defines a semiconductor region. The Schottky barrier diodes are formed by the metal and the semiconductor. In one exemplary implementation, the semiconductor device can be a Silicon Carbide device.

The body contact region 8 may extend in the second direction 107 from the mesa Schottky contact region 7 to the trench body region 5.

The semiconductor cell 100 may form an SBD-integrated MOSFET structure. Alternatively, the semiconductor cell 100 may form an SBD-integrated IGBT structure. For the SBD-integrated IGBT structure, the doping of the substrate is opposite to the doping of the drift layer. For IGBT the substrate doping is opposite to the substrate doping of MOSFET.

In one example, the first semiconductor doping type can be an n-type doping and the second semiconductor doping type can be a p-type doping. In an alternative example, the first semiconductor doping type can be a p-type doping and the second semiconductor doping type can be an n-type doping.

The semiconductor cell 100 shown in Figure 1 may be produced by a method comprising the following process steps:

1) providing a substrate 1 arranged at a bottom surface 101 of the at least one semiconductor cell 100;

2) placing a buffer layer 2 on top of the substrate 1 ;

3) placing a drift layer 3 on top of the buffer layer 2;

4) forming a Schottky section 4, 7 above the substrate 1 , the Schottky section 4, 7 comprising a layer stack of a current spreading layer 4 and a mesa Schottky contact region 7;

5) forming a trench 111 next to the Schottky section 4, 7 and above the substrate 1 along a first direction 104 parallel to the bottom surface 101 , the trench 111 on both sides of the Schottky section 4, 7, the trench 111 comprising a trench bottom 111a and at least one trench side wall 111b;

6) forming a planar channel section 4, 5, 6 above the substrate 1 and below the trench 111 on both sides of the Schottky section 4, 7, the planar channel section comprising a layer stack of the current spreading layer 4, a trench body region 5 and a trench source region 6; 7) forming a body contact region 8 in the Schottky section 4, 7 and the planar channel section 4, 5, 6 along a second direction 107 parallel to the bottom surface 101 , the body contact region 8 electrically connecting the trench body region 5 of the planar channel section 4, 5, 6; and

8) forming a plurality of planar carrier channels 114a, 114b in each planar channel section 4, 5, 6 and forming a plurality of Schottky barrier diodes 116a, 116b in the Schottky section 4, 7.

One way of producing body contact region 8 can be to etch trench I re-grow semiconductor I planarize, but the preferred solution is just to implant region 8, which does not require any trench etching.

The trench source region 6 may be formed self-aligned on the trench body region 5 by using a spacer process.

The above method may comprise the following additional process steps:

9) forming a gate electrode G in the trench 111 above the planar carrier channels 114a, 114b, e.g., as shown in Figures 2a, 2b and 2c, the gate electrode G having an overlay with the trench source region 6;

10) forming a first ohmic contact Q1 in the trench 111 above the trench source region 6 and the body contact region 8, the first ohmic contact Q1 providing a first part of a source contact;

11) forming a second ohmic contact Q2 above the body contact region 8, the second ohmic contact Q2 providing a second part of the source contact; and

12) forming an interlayer dielectric layer ILD electrically separating the gate electrode G from the first and second ohmic contacts Q1 , Q2.

The gate electrode G may be formed self-aligned in the trench 111 by using a spacer process.

The interlayer dielectric layer ILD may be formed self-aligned by using a thermal oxidation process. The first ohmic contact Q1 and the second ohmic contact Q2 may be formed self-aligned by using a selective silicidation process.

Further details of a specific implementation of the above production method are described below with respect to Figure 3.

Fig. 2a shows a 3D structure of the semiconductor cell 100 with an interlayer dielectric layer (ILD) according to a first example.

The semiconductor cell 100 may correspond to the semiconductor cell 100 described above with respect to Figure 1 . In contrast to Figure 1 , Figure 2a additionally illustrates the interlayer dielectric ILD and the ohmic contacts and the Schottky contacts 201 , 202 of the semiconductor cell 100. The ILD layer ILD may be formed by deposition and overlays the mesa.

As can be seen from Figure 2a, the semiconductor cell 100 comprises a gate electrode G formed in the trench 111 (as shown in Figure 1) above the planar carrier channels 114a, 114b (shown in Figure 1). The gate electrode G has an overlay with the trench source region 6.

The semiconductor cell 100 comprises a first ohmic contact Q1 formed in the trench 111 above the trench source region 6 and the body contact region 8. The first ohmic contact Q1 is providing a first part of a source contact.

The semiconductor cell 100 comprises a first Schottky contact 201 formed above the mesa Schottky contact region 7 of a first part of the Schottky section 4, 7.

The semiconductor cell 100 comprises a second Schottky contact 202 formed above the mesa Schottky contact region 7 of a second part of the Schottky section 4, 7.

The semiconductor cell 100 comprises a second ohmic contact Q2 formed above the body contact region 8 between the first Schottky contact 201 and the second Schottky contact 202. The second ohmic contact Q2 is providing a second part of the source contact.

The semiconductor cell 100 comprises an interlayer dielectric layer ILD electrically separating the gate electrode G from the first and second ohmic contacts Q1 , Q2. In the example of Figure 2a, the interlayer dielectric layer ILD is formed in the trench 111 and overlays the mesa Schottky contact region 7 and the body contact region 8 on top of the Schottky section 4, 7.

Fig. 2b shows a 3D structure of the semiconductor cell 100 with an interlayer dielectric layer (ILD) according to a second example.

The semiconductor cell 100 may correspond to the semiconductor cell 100 described above with respect to Figure 2a. The interlayer dielectric ILD and the ohmic contacts of the semiconductor cell 100 are illustrated. In contrast to Figure 2a, the interlayer dielectric ILD has a different shape. The ILD layer may be formed by thermal oxidation of the polysilicon gate and has no overlay with the mesa. The oxide thickness above the source regions is increased comparing to the oxide thickness over the channel regions.

As can be seen from Figure 2b, the interlayer dielectric layer ILD may be formed in the trench 111 without overlaying the mesa Schottky contact region 7 and the body contact region 10 on top of the Schottky section 4, 7.

Fig. 2c shows a 3D structure of the semiconductor cell 100 with an interlayer dielectric layer (ILD) according to a third example.

The semiconductor cell 100 may correspond to the semiconductor cell 100 described above with respect to Figure 2b. The interlayer dielectric ILD and the Ohmic contacts of the semiconductor cell 100 are illustrated. In contrast to Figures 2a and 2b, the interlayer dielectric ILD has a different shape. The ILD layer may be formed by thermal oxidation of the polysilicon gate with reduced thickness and has no overlay with the mesa. The oxide thickness between the trench source region 6 and the gate G is increased over an oxide thickness between the planar carrier channels and the gate G.

The second ohmic contact Q2 may extend onto a portion of the at least one trench side wall 111 b of the trench 111 ; or the second ohmic contact Q2 and the Schottky contact 201 , 202 may extend onto a portion of the at least one trench side wall 111b (see Figure 1) of the trench 111. As can be seen from Figure 2c, the interlayer dielectric layer ILD may be formed in the trench 111 without overlaying the mesa Schottky contact region 7 and the body contact region 8 on top of the Schottky section 4, 7.

Fig. 3 shows a 3D structure of a first embodiment of the semiconductor cell 100.

The semiconductor cell shown in Figure 3 may correspond to the semiconductor cell 100 described above with respect to Figure 1. In the first embodiment shown in Figure 3, the semiconductor cell can form an SBD-embedded SiC MOSFET.

In Figure 3, only the semiconductor part of the device is shown. The device may consist of a substrate of a first semiconductor doping type 1 , a buffer layer of a first semiconductor doping type 2, a drift layer of a first semiconductor doping type 3 and a current spreading layer (CSL) of a first semiconductor doping type 4. Furthermore, the device can be composed of a trench body region of a second semiconductor doping type 5, a trench source region of a first semiconductor doping type 6, a mesa Schottky contact region of a first semiconductor doping type 7 and a body contact region of a second semiconductor doping type 8.

The trench body region 5 has an additional effect of a shield, which protects the trench bottom 111a against high electric fields.

The body contact region 8 can be orthogonal to the unit cell direction 104 (see Figure 1) or it can be arranged at an angle to the unit cell direction (z-direction, 104). This angle can be between 0 degrees and 90 degrees, for example. The body contact region 8 connects the trench body region 5 with the mesa body region 8. The unit cell may contain two or more planar 114a, 114b carrier channels. The planar channels 114a, 114b may extend in the trench body regions 5 near the trench bottom 111a between the trench source regions 6 and the CSL 4.

The device can be fabricated according to the following exemplary process flow: a) The buffer layer 2 is deposited on top of the substrate 1 , the drift layer 3 is deposited on top of the buffer layer 2 and the current spreading layer 4 (optional) is formed on top of the drift layer 3. b) The mesa Schottky contact region 7 (optional) is deposited on top of the CSL 4. c) The stripe-shaped body contact region 8 is implanted into the unit cell; alternatively, the body contact region 8 is fabricated by trench etching and epitaxial regrowth and planarization. d) A mask M1 is deposited on top of the semiconductor and patterned, and the trench is etched. e) A mask M2 is deposited on top of the mask M1 and of the semiconductor. f) The trench body region 5 is implanted. g) The masks M1 and M2 are removed and a spacer S1 is fabricated on the sidewalls of the trench. h) The mesa is masked. i) The trench source region 6 is implanted. j) The spacer S1 is removed.

The device can also be fabricated according to the following exemplary process flow (Alternative method): a) The buffer layer 2 is deposited on top of the substrate 1 , the drift layer 3 is deposited on top of the buffer layer 2 and the current spreading layer 4 (optional) is formed on top of the drift layer 3. b) The mesa Schottky contact region 7 (optional) is deposited on top of the CSL 4. c) The stripe-shaped body contact region 8 is implanted into the unit cell; alternatively, the body contact region 8 is fabricated by trench etching and epitaxial regrowth and planarization. d) A mask M1 is deposited on top of the semiconductor and patterned, and the trench is etched. e) A mask M2 is deposited on top of the mask M1 and of the semiconductor. f) The trench body region 5 is implanted. g) A spacer S1 is fabricated on the sidewalls of the trench and the mask Ml on top of the mask M2. h) The trench source region 6 is implanted. i) The spacer S1 is removed.

The buffer layer 2 and the drift layer 3 and the current spreading layer 4 may be deposited, for example using the chemical vapor deposition (CVD).

The CSL 4 is optional; if not present, the region, where the CSL 4 is located, inherits the properties of the drift layer 3. The effect of the CSL 4 is to increase the doping in the JFET region, which is defined between the trench body regions 5, and below the trench body regions 5, in order to decrease the device resistance.

The trench body region 5 and the trench source region 6 may be fabricated by ion implantation, while the body contact region 10 may be fabricated either by ion implantation or by deposition.

The mesa Schottky contact region 7 is optional; if not present, the region, where the mesa Schottky contact region 7 is located, inherits the properties of the CSL 4 or of the drift region 3. The effect of the mesa Schottky contact region 7 is to defined the electrical properties of the Schottky contact.

The mask M1 can be a thick hard mask, made of silicon dioxide or silicon nitride or polysilicon or other material, for example, whose etching selectivity against silicon carbide should be high and whose thickness should be big enough to block the ions implanted for the mesa body region 5.

The mask M2 can be a thin hard and conformal mask, made of silicon dioxide or silicon nitride or polysilicon or other material, for example, which prevents from trench sidewall doping during implantation of the mesa body region 5. The spacer S1 can be made of silicon dioxide or silicon nitride or polysilicon or other material, for example.

The trench body region 5 may be self-aligned on the trench.

The doping concentration of the trench source region 6 should be lower than the doping concentration of the body contact region 8, in order not to compensate its doping. On the other hand, the doping concentration of the source regions should be high enough, in order to fabricate a low-resistivity ohmic contact on top of those regions.

The planar channels can be self-aligned and their length can be decided by a thickness of the spacer S1.

After fabrication of the semiconductor cell 100 shown in Figure 3, the further structures as shown in Figures 2a, 2b and 2c may be produced.

The next part of the fabrication process may include the following steps: a) The implanted ions may be activated by post implantation annealing at elevated temperatures. b) The semiconductor surface may be preconditioned prior to gate oxide deposition. c) A gate oxide may be formed by deposition or oxidation and optionally followed by post deposition annealing, for example. d) A gate (G) may be formed as a spacer, which is made of in-situ doped polysilicon. e) An interlayer dielectric (ILD) may be formed by deposition of an insulating layer and its patterning, as illustrated in Fig. 2a, for example or by thermal oxidation of the polysilicon gate, as illustrated in Fig. 2b, for example. f) Ohmic contacts may be created in the contact regions, except of the mesa Schottky contact region (SBD) by metal deposition and annealing. g) Opening in the interlayer dielectric to the gate may be created in a gate pad region and the backend processing including front side source metallization (S), backside drain metallization (D), passivation and other steps may be performed. The front side metallization contacts both the ohmic contact region and the mesa Schottky contact region (SBD).

A typical activation temperature of ions implanted into SiC can be in the range from 1500 °C to 1800 °C.

By preconditioning are meant all processes which lead to improvement of trench sidewalls, trench shape (rounding) and semiconductor / oxide interface, for example annealing and I or etching in a hydrogen-ambient.

The gate oxide may be formed using a method providing conformal coverage of sidewalls, for example by TEOS low pressure CVD (LPCVD).

Because the spacer process is used for formation of the gate, the gate is self-aligned on the trench. The width of the spacer gate can be decided by thickness of the deposited layer. The width of the spacer gate should be big enough to overlap the source region.

The interlayer dielectric fabricated using the thermal oxidation can have the following advantages over the deposited layer: a) no photolithography is required and the ILD is selfaligned, b) the mesa is fully exposed to the metal; hence the source contact area is bigger and the source contact resistance is smaller, c) polysilicon is oxidized even in its bottom part, hence the oxide thickness over the source increases and the gate capacitance decreases.

The fabrication of the ILD by the thermal oxidation is possible due to a much smaller oxidation rate of silicon carbide than of polysilicon. The polysilicon can be oxidized at temperatures below 1100 °C, at which the SiC surface is hardly oxidized. However, a very thin oxide layer can be still grown on SiC at these temperature, hence short oxide etching is recommended prior to the contact formation.

The contact may be formed for example by the SALICIDE (Self-Aligned Silicide) method. A metal layer, particularly a nickel-based metal, is deposited on the top surface and annealed at moderate temperatures, particularly at 600 °C - 700 °C for the nickel-based metal. This step leads to alloying of the metal with SiC (silicidation). The step is followed by wet etching (cleaning), which removes the not alloyed metal from the ILD surface. In the next step, the previously alloyed contacts are exposed to higher temperatures around 1000 °C, which assures low-ohmic contact properties.

The full fabrication process may include four self-aligned processes: a) the self-aligned channel (by spacer), b) the self-aligned gate (by spacer), c) the self-aligned ILD (by thermal oxidation), d) the self-aligned contacts (by selective silicidation).

Fig. 4a shows a 3D structure of a second embodiment of the semiconductor cell 100. This second embodiment is a SiC device. The device inherits most properties of the first embodiment shown in Figure 3, but the whole mesa is used for the Schottky contact and the body contact region 8 is present only in the trench part of the device. The body contact region 8 is placed between the trench source regions 6, but its position is arbitrary.

Fig. 4b shows a 3D structure of a third embodiment of the semiconductor cell 100. This third embodiment is a SiC device. The device inherits most properties of the first embodiment shown in Figure 3.

The body contact region 8 is placed in the trench body region 5 between two parts of the trench source region 6. The body contact region 8 extends to the at least one trench side wall 111 b (see Figure 1).

Fig. 5a shows a 3D structure of a fourth embodiment of the semiconductor cell 100. This fourth embodiment is a SiC device. The device inherits most properties of the previous embodiments shown in Figures 4a, 4b, but the body contact region 8 is designed differently.

The body contact region 8 forms a stripe-shaped region extending next to and in parallel to the trench source region 6.

Fig. 5b shows a 3D structure of a fifth embodiment of the semiconductor cell 100. This fifth embodiment is a SiC device. The device inherits most properties of the previous embodiments shown in Figures 4a, 4b, but the body contact region 8 is designed differently.

The body contact region 8 forms a patterned-shaped region with the trench source region 6. A sixth embodiment relates to a SiC device for which the doping type of the substrate 1 is of opposite doping type to the doping type of the drift layer 3. The device forms an IGBT structure.

A seventh embodiment relates to a complementary SiC device for which all semiconductor regions of the previous embodiments are of a reversed doping type.

In the previous sections, a monolithically Schottky barrier diode integrated semiconductor device was presented.

Such a device can be a device with SBD integrated in the mesa region and the body contact which is orthogonal to the cell direction and which extends vertically from the top semiconductor surface (mesa) at least to the depth of the trench body regions; where the body contact region is produced using deep ion implantation or trench etching and epitaxial regrowth and surface planarization. The described implementation of SBD and the body contact region allows for smaller pitch of the device and thus for smaller size.

Such a device can be a device with planar channels, which are self-aligned on the trench, i.e. the trench body regions can be implanted using the same mask which is used for etching of trenches (with an optional thin masking layer on top of it) and the trench source regions can be subsequently implanted through a spacer mask. The device provides decreased pitch of the device due to integration of the self-aligned channel process into the fabrication process flow.

In the above device, the interlayer dielectric may be formed by oxidation of a polysilicon gate spacer, the oxide thickness over the source regions can be increased compared to the oxide thickness over the channels and the mesa can be fully exposed to the metal. Such device is a decreased pitch of the device due to self-aligned ILD; and an increased SBD current due to bigger area exposed to the metal.

A device fabrication process as described above for producing the above device may include four self-aligned processes. Such device offers decreased pitch of the device due to implementation of the self-aligned processes.

The technical solution described in this disclosure can be applied to other semiconductor trench devices, for example to MOSFET and IGBT, fabricated using silicon, gallium oxide or other semiconductor material technologies. While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.

Claims

1 . A monolithically Schottky barrier diode integrated semiconductor device comprising at least one semiconductor cell (100), the at least one semiconductor cell (100) comprising: a substrate (1) being arranged at a bottom surface (101) of the at least one semiconductor cell (100); a Schottky section (4, 7) placed above the substrate (1), the Schottky section (4, 7) comprising a layer stack of a current spreading layer (4) and a mesa Schottky contact region (7); a trench (111) formed next to the Schottky section (4, 7) and above the substrate (1) along a first direction (104) parallel to the bottom surface (101), the trench (111) formed on both sides of the Schottky section (4, 7), the trench (111) comprising a trench bottom (111a) and at least one trench side wall (111b); a planar channel section (4, 5, 6) formed above the substrate (1) and below the trench (111) on both sides of the Schottky section (4, 7), the planar channel section (4, 5, 6) comprising a layer stack of the current spreading layer (4), a trench body region (5) and a trench source region (6); wherein the trench body region (5) forms a shield below the trench (111), the shield covering the trench bottom (111a) for protection against high electric fields; a body contact region (8) formed in the Schottky section (4, 7) and the planar channel section (4, 5, 6) along a second direction (107) parallel to the bottom surface (101), the body contact region (8) electrically connecting the trench body region (5) of the planar channel section (5, 6); wherein two or more planar carrier channels (114a, 114b) are formed in each planar channel section (4, 5, 6) and two or more Schottky barrier diodes (116a, 116b) are formed in the Schottky section (4, 7).

2. The semiconductor device of claim 1 , the at least one semiconductor cell (100) comprising: a buffer layer (2) placed on top of the substrate (1); and a drift layer (3) placed on top of the buffer layer (2); wherein the Schottky section (4, 7) is placed on top of the drift layer (3).

3. The semiconductor device of claim 2, wherein the substrate (1), the buffer layer (2), the drift layer (3), the current spreading layer (4), the trench source region (6) and the mesa Schottky contact region (7) are of a first semiconductor doping type; and wherein the trench body region (5) and the body contact region (8) are of a second semiconductor doping type.

4. The semiconductor device of claim 3, wherein the trench source region (6) is implanted and self-aligned on the trench body region (5).

5. The semiconductor device of any of the preceding claims, wherein the current spreading layer (4) is shallower than the trench body region (5) in the planar channel section (4, 5, 6).

6. The semiconductor device of any of the preceding claims, wherein a first planar carrier channel (114a) in each planar channel section (4, 5, 6) is formed between the trench source region (6) and the current spreading layer (4) of a first part of the planar channel section (4, 5, 6) and a second planar carrier channel (114b) in each planar channel section (4, 5, 6) is formed between the trench source region (6) and the current spreading layer (4) of a second part of the planar channel section (4, 5, 6); wherein a Schottky contact (201 , 202) is formed on top of the mesa Schottky contact region (7); and wherein a first Schottky barrier diode (116a) is formed by a first part of the Schottky contact (201) and the mesa Schottky contact region (7) of a first part of the Schottky section (4, 7) and a second Schottky barrier diode (116b) is formed by a second part of the Schottky contact (202) and the mesa Schottky contact region (7) of a second part of the Schottky section (4, 7).

7. The semiconductor device of any of the preceding claims, wherein the body contact region (8) is placed in the trench body region (5) between two parts of the trench source region (6).

8. The semiconductor device of claim 7, wherein the body contact region (8) extends to the at least one trench side wall (111b).

9. The semiconductor device of claim 7 or 8, wherein the body contact region (8) and the trench source region (6) are arranged staggered along the first direction (104) with respect to each other.

10. The semiconductor device of claim 7, wherein the body contact region (8) forms a stripe-shaped region extending next to and in parallel to the trench source region (6); and/or wherein the body contact region (8) forms a patterned-shaped region with the trench source region (6).

11. The semiconductor device of any of the preceding claims, the at least one semiconductor cell (100) comprising: a gate electrode (G) formed in the trench (111) above the planar carrier channels (114a, 114b), the gate electrode (G) having an overlay with the trench source region (6); a first ohmic contact (Q1) formed in the trench (111) above the trench source region (6) and the body contact region (8), the first ohmic contact (Q1) providing a first part of a source contact; and a first Schottky contact (201) formed above the mesa Schottky contact region (7) of a first part of the Schottky section (4, 7); a second Schottky contact (202) formed above the mesa Schottky contact region (7) of a second part of the Schottky section (4, 7); a second ohmic contact (Q2) formed above the body contact region (8) between the first Schottky contact (201) and the second Schottky contact (202), the second ohmic contact (Q2) providing a second part of the source contact; and an interlayer dielectric layer (ILD) electrically separating the gate electrode (G) from the first and second ohmic contacts (Q1 , Q2).

12. The semiconductor device of claim 11 , wherein the interlayer dielectric layer (ILD) is formed in the trench (111) and overlays the mesa Schottky contact region (7) and the body contact region (8) on top of the Schottky section (4, 7).

13. The semiconductor device of claim 11 , wherein the interlayer dielectric layer (ILD) is formed in the trench (111) without overlaying the mesa Schottky contact region (7) and the body contact region (8) on top of the Schottky section (4, 7).

14. The semiconductor device of claim 13, wherein an oxide thickness between the trench source region (6) and the gate (G) is increased over an oxide thickness between the planar carrier channels (114a, 114b) and the gate (G).

15. The semiconductor device of claim 13, wherein the second ohmic contact (Q2) is extending onto a portion of the at least one trench side wall (111b) of the trench (111); or wherein the second ohmic contact (Q2) and the Schottky contact (201 , 202) are extending onto a portion of the at least one trench side wall (111 b) of the trench (111).

16. The semiconductor device of claim 2, wherein the at least one semiconductor cell (100) is forming a Schottky barrier diode integrated MOSFET structure; or wherein a doping type of the substrate (1) is of opposite doping type to the doping type of the drift layer (3), and the at least one semiconductor cell (100) is forming a Schottky barrier diode integrated IGBT structure.

17. The semiconductor device of any of the preceding claims, wherein the first semiconductor doping type is an n-type doping and the second semiconductor doping type is of a p-type doping; or wherein the first semiconductor doping type is a p-type doping and the second semiconductor doping type is of an n-type doping.

18. A method for producing at least one semiconductor cell (100) of a monolithically Schottky barrier diode integrated semiconductor device, the method comprising: providing a substrate (1) arranged at a bottom surface (101) of the at least one semiconductor cell (100); placing a buffer layer (2) on top of the substrate (1); placing a drift layer (3) on top of the buffer layer (2); forming a Schottky section (4, 7) above the substrate (1), the Schottky section (4, 7) comprising a layer stack of a current spreading layer (4) and a mesa Schottky contact region (7); forming a trench (111) next to the Schottky section (4, 7) and above the substrate (1) along a first direction (104) parallel to the bottom surface (101), the trench (111) on both sides of the Schottky section (4, 7), the trench (111) comprising a trench bottom (111a) and at least one trench side wall (111b); forming a planar channel section (4, 5, 6) above the substrate (1) and below the trench (111) on both sides of the Schottky section (4, 7), the planar channel section (4, 5, 6) comprising a layer stack of the current spreading layer (4), a trench body region (5) and a trench source region (6); forming a body contact region (8) in the Schottky section (4, 7) and the planar channel section (4, 5, 6) along a second direction (107) parallel to the bottom surface (101), the body contact region (8) electrically connecting the trench body region (5) of the planar channel section (4, 5, 6); and forming two or more planar carrier channels (114a, 114b) in each planar channel section (5, 6) and forming two or more Schottky barrier diodes (116a, 116b) in the Schottky section (4, 7).

19. The method of claim 18, wherein the trench source region (6) is formed self-aligned on the trench body region

(5) by using a spacer process.

20. The method of claim 18 or 19, comprising: forming a gate electrode (G) in the trench (111) above the planar carrier channels (114a, 114b), the gate electrode (G) having an overlay with the trench source region

(6); forming a first ohmic contact (Q1) in the trench (111) above the trench source region (6) and the body contact region (8), the first ohmic contact (Q1) providing a first part of a source contact; forming a second ohmic contact (Q2) above the body contact region (8), the second ohmic contact (Q2) providing a second part of the source contact; and forming an interlayer dielectric layer (ILD) electrically separating the gate electrode (G) from the first and second ohmic contacts (Q1 , Q2).

21. The method of claim 20, wherein the gate electrode (G) is formed self-aligned in the trench (111) by using a spacer process; wherein the interlayer dielectric layer (ILD) is formed self-aligned by using a thermal oxidation process; and wherein the first ohmic contact (Q1) and the second ohmic contact (Q2) are formed self-aligned by using a selective silicidation process.