WO2024176280A1

WO2024176280A1 - Integrated device

Info

Publication number: WO2024176280A1
Application number: PCT/JP2023/005895
Authority: WO
Inventors: 幸祐濱中
Original assignee: Tdk株式会社
Priority date: 2023-02-20
Filing date: 2023-02-20
Publication date: 2024-08-29

Abstract

This integrated device comprises: a magnetic element; a first transistor; a second transistor; first via wiring; second via wiring; a write wire; and resistance adjustment wiring. The magnetic element comprises a wiring layer, and a layered body including a first ferromagnetic layer connected to the wiring layer. The first transistor is electrically connected to the layered body. The second transistor has a first active region and a second active region. The first active region of the second transistor and the wiring layer of the magnetic element are connected through the first via wiring. The second active region of the second transistor is connected to the second via wiring. The second via wiring and the write wire are connected by the resistance adjustment wiring, which has a higher resistivity than the second via wiring and the write wire.

Description

Integration device

The present invention relates to an integrated device.

Attention is being focused on next-generation non-volatile memory to replace flash memory and other memory devices, which are reaching the limits of miniaturization. For example, MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistance Random Access Memory), and PCRAM (Phase Change Random Access Memory) are known as next-generation non-volatile memories.

MRAM is a memory element that uses a magnetoresistive element. The resistance value of the magnetoresistive element changes depending on the difference in the relative angle between the magnetization directions of the two magnetic films. MRAM records the resistance value of the magnetoresistive element as data.

There are two-terminal and three-terminal magnetoresistance elements. Two-terminal elements have the same current path when writing and reading data, and operate by controlling the potential difference between two terminals. Three-terminal elements have different current paths when writing and reading data, and operate by controlling the potential difference between three terminals. A spin-orbit torque type magnetoresistance element that uses spin-orbit torque (SOT) (e.g., Patent Document 1) and a domain wall motion type magnetic recording element that uses domain wall motion (e.g., Patent Document 2) are examples of three-terminal elements. Three-terminal elements are connected to semiconductor elements such as transistors by wiring and are controlled.

JP 2017-216286 A Patent No. 5441005

In order for a three-terminal element to operate properly, at least two transistors are required. Depending on where the two transistors are connected in the magnetic element, there may be a difference in the amount of write current when a write current is applied in the forward direction and when a write current is applied in the reverse direction.

The present invention was made in consideration of the above circumstances, and aims to provide an integrated device in which the difference in the amount of write current depending on the direction in which the write current is applied is small.

The integrated device includes a magnetic element, a first transistor, a second transistor, a first via wiring, a second via wiring, a write line, and a resistance adjustment wiring. The magnetic element includes a wiring layer and a stack including a first ferromagnetic layer connected to the wiring layer. The first transistor is electrically connected to the stack. The second transistor has a first active region and a second active region. The first active region of the second transistor and the wiring layer of the magnetic element are connected via the first via wiring. The second active region of the second transistor is connected to the second via wiring. The second via wiring and the write line are connected by the resistance adjustment wiring having a higher resistivity than the second via wiring and the write line.

The integrated device disclosed herein has little difference in the amount of write current depending on the direction in which the write current is applied.

FIG. 2 is a circuit diagram of an integrated device according to the first embodiment. 3 is a cross-sectional view of a characteristic portion of the integrated device according to the first embodiment. FIG. 3 is a cross-sectional view of a first example of a wiring adjustment layer of the integrated device according to the first embodiment. FIG. 4 is a cross-sectional view of a second example of the wiring adjustment layer of the integrated device according to the first embodiment. FIG. 1 is a cross-sectional view of a magnetoresistive effect element according to a first embodiment. 1 is a plan view of a magnetoresistive effect element according to a first embodiment; 10A to 10C are diagrams illustrating the operation of an integrated device according to a comparative example. 5A to 5C are diagrams illustrating the operation of the integration device according to the first embodiment. FIG. 11 is a circuit diagram of an integrated device according to a second embodiment. FIG. 11 is a cross-sectional view of a magnetoresistive effect element according to a third embodiment. FIG. 13 is a cross-sectional view of a magnetization rotating element according to a fourth embodiment. FIG. 13 is a cross-sectional view of a magnetoresistive effect element according to a fifth embodiment. FIG. 11 is a cross-sectional view of a magnetoresistive effect element according to a first modified example.

The present embodiment will now be described in detail with reference to the drawings as appropriate. The drawings used in the following description may show characteristic parts in an enlarged scale for the sake of clarity, and the dimensional ratios of each component may differ from the actual ones. The materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not limited to them. Appropriate modifications can be made within the scope of the effects of the present invention.

First, let us define the directions. One direction on one surface of the substrate Sub (see FIG. 2), which will be described later, is the x-direction, and the direction perpendicular to the x-direction is the y-direction. The x-direction is, for example, the longitudinal direction of the wiring layer 20. The z-direction is a direction perpendicular to the x-direction and y-direction. The z-direction is an example of the stacking direction in which each layer is stacked. Below, the +z direction may be expressed as "up" and the -z direction as "down". Up and down do not necessarily coincide with the direction in which gravity is applied.

In this specification, "extending in the x-direction" means, for example, that the dimension in the x-direction is greater than the smallest dimension among the dimensions in the x-direction, y-direction, and z-direction. The same applies to extending in other directions.

FIG. 1 is a circuit diagram of an integrated device 200 according to a first embodiment. The integrated device 200 includes a plurality of magnetoresistance effect elements 100, a plurality of write wirings WL, a plurality of common wirings CL, a plurality of read wirings RL, a plurality of first transistors Tr1, a plurality of second transistors Tr2, and a plurality of third transistors Tr3. The write wirings WL are an example of a first wiring. The magnetoresistance effect elements 100 are arranged in an array within the integrated device 200. The magnetoresistance effect elements 100 are an example of a magnetic element. In FIG. 1, gate wirings connected to the gates of the first transistor Tr1, the second transistor Tr2, and the third transistor Tr3 are omitted.

Each of the write wirings WL electrically connects a power supply to one or more magnetoresistance effect elements 100. Each of the common wirings CL is a wiring that is used both when writing and reading data. Each of the common wirings CL electrically connects a reference potential to one or more magnetoresistance effect elements 100. The reference potential is, for example, ground. The common wiring CL may be provided for each of the multiple magnetoresistance effect elements 100, or may be provided across the multiple magnetoresistance effect elements 100. Each of the read wirings RL electrically connects a power supply to one or more magnetoresistance effect elements 100. The power supply is connected to the integrated device 200 during use.

Each magnetoresistance effect element 100 is connected to a first transistor Tr1, a second transistor Tr2, and a third transistor Tr3. The first transistor Tr1 is connected between the magnetoresistance effect element 100 and a read wiring RL. The second transistor Tr2 is connected between the magnetoresistance effect element 100 and a write wiring WL. The third transistor Tr3 is connected to a common wiring CL that spans the multiple magnetoresistance effect elements 100.

When a specific second transistor Tr2 and third transistor Tr3 are turned ON, a write current flows between the write wiring WL and the common wiring CL connected to the specific magnetoresistance effect element 100. The write current flows, and data is written to the specific magnetoresistance effect element 100. When a specific first transistor Tr1 and third transistor Tr3 are turned ON, a read current flows between the common wiring CL and the read wiring RL connected to the specific magnetoresistance effect element 100. The read current flows, and data is read from the specific magnetoresistance effect element 100.

FIG. 2 is a cross-sectional view of a characteristic portion of an integrated device 200 according to the first embodiment. FIG. 2 is a cross-section of the magnetoresistance effect element 100 cut in an xz plane passing through the center of the width in the y direction of the wiring layer 20, which will be described later.

The magnetoresistance effect element 100 is connected to the second transistor Tr2 and the via wiring V3. The via wiring V3 is connected to the common wiring CL.

The first transistor Tr1 and the second transistor Tr2 are both field effect transistors. The first transistor Tr1 and the second transistor Tr2 each have a gate electrode G, a gate insulating film GI, and a first active region A1 and a second active region A2 formed in a substrate Sub. The first active region A1 and the second active region A2 are sometimes called a source or a drain. The positional relationship between the source and the drain is determined by the direction of current flow. The substrate Sub is a semiconductor substrate. The first active region A1 and the second active region A2 are semiconductors doped with carriers.

The first active region A1 of the first transistor Tr1 is connected to the readout wiring RL by a via wiring V5.

The second active region A2 of the first transistor Tr1 is connected to a via wiring V4. The via wiring V4 is connected to an in-plane wiring P1. The in-plane wiring P1 is connected to an electrode E of the magnetoresistive effect element 100. The magnetoresistive effect element 100 and the first transistor Tr1 are electrically connected. The magnetoresistive effect element 100 and the first transistor Tr1 are connected, for example, via the in-plane wiring P1, the via wiring V4, and the electrode E.

The first active region A1 of the second transistor Tr2 is connected to the via wiring V1. The via wiring V1 is an example of a first via wiring. The first active region A1 of the second transistor Tr2 and the magnetoresistance effect element 100 are connected via the via wiring V1.

The second active region A2 of the second transistor Tr2 is connected to the via wiring V2. The via wiring V2 is an example of a second via wiring. The via wiring V2 is connected to the resistance adjustment wiring R1. The resistance adjustment wiring R1 is connected to the write wiring WL. The second transistor Tr2 and the write wiring WL are connected via the via wiring V2 and the resistance adjustment wiring R1.

The resistance adjustment wiring R1 is a wiring that connects the via wiring V2 and the write wiring WL. The via wiring V2 is a wiring that extends in the z direction. The write wiring WL is a wiring that extends in one direction, either the x direction or the y direction. The resistance adjustment wiring R1 is, for example, a wiring that extends in any direction within the xy plane, and extends in a direction that intersects with both the via wiring V2 and the write wiring WL.

The resistance adjustment wiring R1 has a higher resistance than the via wiring V2, for example. The resistance of the resistance adjustment wiring R1 may be higher than the resistance of the via wiring V2 due to its shape, or may be higher than the resistance of the via wiring V2 due to its material. The resistance of the resistance adjustment wiring R1 may also be higher than the via wiring V2 due to its shape and material.

FIG. 3 is an xy cross-sectional view of the resistance adjustment wiring R1 according to the first example. The resistance adjustment wiring R1 shown in FIG. 3 has a narrow portion R1A and a wide portion R1B. The wide portion R1B is the portion that contacts the via wiring V2. The cross-sectional area perpendicular to the current flow direction in the resistance adjustment wiring R1 is narrower in the narrow portion R1A than in the wide portion. For example, the width L1 in the y direction of the narrow portion R1A is narrower than the width L2 in the y direction of the wide portion R1B. Due to the shape of the resistance adjustment wiring R1 according to the first example, the resistance of the resistance adjustment wiring R1 can be made higher than that of the via wiring V2. In this case, the material of the resistance adjustment wiring R1 does not matter.

FIG. 4 is an xy cross-sectional view of the resistance adjustment wiring R1 according to the second example. The resistance adjustment wiring R1 shown in FIG. 4 is a meander wiring. The resistance adjustment wiring R1 shown in FIG. 4 has, for example, a first portion R1C extending in the y direction and a second portion R1D extending in the x direction. The resistance adjustment wiring R1 only needs to have portions extending in different directions in the xy plane, and may have a zigzag shape. Due to the shape of the resistance adjustment wiring R1 according to the second example, the resistance of the resistance adjustment wiring R1 can be made higher than the via wiring V2. In this case, the material of the resistance adjustment wiring R1 does not matter.

The resistance adjustment wiring R1 may have a higher resistivity than, for example, the via wiring V2 and the write wiring WL. In this case, the resistance of the resistance adjustment wiring R1 can be made higher than the resistance of the via wiring V2 due to the material.

The resistance adjustment wiring R1 includes, for example, any one selected from the group consisting of W, Pt, Ta, Ti, and Hf. Any one selected from the group consisting of W, Pt, Ta, Ti, and Hf may exist as an elemental metal, or may exist as an oxide, fluoride, or nitride. These materials have a higher resistivity than Al, Ag, Cu, etc., used in the via wiring V2 and the write wiring WL. It is preferable that the resistance adjustment wiring R1 includes the same material as the wiring layer 20 described below. If this configuration is satisfied, it is easy to make the forward and reverse write current amounts equal.

The ratio of the length of the resistance adjustment wiring R1 divided by the cross-sectional area may be, for example, 90% or more and 110% or less of the ratio of the length of the wiring layer described below divided by the cross-sectional area. The length of the resistance adjustment wiring R1 is the length in the direction of current flow. For example, if the resistance adjustment wiring R1 is a meander wiring as shown in Figure 4, it is the length of the current path between the via wiring V2 and the write wiring WL.

The via wirings V1, V2, V3, V4, and V5 are each wiring that extends in the z direction. The write wiring WL, read wiring RL, common wiring CL, and in-plane wiring P1 are each wiring that extends in one of the xy planes. The electrode E is the contact point between the magnetoresistance effect element 100 and the wiring. The via wirings V1, V2, V3, V4, and V5, the write wiring WL, read wiring RL, common wiring CL, in-plane wiring P1, and the electrode E are all made of a highly conductive material, such as Al, Ag, or Cu.

The magnetoresistance effect element 100, the first transistor Tr1, and the second transistor Tr2 are covered with an insulating layer 90. The insulating layer 90 is an insulating layer that insulates between the wirings of the multilayer wiring and between the elements. The insulating layer 90 is, for example, silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon carbide (SiC), chromium nitride, silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO _x ), magnesium oxide (MgO), aluminum nitride (AlN), or the like.

FIG. 5 is a cross-sectional view of the magnetoresistance effect element 100 according to the first embodiment. FIG. 5 is a cross-section of the magnetoresistance effect element 100 cut in the xz plane passing through the center of the width of the wiring layer 20 in the y direction. FIG. 6 is a plan view of the magnetoresistance effect element 100 according to the first embodiment as viewed from the z direction.

The magnetoresistance effect element 100 includes, for example, a laminate 10 and a wiring layer 20.

The magnetoresistance effect element 100 is a magnetic element that utilizes spin orbit torque (SOT), and may be referred to as a spin orbit torque type magnetoresistance effect element, a spin injection type magnetoresistance effect element, or a spin current magnetoresistance effect element. The wiring layer 20 may be referred to as spin orbit torque wiring.

The magnetoresistance effect element 100 is an element that records and stores data. The magnetoresistance effect element 100 records data as the resistance value in the z direction of the stack 10. The resistance value in the z direction of the stack 10 changes when a write current is applied along the wiring layer 20 and spins are injected from the wiring layer 20 into the stack 10. The resistance value in the z direction of the stack 10 can be read by applying a read current in the z direction of the stack 10. The stack 10 is electrically connected to the first transistor Tr1.

The laminate 10 is connected to the wiring layer 20. The laminate 10 shown in FIG. 5 is laminated on the wiring layer 20, for example.

The laminate 10 is a columnar body. The planar shape of the laminate 10 in the z direction is, for example, circular, elliptical, or rectangular. The side surface of the laminate 10 is, for example, inclined with respect to the z direction.

The laminate 10 includes, for example, a first ferromagnetic layer 1, a second ferromagnetic layer 2, a nonmagnetic layer 3, an underlayer 4, a cap layer 5, and a mask layer 6. The resistance value of the laminate 10 changes according to the difference in the relative angle of magnetization between the first ferromagnetic layer 1 and the second ferromagnetic layer 2, which sandwich the nonmagnetic layer 3.

The first ferromagnetic layer 1 faces, for example, the wiring layer 20. The first ferromagnetic layer 1 may be in direct contact with the wiring layer 20, or indirect contact with the wiring layer 20 via the underlayer 4. The first ferromagnetic layer 1 is stacked, for example, on the wiring layer 20.

Spins are injected into the first ferromagnetic layer 1 from the wiring layer 20. The magnetization of the first ferromagnetic layer 1 is subjected to spin-orbit torque (SOT) by the injected spins, and the orientation direction of the magnetization changes. The first ferromagnetic layer 1 is called a magnetization free layer.

The first ferromagnetic layer 1 includes a ferromagnetic material. The ferromagnetic material is, for example, a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, or an alloy containing these metals and at least one of the elements B, C, and N. The ferromagnetic material is, for example, a Co-Fe, Co-Fe-B, Ni-Fe, Co-Ho alloy, Sm-Fe alloy, Fe-Pt alloy, Co-Pt alloy, or CoCrPt alloy.

The first ferromagnetic layer 1 may include a Heusler alloy. The Heusler alloy includes an intermetallic compound having a chemical composition of XYZ or X ₂ YZ. X is a transition metal element or a noble metal element of the Co, Fe, Ni, or Cu group on the periodic table, Y is a transition metal element or an element type of X of the Mn, V, Cr, or Ti group, and Z is a typical element of groups III to V. Examples of the Heusler alloy include Co ₂ FeSi, Co ₂ FeGe, Co ₂ FeGa, Co ₂ MnSi, Co ₂ Mn _1-a Fe _a Al _b Si _1-b , and Co ₂ FeGe _1-c Ga _c . The Heusler alloy has a high spin polarizability.

The second ferromagnetic layer 2 faces the first ferromagnetic layer 1 with a nonmagnetic layer 3 sandwiched therebetween. The second ferromagnetic layer 2 includes a ferromagnetic material. The magnetization of the second ferromagnetic layer 2 is less likely to change orientation than the magnetization of the first ferromagnetic layer 1 when a predetermined external force is applied. The second ferromagnetic layer 2 is called a magnetization fixed layer and a magnetization reference layer. The laminate 10 shown in FIG. 5 has the magnetization fixed layer on the side away from the substrate Sub, and is called a top pin structure.

The material constituting the second ferromagnetic layer 2 is the same as the material constituting the first ferromagnetic layer 1.

The second ferromagnetic layer 2 may have a synthetic antiferromagnetic structure (SAF structure). A synthetic antiferromagnetic structure is composed of two magnetic layers sandwiching a nonmagnetic layer. The second ferromagnetic layer 2 may have two magnetic layers and a spacer layer sandwiched between them. The coercive force of the second ferromagnetic layer 2 increases when the two ferromagnetic layers are antiferromagnetically coupled. The ferromagnetic layer is, for example, IrMn, PtMn, etc. The spacer layer includes, for example, at least one selected from the group consisting of Ru, Ir, and Rh.

The non-magnetic layer 3 is sandwiched between the first ferromagnetic layer 1 and the second ferromagnetic layer 2. The non-magnetic layer 3 includes a non-magnetic material. When the non-magnetic layer 3 is an insulator (when it is a tunnel barrier layer), its material can be, for example, Al ₂ O ₃ , SiO ₂ , MgO, and MgAl ₂ O _4. In addition to these, materials in which a part of Al, Si, and Mg is replaced with Zn, Be, etc. can also be used. Among these, MgO and MgAl ₂ O ₄ are materials that can realize coherent tunneling, so that spins can be efficiently injected. When the non-magnetic layer 3 is a metal, its material can be Cu, Au, Ag, etc. Furthermore, when the non-magnetic layer 3 is a semiconductor, its material can be Si, Ge, CuInSe ₂ , CuGaSe ₂ , Cu(In,Ga)Se ₂ , etc.

The underlayer 4 is, for example, between the first ferromagnetic layer 1 and the wiring layer 20. The underlayer 4 may be omitted.

The underlayer 4 includes, for example, a buffer layer and a seed layer. The buffer layer is a layer that relieves lattice mismatch between different crystals. The seed layer enhances the crystallinity of the layer stacked on the seed layer. The seed layer is formed, for example, on the buffer layer.

The buffer layer is, for example, Ta (single element), TaN (tantalum nitride), CuN (copper nitride), TiN (titanium nitride), NiAl (nickel aluminum). The seed layer is, for example, Pt, Ru, Zr, NiCr alloy, NiFeCr.

The cap layer 5 is on the second ferromagnetic layer 2. The cap layer 5, for example, strengthens the magnetic anisotropy of the second ferromagnetic layer 2. The cap layer 5, for example, strengthens the perpendicular magnetic anisotropy of the second ferromagnetic layer 2. The cap layer 5 is, for example, magnesium oxide, W, Ta, Mo, etc. The film thickness of the cap layer 5 is, for example, 0.5 nm or more and 5.0 nm or less.

The mask layer 6 is on the cap layer 5. The mask layer 6 is part of a hard mask used to process the stack 10 during manufacturing. The mask layer 6 also functions as an electrode. The mask layer 6 includes, for example, Al, Cu, Ta, Ti, Zr, NiCr, nitrides (e.g., TiN, TaN, SiN), and oxides (e.g., _SiO2 ).

The laminate 10 may have layers other than the first ferromagnetic layer 1, the second ferromagnetic layer 2, the nonmagnetic layer 3, the underlayer 4, and the cap layer 5.

The wiring layer 20 extends in the x direction, for example, with its length in the x direction being longer than that in the y direction when viewed from the z direction. The write current flows in the x direction along the wiring layer 20 between the via wiring V1 and the via wiring V3.

The wiring layer 20 induces a spin current by spin-orbit interaction and the interface Rashba effect, and injects spin into the first ferromagnetic layer 1. The wiring layer 20 applies a spin-orbit torque (SOT) to the magnetization of the first ferromagnetic layer 1 that is sufficient to reverse the magnetization of the first ferromagnetic layer 1, for example.

The spin Hall effect is a phenomenon in which, when electric current is passed, a spin current is induced in a direction perpendicular to the direction of electric current flow due to spin-orbit interaction. The spin Hall effect is similar to the regular Hall effect in that the direction of movement of moving charges (electrons) can be bent. In the regular Hall effect, the direction of movement of charged particles moving in a magnetic field is bent by the Lorentz force. In contrast, with the spin Hall effect, the direction of spin movement can be bent simply by the movement of electrons (the flow of electric current) even in the absence of a magnetic field.

For example, when a current flows through the wiring layer 20, the first spins polarized in one direction and the second spins polarized in the opposite direction to the first spins are bent by the spin Hall effect in a direction perpendicular to the direction of the current flow. For example, the first spins polarized in the -y direction are bent from the x direction, which is the direction of travel, to the +z direction, and the second spins polarized in the +y direction are bent from the x direction, which is the direction of travel, to the -z direction.

In non-magnetic materials (materials that are not ferromagnetic), the number of electrons in the first spin and the number of electrons in the second spin caused by the spin Hall effect are equal. In other words, the number of electrons in the first spin facing the +z direction is equal to the number of electrons in the second spin facing the -z direction. The first spins and second spins flow in a direction that eliminates the uneven distribution of spins. When the first spins and second spins move in the z direction, the flow of charges cancels each other out, so the amount of current is zero. Spin current without current is specifically called pure spin current.

If the flow of electrons of the first spin is represented as J _↑ , the flow of electrons of the second spin is represented as J _↓ , and the spin current is represented as _JS , then _JS = J _↑ - J _↓ . The spin current _JS is generated in the z direction. The first spins are injected into the first ferromagnetic layer 1 from the wiring layer 20.

The wiring layer 20 includes any of a metal, alloy, intermetallic compound, metal boride, metal carbide, metal silicide, metal phosphide, and metal nitride that has the function of generating a spin current.

The wiring layer 20 includes, for example, any material selected from the group consisting of heavy metals with atomic numbers of 39 or more, metal oxides, metal nitrides, metal oxynitrides, and topological insulators. The wiring layer 20 may also include a magnetic material.

The wiring layer 20 contains, for example, a nonmagnetic heavy metal as a main component. Heavy metal means a metal having a specific gravity equal to or greater than that of yttrium (Y). The nonmagnetic heavy metal is, for example, a nonmagnetic metal having a large atomic number of 39 or greater and having d electrons or f electrons in the outermost shell. In nonmagnetic heavy metals, stronger spin-orbit interaction occurs than in other metals. The spin Hall effect occurs due to spin-orbit interaction, which tends to cause spins to be unevenly distributed in the wiring layer 20, making it easier for spin current J _S to be generated.

Next, a method for manufacturing the integrated device 200 will be described. The integrated device 200 is formed by a lamination process of each layer and a processing process of processing a part of each layer into a predetermined shape. The lamination of each layer can be performed using a sputtering method, a chemical vapor deposition (CVD) method, an electron beam evaporation method (EB evaporation method), an atomic laser deposition method, or the like. The processing of each layer can be performed using photolithography, or the like.

First, impurities are doped into predetermined positions of the substrate Sub to form a first active region A1 and a second active region A2. Next, a gate insulating film GI and a gate electrode G are formed between the first active region A1 and the second active region A2. The first active region A1, the second active region A2, the gate insulating film GI, and the gate electrode G become the first transistor Tr1 and the second transistor Tr2. The substrate Sub may be a commercially available semiconductor circuit substrate on which transistors are formed.

Then, an insulating layer 90 is formed to cover the transistors. The via wirings V1, V2, V3, V4, and V5 are fabricated by forming holes in the insulating layer 90 and filling the holes with a conductor. The write wiring WL, common wiring CL, read wiring RL, in-plane wiring P1, and resistance adjustment wiring R1 are fabricated by forming grooves in the insulating layer 90 that extend in either direction within the xy plane, and filling the grooves with a conductor.

The magnetoresistance effect element 100 is obtained by stacking the layers that will become the wiring layer 20 and the layers that will become the laminate 10 in that order, and then processing them into a predetermined shape.

The integrated device 200 according to the first embodiment has a resistance adjustment wiring R1, so that the voltage difference between the gate and source of the second transistor Tr2 is the same whether the write current is applied in the forward direction or the reverse direction, and the amount of write current is the same in the forward and reverse directions.

FIG. 7 is a diagram explaining the operation of an integrated device according to a comparative example. The magnetoresistance effect element 100 stores information in the binary form of "1" and "0." For example, when storing information "1" in the magnetoresistance effect element 100, a current I1 is applied in the forward direction, and when storing information "0" in the magnetoresistance effect element 100, a current I2 is applied in the reverse direction.

The upper left diagram in Figure 7 is a schematic diagram of the application of a current I1 in the forward direction, and the lower left diagram in Figure 7 shows the voltage drop when the current I1 is applied in the forward direction. The upper right diagram in Figure 7 is a schematic diagram of the application of a current I2 in the reverse direction, and the lower right diagram in Figure 7 shows the voltage drop when the current I2 is applied in the reverse direction.

When applying a forward current, the potential of the write wiring WL is made higher than the potential of the common wiring CL. In this case, the first active region A1 of the second transistor Tr2 becomes the drain D, and the second active region A2 becomes the source S. The voltage drop between the write wiring WL, which has a high potential, and the source S is caused by the second transistor Tr2. Therefore, the voltage difference V _GS between the gate and source of the second transistor Tr2 corresponds to the voltage drop of the second transistor Tr2.

On the other hand, when a current is applied in the reverse direction, the potential of the common line CL is made higher than the potential of the write line WL. In this case, the second active region A2 of the second transistor Tr2 becomes the drain D, and the first active region A1 becomes the source S. The voltage drop between the common line CL and the source S, which becomes a high potential, is caused by the second transistor Tr2 and the wiring layer 20. Therefore, the voltage difference V _GS between the gate and source of the second transistor Tr2 corresponds to the sum of the voltage drop of the second transistor Tr2 and the voltage drop of the wiring layer 20.

That is, in the integrated device according to the comparative example that does not have the resistance adjustment wiring R1, the voltage difference V _GS between the gate and source of the second transistor Tr2 is different when a current is applied in the forward direction and when a current is applied in the reverse direction. If the voltage difference between the gate and source of the second transistor Tr2 is different when a write current is applied in the forward direction and when a write current is applied in the reverse direction, the amount of write current flowing through the wiring layer 20 is different. In this case, even if the current I2 is applied in the reverse direction, writing of information may become unstable. Furthermore, stabilizing writing when the current I2 is applied in the reverse direction would result in applying an excessive current I1 in the forward direction.

In contrast, FIG. 8 is a diagram explaining the operation of the integrated device 200 according to the first embodiment. The upper left diagram of FIG. 8 is a schematic diagram of application of a forward current I1, and the lower left diagram of FIG. 8 shows the voltage drop when the forward current I1 is applied. The upper right diagram of FIG. 8 is a schematic diagram of application of a reverse current I2, and the lower right diagram of FIG. 8 shows the voltage drop when the reverse current I2 is applied.

When applying a forward current, the potential of the write wiring WL is made higher than the potential of the common wiring CL. In this case, the first active region A1 of the second transistor Tr2 becomes the drain D, and the second active region A2 becomes the source S. The voltage drop between the write wiring WL and the source S, which is at a high potential, is caused by the resistance adjustment wiring R1 and the second transistor Tr2. Therefore, the voltage difference V _GS between the gate and source of the second transistor Tr2 corresponds to the sum of the voltage drop of the resistance adjustment wiring R1 and the voltage drop of the second transistor Tr2.

In the integrated device 200 according to the first embodiment, the difference between the gate-source voltage difference VGS when a current is applied in the forward direction and the gate-source voltage difference _VGS when a current is applied in the reverse direction is smaller than that in the integrated device according to the comparative example by the voltage drop of the resistance-adjusting wiring _R1 . For example, when the voltage drop of the wiring layer 20 and the voltage drop of the resistance-adjusting wiring R1 match, the gate-source voltage difference _VGS when a current is applied in the forward direction and the gate-source voltage difference _VGS when a current is applied in the reverse direction match.

In other words, in the integrated device 200 according to the first embodiment, the voltage difference between the gate and source of the second transistor Tr2 is small when a write current is applied in the forward direction and when it is applied in the reverse direction, and the difference in the amount of write current flowing through the wiring layer 20 is small. This makes it possible to suppress the occurrence of a difference in the write probability when writing information "1" and when writing information "0."

So far, the first embodiment has been illustrated as an example, and a preferred aspect of the present invention has been illustrated, but the present invention is not limited to the first embodiment.

For example, FIG. 9 is a circuit diagram of an integrated device 201 according to the second embodiment. The integrated device 201 includes a plurality of magnetoresistance effect elements 100, a plurality of bit lines BL, a plurality of source lines SL, a plurality of write gate lines WGL, a plurality of read gate lines RGL, a plurality of first transistors Tr1, a plurality of second transistors Tr2, and a plurality of third transistors Tr3.

In the integrated device 201 according to the second embodiment, configurations similar to those in the integrated device 200 according to the first embodiment are given the same reference numerals and will not be described.

The bit line BL is an example of a first wiring. The bit line BL functions as both the write wiring WL and the read wiring RL in the first embodiment. The integrated device 201 according to the second embodiment differs from the integrated device 200 according to the first embodiment in that the write wiring WL and the read wiring RL are combined into the bit line BL. The source line SL is the same as the common wiring CL.

The via wiring V2 and the bit line BL are connected by a resistance adjustment wiring R1 having a higher resistivity than the via wiring V2 and the bit line BL. The via wiring V2 and the bit line BL may be connected by a resistance adjustment wiring R1 having a higher resistance than the via wiring V2.

The integrated device 201 has the same effect as the integrated device 200. In addition, the integrated device 201 shown in FIG. 9 shares a single bit line BL as the write wiring WL and the read wiring RL, which reduces the number of wiring lines and provides excellent integration.

FIG. 10 is a cross-sectional view of a magnetoresistance effect element 101 according to the third embodiment. The magnetoresistance effect element 101 can be substituted for the magnetoresistance effect element 100 of the integrated device 200.

In the integrated device of the third embodiment, configurations similar to those of the integrated device 200 of the first embodiment are given the same reference numerals and will not be described.

The magnetoresistance effect element 101 according to the third embodiment has a laminate 11 and a wiring layer 20. The stacking order of the laminate 11 and the wiring layer 20 is different from the stacking order of the laminate 10 and the wiring layer 20 of the magnetoresistance effect element 100 according to the first embodiment. The wiring layer is stacked on the laminate 11.

The laminate 11 has, in order from the side closest to the substrate Sub, an underlayer 4, a second ferromagnetic layer 2, a non-magnetic layer 3, a first ferromagnetic layer 1, and a cap layer 5. In the magnetoresistance effect element 101, the second ferromagnetic layer 2, which is a magnetization fixed layer, is closer to the substrate Sub than the first ferromagnetic layer 1, and is called a bottom pin structure.

Also, the via wiring V1 and the via wiring V3 are connected to the upper surface of the wiring layer 20. The via wiring V1 and the via wiring V3 may be connected to the lower surface of the wiring layer 20.

The integrated device according to the third embodiment has the same effects as the integrated device 200 according to the first embodiment.

FIG. 11 is a cross-sectional view of a magnetization rotation element 110 according to the fourth embodiment. The magnetization rotation element 100 in FIG. 1 can be replaced with the magnetization rotation element 110. The magnetization rotation element 110 differs from the magnetization rotation element 100 in that the laminate 12 does not have a second ferromagnetic layer 2 or a nonmagnetic layer 3. In the magnetization rotation element 110, the same components as those in the magnetization rotation element 100 are denoted by the same reference numerals and will not be described. The magnetization rotation element 110 is an example of a magnetic element.

The magnetization rotation element 110, for example, irradiates light onto the first ferromagnetic layer 1 and evaluates the light reflected by the first ferromagnetic layer 1. When the magnetization orientation direction changes due to the magnetic Kerr effect, the polarization state of the reflected light changes. The magnetization rotation element 110 can be used, for example, as an optical element for an image display device or the like that utilizes the difference in the polarization state of light.

In addition, the magnetized rotating element 110 can be used alone as an anisotropic magnetic sensor, an optical element using the magnetic Faraday effect, etc.

The magnetization rotation element 110 according to the fourth embodiment is the magnetoresistive element 100 except that the nonmagnetic layer 3 and the second ferromagnetic layer 2 have been removed, and provides the same effects as the magnetoresistive element 100 according to the first embodiment.

FIG. 12 is a cross-sectional view of the magnetoresistance effect element 120 according to the fifth embodiment. FIG. 12 is a cross-section of the magnetoresistance effect element 120 cut in an xz plane passing through the center of the width of the wiring layer 21 in the y direction. The magnetoresistance effect element 120 is an example of a magnetic element. The magnetoresistance effect element 100 in FIG. 1 can be replaced with the magnetoresistance effect element 120.

The magnetoresistance effect element 120 has a stack 13, a wiring layer 21, a first magnetization pinned layer 31, and a second magnetization pinned layer 32. In the magnetoresistance effect element 120, the same configuration as the magnetoresistance effect element 100 is given the same reference numerals and description is omitted. The magnetoresistance effect element 120 is an element in which the resistance value changes due to the movement of the domain wall DW, and may be called a domain wall motion element or a domain wall motion type magnetoresistance effect element.

The laminate 13 has a nonmagnetic layer 7 and a first ferromagnetic layer 8 from the side closest to the wiring layer 21. The nonmagnetic layer 7 is made of the same material as the nonmagnetic layer 3. The first ferromagnetic layer 8 is made of the same material as the first ferromagnetic layer 1. The first ferromagnetic layer 1 is a magnetization fixed layer in which the magnetization is fixed.

The wiring layer 21 is a magnetic layer. The wiring layer 21 includes a ferromagnetic material. The magnetic material constituting the wiring layer 21 can be a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, or an alloy containing these metals and at least one of the elements B, C, and N. Specific examples include Co-Fe, Co-Fe-B, and Ni-Fe.

The wiring layer 21 is a layer capable of magnetically recording information by changing the internal magnetic state. The wiring layer 21 has a first magnetic domain and a second magnetic domain inside. The magnetization M21A of the first magnetic domain and the magnetization M21B of the second magnetic domain are oriented in opposite directions, for example. The boundary between the first magnetic domain and the second magnetic domain is a domain wall DW. The wiring layer 21 can have a domain wall DW inside.

The resistance adjustment wiring R1 preferably contains, for example, the same material as the wiring layer 21. If this configuration is met, it is easy to make the forward and reverse write current amounts equal.

The magnetoresistance effect element 120 according to the fifth embodiment can also obtain the same effect as the magnetoresistance effect element 100 according to the first embodiment. Also, like the magnetoresistance effect element 101 according to the third embodiment, the positional relationship between the wiring layer 21 and the first ferromagnetic layer 8 may be reversed, as shown in FIG. 13.

Thus far, several embodiments have been illustrated as examples of preferred aspects of the present invention, but the present invention is not limited to these embodiments. For example, the characteristic configurations of each embodiment may be applied to other embodiments.

1, 8 First ferromagnetic layer 2 Second

ferromagnetic layer

3, 7 Non-magnetic layer 4 Underlayer 5 Cap layer 6

Mask layer

10, 11, 12, 13

Stacked body

20, 21 Wiring layer 31 First magnetization fixed layer 32 Second magnetization fixed layer 90 Insulating

layer

100, 101, 120 Magnetoresistance effect element 110

Magnetization rotation element

200, 201 Integrated device A1 First active region A2 Second active region BL Bit line CL Common wiring R1 Resistance adjustment wiring R1A Narrowed portion R1B Wide portion R1C First portion R1D Second portion RL Read wiring WL Write wiring SL Source line Tr1 First transistor Tr2 Second transistor Tr3 Third transistor V1, V2, V3, V4, V5 Via wiring

Claims

a magnetic element, a first transistor, a second transistor, a first via wiring, a second via wiring, a first wiring, and a resistance adjustment wiring;
the magnetic element includes a wiring layer and a stack including a first ferromagnetic layer connected to the wiring layer;
the first transistor is electrically connected to the stack;
the second transistor has a first active region and a second active region;
the first active region of the second transistor and the wiring layer of the magnetic element are connected through the first via wiring;
the second active region of the second transistor is connected to the second via wiring;
The second via wiring and the first wiring are connected by the resistance adjustment wiring having a higher resistivity than the second via wiring and the first wiring.
The integrated device of claim 1, wherein the resistance adjustment wiring includes any one of an elemental metal, an oxide, a fluoride, or a nitride, including any one selected from the group consisting of W, Pt, Ta, Ti, and Hf.
The integrated device of claim 1, wherein the resistance adjustment wiring includes the same material as the wiring layer.
The integrated device according to claim 2, wherein the ratio of the length of the resistance adjustment wiring divided by its cross-sectional area is 90% or more and 110% or less of the ratio of the length of the wiring layer divided by its cross-sectional area.
The integrated device according to claim 1, wherein the resistance adjustment wiring is meander wiring.
The integrated device according to claim 1, wherein the resistance adjustment wiring has a narrowed portion in which the cross-sectional area perpendicular to the direction of current flow is narrowed.
the laminate comprises a second ferromagnetic layer and a nonmagnetic layer;
The integrated device of claim 1 , wherein the nonmagnetic layer is sandwiched between the first ferromagnetic layer and the second ferromagnetic layer.
a magnetic element, a first transistor, a second transistor, a first via wiring, a second via wiring, a first wiring, and a resistance adjustment wiring;
the magnetic element includes a wiring layer and a stack including a first ferromagnetic layer connected to the wiring layer;
the first transistor is electrically connected to the stack;
the second transistor has a first active region and a second active region;
the first active region of the second transistor and the wiring layer of the magnetic element are connected through the first via wiring;
the second active region of the second transistor is connected to the second via wiring;
An integrated device, wherein the second via wiring and the first wiring are connected by the resistance adjustment wiring having a higher resistance than the second via wiring.
The integrated device according to claim 8, wherein the resistance adjustment wiring is meander wiring.
The integrated device according to claim 8, wherein the resistance adjustment wiring has a narrowed portion in which the cross-sectional area perpendicular to the direction of current flow is narrowed.
the laminate comprises a second ferromagnetic layer and a nonmagnetic layer;
The integrated device of claim 8 , wherein the non-magnetic layer is sandwiched between the first ferromagnetic layer and the second ferromagnetic layer.