WO2024159681A1 - Storage circuit and memory - Google Patents

Abstract

Disclosed are a storage circuit and a memory. The storage circuit comprises 2n word lines, at least one word line driver and 2n protection modules, wherein n is a positive integer. The at least one word line driver is correspondingly connected to first ends of the 2n word lines. Each protection module is correspondingly connected to a second end of one word line. Each word line driver is configured to receive and respond to a drive enable signal, so as to activate a corresponding word line. Each protection module is configured to receive a protection enable signal, and if the protection enable signal represents that the word line connected to the protection module is not activated, ground the second end of the word line.

Description

A storage circuit and a memory

CROSS-REFERENCE TO RELATED APPLICATIONS

The present disclosure is based on and claims the priority of Chinese patent application with application number 202310114279.5 and application date February 2, 2023. The entire contents of the Chinese patent application are hereby introduced into the present disclosure as a reference.

Technical Field

The present disclosure relates to, but is not limited to, a storage circuit and a memory.

Background Art

During the read/write operation of the memory, the voltage on the word line needs to be changed to activate or shut down the word line. However, the speed at which each part of the word line transmits voltage is not the same, thus affecting the speed at which the entire word line is turned on or off. At the same time, the voltage on the word line may be disturbed and changed, which may have an adverse effect on the stored data.

Summary of the invention

In view of this, the embodiments of the present disclosure provide a storage circuit and a memory, which can accelerate the closing speed of a word line and prevent the word line from being disturbed.

The technical solution of the embodiment of the present disclosure is implemented as follows:

An embodiment of the present disclosure provides a storage circuit, which includes: 2n word lines, at least one word line driver and 2n protection modules; n is a positive integer; at least one of the word line drivers is correspondingly connected to the first ends of the 2n word lines; each of the protection modules is correspondingly connected to the second end of one of the word lines; each of the word line drivers is configured to receive and respond to a drive enable signal to activate the corresponding word line; each of the protection modules is configured to receive a protection enable signal, and if the protection enable signal indicates that the word line connected to the protection module is not activated, the second end of the word line is grounded.

In the above solution, each of the protection modules includes: a first transistor; a source of the first transistor is correspondingly connected to the second end of the word line, a drain of the first transistor is grounded, and a gate of the first transistor receives the protection enable signal.

In the above solution, the first transistor is an NMOS transistor; the device size of the first transistor is smaller than the device size of the transistor in the word line driver.

In the above scheme, at least one of the word line drivers includes: a first word line driver and a second word line driver; the 2n word lines include: n first word lines and n second word lines; the 2n protection modules include: n first protection modules and n second protection modules; each of the first word lines extends in the positive direction of the first direction, and each of the second word lines extends in the reverse direction of the first direction; the n first word lines and the n second word lines are arranged alternately in sequence along the second direction; the second direction is perpendicular to the first direction; the first word line driver connects the first ends of the n first word lines; the second word line driver connects the first ends of the n second word lines; the first word line driver and the second word line driver are located on opposite sides of the 2n word lines along the first direction; each of the first protection modules is correspondingly connected to the second end of one of the first word lines; and each of the second protection modules is correspondingly connected to the second end of one of the second word lines.

In the above scheme, the first word line driver includes: m first drive units; the drive enable signal includes: m first drive signals, n second drive signals and n third drive signals; m is a positive integer; the first end of each of the first drive units receives one of the first drive signals; each of the first drive units includes n/m second ends, n/m third ends and n/m fourth ends; each second end of the first drive unit receives one of the second drive signals; each third end of the first drive unit receives one of the third drive signals; the first drive Each fourth end of the unit is correspondingly connected to the first end of one of the first word lines; each of the first driving units is configured to transmit the corresponding each of the second driving signals to the corresponding each of the first word lines in response to the first driving signal to activate each of the first word lines; or, in response to the first driving signal and the corresponding each of the third driving signals, ground the corresponding first end of each of the first word lines to turn off each of the first word lines.

In the above scheme, the second word line driver includes: m second drive units; the drive enable signal also includes: m fourth drive signals, n fifth drive signals and n sixth drive signals; the first end of each second drive unit receives one of the fourth drive signals; each second drive unit includes n/m second ends, n/m third ends and n/m fourth ends; each second end of the second drive unit receives one of the fifth drive signals; each third end of the second drive unit receives one of the sixth drive signals; each fourth end of the second drive unit is connected to the first end of one of the second word lines; each second drive unit is configured to transmit the corresponding fifth drive signal to the corresponding second word line in response to the fourth drive signal to activate each of the second word lines; or, in response to the fourth drive signal and the corresponding sixth drive signal, ground the first end of each of the second word lines in response to the fourth drive signal and the corresponding sixth drive signal to shut down each of the second word lines.

In the above scheme, each of the first driving units includes n/m first driving sub-units; each of the second driving units includes n/m second driving sub-units; each of the first driving sub-units correspondingly receives the second driving signal and the third driving signal with opposite phases; wherein the amplitude of the second driving signal is greater than the amplitude of the corresponding third driving signal; each of the second driving sub-units correspondingly receives the fifth driving signal and the sixth driving signal with opposite phases; wherein the amplitude of the fifth driving signal is greater than the amplitude of the corresponding sixth driving signal.

In the above scheme, each of the first driving sub-units includes: a second transistor, a third transistor and a fourth transistor; the gate of the second transistor and the gate of the third transistor both receive the first driving signal; the gate of the fourth transistor receives each corresponding third driving signal; the source of the second transistor receives each corresponding second driving signal; the source of the third transistor and the source of the fourth transistor are both grounded; the drain of the second transistor, the drain of the third transistor and the drain of the fourth transistor are all connected to the first end of each corresponding first word line; wherein the width-to-length ratio of the fourth transistor is smaller than the width-to-length ratio of the third transistor; or, the width-to-length ratio of the fourth transistor is less than twice the width-to-length ratio of the third transistor; the width-to-length ratio of the first transistor is greater than the width-to-length ratio of the third transistor and less than the width-to-length ratio of the fourth transistor.

In the above scheme, each of the second driving sub-units includes: a fifth transistor, a sixth transistor and a seventh transistor; the gate of the fifth transistor and the gate of the sixth transistor both receive the fourth driving signal; the gate of the seventh transistor receives each corresponding sixth driving signal; the source of the fifth transistor receives each corresponding fifth driving signal; the source of the sixth transistor and the source of the seventh transistor are both grounded; the drain of the fifth transistor, the drain of the sixth transistor and the drain of the seventh transistor are all connected to the first end of each corresponding second word line; wherein the width-to-length ratio of the seventh transistor is smaller than the width-to-length ratio of the sixth transistor; or, the width-to-length ratio of the seventh transistor is less than twice the width-to-length ratio of the sixth transistor; the width-to-length ratio of the first transistor is greater than the width-to-length ratio of the sixth transistor and less than the width-to-length ratio of the seventh transistor.

In the above scheme, the storage circuit also includes: a first protection enable signal generating module and a second protection enable signal generating module; the first protection enable signal generating module is configured to provide the protection enable signal to n first protection modules; the second protection enable signal generating module is configured to provide the protection enable signal to n second protection modules.

In the above scheme, the first protection enable signal generating module includes: m first transmission gates; the input end of each of the first transmission gates corresponds to receiving the first drive signal corresponding to the first drive unit; the output end of each of the first transmission gates outputs the protection enable signal to n/m of the n first protection modules; the second protection enable signal generating module includes: m second transmission gates; the input end of each of the second transmission gates corresponds to receiving the fourth drive signal corresponding to the second drive unit; the output end of each of the second transmission gates outputs the protection enable signal to n/m of the n second protection modules.

In the above solution, the first protection enable signal generating module includes: m first NOR gates; each of the first The input end of the NOR gate receives n/m second drive signals corresponding to one of the first drive units; the output end of each of the first NOR gates outputs the protection enable signal to n/m of the n first protection modules; wherein the second drive signal is valid at a high level; the second protection enable signal generating module comprises: m second NOR gates; the input end of each of the second NOR gates receives n/m fifth drive signals corresponding to one of the second drive units; the output end of each of the second NOR gates outputs the protection enable signal to n/m of the n second protection modules; wherein the fifth drive signal is valid at a high level.

In the above scheme, the first protection enable signal generating module includes: a first AND gate; the input end of the first AND gate receives m first drive signals; the output end of the first AND gate outputs the protection enable signal to n first protection modules; the first drive signal is valid at a low level; the second protection enable signal generating module includes: a second AND gate; the input end of the second AND gate receives m fourth drive signals; the output end of the second AND gate outputs the protection enable signal to n second protection modules; the fourth drive signal is valid at a low level.

In the above scheme, the first protection enable signal generating module includes: n first inverters; each of the first inverters is configured to transmit the corresponding each of the second drive signals as the protection enable signal to the corresponding each of the first protection modules; the second protection enable signal generating module includes: n second inverters; each of the second inverters is configured to transmit the corresponding each of the fifth drive signals as the protection enable signal to the corresponding each of the second protection modules.

An embodiment of the present disclosure further provides a memory, which includes the storage circuit as described in the above solution.

It can be seen that the embodiment of the present disclosure provides a storage circuit and a memory, wherein the storage circuit includes: 2n word lines, at least one word line driver and 2n protection modules; n is a positive integer. At least one word line driver is connected to the first end of the 2n word lines. Each protection module is connected to the second end of a word line. Each word line driver is configured to receive and respond to a drive enable signal to activate the corresponding word line. Each protection module is configured to receive a protection enable signal, and if the protection enable signal indicates that the word line connected to the protection module is not activated, the second end of the word line is grounded. In this way, on the one hand, the protection module can ground the second end of the word line when the word line changes from an activated state to an inactivated state, thereby accelerating the voltage change speed of the second end of the word line, so that the word line can be closed more quickly. On the other hand, the protection module can continue to ground the second end of the word line when the word line remains in an inactivated state, so that the word line remains at a low level and avoids changes in the level on the word line, thereby preventing interference from occurring to the word line and ensuring the stability of the data in the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a first structural diagram of a storage circuit provided by an embodiment of the present disclosure;

FIG2 is a second structural diagram of a storage circuit provided in an embodiment of the present disclosure;

FIG3 is a third structural diagram of a storage circuit provided in an embodiment of the present disclosure;

FIG4 is a fourth structural diagram of a storage circuit provided in an embodiment of the present disclosure;

FIG5 is a fifth structural diagram of a storage circuit provided in an embodiment of the present disclosure;

FIG6 is a signal diagram of a storage circuit provided in an embodiment of the present disclosure;

FIG7 is a sixth structural diagram of a storage circuit provided in an embodiment of the present disclosure;

FIG8 is a seventh structural diagram of a storage circuit provided in an embodiment of the present disclosure;

FIG9A is a schematic diagram of a structure of a storage circuit according to an embodiment of the present disclosure;

FIG9B is a ninth structural diagram of a storage circuit provided in an embodiment of the present disclosure;

FIG10A is a schematic diagram of a structure of a storage circuit provided in an embodiment of the present disclosure;

FIG10B is a schematic diagram 11 of the structure of a storage circuit provided in an embodiment of the present disclosure;

FIG11A is a structural schematic diagram 12 of a storage circuit provided in an embodiment of the present disclosure;

FIG11B is a thirteenth structural diagram of a storage circuit provided in an embodiment of the present disclosure;

FIG12A is a structural schematic diagram 14 of a storage circuit provided in an embodiment of the present disclosure;

FIG12B is a structural schematic diagram 15 of a storage circuit provided in an embodiment of the present disclosure;

FIG13 is a first schematic diagram of the effect of a storage circuit provided by an embodiment of the present disclosure;

FIG14 is a second schematic diagram of the effect of the storage circuit provided by the embodiment of the present disclosure;

FIG15 is a third schematic diagram of the effect of the storage circuit provided by the embodiment of the present disclosure;

FIG. 16 is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

If similar descriptions of "first/second" appear in the invention document, the following description is added. In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

FIG1 is an optional structural diagram of a storage circuit provided in an embodiment of the present disclosure. As shown in FIG1 , a storage circuit 80 includes: 2n word lines, at least one word line driver 10 and 2n protection modules 20; n is a positive integer. Among them, at least one word line driver 10 corresponds to the first end connected to the 2n word lines. Each protection module 20 corresponds to the second end connected to a word line. Each word line driver 10 is configured to receive and respond to a drive enable signal En_1 to activate the corresponding word line. Each protection module 20 is configured to receive a protection enable signal (not shown in FIG1 ). If the protection enable signal indicates that the word line connected to the protection module is not activated, the second end of the word line is grounded.

In the embodiment of the present disclosure, referring to FIG. 2 , each word line is connected to a number of storage cells. When any word line is activated, the storage cells connected to the word line will be turned on to read or write data. Specifically, when a word line is activated, it is at a high level, and the storage cells connected to the word line are turned on under the trigger of the high level; correspondingly, when a word line is not activated, it is at a low level, and the storage cells connected to the word line remain closed.

In the embodiment of the present disclosure, referring to FIG1 , the word line driver 10 responds to the drive enable signal En_1 to activate the corresponding word line. That is, the word line driver 10 transmits a high level to the corresponding word line to activate the corresponding word line; correspondingly, the word line driver 10 also transmits a low level to the corresponding word line to make the corresponding word line inactive.

However, since the speed at which the word line driver 10 transmits voltage to each part of the word line is different; the part of the word line close to the word line driver 10 is transmitted with a faster speed, and its voltage changes faster; correspondingly, the part of the word line far from the word line driver 10 is transmitted with a slower speed, and its voltage changes slower. The word line driver 10 is connected to the first end of the word line, that is, the first end of the word line is the end close to the word line driver 10, that is, the near end; and the second end of the word line is the end far from the word line driver 10, that is, the far end. Therefore, when the row is activated (that is, the word line is activated), the voltage change speed of the first end of the word line is faster than the voltage change speed of the second end of the word line.

Furthermore, each protection module 20, controlled by receiving a protection enable signal (not shown in FIG. 1 ), can ground the second end of the word line when the protection enable signal indicates that the word line connected to the protection module is not activated. That is, when the word line driver 10 controls the word line to change from a high level to a low level, that is, when the word line changes from an activated state to an inactivated state, the protection module 20 can ground the second end of the word line, so that the second end of the word line quickly changes to a low level.

In the embodiment of the present disclosure, referring to FIG. 1, since the word line driver transmits the signal to the second end of the word line relatively slowly, the second end of the word line is more weakly controlled by the word line driver 10, and the second end of the word line is easily disturbed by other factors and changes to an erroneous voltage state, for example, being disturbed by a Row hammer attack. It should be noted that a Row hammer attack is to repeatedly activate a certain word line and accelerate the leakage speed of the storage cells on other word lines adjacent to the word line through crosstalk between rows, thereby increasing the probability of data errors and damaging the storage cells. Allow.

Furthermore, when the word line remains in an inactive state, the protection module 20 may continue to ground the second end of the word line to keep the word line at a low level, thereby preventing the level on the word line from changing.

It is understandable that, on the one hand, the protection module can ground the second end of the word line when the word line changes from an activated state to an inactivated state, thereby accelerating the voltage change speed of the second end of the word line, so that the word line can be closed more quickly.

On the other hand, the protection module can continue to ground the second end of the word line when the word line remains in an inactive state, so that the word line remains at a low level and the level on the word line is prevented from changing. Thus, the word line can be prevented from interference and the stability of the data in the memory can be ensured. At the same time, since the word line is in an inactive state most of the time, that is, the time each word line is in an active state is much shorter than the time in an inactive state. Therefore, the protection module grounds the second end of the word line when the word line is in an inactive state, thus ensuring that the word line can be protected and prevented from interference most of the time.

In some embodiments of the present disclosure, as shown in Fig. 3, each protection module 20 includes: a first transistor M1. The source of the first transistor M1 corresponds to the second end of the word line, the drain of the first transistor M1 is grounded, and the gate of the first transistor M1 receives a protection enable signal.

It is understandable that by controlling the on and off of the first transistor, the second end of the word line can be grounded when the word line is in an inactive state. In this way, on the one hand, the voltage change speed of the second end of the word line can be accelerated, so that the word line can be turned off more quickly; on the other hand, the word line can be prevented from being disturbed, ensuring the stability of the data in the memory.

In some embodiments of the present disclosure, referring to FIG. 3 , the first transistor M1 is an NMOS transistor, and the device size of the first transistor M1 is smaller than the device size of the transistor in the word line driver 10 .

In the embodiment of the present disclosure, the first transistor M1 in the protection module 20 is different from the transistor in the word line driver 10, and the first transistor M1 does not serve as the main current path for word line discharge. Therefore, the first transistor M1 only needs a smaller device size to achieve its function; that is, the device size of the first transistor M1 is smaller than the device size of the transistor in the word line driver 10.

It can be understood that the device size of the first transistor is relatively small, which can reduce the circuit area occupied by the first transistor, thereby improving the integration of the chip.

In some embodiments of the present disclosure, referring to FIG. 4 , at least one word line driver includes: a first word line driver 101 and a second word line driver 102 . 2n word lines include: n first word lines 301 and n second word lines 302 . 2n protection modules include: n first protection modules 201 and n second protection modules 202 .

Each first word line 201 extends in the positive direction of the first direction X, and each second word line 202 extends in the reverse direction of the first direction X; n first word lines 201 and n second word lines 202 are arranged alternately in sequence along the second direction Y. The second direction Y is perpendicular to the first direction X. The first word line driver 101 is connected to the first ends of the n first word lines 301. The second word line driver 102 is connected to the first ends of the n second word lines 302. The first word line driver 101 and the second word line driver 102 are located on opposite sides of the 2n word lines along the first direction X. Each first protection module 201 is connected to the second end of a first word line 301. Each second protection module 202 is connected to the second end of a second word line 302.

In some embodiments of the present disclosure, referring to FIG5 , the first word line driver 101 includes: m first driving units 401. The driving enable signal includes: m first driving signals MWLB, n second driving signals FX and n third driving signals FXB. Both m and n are positive integers, and n is an integer multiple of m.

It should be noted that in Figure 5, the m first drive signals MWLB are numbered odd numbers, namely MWLB<1>, MWLB<3>, ... and MWLB<2m-1>; the n second drive signals FX are numbered odd numbers, namely FX<1>, FX<3>, FX<5>, FX<7>, ..., FX<2n-3> and FX<2n-1>; the n third drive signals FXB are also numbered odd numbers, namely FXB<1>, FXB<3>, FXB<5>, FXB<7>, ..., FXB<2n-3> and FXB<2n-1>.

In the embodiment of the present disclosure, referring to FIG. 5 , the first end of each first driving unit 401 receives a first driving signal MWLB. Each first driving unit 401 includes n/m second ends, n/m third ends, and n/m fourth ends. Each second end of the first driving unit 401 receives a second driving signal FX. Each third end of the first driving unit 401 receives a third driving signal FXB. Each fourth end of the first driving unit 401 receives a first driving signal FXB. A first end of a word line WL.

It should be noted that in Fig. 5, the first word lines WL are labeled with odd numbers, namely WL_1, WL_3, WL_5, WL_7, ..., WL_2n-3 and WL_2n-1. At the same time, Fig. 5 takes n/m=4 as an example, that is, each first driving unit 401 includes 4 second terminals, 4 third terminals and 4 fourth terminals.

Referring to FIG. 5 , each first driving unit 401 is configured to transmit each corresponding second driving signal FX to each corresponding first word line WL in response to the first driving signal MWLB to activate each first word line WL; or, in response to the first driving signal MWLB and each corresponding third driving signal FXB, ground the first end of each corresponding first word line WL to close each first word line. That is, the first driving unit 401 can transmit the second driving signal FX at a high level to the corresponding first word line WL in response to the first driving signal MWLB, so that the first word line WL is at a high level (i.e., activate the first word line WL). Correspondingly, the first driving unit 401 can also ground the first end of the first word line WL in response to the first driving signal MWLB and the corresponding third driving signal FXB, so that the first word line WL is at a low level (i.e., close the first word line WL, so that the first word line WL is in an inactive state). In this way, each first driving unit 401 can control the state of the corresponding first word line WL.

In some embodiments of the present disclosure, referring to Fig. 5, the second word line driver 102 includes: m second driving units 402. The driving enable signal also includes: m fourth driving signals MWLB, n fifth driving signals FX and n sixth driving signals FXB. Both m and n are positive integers.

It should be noted that in Figure 5, the m fourth drive signals MWLB are numbered as even numbers, namely MWLB<0>, MWLB<2>, ... and MWLB<2m-2>; the n fifth drive signals FX are numbered as even numbers, namely FX<0>, FX<2>, FX<4>, FX<6>, ..., FX<2n-4> and FX<2n-2>; and the n sixth drive signals FXB are also numbered as odd numbers, namely FXB<0>, FXB<2>, FXB<4>, FXB<6>, ..., FXB<2n-4> and FXB<2n-2>.

In the embodiment of the present disclosure, referring to FIG. 5 , the first end of each second driving unit 402 receives a fourth driving signal MWLB. Each second driving unit 402 includes n/m second ends, n/m third ends, and n/m fourth ends. Each second end of the second driving unit 402 receives a fifth driving signal FX. Each third end of the second driving unit 402 receives a sixth driving signal FXB. Each fourth end of the second driving unit 402 is connected to the first end of a second word line WL.

It should be noted that in Fig. 5, the second word lines WL are numbered even numbers, namely WL_0, WL_2, WL_4, WL_6, ..., WL_2n-4 and WL_2n-2. Meanwhile, Fig. 5 takes n/m=4 as an example, that is, each second driving unit 402 includes 4 second terminals, 4 third terminals and 4 fourth terminals.

Each second driving unit 402 is configured to transmit the corresponding fifth driving signal FX to each corresponding second word line WL in response to the fourth driving signal MWLB to activate each second word line WL; or, in response to the fourth driving signal MWLB and each corresponding sixth driving signal FXB, ground the first end of each corresponding second word line WL to turn off each second word line WL. That is, the second driving unit 402 can transmit the fifth driving signal FX at a high level to the corresponding second word line WL in response to the fourth driving signal MWLB, so that the second word line WL is at a high level (i.e., activate the second word line WL). Correspondingly, the second driving unit 402 can also ground the first end of the second word line WL in response to the fourth driving signal MWLB and the corresponding sixth driving signal FXB, so that the second word line WL is at a low level (i.e., turn off the second word line WL and make the second word line WL in an inactive state). In this way, each second driving unit 402 can control the state of the corresponding second word line WL.

Fig. 6 shows the waveforms of the signals MWLB, FX and FXB, wherein the signals MWLB, FX and FXB can be respectively used as the first drive signal, the second drive signal and the third drive signal, and input to the first drive unit 401; correspondingly, the signals MWLB, FX and FXB can also be respectively used as the fourth drive signal, the fifth drive signal and the sixth drive signal, and input to the second drive unit 402.

It should be noted that the waveforms of the signals with different labels shown in Figure 5 are not the same. For example, the signal MWLB<1> and the signal MWLB<3> are two different signals with different waveforms. For example, the signal FX<1> and FX<3> are two different signals with different waveforms.

6 shows the waveforms of the signals MWLB, FX and FXB, which are merely examples of the waveforms of the signals input to the same first The waveforms of the first drive signal, the second drive signal and the third drive signal of the drive unit 401 are illustrated, or the waveforms of the fourth drive signal, the fifth drive signal and the sixth drive signal input to the same second drive unit 402 are illustrated. For example, the waveforms of the first drive signal MWLB<1>, the second drive signal FX<1> and the third drive signal FXB<1> are illustrated in FIG6 , and the waveforms of the fourth drive signal MWLB<0>, the fifth drive signal FX<0> and the sixth drive signal FXB<0> are illustrated in FIG6 .

In some embodiments of the present disclosure, each first driving unit 401 includes n/m first driving sub-units; each second driving unit 402 includes n/m second driving sub-units. Each first driving sub-unit receives a second driving signal FX and a third driving signal FXB with opposite phases; wherein the amplitude of the second driving signal FX is greater than the amplitude of the corresponding third driving signal FXB. Each second driving sub-unit receives a fifth driving signal FX and a sixth driving signal FXB with opposite phases; wherein the amplitude of the fifth driving signal FX is greater than the amplitude of the corresponding sixth driving signal FXB.

Fig. 7 takes n/m=4 as an example to show the circuit structure of a first driving unit 401. The second driving unit 402 has a circuit structure similar to that of the first driving unit 401, which can be understood by referring to Fig. 7 .

It should be noted that the first driving unit 401 shown in FIG7 includes four first driving sub-units 4011, and the four first driving sub-units 4011 all receive the first driving signal MWLB<1>. At the same time, the four first driving sub-units 4011 respectively receive different second driving signals FX and third driving signals FXB. Specifically, the first first driving sub-unit 4011 receives the second driving signal FX<1> and the third driving signal FXB<1>, the second first driving sub-unit 4011 receives the second driving signal FX<3> and the third driving signal FXB<3>, the third first driving sub-unit 4011 receives the second driving signal FX<5> and the third driving signal FXB<5>, and the fourth first driving sub-unit 4011 receives the second driving signal FX<7> and the third driving signal FXB<7>.

In conjunction with FIG6 and FIG7, the second drive signal FX<1> and the third drive signal FXB<1> have opposite phases, and the amplitude of the second drive signal FX<1> is greater than the amplitude of the third drive signal FXB<1>, and the waveforms of the second drive signal FX<1> and the third drive signal FXB<1> can refer to the signals FX and FXB shown in FIG6. Correspondingly, the second drive signal FX<3> and the third drive signal FXB<3> have opposite phases, and the amplitude of the second drive signal FX<3> is greater than the amplitude of the third drive signal FXB<3>, and the waveforms of the second drive signal FX<3> and the third drive signal FXB<3> can also refer to the signals FX and FXB shown in FIG6, and so on.

In some embodiments of the present disclosure, referring to FIG. 7 , each first driver subunit 4011 includes: a second transistor M2, a third transistor M3, and a fourth transistor M4. The gate of the second transistor M2 and the gate of the third transistor M3 both receive the first drive signal MWLB. The gate of the fourth transistor M4 receives each corresponding third drive signal FXB. The source of the second transistor M2 receives each corresponding second drive signal FX. The source of the third transistor M3 and the source of the fourth transistor M4 are both grounded. The drain of the second transistor M2, the drain of the third transistor M3, and the drain of the fourth transistor M4 are all connected to the first end of each corresponding first word line WL.

In the embodiment of the present disclosure, in combination with FIG. 6 and FIG. 7 , the first first driver subunit 4011 in FIG. 7 is taken as an example for description. The transistor in the first first driver subunit 4011 receives the first drive signal MWLB<1>, the second drive signal FX<1> and the third drive signal FXB<1>, and is connected to the first word line WL_1. When the first drive signal MWLB<1> is at a low level, the second drive signal FX<1> is at a high level, and the third drive signal FXB<1> is at a low level; at this time, the second transistor M2 is turned on, and the third transistor M3 and the fourth transistor M4 are turned off; the second drive signal FX<1> is transmitted to the first word line WL_1 through the second transistor M2, so that the first word line WL_1 is at a high level, that is, the first word line WL_1 is activated. When the first drive signal MWLB<1> is at a high level, the second drive signal FX<1> is at a low level, and the third drive signal FXB<1> is at a high level; at this time, the second transistor M2 is turned off, and the third transistor M3 and the fourth transistor M4 are turned on; the first word line WL_1 is connected to the ground terminal GND through the third transistor M3 and the fourth transistor M4, and the first word line WL_1 is at a low level, that is, the first word line WL_1 is turned off and is in an inactive state.

In some embodiments of the present disclosure, referring to FIG. 7 , the width-to-length ratio of the fourth transistor M4 is smaller than the width-to-length ratio of the third transistor M3 . In other words, the device size of the fourth transistor M4 can be designed to be smaller, thereby saving the area occupied by the circuit and improving the integration.

In some other embodiments of the present disclosure, referring to FIG. 7 , the width-to-length ratio of the fourth transistor M4 is smaller than that of the third transistor M4. The width-to-length ratio of the first transistor M1 is twice that of the third transistor M3; the width-to-length ratio of the first transistor M1 is greater than the width-to-length ratio of the third transistor M3, and less than or equal to the width-to-length ratio of the fourth transistor M4. In other words, the first transistor and the fourth transistor together constitute the main discharge path, which is conducive to sharing the discharge pressure of the original fourth transistor, while balancing the size ratio of the fourth transistor and the second transistor, which is convenient for layout.

In some other embodiments, the aspect ratio of the fourth transistor is 3.5 to 4.5 times the aspect ratio of the second transistor and the aspect ratio of the first transistor, for example 3.75, 4, or 4.25 times, and the aspect ratio of the first transistor is similar to that of the second transistor.

In some embodiments of the present disclosure, each second driver subunit includes: a fifth transistor, a sixth transistor, and a seventh transistor. The gate of the fifth transistor and the gate of the sixth transistor both receive the fourth drive signal. The gate of the seventh transistor receives each corresponding sixth drive signal. The source of the fifth transistor receives each corresponding fifth drive signal. The source of the sixth transistor and the source of the seventh transistor are both grounded. The drain of the fifth transistor, the drain of the sixth transistor, and the drain of the seventh transistor are all connected to the first end of each corresponding second word line.

It should be noted that the circuit structure of the second driving subunit can be understood with reference to the circuit structure of the first driving subunit 401 shown in FIG7 . Among them, the fifth transistor corresponds to the second transistor M2 in FIG7 , the sixth transistor corresponds to the third transistor M3 in FIG7 , the seventh transistor corresponds to the fourth transistor M4 in FIG7 , the fourth driving signal corresponds to the first driving signal MWLB in FIG7 , the fifth driving signal corresponds to the second driving signal FX in FIG7 , and the sixth driving signal corresponds to the third driving signal FXB in FIG7 .

Accordingly, in some embodiments of the present disclosure, the aspect ratio of the seventh transistor is smaller than that of the sixth transistor. In other words, the device size of the seventh transistor can be designed to be smaller. In this way, the area occupied by the circuit can be saved and the integration can be improved.

In some other embodiments of the present disclosure, the width-to-length ratio of the seventh transistor is less than twice the width-to-length ratio of the sixth transistor; the width-to-length ratio of the first transistor is greater than the width-to-length ratio of the sixth transistor and less than the width-to-length ratio of the seventh transistor.

In some other embodiments, the aspect ratio of the seventh transistor is 3.5 to 4.5 times, such as 3.75, 4, or 4.25 times, of the aspect ratio of the fifth transistor and the aspect ratio of the first transistor, and the aspect ratio of the first transistor is similar to that of the fifth transistor.

It is understandable that each driving unit (first driving unit 401 or second driving unit 402) can control the state of a corresponding word line according to the driving signal it receives, so as to achieve accurate control of each word line and ensure the execution of various operations in the memory.

In some embodiments of the present disclosure, referring to FIG8 , the storage circuit 80 further includes: a first protection enable signal generating module 501 and a second protection enable signal generating module 502. The first protection enable signal generating module 501 is configured to provide a protection enable signal En_2 to the n first protection modules 201. The second protection enable signal generating module 502 is configured to provide a protection enable signal En_2 to the n second protection modules 202.

In the embodiment of the present disclosure, referring to FIG8 , the row address decoder 60 can decode and generate a corresponding drive enable signal En_1 (including signals MWLB, FX and FXB) according to the row address signal during the RAS (row strobe) process, and send the drive enable signal En_1 to the first word line driver 101 and the second word line driver 102. The first protection enable signal generation module 501 can receive a portion of the drive enable signal En_1 corresponding to the first word line driver 101, generate and send a protection enable signal En_2 to the corresponding first protection module 201; correspondingly, the second protection enable signal generation module 502 can receive a portion of the drive enable signal En_1 corresponding to the second word line driver 102, generate and send a protection enable signal En_2 to the corresponding second protection module 202.

In some embodiments of the present disclosure, referring to FIG. 9A , the first protection enable signal generating module 501 includes: m first transmission gates TG1. The input end of each first transmission gate TG1 receives a first drive signal (MWLB<1>, MWLB<3>, ... or MWLB<2m-1>) corresponding to a first drive unit. The output end of each first transmission gate TG1 outputs a protection enable signal (En_2_1, En_2_3, ... or En_2_2m-1) to n/m of the n first protection modules.

Correspondingly, referring to FIG. 9B , the second protection enable signal generating module 502 includes: m second transmission gates TG2 . The input end of each second transmission gate TG2 receives a fourth driving signal (MWLB<0>, MWLB<2>, ... or MWLB<2m-2>) corresponding to a second driving unit. The output end of each second transmission gate outputs a protection enable signal (En_2_0, En_2_2, ... or En_2_2m-2) to n/m of the n second protection modules.

In the embodiment of the present disclosure, in combination with FIG. 5 and FIG. 9A , the first first transmission gate TG1 and the first first driving unit 401 are taken as an example for description. The first first transmission gate TG1 corresponds to the first first driving unit 401, and they both receive the first driving signal MWLB<1>. Furthermore, the protection enable signal En_2_1 output by the first first transmission gate TG1 is transmitted to the first protection module connected to the first word lines WL_1, WL_3, WL_5 and WL_7.

Furthermore, since the first drive signal MWLB<1> can control the states of the first word lines WL_1, WL_3, WL_5 and WL_7, the first first transmission gate TG1 obtains the protection enable signal En_2_1 according to the first drive signal MWLB<1>, and further controls the corresponding first protection module. In this way, the first protection module can ground the second ends of the first word lines WL_1, WL_3, WL_5 and WL_7 when the first word lines WL_1, WL_3, WL_5 and WL_7 are in an inactive state.

In addition, other first transmission gates TG1 and other first driving units 401 , as well as the second transmission gate TG2 and the second driving unit 402 , can be understood with reference to the first first transmission gate TG1 and the first first driving unit 401 .

It can be understood that the first transmission gate can generate a protection enable signal corresponding to the first protection module according to the first drive signal, and the second transmission gate can generate a protection enable signal corresponding to the second protection module according to the fourth drive signal. In this way, by multiplexing the first drive signal and the fourth drive signal in the drive enable signal, the control of the protection module is completed without introducing a new control signal, thereby simplifying the circuit design and improving the integration.

In some embodiments of the present disclosure, referring to FIG. 10A , the first protection enable signal generating module 501 includes: m first NOR gates NOR1. The input end of each first NOR gate NOR1 receives n/m second drive signals FX corresponding to a first drive unit. The output end of each first NOR gate NOR1 outputs a protection enable signal (En_2_1, En_2_3, ... or En_2_2m-1) to n/m of the n first protection modules. The second drive signal is high level valid.

Accordingly, in some embodiments of the present disclosure, referring to FIG. 10B , the second protection enable signal generating module 502 includes: m second NOR gates NOR2. The input end of each second NOR gate NOR2 receives n/m fifth drive signals FX corresponding to a second drive unit; the output end of each second NOR gate NOR2 outputs a protection enable signal (En_2_0, En_2_2, ... or En_2_2m-2) to n/m of the n second protection modules. The fifth drive signal is high level valid.

In the embodiment of the present disclosure, in combination with FIG. 5 and FIG. 10A, the first first NOR gate NOR1 and the first first driving unit 401 are taken as an example for description. The first first NOR gate NOR1 corresponds to the first first driving unit 401, and they both receive the second driving signals FX<1>, FX<3>, FX<5> and FX<7>. Furthermore, the protection enable signal En_2_1 output by the first first NOR gate NOR1 is transmitted to the first protection module connected to the first word lines WL_1, WL_3, WL_5 and WL_7.

Furthermore, since the second drive signals FX<1>, FX<3>, FX<5> and FX<7> can be transmitted to the first word lines WL_1, WL_3, WL_5 and WL_7 accordingly to control the states of the first word lines WL_1, WL_3, WL_5 and WL_7; then, the first first NOR gate NOR1 obtains the protection enable signal En_2_1 according to the second drive signals FX<1>, FX<3>, FX<5> and FX<7>, and further controls the corresponding first protection module. In this way, the first protection module can ground the second ends of the first word lines WL_1, WL_3, WL_5 and WL_7 when the first word lines WL_1, WL_3, WL_5 and WL_7 are all in an inactive state; correspondingly, the first protection module can also disconnect the second ends of the first word lines WL_1, WL_3, WL_5 and WL_7 from the ground end when any one of the first word lines WL_1, WL_3, WL_5 and WL_7 is in an activated state.

In addition, other first NOR gates NOR1 and other first driving units 401 , as well as the second NOR gate NOR2 and the second driving unit 402 , can be understood with reference to the first first NOR gate NOR1 and the first first driving unit 401 .

It is understandable that the first NOR gate can generate a protection enable signal corresponding to the first protection module according to the second drive signal. The second NOR gate can generate a protection enable signal corresponding to the second protection module according to the fifth drive signal. In this way, the protection module is controlled by multiplexing the second drive signal and the fifth drive signal in the drive enable signal without introducing a new control signal, thereby simplifying the circuit design and improving the integration.

In some embodiments of the present disclosure, referring to FIG. 11A , the first protection enable signal generating module 501 includes: a first AND gate AND1. The input end of the first AND gate AND1 receives m first drive signals (including MWLB<1>, MWLB<3>, ... and MWLB<2m-1>). The output end of the first AND gate AND1 outputs the protection enable signal En_2_1 to n first protection modules. Among them, the m first drive signals are all low level effective.

Accordingly, in some embodiments of the present disclosure, referring to FIG. 11B , the second protection enable signal generating module 502 includes: a second AND gate AND2. The input end of the second AND gate AND2 receives m fourth drive signals (including MWLB<0>, MWLB<2>, ... and MWLB<2m-2>). The output end of the second AND gate AND2 outputs the protection enable signal En_2_0 to n second protection modules. Among them, the m fourth drive signals are low level effective.

In the disclosed embodiment, in combination with FIG. 5 and FIG. 11A, due to the m first drive signals (including MWLB<1>, MWLB<3>, ... and MWLB<2m-1>), the states of n first word lines (including WL_1, WL_3, ... and WL_2n-1) can be controlled; then, the first AND gate AND1 obtains the protection enable signal En_2_1 according to the m first drive signals, and then controls the first protection modules corresponding to the n first word lines. In this way, the first protection module can ground the second ends of the n first word lines when all the n first word lines are in an inactive state; correspondingly, the first protection module can disconnect the second ends of the n first word lines from the ground end when any one of the n first word lines is in an active state.

5 and 11B , since the m fourth drive signals (including MWLB<0>, MWLB<2>, ... and MWLB<2m-2>) can control the states of n second word lines (including WL_0, WL_2, ... and WL_2n-2); then, the second AND gate AND2 obtains the protection enable signal En_2_0 according to the m fourth drive signals, and further controls the second protection modules corresponding to the n second word lines; in this way, the second protection module can ground the second ends of the n second word lines when the n second word lines are in an inactive state.

It can be understood that the first AND gate can generate a protection enable signal corresponding to the first protection module according to the first drive signal, and the second AND gate can generate a protection enable signal corresponding to the second protection module according to the fourth drive signal. In this way, by multiplexing the first drive signal and the fourth drive signal in the drive enable signal, the control of the protection module is completed without introducing a new control signal, thereby simplifying the circuit design and improving the integration.

In some embodiments of the present disclosure, referring to FIG. 12A , the first protection enable signal generating module 501 includes: n first inverters INV1. Each first inverter INV1 is configured to transmit each corresponding second drive signal (FX<1>, FX<3>, ... or FX<2n-1>) as a protection enable signal (En_2_1, En_2_3, ... or En_2_2n-1) to each corresponding first protection module.

Accordingly, in some embodiments of the present disclosure, referring to FIG. 12B , the second protection enable signal generating module 502 includes: n second inverters INV2. Each second inverter INV2 is configured to transmit each corresponding fifth drive signal (FX<0>, FX<2>, ... or FX<2n-2>) as a protection enable signal (En_2_0, En_2_2, ... or En_2_2n-2) to each corresponding second protection module.

It can be understood that, since the second drive signal can be transmitted to the first word line to control the state of the first word line, the fifth drive signal can be transmitted to the second word line to control the state of the second word line. The first inverter transmits the second drive signal to the corresponding first protection module to ground the second end of the first word line when the first word line is in an inactive state; the second inverter transmits the fifth drive signal to the corresponding second protection module to ground the second end of the second word line when the second word line is in an inactive state. In this way, by multiplexing the second drive signal and the fifth drive signal in the drive enable signal, the control of the protection module is completed without introducing a new control signal, thereby simplifying the circuit design and improving the integration.

13 to 15 show the voltage variation at both ends of a word line when the embodiment of the present disclosure is not adopted, wherein the proximal voltage 1 is a voltage variation curve of the first end of the word line, and the distal voltage 1 is a voltage variation curve of the second end of the word line.

13 to 15 also show the voltage variation of the word line when the embodiment of the present disclosure is adopted, wherein the proximal voltage 2 is the voltage variation curve of the first end of the word line, and the distal voltage 2 is the voltage variation curve of the second end of the word line.

13 , when the word line is activated, the proximal voltage 1 coincides with the proximal voltage 2, and the distal voltage 1 coincides with the distal voltage 2. That is, the use of the disclosed embodiment will not affect the activation process of the word line, and the word line can be activated normally.

Referring to FIG. 14 , the variation amplitude of the proximal voltage 2 is smaller than that of the proximal voltage 1, and the variation amplitude of the distal voltage 2 is significantly smaller than that of the distal voltage 1. That is, when a word line is attacked by a Row Hammer, if the disclosed embodiment is used, the word line adjacent to the Row Hammer attack row is less affected by the crosstalk, and the degree of optimization of the distal voltage is more obvious, indicating that the disclosed embodiment can effectively enhance the memory's defense capability against Row Hammer attacks.

Referring to FIG15 , the falling speed of the proximal voltage 2 is faster than that of the proximal voltage 1, and the falling speed of the distal voltage 2 is significantly faster than that of the distal voltage 1. In other words, by adopting the embodiment of the present disclosure, the speed of closing the word line can be accelerated; accordingly, the device size of the transistor in the word line driver can be optimized, thereby reducing the circuit area and improving the integration.

The embodiment of the present disclosure further provides a memory. As shown in FIG. 16 , the memory 90 includes a storage circuit 80 .

In some embodiments of the present disclosure, referring to FIG. 16 , the memory 90 includes a dynamic random access memory DRAM.

It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Industrial Applicability

The embodiment of the present disclosure provides a storage circuit and a memory, wherein the storage circuit includes: 2n word lines, at least one word line driver and 2n protection modules; n is a positive integer. At least one word line driver is connected to the first end of the 2n word lines. Each protection module is connected to the second end of a word line. Each word line driver is configured to receive and respond to a drive enable signal to activate the corresponding word line. Each protection module is configured to receive a protection enable signal, and if the protection enable signal indicates that the word line connected to the protection module is not activated, the second end of the word line is grounded. In this way, on the one hand, the protection module can ground the second end of the word line when the word line changes from an activated state to an inactivated state, thereby accelerating the voltage change speed of the second end of the word line, so that the word line can be closed more quickly. On the other hand, the protection module can continue to ground the second end of the word line when the word line remains in an inactivated state, so that the word line remains at a low level and avoids changes in the level on the word line, thereby preventing interference from occurring to the word line and ensuring the stability of the data in the memory.

Claims (15)

1. A storage circuit (80), comprising: 2n word lines, at least one word line driver (10) and 2n protection modules (20); n is a positive integer;

   At least one of the word line drivers (10) is connected to the first ends of the 2n word lines; each of the protection modules (20) is connected to the second end of one of the word lines;

   Each of the word line drivers (10) is configured to receive and respond to a drive enable signal to activate the corresponding word line;

   Each of the protection modules (20) is configured to receive a protection enable signal, and if the protection enable signal indicates that the word line connected to the protection module (20) is not activated, the second end of the word line is grounded.
2. The storage circuit (80) according to claim 1, wherein each of the protection modules (20) comprises: a first transistor (M1);

   The source of the first transistor (M1) is correspondingly connected to the second end of the word line, the drain of the first transistor (M1) is grounded, and the gate of the first transistor (M1) receives the protection enable signal.
3. The memory circuit (80) according to claim 2, wherein:

   The first transistor (M1) is an NMOS transistor;

   The device size of the first transistor (M1) is smaller than the device size of the transistor in the word line driver (10).
4. The storage circuit (80) according to claim 2 or 3, wherein at least one of the word line drivers (10) comprises: a first word line driver (101) and a second word line driver (102); the 2n word lines comprise: n first word lines (301) and n second word lines (302); the 2n protection modules (20) comprise: n first protection modules (201) and n second protection modules (202);

   Each of the first word lines (301) extends in a positive direction of a first direction, and each of the second word lines (302) extends in a negative direction of the first direction; n first word lines (301) and n second word lines (302) are alternately arranged in sequence along a second direction; the second direction is perpendicular to the first direction;

   The first word line driver (101) is connected to the first ends of n first word lines (301); the second word line driver (102) is connected to the first ends of n second word lines (302); the first word line driver (101) and the second word line driver (102) are located on opposite sides of the 2n word lines along the first direction;

   Each of the first protection modules (201) is connected to a second end of the first word line (301); and each of the second protection modules (202) is connected to a second end of the second word line (302).
5. The storage circuit (80) according to claim 4, wherein the first word line driver (101) comprises: m first drive units (401); the drive enable signal comprises: m first drive signals, n second drive signals and n third drive signals; m is a positive integer;

   The first end of each of the first driving units (401) receives a first driving signal;

   Each of the first driving units (401) comprises n/m second ends, n/m third ends and n/m fourth ends; each second end of the first driving unit (401) receives a corresponding second driving signal; each third end of the first driving unit (401) receives a corresponding third driving signal;

   Each fourth end of the first driving unit (401) is correspondingly connected to a first end of the first word line (301);

   Each of the first driving units (401) is configured to transmit, in response to the first driving signal, each of the corresponding second driving signals to each of the corresponding first word lines (301) so as to activate each of the first word lines (301); or, in response to the first driving signal and each of the corresponding third driving signals, ground the first end of each of the corresponding first word lines (301) so as to shut down each of the first word lines (301).
6. The storage circuit (80) according to claim 5, wherein the second word line driver (102) comprises: m second drive units (402); the drive enable signal further comprises: m fourth drive signals, n fifth drive signals and n sixth drive signals;

   The first end of each of the second driving units (402) receives a fourth driving signal;

   Each of the second driving units (402) comprises n/m second ends, n/m third ends and n/m fourth ends; each second end of the second driving unit (402) receives one of the fifth driving signals correspondingly; each third end of the second driving unit (402) receives one of the sixth driving signals correspondingly;

   Each fourth end of the second driving unit (402) is correspondingly connected to a first end of the second word line (302);

   Each of the second driving units (402) is configured to transmit, in response to the fourth driving signal, each of the corresponding fifth driving signals to each of the corresponding second word lines (302) so as to activate each of the second word lines (302); or, in response to the fourth driving signal and each of the corresponding sixth driving signals, ground the first end of each of the corresponding second word lines (302) so as to shut down each of the second word lines (302).
7. The storage circuit (80) according to claim 6, wherein each of the first driving units (401) comprises n/m first driving sub-units; and each of the second driving units (402) comprises n/m second driving sub-units;

   Each of the first driving sub-units correspondingly receives the second driving signal and the third driving signal with opposite phases; wherein the amplitude of the second driving signal is greater than the amplitude of the corresponding third driving signal;

   Each of the second driving sub-units correspondingly receives the fifth driving signal and the sixth driving signal with opposite phases; wherein the amplitude of the fifth driving signal is greater than the amplitude of the corresponding sixth driving signal.
8. The storage circuit (80) according to claim 7, wherein each of the first driving subunits comprises: a second transistor (M2), a third transistor (M3) and a fourth transistor (M4);

   The gate of the second transistor (M2) and the gate of the third transistor (M3) both receive the first drive signal; the gate of the fourth transistor (M4) receives each corresponding third drive signal;

   The source of the second transistor (M2) receives each corresponding second drive signal; the source of the third transistor (M3) and the source of the fourth transistor (M4) are both grounded;

   The drain of the second transistor (M2), the drain of the third transistor (M3) and the drain of the fourth transistor (M4) are all connected to the first end of each corresponding first word line (301);

   Wherein, the width-to-length ratio of the fourth transistor (M4) is smaller than the width-to-length ratio of the third transistor (M3);

   Alternatively, the width-to-length ratio of the fourth transistor (M4) is less than twice the width-to-length ratio of the third transistor (M3); the width-to-length ratio of the first transistor (M1) is greater than the width-to-length ratio of the third transistor (M3) and less than the width-to-length ratio of the fourth transistor (M4).
9. The storage circuit (80) according to claim 7 or 8, wherein each of the second driving subunits comprises: a fifth transistor, a sixth transistor and a seventh transistor;

   The gate of the fifth transistor and the gate of the sixth transistor both receive the fourth driving signal; the gate of the seventh transistor receives each corresponding sixth driving signal;

   The source of the fifth transistor receives each corresponding fifth driving signal; the source of the sixth transistor and the source of the seventh transistor are both grounded;

   The drain of the fifth transistor, the drain of the sixth transistor and the drain of the seventh transistor are all connected to the first end of each corresponding second word line (302);

   Wherein, the aspect ratio of the seventh transistor is smaller than the aspect ratio of the sixth transistor;

   Alternatively, the aspect ratio of the seventh transistor is less than twice the aspect ratio of the sixth transistor; the aspect ratio of the first transistor (M1) is greater than the aspect ratio of the sixth transistor and less than the aspect ratio of the seventh transistor.
10. The storage circuit (80) according to any one of claims 6 to 9, wherein the storage circuit (80) further comprises: a first protection enable signal generating module (501) and a second protection enable signal generating module (502);

    The first protection enable signal generating module (501) is configured to provide the protection enable signal to n first protection modules (201);

    The second protection enable signal generating module (502) is configured to provide the protection enable signal to n second protection modules (202).
11. The memory circuit (80) according to claim 10, wherein:

    The first protection enable signal generating module (501) comprises: m first transmission gates (TG1);

    The input end of each first transmission gate (TG1) receives the first driving signal corresponding to one first driving unit (401); the output end of each first transmission gate (TG1) outputs the protection enable signal to n/m of the n first protection modules (201);

    The second protection enable signal generating module (502) comprises: m second transmission gates (TG2);

    The input end of each second transmission gate (TG2) receives the fourth drive signal corresponding to one of the second drive units (402); the output end of each second transmission gate (TG2) outputs the protection enable signal to n/m of the n second protection modules (202).
12. The memory circuit (80) according to claim 10, wherein:

    The first protection enable signal generating module (501) comprises: m first NOR gates (NOR1);

    The input end of each first NOR gate (NOR1) receives n/m second drive signals corresponding to one first drive unit (401); the output end of each first NOR gate (NOR1) outputs the protection enable signal to n/m of the n first protection modules (201); wherein the second drive signal is high level valid;

    The second protection enable signal generating module (502) comprises: m second NOR gates (NOR2);

    The input end of each second NOR gate (NOR2) receives n/m fifth drive signals corresponding to one second drive unit (402); the output end of each second NOR gate (NOR2) outputs the protection enable signal to n/m of the n second protection modules (202); wherein the fifth drive signal is valid at a high level.
13. The memory circuit (80) according to claim 10, wherein:

    The first protection enable signal generating module (501) comprises: a first AND gate (AND1);

    The input end of the first AND gate (AND1) receives m first drive signals; the output end of the first AND gate (AND1) outputs the protection enable signal to n first protection modules (201); the first drive signal is valid at a low level;

    The second protection enable signal generating module (502) comprises: a second AND gate (AND2);

    The input end of the second AND gate (AND2) receives m fourth drive signals; the output end of the second AND gate (AND2) outputs the protection enable signal to n second protection modules (202); the fourth drive signal is valid at a low level.
14. The memory circuit (80) according to claim 10, wherein:

    The first protection enable signal generating module (501) comprises: n first inverters (INV1);

    Each of the first inverters (INV1) is configured to transmit each of the corresponding second drive signals as the protection enable signal to each of the corresponding first protection modules (201);

    The second protection enable signal generating module (502) comprises: n second inverters (INV2);

    Each of the second inverters (INV2) is configured to transmit each of the corresponding fifth driving signals as the protection enable signal to each of the corresponding second protection modules (202).
15. A memory (90), comprising the storage circuit (80) according to any one of claims 1 to 14.