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WO2024139661A1 - Array substrate, display panel, and array substrate preparation method - Google Patents

Array substrate, display panel, and array substrate preparation method Download PDF

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Publication number
WO2024139661A1
WO2024139661A1 PCT/CN2023/128287 CN2023128287W WO2024139661A1 WO 2024139661 A1 WO2024139661 A1 WO 2024139661A1 CN 2023128287 W CN2023128287 W CN 2023128287W WO 2024139661 A1 WO2024139661 A1 WO 2024139661A1
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Prior art keywords
doped portion
layer
doped
active sub
doping
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PCT/CN2023/128287
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French (fr)
Chinese (zh)
Inventor
史金明
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Publication of WO2024139661A1 publication Critical patent/WO2024139661A1/en

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the first doped portion includes a first heavily doped portion and a first lightly doped portion that are adjacent to each other, the first lightly doped portion is connected to the first active sub-portion, the first heavily doped portion is connected to the second active sub-portion, and the gate is electrically connected to the first heavily doped portion through the first connection hole.
  • the thickness of the first active sub-portion is smaller than the thickness of the first doped portion and/or the thickness of the second doped portion.
  • the present application also provides a display panel, comprising the above array substrate
  • an embodiment of the present application further provides a method for preparing an array substrate, comprising:
  • S2 forming a doping layer on the substrate, and patterning the doping layer to form a first opening, a second opening, a first doping portion, a second doping portion, and a third doping portion, wherein the first doping portion is located between the first opening and the second opening, the second doping portion is located on a side of the first opening away from the second opening, and the third doping portion is located on a side of the second opening away from the first opening;
  • S5 forming a first insulating layer on the substrate and covering the doped layer and the active layer, wherein the first insulating layer is formed with a first connection hole, and forming a gate on the first insulating layer, wherein the gate overlaps with the first active sub-portion and the second active sub-portion, and the gate passes through the first connection hole and is connected to the first doped portion;
  • S7 Form a source-drain layer on the second insulating layer, wherein the second insulating layer is formed with a second connection hole and a third connection hole, and the source-drain layer is patterned to form a first electrode and a second electrode, the first electrode is connected to the second doped portion through the second connection hole, and the second electrode is connected to the third doped portion through the third connection hole.
  • the step of S4: performing a crystallization process on the first active sub-section and the second active sub-section includes:
  • the blue laser also irradiates the first doped portion, the second doped portion and the third doped portion, so that the first doped portion forms a first heavily doped portion and a first lightly doped portion arranged adjacent to each other, the second doped portion forms a second heavily doped portion and a second lightly doped portion arranged adjacent to each other, and the third doped portion forms a third heavily doped portion and a third lightly doped portion arranged adjacent to each other.
  • the present application forms two conductive channels by forming two active sub-portions to achieve the effect of extending the conductive channel, thereby increasing the mobility of the active layer and correspondingly reducing the leakage current.
  • FIG1 is a schematic structural diagram of an array substrate provided in an embodiment of the present application.
  • FIG3 is a schematic structural diagram of step S1 in the method for preparing an array substrate provided in an embodiment of the present application;
  • FIG5 is a schematic structural diagram of step S3 in the method for preparing an array substrate provided in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of step S7 in the method for preparing an array substrate provided in an embodiment of the present application.
  • the doping layer 20 is disposed on the substrate 10, and the doping layer 20 is provided with a first opening 24 and a second opening 25.
  • the doping layer 20 includes a first doping portion 21, a second doping portion 22 and a third doping portion 23.
  • the first doping portion 21 is located between the first opening 24 and the second opening 25, the second doping portion 22 is located on a side of the first opening 24 away from the second opening 25, and the third doping portion 23 is located on a side of the second opening 25 away from the first opening 24.
  • the active layer 30 is disposed on the substrate 10, and the active layer includes a first active sub-portion 31 and a second active sub-portion 32.
  • the array substrate 100 of the embodiment of the present application connects the gate 50 to the first doped portion 21 located between the first active sub-portion 31 and the second active sub-portion 32.
  • the gate 50 can not only provide control over the first active sub-portion 31 and the second active sub-portion 32, but also multiplexes as a source and a drain, that is, the gate 50 can also provide input voltage and output voltage. In this way, an electric field can be generated between the second doped portion 22 connected to the first electrode 71 of the source and drain layer and the first doped portion 21, and an electric field can be generated between the third doped portion 23 connected to the second electrode 72 of the source and drain layer and the first doped portion 21.
  • the present application forms two conductive channels by forming two active sub-portions to achieve the effect of extending the conductive channel, thereby increasing the mobility of the active layer and correspondingly reducing the leakage current.
  • the active layer 30 may be low-temperature polysilicon, which may be obtained by annealing amorphous silicon through blue laser, so that the first active sub-section 31 and the second active sub-section 32 have high mobility.
  • the first insulating layer 40 and the second insulating layer 60 may be inorganic film layers such as SiOx and SiNx or their stacks, and the gate 50 may be made of metal materials such as Mo, Ti, and W.
  • the source-drain electrode layer 70 may be made of metal such as Mo, Ti, Cu, etc.
  • the source-drain electrode layer 70 may be patterned to form a first electrode 71 and a second electrode 72.
  • the first electrode 71 may be one of the source electrode or the drain electrode, and the second electrode 72 is the other of the source electrode and the drain electrode.
  • the first insulating layer 40 and the second insulating layer 60 are provided with a second connection hole 61 and a third connection hole 62 corresponding to the first electrode 71 and the second electrode 72, respectively.
  • the array substrate 100 may further include a passivation layer 80, which is formed on the first electrode 71 and the second electrode 72 by chemical vapor deposition.
  • the material of the passivation layer 80 may be an inorganic film layer such as SiOx and SiNx or a laminate thereof.
  • the first doped portion 21 includes a first heavily doped portion 211 and a first lightly doped portion 212 disposed adjacently, the first lightly doped portion 212 is connected to the first active sub-portion 31, the first heavily doped portion 211 is connected to the second active sub-portion 32, and the gate 50 is electrically connected to the first heavily doped portion 211 through the first connection hole 41.
  • the first heavily doped portion 211 and the first lightly doped portion 212 disposed adjacently are formed by forming an ion concentration difference inside the first doped portion 21.
  • the ion concentration of the first heavily doped portion 211 is greater than the ion concentration of the first lightly doped portion 212.
  • the third doped portion 23 includes a third heavily doped portion 231 and a third lightly doped portion 232 which are arranged adjacent to each other, the third heavily doped portion 231 being located on a side of the third lightly doped portion 232 away from the first heavily doped portion 211, and the second electrode 72 of the source-drain layer is connected to the third heavily doped portion 231 through the third connection hole 62. It can be understood that the ion concentration of the third heavily doped portion 231 is greater than the ion concentration of the third lightly doped portion 232.
  • S3 forming an active layer on the substrate 10, the active layer comprising a first active sub-portion 31 and a second active sub-portion 32, the first active sub-portion 31 covers the first opening 24 and is connected to the first doped portion 21 and the second doped portion 22, the second active sub-portion 32 covers the second opening 25 and is connected to the first doped portion 21 and the third doped portion 23 respectively;
  • S5 forming a first insulating layer on the substrate and covering the doped layer and the active layer, wherein the first insulating layer is formed with a first connection hole, and forming a gate on the first insulating layer, wherein the gate overlaps with the first active sub-portion and the second active sub-portion, and the gate passes through the first connection hole and is connected to the first doped portion;
  • a source-drain layer is formed on the second insulating layer 60 , wherein the second insulating layer 60 is formed with a second connection hole 61 and a third connection hole 62 , and the source-drain layer is patterned to form a first electrode 71 and a second electrode 72 , wherein the first electrode 71 is connected to the second doped portion 22 through the second connection hole 61 , and the second electrode 72 is connected to the third doped portion 23 through the third connection hole 62 .
  • the gate 50 can not only provide control over the first active sub-portion 31 and the second active sub-portion 32, but also multiplex the gate 50 as the source and drain, that is, the gate 50 can also provide input voltage and output voltage. In this way, an electric field can be generated between the second doped portion 22 connected to the first electrode 71 of the source-drain layer and the first doped portion 21, and an electric field can be generated between the third doped portion 23 connected to the second electrode 72 of the source-drain layer and the first doped portion 21.
  • the present application forms two conductive channels by forming two active sub-portions to achieve the effect of extending the conductive channel, thereby increasing the mobility of the active layer and correspondingly reducing the leakage current.
  • a first connection hole 41 can be formed by etching at a position of the first insulating layer 40 corresponding to the first portion 51 of the gate 50, so as to facilitate the subsequent connection between the second portion 52 of the gate 50 and the first portion 51, and then the second portion 52 of the gate 50 is formed on the first insulating layer 40 by physical vapor deposition, so that the second portion 52 passes through the first connection hole 41 and is electrically connected to the first portion 51.
  • the second portion 52 completely overlaps with the first active sub-portion 31 and the second active sub-portion 32, so as to control the first active sub-portion 31 and the second active sub-portion 32.
  • the second connection hole 61 can be formed by etching the first insulating layer 40 and the second insulating layer 60 at the position relative to the second doping part 22, and the third connection hole 62 can be formed by etching the first insulating layer 40 and the second insulating layer 60 at the position relative to the third doping part 23.
  • a source-drain electrode layer is formed on the second insulating layer 60 by using physical vapor deposition of metal materials such as Mo, Ti, and Cu, and the source-drain electrode layer 70 is deposited in the first connection hole 41 and the second connection hole 61 to be connected to the second doping part 22 and the third doping part 23 respectively.
  • the source-drain electrode layer is etched to form a first electrode 71 and a second electrode 72 to serve as a source and a drain respectively.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The present application discloses an array substrate, a display panel, and an array substrate preparation method. The array substrate comprises a base, a doped layer, an active layer, a first insulating layer, a gate, a second insulating layer, and a source/drain layer. The doped layer is arranged on the base and comprises a first doped part, a second doped part, and a third doped part.

Description

阵列基板、显示面板及阵列基板的制备方法Array substrate, display panel and method for preparing array substrate 技术领域Technical Field

本申请涉及显示技术领域，尤其涉及一种阵列基板、显示面板及阵列基板的制备方法。The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a method for preparing the array substrate.

背景技术Background technique

随着低温多晶硅（Low Temperature Poly-Silicon，LTPS）半导体薄膜晶体管（Thin-film transistor，TFT）的发展，以及由于LTPS半导体本身超高载流子迁移率的特性，相应的面板周边集成电路也成为大家关注的焦点。With the development of low temperature polysilicon (LTPS) semiconductor thin-film transistors (TFTs) and the ultra-high carrier mobility characteristics of LTPS semiconductors themselves, the corresponding panel peripheral integrated circuits have also become the focus of everyone's attention.

发明概述SUMMARY OF THE INVENTION

在对现有技术的研究和实践过程中，本申请的发明人发现，现有的LTPS TFT大都采用准分子激光退火技术(Excimer Laser Annealing，ELA)，其结晶晶粒小，导致其迁移率仅在50~100cm 2/Vs，而采用蓝色激光退火技术(Blue Laser Diode Annealing，BLDA)制成的LTPS-TFT，由于能量密度大，结晶晶粒大，迁移率可以做到0cm 2/Vs以上，如此以达到更大迁移率的效果。但是正是由于这种高迁移率的特性，使得LTPS-TFT器件的漏电流也变大很多，而这种大的漏电流会影响器件正常工作，因此，如何降低漏电流成为在LTPS设计中不可忽略的一部分。 In the process of research and practice of the prior art, the inventors of the present application found that most of the existing LTPS TFTs adopt the excimer laser annealing technology (ELA), and their crystal grains are small, resulting in their mobility of only 50~ 100cm2 /Vs, while the LTPS-TFT made by the blue laser annealing technology (BLDA) has a high energy density and large crystal grains, and the mobility can be above 0cm2 /Vs, thus achieving a higher mobility effect. However, it is precisely because of this high mobility characteristic that the leakage current of the LTPS-TFT device becomes much larger, and this large leakage current will affect the normal operation of the device. Therefore, how to reduce the leakage current has become an important part in the LTPS design that cannot be ignored.

本申请实施例提供一种阵列基板、显示面板及阵列基板的制备方法，可以解决在提高迁移率的同时避免漏电流过大。The embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing the array substrate, which can solve the problem of improving mobility while avoiding excessive leakage current.

本申请实施例提供一种阵列基板，包括：The present application provides an array substrate, comprising:

衬底；substrate;

掺杂层，所述掺杂层设于所述衬底上，所述掺杂层开设有第一开口和第二开口，所述掺杂层包括第一掺杂部、第二掺杂部以及第三掺杂部，所述第一掺杂部位于所述第一开口和所述第二开口之间，所述第二掺杂部位于所述第一开口远离所述第二开口的一侧，所述第三掺杂部位于所述第二开口远离所述第一开口的一侧；a doping layer, the doping layer being disposed on the substrate, the doping layer being provided with a first opening and a second opening, the doping layer comprising a first doping portion, a second doping portion and a third doping portion, the first doping portion being located between the first opening and the second opening, the second doping portion being located on a side of the first opening away from the second opening, and the third doping portion being located on a side of the second opening away from the first opening;

有源层，所述有源层设于所述衬底上，且所述有源层包括第一有源子部和第二有源子部，所述第一有源子部位于所述第一开口内，且分别与所述第一掺杂部和所述第二掺杂部连接，所述第二有源子部位于所述第二开口内，且分别与所述第一掺杂部和所述第三掺杂部连接；an active layer, the active layer being disposed on the substrate, and the active layer comprising a first active sub-portion and a second active sub-portion, the first active sub-portion being located in the first opening and being connected to the first doped portion and the second doped portion respectively, the second active sub-portion being located in the second opening and being connected to the first doped portion and the third doped portion respectively;

第一绝缘层，所述第一绝缘层设于所述衬底上，并覆盖所述掺杂层和所述有源层；a first insulating layer, the first insulating layer being disposed on the substrate and covering the doped layer and the active layer;

栅极，所述栅极至少部分设于所述第一绝缘层上，且所述栅极分别与所述第一有源子部和所述第二有源子部重叠，所述第一绝缘层开设有第一连接孔，所述栅极通过所述第一连接孔与所述第一掺杂部电连接；a gate, wherein the gate is at least partially disposed on the first insulating layer, and the gate overlaps with the first active sub-portion and the second active sub-portion respectively, the first insulating layer is provided with a first connection hole, and the gate is electrically connected to the first doped portion through the first connection hole;

第二绝缘层，所述第二绝缘层设于所述第一绝缘层上，并覆盖所述栅极；以及a second insulating layer, the second insulating layer being disposed on the first insulating layer and covering the gate; and

源漏极层，所述源漏极层设置于所述第二绝缘层上，所述源漏极层与所述第二掺杂部之间的所述第一绝缘层和所述第二绝缘层设置有第二连接孔，所述源漏极层与所述第三掺杂部之间的所述第一绝缘层和所述第二绝缘层设置有第三连接孔，所述源漏极层包括第一电极和第二电极，所述第一电极通过所述第二连接孔与所述第二掺杂部连接，所述第二电极通过所述第三连接孔与所述第三掺杂部连接。A source-drain layer, wherein the source-drain layer is arranged on the second insulating layer, the first insulating layer and the second insulating layer between the source-drain layer and the second doped portion are provided with a second connection hole, the first insulating layer and the second insulating layer between the source-drain layer and the third doped portion are provided with a third connection hole, the source-drain layer includes a first electrode and a second electrode, the first electrode is connected to the second doped portion through the second connection hole, and the second electrode is connected to the third doped portion through the third connection hole.

可选的，在本申请的一些实施例中，所述栅极为单层结构。Optionally, in some embodiments of the present application, the gate is a single-layer structure.

可选的，在本申请的一些实施例中，所述栅极包括第一部和第二部，所述第一部设置于所述第一掺杂部上；所述第二部设置于所述第一绝缘层上，并与所述第一有源子部和所述第二有源子部重叠，所述第一部和所述第二部通过所述第一连接孔连接。Optionally, in some embodiments of the present application, the gate includes a first portion and a second portion, the first portion is arranged on the first doped portion; the second portion is arranged on the first insulating layer and overlaps with the first active sub-portion and the second active sub-portion, and the first portion and the second portion are connected through the first connecting hole.

可选的，在本申请的一些实施例中，所述第一掺杂部包括相邻设置的第一重掺杂部和第一轻掺杂部，所述第一轻掺杂部与所述第一有源子部连接，所述第一重掺杂部与所述第二有源子部连接，所述栅极穿过所述第一连接孔与所述第一重掺杂部电连接。Optionally, in some embodiments of the present application, the first doped portion includes a first heavily doped portion and a first lightly doped portion that are adjacent to each other, the first lightly doped portion is connected to the first active sub-portion, the first heavily doped portion is connected to the second active sub-portion, and the gate is electrically connected to the first heavily doped portion through the first connection hole.

可选的，在本申请的一些实施例中，所述第二掺杂部包括相邻设置的第二重掺杂部和第二轻掺杂部，所述第二轻掺杂部位于所述第二重掺杂部远离所述第一轻掺杂部的一侧，所述源漏极层的第一电极穿过所述第二连接孔与所述第二重掺杂部连接。Optionally, in some embodiments of the present application, the second doped portion includes a second heavily doped portion and a second lightly doped portion that are adjacent to each other, the second lightly doped portion is located on a side of the second heavily doped portion away from the first lightly doped portion, and the first electrode of the source and drain layer is connected to the second heavily doped portion through the second connecting hole.

可选的，在本申请的一些实施例中，所述第三掺杂部包括相邻设置的第三重掺杂部和第三轻掺杂部，所述第三重掺杂部位于所述第三轻掺杂部部远离所述第一重掺杂部的一侧，所述源漏极层的第二电极穿过所述第三连接孔与所述第三重掺杂部连接。Optionally, in some embodiments of the present application, the third doped portion includes a third heavily doped portion and a third lightly doped portion that are adjacent to each other, the third heavily doped portion is located on a side of the third lightly doped portion away from the first heavily doped portion, and the second electrode of the source and drain layer is connected to the third heavily doped portion through the third connecting hole.

可选的，在本申请的一些实施例中，所述第一有源子部的厚度小于所述第一掺杂部的厚度和/或所述第二掺杂部的厚度。Optionally, in some embodiments of the present application, the thickness of the first active sub-portion is smaller than the thickness of the first doped portion and/or the thickness of the second doped portion.

可选的，在本申请的一些实施例中，所述第二有源子部的厚度小于所述第一掺杂部的厚度和/或所述第三掺杂部的厚度。Optionally, in some embodiments of the present application, the thickness of the second active sub-portion is smaller than the thickness of the first doped portion and/or the thickness of the third doped portion.

相应的，本申请实施例还提供一种显示面板，包括上述的阵列基板Accordingly, the present application also provides a display panel, comprising the above array substrate

相应的，本申请实施例还提供一种阵列基板的制备方法，包括：Accordingly, an embodiment of the present application further provides a method for preparing an array substrate, comprising:

S1：提供一衬底；S1: providing a substrate;

S2：在所述衬底上形成掺杂层，对所述掺杂层图案化以形成第一开口、第二开口、第一掺杂部、第二掺杂部以及第三掺杂部，所述第一掺杂部位于所述第一开口和所述第二开口之间，所述第二掺杂部位于所述第一开口远离所述第二开口的一侧，所述第三掺杂部位于所述第二开口远离所述第一开口的一侧；S2: forming a doping layer on the substrate, and patterning the doping layer to form a first opening, a second opening, a first doping portion, a second doping portion, and a third doping portion, wherein the first doping portion is located between the first opening and the second opening, the second doping portion is located on a side of the first opening away from the second opening, and the third doping portion is located on a side of the second opening away from the first opening;

S3：在所述衬底上形成有源层，所述有源层包括第一有源子部和第二有源子部，所述第一有源子部覆盖所述第一开口内，并与所述第一掺杂部和所述第二掺杂部连接，所述第二有源子部覆盖所述第二开口内，且分别与所述第一掺杂部和所述第三掺杂部连接；S3: forming an active layer on the substrate, the active layer comprising a first active sub-portion and a second active sub-portion, the first active sub-portion covers the first opening and is connected to the first doped portion and the second doped portion, the second active sub-portion covers the second opening and is respectively connected to the first doped portion and the third doped portion;

S4：对所述第一有源子部和所述第二有源子部进行退火结晶处理；S4: performing annealing and crystallization treatment on the first active sub-section and the second active sub-section;

S5：在所述衬底上形成第一绝缘层上，并覆盖所述掺杂层和所述有源层，所述第一绝缘层形成有第一连接孔，在所述第一绝缘层形成栅极，所述栅极与所述第一有源子部和所述第二有源子部重叠，所述栅极穿过所述第一连接孔与所述第一掺杂部连接；S5: forming a first insulating layer on the substrate and covering the doped layer and the active layer, wherein the first insulating layer is formed with a first connection hole, and forming a gate on the first insulating layer, wherein the gate overlaps with the first active sub-portion and the second active sub-portion, and the gate passes through the first connection hole and is connected to the first doped portion;

S6：在所述第一绝缘层上形成第二绝缘层，并覆盖所述栅极；S6: forming a second insulating layer on the first insulating layer and covering the gate;

S7：在所述第二绝缘层上形成源漏极层，所述第二绝缘层形成有第二连接孔和第三连接孔，且所述源漏极层图案化以形成第一电极和第二电极，所述第一电极通过所述第二连接孔与所述第二掺杂部连接，所述第二电极通过所述第三连接孔与所述第三掺杂部连接。S7: Form a source-drain layer on the second insulating layer, wherein the second insulating layer is formed with a second connection hole and a third connection hole, and the source-drain layer is patterned to form a first electrode and a second electrode, the first electrode is connected to the second doped portion through the second connection hole, and the second electrode is connected to the third doped portion through the third connection hole.

可选的，在本申请的一些实施例中，所述S4：对所述第一有源子部和所述第二有源子部进行结晶处理的步骤包括：Optionally, in some embodiments of the present application, the step of S4: performing a crystallization process on the first active sub-section and the second active sub-section includes:

蓝色激光沿预定方向移动，以对所述第一有源子部和所述第二有源子部进行激光退火处理。The blue laser moves along a predetermined direction to perform laser annealing on the first active sub-section and the second active sub-section.

可选的，在本申请的一些实施例中，所述S4：对所述第一有源子部和所述第二有源子部进行结晶处理的步骤还包括：Optionally, in some embodiments of the present application, the step of S4: performing a crystallization process on the first active sub-section and the second active sub-section further includes:

所述蓝色激光还对所述第一掺杂部、所述第二掺杂部以及所述第三掺杂部进行照射，以使所述第一掺杂部形成相邻设置的第一重掺杂部和第一轻掺杂部，所述第二掺杂部形成相邻设置的第二重掺杂部和第二轻掺杂部，所述第三掺杂部形成相邻设置的第三重掺杂部和第三轻掺杂部。The blue laser also irradiates the first doped portion, the second doped portion and the third doped portion, so that the first doped portion forms a first heavily doped portion and a first lightly doped portion arranged adjacent to each other, the second doped portion forms a second heavily doped portion and a second lightly doped portion arranged adjacent to each other, and the third doped portion forms a third heavily doped portion and a third lightly doped portion arranged adjacent to each other.

有益效果Beneficial Effects

本申请实施例的有益效果：本申请实施例的阵列基板通过使栅极与位于第一有源子部和第二有源子部之间的第一掺杂部连接，该栅极不仅可以提供对第一有源子部和第二有源子部的控制，同时该栅极还起到复用为源极和漏极的作用，即该栅极还可以提供输入电压和输出电压的作用。如此可使得源漏极层的第一电极连接的第二掺杂部与第一掺杂部之间产生电场，且源漏极层的第二电极连接的第三掺杂部与第一掺杂部之间产生电场。从而相较于现有技术中单个导电沟道的设置，本申请通过形成两个有源子部的设置以形成两个导电沟道，以达到了延长导电沟道的效果，如此既增大有源层的迁移率，又相应的减小漏电流。Beneficial effects of the embodiments of the present application: The array substrate of the embodiments of the present application connects the gate to the first doped portion located between the first active sub-portion and the second active sub-portion. The gate can not only provide control over the first active sub-portion and the second active sub-portion, but also multiplex as a source and a drain, that is, the gate can also provide input voltage and output voltage. In this way, an electric field can be generated between the second doped portion connected to the first electrode of the source and drain layer and the first doped portion, and an electric field can be generated between the third doped portion connected to the second electrode of the source and drain layer and the first doped portion. Therefore, compared with the setting of a single conductive channel in the prior art, the present application forms two conductive channels by forming two active sub-portions to achieve the effect of extending the conductive channel, thereby increasing the mobility of the active layer and correspondingly reducing the leakage current.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

图1是本申请实施例提供的阵列基板的结构示意图；FIG1 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

图2是本申请实施例提供的阵列基板的制备方法的流程示意图；FIG2 is a schematic diagram of a process of preparing an array substrate provided in an embodiment of the present application;

图3是本申请实施例提供的阵列基板的制备方法中步骤S1的结构示意图；FIG3 is a schematic structural diagram of step S1 in the method for preparing an array substrate provided in an embodiment of the present application;

图4是本申请实施例提供的阵列基板的制备方法中步骤S2的结构示意图；FIG4 is a schematic structural diagram of step S2 in the method for preparing an array substrate provided in an embodiment of the present application;

图5是本申请实施例提供的阵列基板的制备方法中步骤S3的结构示意图；FIG5 is a schematic structural diagram of step S3 in the method for preparing an array substrate provided in an embodiment of the present application;

图6是本申请实施例提供的阵列基板的制备方法中步骤S4的结构示意图；FIG6 is a schematic structural diagram of step S4 in the method for preparing an array substrate provided in an embodiment of the present application;

图7是本申请实施例提供的阵列基板的制备方法中步骤S5的结构示意图；FIG. 7 is a schematic structural diagram of step S5 in the method for preparing an array substrate provided in an embodiment of the present application;

图8是本申请实施例提供的阵列基板的制备方法中步骤S6的结构示意图；FIG8 is a schematic structural diagram of step S6 in the method for preparing an array substrate provided in an embodiment of the present application;

图9是本申请实施例提供的阵列基板的制备方法中步骤S7的结构示意图；FIG. 9 is a schematic structural diagram of step S7 in the method for preparing an array substrate provided in an embodiment of the present application;

图10是本申请实施例提供的阵列基板的制备方法中步骤S8的结构示意图；FIG. 10 is a schematic structural diagram of step S8 in the method for preparing an array substrate provided in an embodiment of the present application;

图11是本申请实施例提供的阵列基板的制备方法中步骤S9的结构示意图。FIG. 11 is a schematic structural diagram of step S9 in the method for preparing an array substrate provided in an embodiment of the present application.

本发明的实施方式Embodiments of the present invention

以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。The following descriptions of the embodiments are made with reference to the attached drawings to illustrate specific embodiments that the present application may be implemented in. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the drawings, units with similar structures are represented by the same reference numerals.

下面结合附图和具体实施例对本申请做进一步的说明：The present application is further described below with reference to the accompanying drawings and specific embodiments:

本申请实施例提供一种阵列基板、显示面板及阵列基板的制备方法。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。The embodiments of the present application provide an array substrate, a display panel and a method for manufacturing the array substrate. The following are detailed descriptions of each. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

参照图1，本申请实施例提供一种阵列基板100，该阵列基板100包括衬底10、掺杂层20、有源层30、第一绝缘层40、栅极50、第二绝缘层60以及源漏极层70。1 , an embodiment of the present application provides an array substrate 100 , which includes a substrate 10 , a doping layer 20 , an active layer 30 , a first insulating layer 40 , a gate 50 , a second insulating layer 60 , and a source-drain layer 70 .

掺杂层20设于衬底10上，掺杂层20开设有第一开口24和第二开口25。掺杂层20包括第一掺杂部21、第二掺杂部22以及第三掺杂部23，第一掺杂部21位于第一开口24和第二开口25之间，第二掺杂部22位于第一开口24远离第二开口25的一侧，第三掺杂部23位于第二开口25远离第一开口24的一侧。有源层30设于衬底10上，且有源层包括第一有源子部31和第二有源子部32，第一有源子部31位于第一开口24内，且分别与第一掺杂部21和第二掺杂部22连接，第二有源子部32位于第二开口25内，且分别与第一掺杂部21和第三掺杂部23连接。第一绝缘层40设于衬底10上，并覆盖掺杂层20和有源层30。栅极50至少部分设于第一绝缘层40上，且栅极50分别与第一有源子部31和第二有源子部32重叠，第一绝缘层40开设有第一连接孔41，栅极50通过第一连接孔41与第一掺杂部21电连接。第二绝缘层60设于第一绝缘层40上，并覆盖栅极50。源漏极层70设置于第二绝缘层60上，第二绝缘层60设置有第二连接孔61和第三连接孔62。源漏极层70包括第一电极71和第二电极72，第一电极71通过第二连接孔61与第二掺杂部22连接，第二电极72通过第三连接孔62与第三掺杂部23连接。The doping layer 20 is disposed on the substrate 10, and the doping layer 20 is provided with a first opening 24 and a second opening 25. The doping layer 20 includes a first doping portion 21, a second doping portion 22 and a third doping portion 23. The first doping portion 21 is located between the first opening 24 and the second opening 25, the second doping portion 22 is located on a side of the first opening 24 away from the second opening 25, and the third doping portion 23 is located on a side of the second opening 25 away from the first opening 24. The active layer 30 is disposed on the substrate 10, and the active layer includes a first active sub-portion 31 and a second active sub-portion 32. The first active sub-portion 31 is located in the first opening 24 and is connected to the first doping portion 21 and the second doping portion 22, respectively. The second active sub-portion 32 is located in the second opening 25 and is connected to the first doping portion 21 and the third doping portion 23, respectively. The first insulating layer 40 is disposed on the substrate 10 and covers the doping layer 20 and the active layer 30. The gate 50 is at least partially disposed on the first insulating layer 40, and the gate 50 overlaps the first active sub-portion 31 and the second active sub-portion 32 respectively. The first insulating layer 40 is provided with a first connection hole 41, and the gate 50 is electrically connected to the first doped portion 21 through the first connection hole 41. The second insulating layer 60 is disposed on the first insulating layer 40 and covers the gate 50. The source-drain electrode layer 70 is disposed on the second insulating layer 60, and the second insulating layer 60 is provided with a second connection hole 61 and a third connection hole 62. The source-drain electrode layer 70 includes a first electrode 71 and a second electrode 72, the first electrode 71 is connected to the second doped portion 22 through the second connection hole 61, and the second electrode 72 is connected to the third doped portion 23 through the third connection hole 62.

本申请实施例的阵列基板100通过使栅极50与位于第一有源子部31和第二有源子部32之间的第一掺杂部21连接，该栅极50不仅可以提供对第一有源子部31和第二有源子部32的控制，同时该栅极50还起到复用为源极和漏极的作用，即该栅极50还可以提供输入电压和输出电压的作用。如此可使得源漏极层的第一电极71连接的第二掺杂部22与第一掺杂部21之间产生电场，且源漏极层的第二电极72连接的第三掺杂部23与第一掺杂部21之间产生电场。从而相较于现有技术中单个导电沟道的设置，本申请通过形成两个有源子部的设置以形成两个导电沟道，以达到了延长导电沟道的效果，如此既增大有源层的迁移率，又相应的减小漏电流。The array substrate 100 of the embodiment of the present application connects the gate 50 to the first doped portion 21 located between the first active sub-portion 31 and the second active sub-portion 32. The gate 50 can not only provide control over the first active sub-portion 31 and the second active sub-portion 32, but also multiplexes as a source and a drain, that is, the gate 50 can also provide input voltage and output voltage. In this way, an electric field can be generated between the second doped portion 22 connected to the first electrode 71 of the source and drain layer and the first doped portion 21, and an electric field can be generated between the third doped portion 23 connected to the second electrode 72 of the source and drain layer and the first doped portion 21. Therefore, compared with the setting of a single conductive channel in the prior art, the present application forms two conductive channels by forming two active sub-portions to achieve the effect of extending the conductive channel, thereby increasing the mobility of the active layer and correspondingly reducing the leakage current.

参照图1，其中，衬底10包括基板11和缓冲层12，该基板11可以是玻璃基板11，该玻璃基板11材质均匀，具有高透明度和低反射率，并且有好的热稳定性，从而能在多次高温工艺之后保持性质稳定。由于TFT制造工艺中用到的化学药品很多，因而，该玻璃基板11需具有很好的化学耐药性。该玻璃基板11还需要具有足够的机械强度，还需要有很好的精密机械加工特性以及要有优良的电学绝缘特性。而该缓冲层12可以通过化学沉积的方式形成于基板11上，缓冲层12可以是氮化硅和氧化硅中的一种或多种的组合，缓冲层12的作用是隔绝玻璃基板11和有源层，以防止玻璃基板11内的金属离子扩散到有源层中，进一步降低漏电流的产生，同时缓冲层12还可以对其它膜层起到支撑缓冲作用。进一步地，可以通过化学气相沉积的方式在缓冲层12上形成掺杂层20以提高导电性能。该掺杂层20可以为硅层掺杂磷离子(P)。通过图案化以使掺杂层20形成第一开口24和第二开口25，并形成间隔设置的第一掺杂部21、第二掺杂部22以及第三掺杂部23。该有源层可以通过化学气相沉积的方式在第一开口24形成第一有源子部31，以及在第二开口25内形成第二有源子部32，从而实现第一有源子部31与第一掺杂部21和第二掺杂部22连接，而第二有源子部32与第一掺杂部21和第三掺杂部23连接。如此薄膜晶体管的载流子迁移路径需经过第一掺杂部21、第二掺杂部22以及第三掺杂部23，从而也同步达到延长导电沟道长度，也可以达到减小漏电流同时兼顾较高迁移率的效果。Referring to FIG. 1 , the substrate 10 includes a substrate 11 and a buffer layer 12. The substrate 11 may be a glass substrate 11. The glass substrate 11 is made of uniform material, has high transparency and low reflectivity, and has good thermal stability, so that the properties can be kept stable after multiple high-temperature processes. Since a lot of chemicals are used in the TFT manufacturing process, the glass substrate 11 needs to have good chemical resistance. The glass substrate 11 also needs to have sufficient mechanical strength, good precision machining properties, and excellent electrical insulation properties. The buffer layer 12 can be formed on the substrate 11 by chemical deposition. The buffer layer 12 can be a combination of one or more of silicon nitride and silicon oxide. The function of the buffer layer 12 is to isolate the glass substrate 11 and the active layer to prevent the metal ions in the glass substrate 11 from diffusing into the active layer, further reducing the generation of leakage current. At the same time, the buffer layer 12 can also play a supporting and buffering role for other film layers. Further, a doping layer 20 can be formed on the buffer layer 12 by chemical vapor deposition to improve the conductive performance. The doping layer 20 can be a silicon layer doped with phosphorus ions (P). The doping layer 20 is patterned to form a first opening 24 and a second opening 25, and to form a first doping portion 21, a second doping portion 22 and a third doping portion 23 arranged at intervals. The active layer can form a first active sub-portion 31 in the first opening 24 and a second active sub-portion 32 in the second opening 25 by chemical vapor deposition, so that the first active sub-portion 31 is connected to the first doping portion 21 and the second doping portion 22, and the second active sub-portion 32 is connected to the first doping portion 21 and the third doping portion 23. In this way, the carrier migration path of the thin film transistor needs to pass through the first doping portion 21, the second doping portion 22 and the third doping portion 23, thereby simultaneously extending the conductive channel length, and also achieving the effect of reducing leakage current while taking into account higher mobility.

需要说明的是，该有源层30可以为低温多晶硅，其可以由非晶硅通过蓝色激光退火得到，如此以使得该第一有源子部31和第二有源子部32具有高迁移率。而第一绝缘层40和第二绝缘层60可以是SiOx和SiNx等无机膜层或其叠层，而该栅极50可以由Mo、Ti、W等金属材质制成。而第一绝缘层40上设置有栅极50对应与第一连接孔41，第一连接孔41沿第二绝缘层60朝向第一绝缘层40的叠层方向延伸，且第一连接孔41在衬底10的正投影位于第一掺杂部21在衬底10的正投影上，从而栅极50可以穿过第一连接孔41与第一掺杂部21连接。此外，栅极50在衬底10上的正投影分别与第一有源子部31和第二有源子部32在衬底10上的正投影至少部分重合，如此以实现栅极50分别与第一有源子部31和第二有源子部32重叠。It should be noted that the active layer 30 may be low-temperature polysilicon, which may be obtained by annealing amorphous silicon through blue laser, so that the first active sub-section 31 and the second active sub-section 32 have high mobility. The first insulating layer 40 and the second insulating layer 60 may be inorganic film layers such as SiOx and SiNx or their stacks, and the gate 50 may be made of metal materials such as Mo, Ti, and W. The first insulating layer 40 is provided with a gate 50 corresponding to the first connection hole 41, which extends along the stacking direction of the second insulating layer 60 toward the first insulating layer 40, and the orthographic projection of the first connection hole 41 on the substrate 10 is located on the orthographic projection of the first doped portion 21 on the substrate 10, so that the gate 50 can pass through the first connection hole 41 to connect with the first doped portion 21. In addition, the orthographic projection of the gate 50 on the substrate 10 at least partially overlaps with the orthographic projections of the first active sub-portion 31 and the second active sub-portion 32 on the substrate 10 , so that the gate 50 overlaps with the first active sub-portion 31 and the second active sub-portion 32 .

该源漏极层70可以是Mo、Ti、Cu等金属制成。而该源漏极层70可以通过图案化形成第一电极71和第二电极72，该第一电极71可以为源极或漏极的其中之一，则第二电极72为源极和漏极的其中之另一。而第一绝缘层40和第二绝缘层60上设置有分别与第一电极71和第二电极72对应的第二连接孔61和第三连接孔62，第二连接孔61与第三连接孔62沿第二绝缘层60朝向第一绝缘层40的叠层方向延伸，且第二连接孔61朝向衬底10的正投影位于第二掺杂部22在衬底10的正投影上，且第三连接孔62朝向衬底10的正投影位于第三掺杂部23在衬底10的正投影上，如此以使得第一电极71垂直穿过第二连接孔61与第二掺杂部22电连接，第二电极72垂直穿过第三连接孔62与第三掺杂部23电连接。此外，该阵列基板100还可以包括钝化层80，采用化学气相沉积法在第一电极71和第二电极72上形成钝化层80。钝化层80的材料可以为SiOx和SiNx等无机膜层或其叠层。The source-drain electrode layer 70 may be made of metal such as Mo, Ti, Cu, etc. The source-drain electrode layer 70 may be patterned to form a first electrode 71 and a second electrode 72. The first electrode 71 may be one of the source electrode or the drain electrode, and the second electrode 72 is the other of the source electrode and the drain electrode. The first insulating layer 40 and the second insulating layer 60 are provided with a second connection hole 61 and a third connection hole 62 corresponding to the first electrode 71 and the second electrode 72, respectively. The second connection hole 61 and the third connection hole 62 extend along the stacking direction of the second insulating layer 60 toward the first insulating layer 40, and the orthographic projection of the second connection hole 61 toward the substrate 10 is located on the orthographic projection of the second doped portion 22 on the substrate 10, and the orthographic projection of the third connection hole 62 toward the substrate 10 is located on the orthographic projection of the third doped portion 23 on the substrate 10, so that the first electrode 71 vertically passes through the second connection hole 61 to be electrically connected to the second doped portion 22, and the second electrode 72 vertically passes through the third connection hole 62 to be electrically connected to the third doped portion 23. In addition, the array substrate 100 may further include a passivation layer 80, which is formed on the first electrode 71 and the second electrode 72 by chemical vapor deposition. The material of the passivation layer 80 may be an inorganic film layer such as SiOx and SiNx or a laminate thereof.

参照图1，可选的，栅极50包括第一部51和第二部52，第一部51设置于第一掺杂部21上。第二部52设置于第一绝缘层40上，并与第一有源子部31和第二有源子部32重叠，第一部51和第二部52通过第一连接孔41连接。其中，可以直接第一掺杂部21上形成第一部51，之后形成第一绝缘层40覆盖第一部51后，再设置栅极50的第二部52，第二部52通过第一绝缘层40的第一连接孔41与第一部51电连接。如此以该栅极50形成为双层结构，如此以便于控制栅极50与第一掺杂部21的接触面积，进而以控制栅极50与第一掺杂部21之间的导电能力，以根据需求选择调整保证驱动能力。可以理解的是，第二部52在衬底10上的方向正投影分别与第一有源子部31和第二有源子部32在衬底上的正投影完全重叠，如此以提高对第一有源子部31和第二有源子部32控制。Referring to FIG. 1 , optionally, the gate 50 includes a first portion 51 and a second portion 52, and the first portion 51 is disposed on the first doped portion 21. The second portion 52 is disposed on the first insulating layer 40 and overlaps with the first active sub-portion 31 and the second active sub-portion 32, and the first portion 51 and the second portion 52 are connected through the first connection hole 41. Among them, the first portion 51 can be directly formed on the first doped portion 21, and then the first insulating layer 40 is formed to cover the first portion 51, and then the second portion 52 of the gate 50 is disposed, and the second portion 52 is electrically connected to the first portion 51 through the first connection hole 41 of the first insulating layer 40. In this way, the gate 50 is formed into a double-layer structure, so as to control the contact area between the gate 50 and the first doped portion 21, and then control the conductivity between the gate 50 and the first doped portion 21, so as to select and adjust the driving capability according to the needs. It can be understood that the directional orthographic projection of the second portion 52 on the substrate 10 completely overlaps with the orthographic projections of the first active sub-portion 31 and the second active sub-portion 32 on the substrate, respectively, so as to improve the control over the first active sub-portion 31 and the second active sub-portion 32.

在另一实施例中，栅极为单层结构（未图示）。可以理解的是，该栅极也可以直接在第一绝缘层设置后，在第一绝缘层开设第一连接孔，从而通过在第一绝缘层上形成栅极后通过第一连接孔直接与第一掺杂部电连接，如此以提高制备效率。In another embodiment, the gate is a single-layer structure (not shown). It is understandable that the gate can also be directly provided with a first connection hole in the first insulating layer after the first insulating layer is provided, so that the gate is directly electrically connected to the first doped part through the first connection hole after the gate is formed on the first insulating layer, thereby improving the manufacturing efficiency.

参照图1，可选的，第一掺杂部21包括相邻设置的第一重掺杂部211和第一轻掺杂部212，第一轻掺杂部212与第一有源子部31连接，第一重掺杂部211与第二有源子部32连接，栅极50穿过第一连接孔41与第一重掺杂部211电连接。可以理解的是，通过使第一掺杂部21内部形成离子浓度差以形成相邻设置的第一重掺杂部211和第一轻掺杂部212。第一重掺杂部211的离子浓度大于第一轻掺杂部212的离子浓度。而通过使得第一掺杂部21形成第一重掺杂部211和第一轻掺杂部212形成轻掺杂漏极 (light dopping drain，LDD)结构，以减弱电场，改善热载流子效应，减少关态下连接端的电子迁移现象，进而降低薄膜晶体管漏电流，减少功率损耗，从而进一步达到降低漏电流的作用。需要说明的是，第一重掺杂部211和第一轻掺杂部212即可以直接采用离子注入的方式以形成离子浓度差。或者还可以通过蓝色激光退火技术处理的方式形成离子浓度，以对第一掺杂部21进行照射，使第一掺杂部21瞬间熔融，从而第一掺杂部21内注入的磷离子会在熔融后进行扩散，即朝向激光扫描方向产生离子浓度差，进而形成第一重掺杂部211和第一轻掺杂部212。Referring to FIG. 1 , optionally, the first doped portion 21 includes a first heavily doped portion 211 and a first lightly doped portion 212 disposed adjacently, the first lightly doped portion 212 is connected to the first active sub-portion 31, the first heavily doped portion 211 is connected to the second active sub-portion 32, and the gate 50 is electrically connected to the first heavily doped portion 211 through the first connection hole 41. It can be understood that the first heavily doped portion 211 and the first lightly doped portion 212 disposed adjacently are formed by forming an ion concentration difference inside the first doped portion 21. The ion concentration of the first heavily doped portion 211 is greater than the ion concentration of the first lightly doped portion 212. And by forming the first heavily doped portion 211 and the first lightly doped portion 212 in the first doped portion 21 to form a lightly doped drain (LDD) structure, the electric field is weakened, the hot carrier effect is improved, and the electron migration phenomenon at the connection end in the off state is reduced, thereby reducing the leakage current of the thin film transistor and reducing the power loss, thereby further achieving the effect of reducing the leakage current. It should be noted that the first heavily doped portion 211 and the first lightly doped portion 212 can be directly formed by ion implantation to form an ion concentration difference. Alternatively, the ion concentration can be formed by a blue laser annealing process to irradiate the first doped portion 21 to melt the first doped portion 21 instantly, so that the phosphorus ions injected into the first doped portion 21 diffuse after melting, that is, an ion concentration difference is generated in the laser scanning direction, thereby forming the first heavily doped portion 211 and the first lightly doped portion 212.

进一步地，第二掺杂部22包括相邻设置的第二重掺杂部221和第二轻掺杂部222，第二轻掺杂部222位于第二重掺杂部221远离第一轻掺杂部212的一侧，源漏极层的第一电极71穿过第二连接孔61与第二重掺杂部221连接。可以理解的是，第二重掺杂部221的离子浓度大于第二轻掺杂部222的离子浓度。而通过使得第二掺杂部22形成第二重掺杂部221和第二轻掺杂部222形成轻掺杂漏极结构，以减弱电场，改善热载流子效应，减少关态下连接端的电子迁移现象，进而降低薄膜晶体管漏电流，减少功率损耗，从而进一步达到降低漏电流的作用。需要说明的是，第二重掺杂部221和第二轻掺杂部222可以直接采用离子注入的方式以形成离子浓度差。也可以通过蓝色激光退火技术处理的方式形成离子浓度差，以对第二掺杂部22进行照射，使第二掺杂部22瞬间熔化，从而第二掺杂部22内注入的磷离子会在熔化后进行扩散，即朝向激光扫描方向产生离子浓度差，进而形成第二重掺杂部221和第二轻掺杂部222。Further, the second doped portion 22 includes a second heavily doped portion 221 and a second lightly doped portion 222 that are adjacently arranged, the second lightly doped portion 222 is located on a side of the second heavily doped portion 221 away from the first lightly doped portion 212, and the first electrode 71 of the source-drain layer is connected to the second heavily doped portion 221 through the second connection hole 61. It can be understood that the ion concentration of the second heavily doped portion 221 is greater than the ion concentration of the second lightly doped portion 222. By making the second doped portion 22 form a second heavily doped portion 221 and a second lightly doped portion 222 to form a lightly doped drain structure, the electric field is weakened, the hot carrier effect is improved, and the electron migration phenomenon at the connection end in the off state is reduced, thereby reducing the leakage current of the thin film transistor and reducing the power loss, thereby further achieving the effect of reducing the leakage current. It should be noted that the second heavily doped portion 221 and the second lightly doped portion 222 can directly form an ion concentration difference by ion implantation. The ion concentration difference can also be formed by blue laser annealing technology to irradiate the second doping portion 22, causing the second doping portion 22 to melt instantly, so that the phosphorus ions injected into the second doping portion 22 will diffuse after melting, that is, an ion concentration difference is generated in the laser scanning direction, thereby forming a second heavily doped portion 221 and a second lightly doped portion 222.

可选地，第三掺杂部23包括相邻设置的第三重掺杂部231和第三轻掺杂部232，第三重掺杂部231位于第三轻掺杂部232部远离第一重掺杂部211的一侧，源漏极层的第二电极72穿过第三连接孔62与第三重掺杂部231连接。可以理解的是，第三重掺杂部231的离子浓度大于第三轻掺杂部232的离子浓度。而通过使得第三掺杂部23形成第三重掺杂部231和第三轻掺杂部232形成轻掺杂漏极结构，以减弱电场，改善热载流子效应，减少关态下连接端的电子迁移现象，进而降低薄膜晶体管漏电流，减少功率损耗，从而进一步达到降低漏电流的作用。需要说明的是，第三重掺杂部231和第三轻掺杂部232可以直接采用离子注入的方式以形成离子浓度差。也可以通过蓝色激光退火技术处理的方式以形成离子浓度差，以对第三掺杂部23进行照射，使第三掺杂部23瞬间熔化，从而第三掺杂部23内注入的磷离子会在熔化后进行扩散，即朝向激光扫描方向形成产生离子浓度差，进而形成第三重掺杂部231和第三轻掺杂部232。Optionally, the third doped portion 23 includes a third heavily doped portion 231 and a third lightly doped portion 232 which are arranged adjacent to each other, the third heavily doped portion 231 being located on a side of the third lightly doped portion 232 away from the first heavily doped portion 211, and the second electrode 72 of the source-drain layer is connected to the third heavily doped portion 231 through the third connection hole 62. It can be understood that the ion concentration of the third heavily doped portion 231 is greater than the ion concentration of the third lightly doped portion 232. By making the third heavily doped portion 23 form the third heavily doped portion 231 and the third lightly doped portion 232 of the third doped portion 23 to form a lightly doped drain structure, the electric field is weakened, the hot carrier effect is improved, and the electron migration phenomenon at the connection end in the off state is reduced, thereby reducing the leakage current of the thin film transistor and reducing the power loss, thereby further achieving the effect of reducing the leakage current. It should be noted that the third heavily doped portion 231 and the third lightly doped portion 232 can be directly formed by ion implantation to form an ion concentration difference. The third doped portion 23 may also be irradiated with blue laser annealing technology to form an ion concentration difference, so that the third doped portion 23 is melted instantly, and the phosphorus ions injected into the third doped portion 23 diffuse after melting, that is, an ion concentration difference is formed in the laser scanning direction, thereby forming a third heavily doped portion 231 and a third lightly doped portion 232.

参照图1，可选地，第一有源子部31的厚度小于第一掺杂部21的厚度和/或第二掺杂部22的厚度。其中，在衬底10上，第一有源子部31的厚度既可以小于第一掺杂部21的厚度，或者第一有源子部31的厚度也可以小于第二掺杂部22的厚度，或者第一有源子部31同时小于第一掺杂部21的厚度和第二掺杂部22的厚度。如此通过薄化第一有源子部31的厚度，以使得第一有源子部31传输载流子的截面的面积减小，以增大第一有源子部31的电阻，进而有利于减小薄膜晶体管的漏电流。此外，第一有源子部31的厚度薄化，有利于提高栅极50对第一有源子部31的控制能力。Referring to FIG. 1 , optionally, the thickness of the first active sub-portion 31 is less than the thickness of the first doped portion 21 and/or the thickness of the second doped portion 22. Wherein, on the substrate 10, the thickness of the first active sub-portion 31 may be less than the thickness of the first doped portion 21, or the thickness of the first active sub-portion 31 may be less than the thickness of the second doped portion 22, or the first active sub-portion 31 is simultaneously less than the thickness of the first doped portion 21 and the thickness of the second doped portion 22. In this way, by thinning the thickness of the first active sub-portion 31, the area of the cross section of the first active sub-portion 31 for transmitting carriers is reduced, so as to increase the resistance of the first active sub-portion 31, thereby facilitating the reduction of the leakage current of the thin film transistor. In addition, the thinning of the thickness of the first active sub-portion 31 is conducive to improving the control capability of the gate 50 over the first active sub-portion 31.

可选地，第二有源子部32的厚度小于第一掺杂部21的厚度和/或第三掺杂部23的厚度。其中，在衬底10上，第二有源子部32的厚度既可以小于第一掺杂部21的厚度，或者第二有源子部32的厚度也可以小于第三掺杂部23的厚度，或者第二有源子部32同时小于第一掺杂部21的厚度和第三掺杂部23的厚度。如此通过薄化第二有源子部32的厚度，以使得第二有源子部32传输载流子的截面的面积减小，以增大第二有源子部32的电阻，进而有利于减小薄膜晶体管的漏电流。此外，第二有源子部32的厚度薄化，有利于提高栅极50对第二有源子部32的控制能力。Optionally, the thickness of the second active sub-portion 32 is less than the thickness of the first doped portion 21 and/or the thickness of the third doped portion 23. Among them, on the substrate 10, the thickness of the second active sub-portion 32 can be less than the thickness of the first doped portion 21, or the thickness of the second active sub-portion 32 can also be less than the thickness of the third doped portion 23, or the second active sub-portion 32 is simultaneously less than the thickness of the first doped portion 21 and the thickness of the third doped portion 23. In this way, by thinning the thickness of the second active sub-portion 32, the area of the cross-section of the second active sub-portion 32 for transmitting carriers is reduced, so as to increase the resistance of the second active sub-portion 32, thereby facilitating the reduction of the leakage current of the thin film transistor. In addition, the thinning of the thickness of the second active sub-portion 32 is conducive to improving the control ability of the gate 50 over the second active sub-portion 32.

本申请还提供一种显示面板，显示面板包括上述的阵列基板100、与阵列基板100相对设置的彩膜基板以及设置于阵列基板100与彩膜基板之间的液晶层。The present application also provides a display panel, which includes the above-mentioned array substrate 100, a color filter substrate arranged opposite to the array substrate 100, and a liquid crystal layer arranged between the array substrate 100 and the color filter substrate.

参照图2，本申请还提供一种阵列基板100的制备方法，包括：2 , the present application also provides a method for preparing an array substrate 100 , comprising:

S1：提供一衬底10；S1: providing a substrate 10;

S2：在衬底10上形成掺杂层20，对掺杂层20图案化以形成第一开口24、第二开口25、第一掺杂部21、第二掺杂部22以及第三掺杂部23，第一掺杂部21位于第一开口24和第二开口25之间，第二掺杂部22位于第一开口24远离第二开口25的一侧，第三掺杂部23位于第二开口25远离第一开口24的一侧；S2: forming a doping layer 20 on the substrate 10, and patterning the doping layer 20 to form a first opening 24, a second opening 25, a first doping portion 21, a second doping portion 22, and a third doping portion 23, wherein the first doping portion 21 is located between the first opening 24 and the second opening 25, the second doping portion 22 is located on a side of the first opening 24 away from the second opening 25, and the third doping portion 23 is located on a side of the second opening 25 away from the first opening 24;

S3：在衬底10上形成有源层，有源层包括第一有源子部31和第二有源子部32，第一有源子部31覆盖第一开口24内，并与第一掺杂部21和第二掺杂部22连接，第二有源子部32覆盖第二开口25内，且分别与第一掺杂部21和第三掺杂部23连接；S3: forming an active layer on the substrate 10, the active layer comprising a first active sub-portion 31 and a second active sub-portion 32, the first active sub-portion 31 covers the first opening 24 and is connected to the first doped portion 21 and the second doped portion 22, the second active sub-portion 32 covers the second opening 25 and is connected to the first doped portion 21 and the third doped portion 23 respectively;

S4：对第一有源子部31和第二有源子部32进行退火结晶处理；S4: performing annealing and crystallization treatment on the first active sub-section 31 and the second active sub-section 32;

S5：在所述衬底上形成第一绝缘层上，并覆盖所述掺杂层和所述有源层，所述第一绝缘层形成有第一连接孔，在所述第一绝缘层形成栅极，所述栅极与所述第一有源子部和所述第二有源子部重叠，所述栅极穿过所述第一连接孔与所述第一掺杂部连接；S5: forming a first insulating layer on the substrate and covering the doped layer and the active layer, wherein the first insulating layer is formed with a first connection hole, and forming a gate on the first insulating layer, wherein the gate overlaps with the first active sub-portion and the second active sub-portion, and the gate passes through the first connection hole and is connected to the first doped portion;

S6：在第一绝缘层40上形成第二绝缘层60，并覆盖栅极50；S6: forming a second insulating layer 60 on the first insulating layer 40 and covering the gate 50;

S7：在第二绝缘层60上形成源漏极层，第二绝缘层60形成有第二连接孔61和第三连接孔62，且源漏极层图案化以形成第一电极71和第二电极72，第一电极71通过第二连接孔61与第二掺杂部22连接，第二电极72通过第三连接孔62与第三掺杂部23连接。S7: A source-drain layer is formed on the second insulating layer 60 , wherein the second insulating layer 60 is formed with a second connection hole 61 and a third connection hole 62 , and the source-drain layer is patterned to form a first electrode 71 and a second electrode 72 , wherein the first electrode 71 is connected to the second doped portion 22 through the second connection hole 61 , and the second electrode 72 is connected to the third doped portion 23 through the third connection hole 62 .

可以理解的是，在本实施例的阵列基板100通过使栅极50与位于第一有源子部31和第二有源子部32之间的第一掺杂部21连接，该栅极50不仅可以提供对第一有源子部31和第二有源子部32的控制，同时该栅极50还起到复用为源极和漏极的作用，即该栅极50还可以提供输入电压和输出电压的作用。如此可使得源漏极层的第一电极71连接的第二掺杂部22与第一掺杂部21之间产生电场，且源漏极层的第二电极72连接的第三掺杂部23与第一掺杂部21之间产生电场。从而相较于现有技术中单个导电沟道的设置，本申请通过形成两个有源子部的设置以形成两个导电沟道，以达到了延长导电沟道的效果，如此既增大有源层的迁移率，又相应的减小漏电流。It can be understood that in the array substrate 100 of the present embodiment, by connecting the gate 50 to the first doped portion 21 located between the first active sub-portion 31 and the second active sub-portion 32, the gate 50 can not only provide control over the first active sub-portion 31 and the second active sub-portion 32, but also multiplex the gate 50 as the source and drain, that is, the gate 50 can also provide input voltage and output voltage. In this way, an electric field can be generated between the second doped portion 22 connected to the first electrode 71 of the source-drain layer and the first doped portion 21, and an electric field can be generated between the third doped portion 23 connected to the second electrode 72 of the source-drain layer and the first doped portion 21. Therefore, compared with the setting of a single conductive channel in the prior art, the present application forms two conductive channels by forming two active sub-portions to achieve the effect of extending the conductive channel, thereby increasing the mobility of the active layer and correspondingly reducing the leakage current.

下面将对阵列基板100的制备方法进行详细的阐述：The following is a detailed description of the method for preparing the array substrate 100:

参照图3，S1：提供一衬底10。该衬底10包括基板11和缓冲层12，基板11可以是玻璃基板11，该缓冲层12可以通过化学沉积的方式形成于基板11上，缓冲层12可以是氮化硅和氧化硅中的一种或多种的组合，缓冲层12的作用是隔绝玻璃基板11和有源层，以防止玻璃基板11内的金属离子扩散到有源层中，进一步降低漏电流的产生，同时缓冲层12还可以对其它膜层起到支撑缓冲作用。Referring to Fig. 3, S1: providing a substrate 10. The substrate 10 includes a substrate 11 and a buffer layer 12, the substrate 11 may be a glass substrate 11, the buffer layer 12 may be formed on the substrate 11 by chemical deposition, the buffer layer 12 may be a combination of one or more of silicon nitride and silicon oxide, the function of the buffer layer 12 is to isolate the glass substrate 11 from the active layer to prevent the metal ions in the glass substrate 11 from diffusing into the active layer, further reducing the generation of leakage current, and the buffer layer 12 may also play a supporting and buffering role for other film layers.

参照图4，S2：在衬底10上形成掺杂层20，对掺杂层20图案化以形成第一开口24、第二开口25、第一掺杂部21、第二掺杂部22以及第三掺杂部23，第一掺杂部21位于第一开口24和第二开口25之间，第二掺杂部22位于第一开口24远离第二开口25的一侧，第三掺杂部23位于第二开口25远离第一开口24的一侧。其中，通过在缓冲层12通过化学沉积的方式形成掺杂层20，该掺杂层20可以为硅层掺杂磷离子(P)。之后再通过刻蚀的方式以使掺杂层20图案化以形成第一开口24、第二开口25、第一掺杂部21、第二掺杂部22以及第三掺杂部23。Referring to FIG. 4 , S2: forming a doping layer 20 on the substrate 10, patterning the doping layer 20 to form a first opening 24, a second opening 25, a first doping portion 21, a second doping portion 22, and a third doping portion 23, wherein the first doping portion 21 is located between the first opening 24 and the second opening 25, the second doping portion 22 is located on a side of the first opening 24 away from the second opening 25, and the third doping portion 23 is located on a side of the second opening 25 away from the first opening 24. The doping layer 20 is formed by chemical deposition on the buffer layer 12, and the doping layer 20 may be a silicon layer doped with phosphorus ions (P). Then, the doping layer 20 is patterned by etching to form the first opening 24, the second opening 25, the first doping portion 21, the second doping portion 22, and the third doping portion 23.

参照图5，S3：在衬底10上形成有源层30，有源层30包括第一有源子部31和第二有源子部32，第一有源子部31覆盖第一开口24内，并与第一掺杂部21和第二掺杂部22连接，第二有源子部32覆盖第二开口25内，且分别与第一掺杂部21和第三掺杂部23连接。其中，该有源层可以通过化学气相沉积的方式在第一开口24形成第一有源子部31，以及在第二开口25内形成第二有源子部32，从而实现第一有源子部31与第一掺杂部21和第二掺杂部22连接，而第二有源子部32与第一掺杂部21和第三掺杂部23连接。如此薄膜晶体管的载流子迁移路径需经过第一掺杂部21、第二掺杂部22以及第三掺杂部23，从而也同步达到延长导电沟道长度，也可以达到减小漏电流同时兼顾较高迁移率的效果。Referring to FIG. 5 , S3: forming an active layer 30 on the substrate 10, the active layer 30 including a first active sub-section 31 and a second active sub-section 32, the first active sub-section 31 covers the first opening 24 and is connected to the first doped section 21 and the second doped section 22, the second active sub-section 32 covers the second opening 25 and is respectively connected to the first doped section 21 and the third doped section 23. The active layer can be formed by chemical vapor deposition to form the first active sub-section 31 in the first opening 24 and the second active sub-section 32 in the second opening 25, so that the first active sub-section 31 is connected to the first doped section 21 and the second doped section 22, and the second active sub-section 32 is connected to the first doped section 21 and the third doped section 23. In this way, the carrier migration path of the thin film transistor needs to pass through the first doped section 21, the second doped section 22 and the third doped section 23, thereby simultaneously extending the conductive channel length, and also achieving the effect of reducing leakage current while taking into account higher mobility.

S4：对第一有源子部31和第二有源子部32进行退火结晶处理。其中，通过该有源层可以由非晶硅退火处理为低温多晶硅，以提高迁移率。S4: performing annealing and crystallization treatment on the first active sub-section 31 and the second active sub-section 32. The active layer can be annealed from amorphous silicon to low-temperature polysilicon to improve mobility.

参照图6，进一步地，S4的步骤包括：蓝色激光沿预定方向移动，以对第一有源子部31和第二有源子部32进行激光退火处理。其中，该蓝色激光可由激光设备200发出，且该激光设备200沿预定方向移动，以使得激光设备200发出的蓝色激光沿预定方向移动，该预定方向如图6中虚线所示。该预定方向可以为第一有源子部31朝向第二有源子部32的方向，以对第一有源子部31和第二有源子部32依次进行蓝色激光扫描，或者预定方向也可以第二有源子部32朝向第一有源子部31的方向，以依次经过第二有源子部32和第一有源子部31进行蓝色激光扫描。利用蓝色激光退火技术，实现非晶硅到多晶硅的转变，大大提升了的迁移率。Referring to FIG6 , further, the step of S4 includes: the blue laser moves along a predetermined direction to perform laser annealing on the first active sub-section 31 and the second active sub-section 32. The blue laser can be emitted by the laser device 200, and the laser device 200 moves along a predetermined direction so that the blue laser emitted by the laser device 200 moves along a predetermined direction, and the predetermined direction is shown by a dotted line in FIG6 . The predetermined direction can be the direction from the first active sub-section 31 to the second active sub-section 32, so as to perform blue laser scanning on the first active sub-section 31 and the second active sub-section 32 in sequence, or the predetermined direction can also be the direction from the second active sub-section 32 to the first active sub-section 31, so as to perform blue laser scanning on the second active sub-section 32 and the first active sub-section 31 in sequence. The blue laser annealing technology is used to realize the transformation from amorphous silicon to polycrystalline silicon, which greatly improves the mobility.

更进一步地，步骤S4还包括：蓝色激光还对第一掺杂部21、第二掺杂部22以及第三掺杂部23进行照射，以使第一掺杂部21形成相邻设置的第一重掺杂部211和第一轻掺杂部212，第二掺杂部22形成相邻设置的第二重掺杂部221和第二轻掺杂部222，第三掺杂部23形成相邻设置的第三重掺杂部231和第三轻掺杂部232。Furthermore, step S4 also includes: the blue laser also irradiates the first doping part 21, the second doping part 22 and the third doping part 23, so that the first doping part 21 forms a first heavily doped part 211 and a first lightly doped part 212 arranged adjacently, the second doping part 22 forms a second heavily doped part 221 and a second lightly doped part 222 arranged adjacently, and the third doping part 23 forms a third heavily doped part 231 and a third lightly doped part 232 arranged adjacently.

可以理解的是，蓝色激光经过第一有源子部31和第二有源子部32的同时也会经过第一掺杂部21、第二掺杂部22以及第三掺杂部23，如此以使第一掺杂部21，第二掺杂部22以及第三掺杂部23均在蓝色激光作用下形成熔融状态，进而第一掺杂部21第二掺杂部22以及第三掺杂部23内注入的磷离子会在熔融后进行扩散，即朝向激光扫描方向产生离子浓度差，进而形成第一重掺杂部211和第一轻掺杂部212，第二重掺杂部221和第二轻掺杂部222，第三重掺杂部231和第三轻掺杂部232。进而以减弱电场，改善热载流子效应，减少关态下连接端的电子迁移现象，进而降低薄膜晶体管漏电流，减少功率损耗，从而进一步达到降低漏电流的作用。It can be understood that the blue laser passes through the first active sub-section 31 and the second active sub-section 32 while also passing through the first doped section 21, the second doped section 22 and the third doped section 23, so that the first doped section 21, the second doped section 22 and the third doped section 23 are all in a molten state under the action of the blue laser, and then the phosphorus ions injected into the first doped section 21, the second doped section 22 and the third doped section 23 will diffuse after melting, that is, an ion concentration difference is generated in the laser scanning direction, and then the first heavily doped section 211 and the first lightly doped section 212, the second heavily doped section 221 and the second lightly doped section 222, the third heavily doped section 231 and the third lightly doped section 232 are formed. Then, the electric field is weakened, the hot carrier effect is improved, and the electron migration phenomenon at the connection end in the off state is reduced, thereby reducing the leakage current of the thin film transistor and reducing the power loss, thereby further achieving the effect of reducing the leakage current.

需要说明的是，在步骤S4前，阵列基板100的制备方法还包括对有源层进行去氢处理。其中，高温烘烤炉对有源层层进行脱氢处理，具体温度可以在400℃至500℃之间，例如400℃、450℃以及500℃，加热时间1小时至3小时，例如1小时、2小时以及3小时，以防止后续步骤中采用高能量激光照射有源层时产生的气体撑破有源层。It should be noted that, before step S4, the preparation method of the array substrate 100 further includes dehydrogenating the active layer. The high-temperature baking furnace dehydrogenates the active layer, and the specific temperature may be between 400°C and 500°C, such as 400°C, 450°C and 500°C, and the heating time may be 1 hour to 3 hours, such as 1 hour, 2 hours and 3 hours, to prevent the gas generated when the high-energy laser is used to irradiate the active layer in the subsequent steps from breaking the active layer.

参照图7至图9，S5的步骤包括：在所述衬底10上形成第一绝缘层40上，并覆盖所述掺杂层20和所述有源层30，所述第一绝缘层40形成有第一连接孔41，在所述第一绝缘层40形成栅极50，所述栅极50与所述第一有源子部31和所述第二有源子部32重叠，所述栅极50穿过所述第一连接孔41与所述第一掺杂部21连接。其中，该栅极50可以由Mo、Ti、W等金属材质制成。该第一绝缘层40可以是SiOx和SiNx等无机膜层。7 to 9, step S5 includes: forming a first insulating layer 40 on the substrate 10 and covering the doped layer 20 and the active layer 30, the first insulating layer 40 is formed with a first connection hole 41, forming a gate 50 on the first insulating layer 40, the gate 50 overlaps the first active sub-section 31 and the second active sub-section 32, and the gate 50 passes through the first connection hole 41 and is connected to the first doped section 21. The gate 50 can be made of metal materials such as Mo, Ti, and W. The first insulating layer 40 can be an inorganic film layer such as SiOx and SiNx.

进一步地，S5的步骤包括：Furthermore, the step of S5 includes:

参照图7，S51：在第一掺杂部21上形成栅极50的第一部51。其中，可以通过物理气相沉积在第一掺杂部21形成栅极50的第一部51。7 , S51 : forming a first portion 51 of the gate 50 on the first doped portion 21 . The first portion 51 of the gate 50 may be formed on the first doped portion 21 by physical vapor deposition.

参照图8，S52：在衬底10上形成第一绝缘层40，并覆盖掺杂层20、有源层以及栅极50的第一部51。通过化学气相沉积形成第一绝缘层40。8, S52: forming a first insulating layer 40 on the substrate 10, and covering the doping layer 20, the active layer and the first portion 51 of the gate 50. The first insulating layer 40 is formed by chemical vapor deposition.

参照图9，S53：在第一绝缘层40上形成栅极50的第二部52，且第二部52与第一有源子部31和第二有源子部32重叠，栅极50与第一掺杂部21之间的第一绝缘层40开设有第一连接孔41，栅极50的第二部52穿过第一连接孔41与第一部51连接。Referring to Figure 9, S53: a second portion 52 of the gate 50 is formed on the first insulating layer 40, and the second portion 52 overlaps with the first active sub-portion 31 and the second active sub-portion 32, and a first connecting hole 41 is opened in the first insulating layer 40 between the gate 50 and the first doped portion 21, and the second portion 52 of the gate 50 is connected to the first portion 51 through the first connecting hole 41.

其中，同时可以通过刻蚀的方式在第一绝缘层40对应栅极50的第一部51的位置形成第一连接孔41，以便于后续栅极50的第二部52与第一部51的连接，之后再通过物理气相沉积在第一绝缘层40上形成栅极50的第二部52，以使第二部52穿过第一连接孔41与第一部51电连接。而该第二部52与第一有源子部31和第二有源子部32完全重叠，如此以对第一有源子部31和第二有源子部32进行控制。At the same time, a first connection hole 41 can be formed by etching at a position of the first insulating layer 40 corresponding to the first portion 51 of the gate 50, so as to facilitate the subsequent connection between the second portion 52 of the gate 50 and the first portion 51, and then the second portion 52 of the gate 50 is formed on the first insulating layer 40 by physical vapor deposition, so that the second portion 52 passes through the first connection hole 41 and is electrically connected to the first portion 51. The second portion 52 completely overlaps with the first active sub-portion 31 and the second active sub-portion 32, so as to control the first active sub-portion 31 and the second active sub-portion 32.

参照图10，S6：在第一绝缘层40上形成第二绝缘层60，并覆盖栅极50的第二部52。其中，通过化学气相沉积在第一绝缘层40上形成第二绝缘层60，该第二绝缘层60可以是SiOx和SiNx等无机膜层或其叠层，以对栅极50的第二部52进行保护。10 , S6: forming a second insulating layer 60 on the first insulating layer 40 and covering the second portion 52 of the gate 50. The second insulating layer 60 is formed on the first insulating layer 40 by chemical vapor deposition, and the second insulating layer 60 may be an inorganic film layer such as SiOx and SiNx or a stack thereof, so as to protect the second portion 52 of the gate 50.

参照图11，S7：在第二绝缘层60上形成源漏极层70，第二绝缘层60形成有第二连接孔61和第三连接孔62，且源漏极层70图案化以形成第一电极71和第二电极72，第一电极71通过第二连接孔61与第二掺杂部22连接，第二电极72通过第三连接孔62与第三掺杂部23连接。Referring to Figure 11, S7: a source-drain layer 70 is formed on the second insulating layer 60, the second insulating layer 60 is formed with a second connection hole 61 and a third connection hole 62, and the source-drain layer 70 is patterned to form a first electrode 71 and a second electrode 72, the first electrode 71 is connected to the second doped portion 22 through the second connection hole 61, and the second electrode 72 is connected to the third doped portion 23 through the third connection hole 62.

其中，可以通过刻蚀液在第一绝缘层40和第二绝缘层60相对于第二掺杂部22的位置刻蚀形成第二连接孔61，同时在第一绝缘层40和第二绝缘层60相对于第三掺杂部23的位置刻蚀形成第三连接孔62。之后再通过采用物理气相沉积Mo、Ti、Cu等金属材料在第二绝缘层60上形成源漏极层，且该源漏极层70沉积于第一连接孔41和第二连接孔61内以分别与第二掺杂部22和第三掺杂部23连接。之后再通过刻蚀以使源漏极层形成第一电极71和第二电极72，以分别作为源极和漏极。Among them, the second connection hole 61 can be formed by etching the first insulating layer 40 and the second insulating layer 60 at the position relative to the second doping part 22, and the third connection hole 62 can be formed by etching the first insulating layer 40 and the second insulating layer 60 at the position relative to the third doping part 23. Then, a source-drain electrode layer is formed on the second insulating layer 60 by using physical vapor deposition of metal materials such as Mo, Ti, and Cu, and the source-drain electrode layer 70 is deposited in the first connection hole 41 and the second connection hole 61 to be connected to the second doping part 22 and the third doping part 23 respectively. Then, the source-drain electrode layer is etched to form a first electrode 71 and a second electrode 72 to serve as a source and a drain respectively.

参照图1和图2，进一步地，阵列基板的制备方法还包括S8：在源漏极层以及绝缘层上形成钝化层80。可选的，采用化学气相沉积法在第一电极71和第二电极72上形成钝化层80。钝化层80的材料可以为SiOx和SiNx等无机膜层或其叠层。1 and 2, further, the method for preparing the array substrate further includes S8: forming a passivation layer 80 on the source and drain electrode layer and the insulating layer. Optionally, the passivation layer 80 is formed on the first electrode 71 and the second electrode 72 by chemical vapor deposition. The material of the passivation layer 80 can be an inorganic film layer such as SiOx and SiNx or a stack thereof.

以上对本申请实施例所提供的一种阵列基板、显示面板及阵列基板的制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。The above is a detailed introduction to an array substrate, a display panel and a method for preparing an array substrate provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

综上所述，虽然本申请以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为基准。In summary, although the present application is disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims (20)

一种阵列基板，包括：An array substrate, comprising: 衬底；substrate; 掺杂层，所述掺杂层设于所述衬底上，所述掺杂层开设有第一开口和第二开口，所述掺杂层包括第一掺杂部、第二掺杂部以及第三掺杂部，所述第一掺杂部位于所述第一开口和所述第二开口之间，所述第二掺杂部位于所述第一开口远离所述第二开口的一侧，所述第三掺杂部位于所述第二开口远离所述第一开口的一侧；a doping layer, the doping layer being disposed on the substrate, the doping layer being provided with a first opening and a second opening, the doping layer comprising a first doping portion, a second doping portion and a third doping portion, the first doping portion being located between the first opening and the second opening, the second doping portion being located on a side of the first opening away from the second opening, and the third doping portion being located on a side of the second opening away from the first opening; 有源层，所述有源层设于所述衬底上，且所述有源层包括第一有源子部和第二有源子部，所述第一有源子部位于所述第一开口内，且分别与所述第一掺杂部和所述第二掺杂部连接，所述第二有源子部位于所述第二开口内，且分别与所述第一掺杂部和所述第三掺杂部连接；an active layer, the active layer being disposed on the substrate, and the active layer comprising a first active sub-portion and a second active sub-portion, the first active sub-portion being located in the first opening and being connected to the first doped portion and the second doped portion respectively, the second active sub-portion being located in the second opening and being connected to the first doped portion and the third doped portion respectively; 第一绝缘层，所述第一绝缘层设于所述衬底上，并覆盖所述掺杂层和所述有源层；a first insulating layer, the first insulating layer being disposed on the substrate and covering the doped layer and the active layer; 栅极，所述栅极至少部分设于所述第一绝缘层上，且所述栅极分别与所述第一有源子部和所述第二有源子部重叠，所述第一绝缘层开设有第一连接孔，所述栅极通过所述第一连接孔与所述第一掺杂部电连接；a gate, wherein the gate is at least partially disposed on the first insulating layer, and the gate overlaps with the first active sub-portion and the second active sub-portion respectively, the first insulating layer is provided with a first connection hole, and the gate is electrically connected to the first doped portion through the first connection hole; 第二绝缘层，所述第二绝缘层设于所述第一绝缘层上，并覆盖所述栅极；以及a second insulating layer, the second insulating layer being disposed on the first insulating layer and covering the gate; and 源漏极层，所述源漏极层设置于所述第二绝缘层上，所述第二绝缘层设置有第二连接孔和第三连接孔，所述源漏极层包括第一电极和第二电极，所述第一电极通过所述第二连接孔与所述第二掺杂部连接，所述第二电极通过所述第三连接孔与所述第三掺杂部连接。A source-drain layer, wherein the source-drain layer is arranged on the second insulating layer, the second insulating layer is provided with a second connection hole and a third connection hole, the source-drain layer includes a first electrode and a second electrode, the first electrode is connected to the second doped portion through the second connection hole, and the second electrode is connected to the third doped portion through the third connection hole. 如权利要求1所述的阵列基板，其中，所述栅极为单层结构。The array substrate according to claim 1, wherein the gate is a single-layer structure. 如权利要求1所述的阵列基板，其中，所述栅极包括第一部和第二部，所述第一部设置于所述第一掺杂部上；所述第二部设置于所述第一绝缘层上，并与所述第一有源子部和所述第二有源子部重叠，所述第一部和所述第二部通过所述第一连接孔连接。The array substrate as described in claim 1, wherein the gate includes a first portion and a second portion, the first portion is arranged on the first doped portion; the second portion is arranged on the first insulating layer and overlaps with the first active sub-portion and the second active sub-portion, and the first portion and the second portion are connected through the first connecting hole. 如权利要求1所述的阵列基板，其中，所述第一掺杂部包括相邻设置的第一重掺杂部和第一轻掺杂部，所述第一轻掺杂部与所述第一有源子部连接，所述第一重掺杂部与所述第二有源子部连接，所述栅极穿过所述第一连接孔与所述第一重掺杂部电连接The array substrate according to claim 1, wherein the first doped portion comprises a first heavily doped portion and a first lightly doped portion that are adjacently arranged, the first lightly doped portion is connected to the first active sub-portion, the first heavily doped portion is connected to the second active sub-portion, and the gate is electrically connected to the first heavily doped portion through the first connection hole. 如权利要求4所述的阵列基板，其中，所述第二掺杂部包括相邻设置的第二重掺杂部和第二轻掺杂部，所述第二轻掺杂部位于所述第二重掺杂部远离所述第一轻掺杂部的一侧，所述源漏极层的第一电极穿过所述第二连接孔与所述第二重掺杂部连接。The array substrate as described in claim 4, wherein the second doped portion includes a second heavily doped portion and a second lightly doped portion arranged adjacent to each other, the second lightly doped portion is located on a side of the second heavily doped portion away from the first lightly doped portion, and the first electrode of the source and drain layer is connected to the second heavily doped portion through the second connecting hole. 如权利要求4所述的阵列基板，其中，所述第三掺杂部包括相邻设置的第三重掺杂部和第三轻掺杂部，所述第三重掺杂部位于所述第三轻掺杂部部远离所述第一重掺杂部的一侧，所述源漏极层的第二电极穿过所述第三连接孔与所述第三重掺杂部连接。The array substrate as described in claim 4, wherein the third doped portion includes a third heavily doped portion and a third lightly doped portion arranged adjacent to each other, the third heavily doped portion is located on a side of the third lightly doped portion away from the first heavily doped portion, and the second electrode of the source and drain layer is connected to the third heavily doped portion through the third connecting hole. 如权利要求1所述的阵列基板，其中，所述第一有源子部的厚度小于所述第一掺杂部的厚度和/或所述第二掺杂部的厚度。The array substrate according to claim 1, wherein the thickness of the first active sub-portion is less than the thickness of the first doped portion and/or the thickness of the second doped portion. 如权利要求1所述的阵列基板，其中，所述第二有源子部的厚度小于所述第一掺杂部的厚度和/或所述第三掺杂部的厚度。The array substrate according to claim 1, wherein the thickness of the second active sub-portion is less than the thickness of the first doped portion and/or the thickness of the third doped portion. 一种显示面板，包括阵列基板，所述阵列基板包括：A display panel includes an array substrate, wherein the array substrate includes: 衬底；substrate; 掺杂层，所述掺杂层设于所述衬底上，所述掺杂层开设有第一开口和第二开口，所述掺杂层包括第一掺杂部、第二掺杂部以及第三掺杂部，所述第一掺杂部位于所述第一开口和所述第二开口之间，所述第二掺杂部位于所述第一开口远离所述第二开口的一侧，所述第三掺杂部位于所述第二开口远离所述第一开口的一侧；a doping layer, the doping layer being disposed on the substrate, the doping layer being provided with a first opening and a second opening, the doping layer comprising a first doping portion, a second doping portion and a third doping portion, the first doping portion being located between the first opening and the second opening, the second doping portion being located on a side of the first opening away from the second opening, and the third doping portion being located on a side of the second opening away from the first opening; 有源层，所述有源层设于所述衬底上，且所述有源层包括第一有源子部和第二有源子部，所述第一有源子部位于所述第一开口内，且分别与所述第一掺杂部和所述第二掺杂部连接，所述第二有源子部位于所述第二开口内，且分别与所述第一掺杂部和所述第三掺杂部连接；an active layer, the active layer being disposed on the substrate, and the active layer comprising a first active sub-portion and a second active sub-portion, the first active sub-portion being located in the first opening and being connected to the first doped portion and the second doped portion respectively, the second active sub-portion being located in the second opening and being connected to the first doped portion and the third doped portion respectively; 第一绝缘层，所述第一绝缘层设于所述衬底上，并覆盖所述掺杂层和所述有源层；a first insulating layer, the first insulating layer being disposed on the substrate and covering the doped layer and the active layer; 栅极，所述栅极至少部分设于所述第一绝缘层上，且所述栅极分别与所述第一有源子部和所述第二有源子部重叠，所述第一绝缘层开设有第一连接孔，所述栅极通过所述第一连接孔与所述第一掺杂部电连接；a gate, wherein the gate is at least partially disposed on the first insulating layer, and the gate overlaps with the first active sub-portion and the second active sub-portion respectively, the first insulating layer is provided with a first connection hole, and the gate is electrically connected to the first doped portion through the first connection hole; 第二绝缘层，所述第二绝缘层设于所述第一绝缘层上，并覆盖所述栅极；以及a second insulating layer, the second insulating layer being disposed on the first insulating layer and covering the gate; and 源漏极层，所述源漏极层设置于所述第二绝缘层上，所述第二绝缘层设置有第二连接孔和第三连接孔，所述源漏极层包括第一电极和第二电极，所述第一电极通过所述第二连接孔与所述第二掺杂部连接，所述第二电极通过所述第三连接孔与所述第三掺杂部连接。A source-drain layer, wherein the source-drain layer is arranged on the second insulating layer, the second insulating layer is provided with a second connection hole and a third connection hole, the source-drain layer includes a first electrode and a second electrode, the first electrode is connected to the second doped portion through the second connection hole, and the second electrode is connected to the third doped portion through the third connection hole. 如权利要求9所述的显示面板，其中，所述栅极为单层结构。The display panel as claimed in claim 9, wherein the gate electrode is a single-layer structure. 如权利要求9所述的显示面板，其中，所述栅极包括第一部和第二部，所述第一部设置于所述第一掺杂部上；所述第二部设置于所述第一绝缘层上，并与所述第一有源子部和所述第二有源子部重叠，所述第一部和所述第二部通过所述第一连接孔连接。The display panel as claimed in claim 9, wherein the gate comprises a first portion and a second portion, the first portion is arranged on the first doped portion; the second portion is arranged on the first insulating layer and overlaps with the first active sub-portion and the second active sub-portion, and the first portion and the second portion are connected through the first connecting hole. 如权利要求9所述的显示面板，其中，所述第一掺杂部包括相邻设置的第一重掺杂部和第一轻掺杂部，所述第一轻掺杂部与所述第一有源子部连接，所述第一重掺杂部与所述第二有源子部连接，所述栅极穿过所述第一连接孔与所述第一重掺杂部电连接The display panel according to claim 9, wherein the first doped portion comprises a first heavily doped portion and a first lightly doped portion disposed adjacent to each other, the first lightly doped portion is connected to the first active sub-portion, the first heavily doped portion is connected to the second active sub-portion, and the gate is electrically connected to the first heavily doped portion through the first connection hole. 如权利要求12所述的显示面板，其中，所述第二掺杂部包括相邻设置的第二重掺杂部和第二轻掺杂部，所述第二轻掺杂部位于所述第二重掺杂部远离所述第一轻掺杂部的一侧，所述源漏极层的第一电极穿过所述第二连接孔与所述第二重掺杂部连接。The display panel as described in claim 12, wherein the second doped portion includes a second heavily doped portion and a second lightly doped portion arranged adjacent to each other, the second lightly doped portion is located on a side of the second heavily doped portion away from the first lightly doped portion, and the first electrode of the source and drain layer is connected to the second heavily doped portion through the second connecting hole. 如权利要求12所述的显示面板，其中，所述第三掺杂部包括相邻设置的第三重掺杂部和第三轻掺杂部，所述第三重掺杂部位于所述第三轻掺杂部部远离所述第一重掺杂部的一侧，所述源漏极层的第二电极穿过所述第三连接孔与所述第三重掺杂部连接。The display panel as claimed in claim 12, wherein the third doped portion comprises a third heavily doped portion and a third lightly doped portion arranged adjacent to each other, the third heavily doped portion is located on a side of the third lightly doped portion away from the first heavily doped portion, and the second electrode of the source and drain layer is connected to the third heavily doped portion through the third connecting hole. 如权利要求9所述的显示面板，其中，所述第一有源子部的厚度小于所述第一掺杂部的厚度和/或所述第二掺杂部的厚度。The display panel as claimed in claim 9, wherein the thickness of the first active sub-portion is less than the thickness of the first doped portion and/or the thickness of the second doped portion. 如权利要求9所述的显示面板，其中，所述第二有源子部的厚度小于所述第一掺杂部的厚度和/或所述第三掺杂部的厚度。The display panel as claimed in claim 9, wherein the thickness of the second active sub-portion is less than the thickness of the first doped portion and/or the thickness of the third doped portion. 一种阵列基板的制备方法，包括：A method for preparing an array substrate, comprising: S1：提供一衬底；S1: providing a substrate; S2：在所述衬底上形成掺杂层，对所述掺杂层图案化以形成第一开口、第二开口、第一掺杂部、第二掺杂部以及第三掺杂部，所述第一掺杂部位于所述第一开口和所述第二开口之间，所述第二掺杂部位于所述第一开口远离所述第二开口的一侧，所述第三掺杂部位于所述第二开口远离所述第一开口的一侧；S2: forming a doping layer on the substrate, and patterning the doping layer to form a first opening, a second opening, a first doping portion, a second doping portion, and a third doping portion, wherein the first doping portion is located between the first opening and the second opening, the second doping portion is located on a side of the first opening away from the second opening, and the third doping portion is located on a side of the second opening away from the first opening; S3：在所述衬底上形成有源层，所述有源层包括第一有源子部和第二有源子部，所述第一有源子部覆盖所述第一开口内，并与所述第一掺杂部和所述第二掺杂部连接，所述第二有源子部覆盖所述第二开口内，且分别与所述第一掺杂部和所述第三掺杂部连接；S3: forming an active layer on the substrate, the active layer comprising a first active sub-portion and a second active sub-portion, the first active sub-portion covers the first opening and is connected to the first doped portion and the second doped portion, the second active sub-portion covers the second opening and is respectively connected to the first doped portion and the third doped portion; S4：对所述第一有源子部和所述第二有源子部进行退火结晶处理；S4: performing annealing and crystallization treatment on the first active sub-section and the second active sub-section; S5：在所述衬底上形成第一绝缘层上，并覆盖所述掺杂层和所述有源层，所述第一绝缘层形成有第一连接孔，在所述第一绝缘层形成栅极，所述栅极与所述第一有源子部和所述第二有源子部重叠，所述栅极穿过所述第一连接孔与所述第一掺杂部连接；S5: forming a first insulating layer on the substrate and covering the doped layer and the active layer, wherein the first insulating layer is formed with a first connection hole, and forming a gate on the first insulating layer, wherein the gate overlaps with the first active sub-portion and the second active sub-portion, and the gate passes through the first connection hole and is connected to the first doped portion; S6：在所述第一绝缘层上形成第二绝缘层，并覆盖所述栅极；S6: forming a second insulating layer on the first insulating layer and covering the gate; S7：在所述第二绝缘层上形成源漏极层，所述第二绝缘层形成有第二连接孔和第三连接孔，且所述源漏极层图案化以形成第一电极和第二电极，所述第一电极通过所述第二连接孔与所述第二掺杂部连接，所述第二电极通过所述第三连接孔与所述第三掺杂部连接。S7: Form a source-drain layer on the second insulating layer, wherein the second insulating layer is formed with a second connection hole and a third connection hole, and the source-drain layer is patterned to form a first electrode and a second electrode, the first electrode is connected to the second doped portion through the second connection hole, and the second electrode is connected to the third doped portion through the third connection hole. 如权利要求17所述的制备方法，其中，所述S4：对所述第一有源子部和所述第二有源子部进行结晶处理的步骤包括：The preparation method according to claim 17, wherein the step of performing crystallization treatment on the first active sub-section and the second active sub-section in step S4 comprises: 蓝色激光沿预定方向移动，以对所述第一有源子部和所述第二有源子部进行激光退火处理。The blue laser moves along a predetermined direction to perform laser annealing on the first active sub-section and the second active sub-section. 如权利要求18所述的制备方法，其中，所述S4：对所述第一有源子部和所述第二有源子部进行结晶处理的步骤还包括：The preparation method according to claim 18, wherein the step of S4: performing crystallization treatment on the first active sub-section and the second active sub-section further comprises: 所述蓝色激光还对所述第一掺杂部、所述第二掺杂部以及所述第三掺杂部进行照射，以使所述第一掺杂部形成相邻设置的第一重掺杂部和第一轻掺杂部，所述第二掺杂部形成相邻设置的第二重掺杂部和第二轻掺杂部，所述第三掺杂部形成相邻设置的第三重掺杂部和第三轻掺杂部。The blue laser also irradiates the first doped portion, the second doped portion and the third doped portion, so that the first doped portion forms a first heavily doped portion and a first lightly doped portion arranged adjacent to each other, the second doped portion forms a second heavily doped portion and a second lightly doped portion arranged adjacent to each other, and the third doped portion forms a third heavily doped portion and a third lightly doped portion arranged adjacent to each other. 如权利要求17所述的制备方法，其中，所述第一有源子部的厚度小于所述第一掺杂部的厚度和/或所述第二掺杂部的厚度。The preparation method according to claim 17, wherein the thickness of the first active sub-section is less than the thickness of the first doped section and/or the thickness of the second doped section.
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CN107425075A (en) * 2017-05-17 2017-12-01 厦门天马微电子有限公司 Film transistor device and its manufacture method, array base palte and display device
CN114843285A (en) * 2022-04-25 2022-08-02 Tcl华星光电技术有限公司 Array substrate, manufacturing method thereof and display panel

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