WO2024109061A1 - 一种显示面板及显示装置 - Google Patents
一种显示面板及显示装置 Download PDFInfo
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- WO2024109061A1 WO2024109061A1 PCT/CN2023/104265 CN2023104265W WO2024109061A1 WO 2024109061 A1 WO2024109061 A1 WO 2024109061A1 CN 2023104265 W CN2023104265 W CN 2023104265W WO 2024109061 A1 WO2024109061 A1 WO 2024109061A1
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- Prior art keywords
- layer
- display area
- substrate
- conductive
- area
- Prior art date
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- 239000010410 layer Substances 0.000 claims abstract description 163
- 239000002346 layers by function Substances 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims description 74
- 238000005538 encapsulation Methods 0.000 claims description 24
- 230000002159 abnormal effect Effects 0.000 abstract description 9
- 238000000034 method Methods 0.000 description 14
- 238000010329 laser etching Methods 0.000 description 12
- 238000009826 distribution Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 101000827703 Homo sapiens Polyphosphoinositide phosphatase Proteins 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 102100023591 Polyphosphoinositide phosphatase Human genes 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZXVONLUNISGICL-UHFFFAOYSA-N 4,6-dinitro-o-cresol Chemical compound CC1=CC([N+]([O-])=O)=CC([N+]([O-])=O)=C1O ZXVONLUNISGICL-UHFFFAOYSA-N 0.000 description 1
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 1
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 1
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Definitions
- the present application relates to the field of display technology, and in particular to a display panel and a display device.
- OLED Organic light-emitting display
- OLED organic laser display
- OLED has the advantages of low voltage requirement, high power saving efficiency, fast response, light weight, thin thickness, simple structure, low cost, wide viewing angle, almost infinite contrast, low power consumption, and extremely high response speed. It has become one of the most important display technologies today.
- the light-emitting functional layer will reserve the alignment accuracy when designing the frame, and the range of the light-emitting functional layer in the frame is related to the manufacturer's production capabilities.
- the distribution range of the light-emitting functional layer can be compressed, but it may cause the thickness of the light-emitting functional layer in some openings at the edge of the pixel definition layer to be thin, which will lead to abnormal light emission of the display panel, and the existing process may not be able to compress the distribution range of the light-emitting functional layer; on the other hand, if the distribution range of the light-emitting functional layer is not compressed, it will cause the light-emitting functional layer to cover the conductive unit in the non-display area, thereby affecting the overlap between the conductive unit in the non-display area and the cathode, causing the display panel to be abnormal and scrapped.
- the object of the present invention is to provide a display panel and a display device, which can solve the problems of abnormal display panel light emission and great process difficulty caused by compressing the distribution range of the light-emitting functional layer in the prior art; and abnormal display panel scrapping caused by not compressing the distribution range of the light-emitting functional layer.
- the present invention provides a display panel, comprising: a display area and a non-display area arranged on at least one side of the display area, the non-display area comprising: a first routing sub-area, a gate driving sub-area, and a second routing sub-area arranged in sequence and gradually approaching the display area;
- the display panel also comprises: a substrate; a driving circuit layer, arranged on one side of the substrate;
- the driving circuit layer comprises: a pixel driving circuit arranged in the display area, a first routing arranged in the first routing sub-area, a gate driving circuit arranged in the gate driving sub-area, and a second routing arranged in the second routing sub-area, the gate driving circuit is electrically connected to the corresponding pixel driving circuit, and the second routing is electrically connected to the corresponding pixel driving circuit;
- a planar layer arranged on a side of the driving circuit layer away from the substrate; a first conductive layer, arranged on the planar layer away from the substrate
- a boundary of the light-emitting functional layer in the non-display area is between the second wiring and the display area.
- the conductive trace is spaced apart from the light-emitting functional layer, and the second conductive layer is in direct contact with at least a portion of the upper surface of the planar layer between the conductive trace and the light-emitting functional layer.
- the roughness of the surface of at least part of the conductive traces away from the substrate is greater than the roughness of the surface of the first electrode away from the substrate.
- the thickness of the planar layer between the conductive trace and the pixel definition layer is smaller than the thickness of the planar layer in the display area.
- the pixel definition layer has a step structure on a side close to the non-display area, and a boundary of the light-emitting functional layer in the non-display area is between the step structure and the display area.
- the second conductive layer covers the step structure.
- the display panel also includes: a first dam, arranged on a side of the flat layer away from the substrate, and at least part of the conductive traces are arranged between the first dam and the flat layer; a second dam, arranged on a side of the flat layer away from the substrate, and located on a side of the first dam away from the display area, wherein at least part of the conductive traces are arranged between the first dam and the flat layer.
- the display panel also includes: an encapsulation layer, which is arranged on a side of the second conductive layer away from the substrate, and the encapsulation layer includes a first inorganic encapsulation sublayer, an organic encapsulation sublayer, and a second inorganic encapsulation sublayer stacked in sequence; the first inorganic encapsulation sublayer is in direct contact with the upper surface of the conductive trace between the first dam and the second dam.
- the present invention further provides a display device, which includes the display panel of the present invention.
- the distribution range of the light-emitting functional layer is not compressed.
- the conductive traces covering the non-display area, the flat layer of the non-display area and the light-emitting functional layer on the pixel definition layer of part of the non-display area are removed by laser etching, so that the boundary of the light-emitting functional layer in the non-display area is located between the second trace sub-area and the display area.
- the narrow frame is designed, the light-emitting functional layer is prevented from covering the conductive traces in the non-display area, and abnormal electrical connection between the conductive traces in the non-display area and the second conductive layer is avoided.
- FIG1 is a schematic plan view of a display panel according to Embodiment 1 of the present invention.
- Fig. 2 is a cross-sectional view taken along line A-A of Fig. 1;
- Example 3 is a schematic structural diagram of a light-emitting unit and a light-emitting functional layer on a pixel electrode in Example 1;
- FIG4 is a diagram showing steps for preparing a display panel according to Embodiment 1 of the present invention.
- FIG. 5 is a schematic diagram of laser etching a light-emitting functional layer on a conductive unit according to Embodiment 1 of the present invention.
- FIG. 6 is a schematic structural diagram of a display panel according to Embodiment 2 of the present invention.
- FIG. 7 is a schematic diagram of laser etching a light-emitting functional layer on a conductive unit according to Embodiment 2 of the present invention.
- the display device includes a mobile phone, a computer, an MP3, an MP4, a tablet computer, a television, or a digital camera.
- the display device includes a display panel 100.
- the display panel 100 includes a display area 101 and a non-display area 102 of the display area 101 disposed on at least one side of the display area.
- the display panel 100 includes a display area 101 and a non-display area 102 surrounding the display area 101 .
- the non-display area 102 includes: a first wiring sub-area 1021 , a gate driving sub-area 1022 , and a second wiring sub-area 1023 which are arranged gradually close to the display area 101 in sequence.
- the display panel 100 includes: a substrate 1 , a driving circuit layer 2 , a planar layer 3 , a first conductive layer 4 , a pixel definition layer 5 , a light emitting functional layer 6 and a second conductive layer 7 .
- the material of the substrate 1 includes glass, polyimide, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, etc.
- the material of the substrate 1 is polyimide, so the substrate 1 has good impact resistance and can effectively protect the display panel 100 .
- the driving circuit layer 2 is disposed on one side of the substrate 1 .
- the driving circuit layer 2 includes: a pixel driving circuit 21 , a first wiring 22 , a gate driving circuit 23 , a second wiring 24 and an insulating layer 25 .
- the pixel driving circuit 21 is arranged on one side of the substrate 1 of the display area 101.
- a plurality of pixel driving circuits 21 are arranged on the substrate 1 of the display area 101 at intervals.
- the pixel driving circuit 21 includes: an active layer (not shown), a gate (not shown), a source and drain (not shown), a gate insulating layer (not shown) and other film structures.
- the first wiring 22 is disposed on one side of the substrate 1 in the first wiring sub-area 1021.
- the first wiring 22 is a low voltage power line.
- the gate driving circuit 23 is disposed on one side of the substrate 1 in the gate driving sub-area 1022 .
- the gate driving circuit 23 is electrically connected to the corresponding pixel driving circuit 21 .
- the second wiring 24 is disposed on one side of the substrate 1 in the second wiring sub-area 1023.
- the second wiring 24 is a reset signal line and is electrically connected to the corresponding pixel driving circuit 21.
- the insulating layer 25 is disposed on the substrate 1 between two adjacent pixel driving circuits 21, and is also disposed on the substrate 1 between the first wiring 22 and the gate driving circuit 23, and is also disposed on the substrate 1 between the gate driving circuit 23 and the second wiring 24, and is also disposed on the substrate 1 between the second wiring 24 and the pixel driving circuit 21.
- the insulating layer 25 can be formed by extending an insulating film layer such as a gate insulating layer of the pixel driving circuit 21.
- the flat layer 3 is disposed on the side of the driving circuit layer 2 away from the substrate 1.
- the material of the flat layer 3 can be SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx.
- the flat layer 3 is mainly used to provide a flat surface for the preparation of the film layer on the side away from the substrate 1.
- the first conductive layer 4 is arranged on a side of the flat layer 3 away from the substrate 1.
- the first conductive layer 4 includes: a conductive trace 41 arranged in the non-display area 102 and a first electrode 42 arranged in the display area 101.
- the first electrode 42 is electrically connected to the corresponding pixel driving circuit 21, and the conductive trace 41 is electrically connected to the first trace 22.
- each first electrode 42 passes through the flat layer 3 and is electrically connected to a drain of the pixel driving circuit 21.
- the material of the first electrode 42 is the same as that of the conductive trace 41, so the first electrode 42 and the conductive trace 41 can be prepared by the same process. In other embodiments, the material of the first electrode 42 may be different from that of the conductive trace 41.
- the pixel definition layer 5 is disposed on a side of the first conductive layer 4 away from the substrate 1, and the pixel definition layer 5 is provided with a pixel opening corresponding to the first electrode 42. It is worth noting that, in this embodiment, the boundary between the display area 101 and the non-display area 102 is the boundary of the projection of the outermost pixel opening of the pixel definition layer 5 on the substrate 1.
- the light-emitting functional layer 6 is disposed on a side of the pixel definition layer 5 away from the substrate 1 , and the light-emitting functional layer 6 covers the display area 101 and extends to the non-display area 102 .
- the boundary of the light-emitting functional layer 6 in the non-display area 102 is between the second wiring sub-area 1023 and the display area 101. Specifically, the boundary of the light-emitting functional layer 6 in the non-display area 102 is between the second wiring 24 and the display area 101.
- the distribution range of the light-emitting functional layer 6 is not compressed, and the light-emitting functional layer 6 covering the conductive wiring 41 in the non-display area 102, the flat layer 3 in the non-display area 102, and the pixel definition layer 5 in part of the non-display area 102 are removed by laser etching, so that the boundary of the light-emitting functional layer 6 in the non-display area 102 is between the second wiring 24 and the display area 101, and further, when the narrow frame is designed, the light-emitting functional layer 6 is prevented from covering the conductive wiring 41 in the non-display area 102, and the abnormal electrical connection between the conductive wiring 41 in the non-display area 102 and the second conductive layer 7 is avoided.
- the second conductive layer 7 is disposed on a side of the light-emitting functional layer 6 away from the substrate 1 , covers the display area 101 and extends to the non-display area 102 , and is electrically connected to the conductive trace 41 .
- the conductive trace 41 is spaced apart from the light-emitting functional layer 6 , and the second conductive layer 7 is in direct contact with at least a portion of the upper surface of the planar layer 3 between the conductive trace 41 and the light-emitting functional layer 6 .
- the display panel 100 further includes a first dam 8 and a second dam 9.
- the first dam 8 is disposed on a side of the planar layer 3 away from the substrate 1 , and at least a portion of the conductive traces 41 are disposed between the first dam 8 and the planar layer 3 .
- the second dam 9 is arranged on a side of the planar layer 3 away from the substrate 1 and on a side of the first dam 8 away from the display area 101 , wherein at least part of the conductive trace 41 is arranged between the first dam 8 and the planar layer 3 .
- the display panel 100 further includes a plurality of light emitting units 10 .
- the light emitting units 10 are disposed in the pixel openings of the pixel definition layer 5 in a one-to-one correspondence.
- the light-emitting functional layer 6 includes a first light-emitting functional layer 61 and a second light-emitting functional layer 62 .
- the first light-emitting functional layer 61 is disposed between the light-emitting unit 10 and the first electrode 42, and extends to cover the surface of the pixel definition layer 5 on the side away from the substrate 1.
- the first light-emitting functional layer 61 includes a hole injection layer, a hole transport layer, an electron blocking layer and other film structures.
- the second light-emitting functional layer 62 is disposed on the side of the light-emitting unit 10 away from the substrate 1, and extends to cover the first light-emitting functional layer 61.
- the second light-emitting functional layer 62 includes a film structure such as an electron transport layer, an electron injection layer, and a hole blocking layer.
- the display panel 100 also includes: an encapsulation layer (not shown), which is arranged on the side of the second conductive layer 7 away from the substrate 1, and the encapsulation layer includes a first inorganic encapsulation sublayer, an organic encapsulation sublayer, and a second inorganic encapsulation sublayer stacked in sequence; the first inorganic encapsulation sublayer is in direct contact with the upper surface of the conductive trace 41 between the first dam 8 and the second dam 9.
- an encapsulation layer (not shown), which is arranged on the side of the second conductive layer 7 away from the substrate 1, and the encapsulation layer includes a first inorganic encapsulation sublayer, an organic encapsulation sublayer, and a second inorganic encapsulation sublayer stacked in sequence; the first inorganic encapsulation sublayer is in direct contact with the upper surface of the conductive trace 41 between the first dam 8 and the second dam 9.
- this embodiment further provides a method for preparing the display panel 100 of this embodiment, comprising the following steps: S1, providing a substrate 1, defining a display area 101 and a non-display area 102 arranged on at least one side of the display area 101 on the substrate 1, wherein the non-display area 102 comprises: a first wiring sub-area 1021, a gate driving sub-area 1022, and a second wiring sub-area 1023 which are arranged gradually close to the display area 101 in sequence; S2, preparing a driving circuit layer 2 on the substrate 1 in the non-display area 102, wherein the gate driving sub-area 1022 and the second wiring sub-area 1023 are provided;
- the circuit layer 2 includes: a pixel driving circuit 21 arranged in the display area 101, a first wiring 22 arranged in the first wiring sub-area 1021, a gate driving circuit 23 arranged in the gate driving sub-area 1022, and a second wiring 24 arranged in the second wiring sub-area 1023, wherein the gate driving circuit 23 is
- the conductive trace 41 and the first electrode 42 are formed by the same process. In other embodiments, the conductive trace 41 and the first electrode 42 may be prepared separately.
- step S6 when performing a narrow frame design, since the distribution range of the light-emitting functional layer 6 is not compressed, the light-emitting functional layer 6 will cover the flat layer 3 and the conductive wiring 41 in the non-display area.
- the light-emitting functional layer 6 covering the conductive wiring 41 in the non-display area 102, the flat layer 3 in the non-display area 102 and part of the pixel definition layer 5 in the non-display area 102 are removed by a laser etching process, so that the boundary of the light-emitting functional layer 6 in the non-display area 102 is between the second wiring 24 and the display area 101, and further, when designing a narrow frame, the light-emitting functional layer 6 is prevented from covering the conductive wiring 41 in the non-display area 102, and abnormal electrical connection between the conductive wiring 41 in the non-display area 102 and the second conductive layer 7 is avoided.
- the surface of a part of the conductive trace 41 away from the substrate 1 is a rough surface.
- the roughness of the surface of at least a part of the conductive trace 41 away from the substrate 1 is greater than the roughness of the surface of the first electrode 42 away from the substrate 1.
- the thickness of the planar layer 3 between the conductive trace 41 and the pixel definition layer 5 is smaller than the thickness of the planar layer 3 in the display area 101 .
- this embodiment includes most of the technical features of Embodiment 1, and the difference between this embodiment and Embodiment 1 is that: in this embodiment, the pixel definition layer 5 in the non-display area is provided with at least one step structure 51 on the side close to the non-display area 102. Wherein, the boundary of the light-emitting functional layer 6 in the non-display area 102 is between the step structure 51 and the display area 102.
- the second conductive layer 7 covers the step structure 51.
- the shape of the step structure 51 includes at least one of a right angle and a rounded corner. In this embodiment, the shape of the step structure 51 is a right angle.
- At least one step structure 51 is formed on the pixel definition layer 5 in the non-display area on the side close to the non-display area 102.
- at least one step structure 51 can be formed on the pixel definition layer 5 in the non-display area 102 on the side close to the non-display area 102 during the process of removing the light-emitting functional layer 6 by laser etching.
- the light-emitting functional layer 6 when a narrow frame design is performed, since the distribution range of the light-emitting functional layer is not compressed, the light-emitting functional layer 6 will cover the flat layer 3 and the conductive trace 41 of the non-display area 102.
- the light-emitting functional layer 6 covering the conductive trace 41 of the non-display area 102, the flat layer 3 of the non-display area 102 and part of the pixel definition layer 5 of the non-display area 102 is removed by a laser etching process, so that the boundary of the light-emitting functional layer 6 in the non-display area 102 is between the second trace 24 and the display area 101.
- the light-emitting functional layer 6 is prevented from covering the conductive trace 41 of the non-display area 102, and abnormal electrical connection between the conductive trace 41 of the non-display area 102 and the second conductive layer 7 is prevented.
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Abstract
一种显示面板及显示装置。显示面板（100）的发光功能层（6）在非显示区（102）中的边界位于第二走线子区（1023）和显示区（101）之间，进而在窄边框设计时，避免发光功能层（6）覆盖于非显示区（102）的导电走线（41）上，避免非显示区（102）的导电走线（41）和第二导电层（7）之间出现电连接异常的现象。
Description
本申请涉及显示技术领域，具体涉及一种显示面板及显示装置。
有机发光显示装置(英文全称：Organic Light-Emitting Diode, 简称OLED)又称为有机电激光显示装置、有机发光半导体。OLED具有电压需求低、省电效率高、反应快、重量轻、厚度薄，构造简单，成本低、广视角、几乎无穷高的对比度、较低耗电、极高反应速度等优点，已经成为当今最重要的显示技术之一。
为了提升用户的体验感，显示面板的边框在逐渐减小。为了满足客户的需求，显示面板厂内也在同步开发窄边框技术。
目前，为了防止发光功能层影响导电单元和阴极的电连接性能，发光功能层在边框设计时会预留对位精度，而发光功能层在边框分布的范围大小与厂商的制作能力相关。当进行窄边框设计时，一方面可以将发光功能层的分布范围进行压缩，但是可能会导致像素定义层的边缘处的部分开口内的发光功能层厚度偏薄，进而导致显示面板的发光异常，而且现有工艺可能无法对发光功能层的分布范围进行压缩；另一方面，如果不对发光功能层的分布范围进行压缩，会导致发光功能层覆盖于非显示区的导电单元上，进而影响非显示区的导电单元和阴极之间的搭接，导致显示面板异常报废。
本发明的目的是提供一种显示面板及显示装置，其能够解决现有技术将发光功能层的分布范围进行压缩存在的显示面板发光异常、工艺难度大；不对发光功能层的分布范围进行压缩导致显示面板异常报废等问题。
为了解决上述问题，本发明提供一种显示面板，其包括：显示区和设置于所述显示区至少一侧的非显示区，所述非显示区包括：依次逐渐靠近所述显示区设置的第一走线子区、栅极驱动子区、第二走线子区；所述显示面板还包括：基板；驱动电路层，设置于所述基板的一侧；所述驱动电路层包括：设置于所述显示区的像素驱动电路、设置在所述第一走线子区的第一走线、设置在所述栅极驱动子区的栅极驱动电路、设置在所述第二走线子区的第二走线，所述栅极驱动电路与对应的所述像素驱动电路电连接，所述第二走线与对应的所述像素驱动电路电连接；平坦层，设置于所述驱动电路层远离所述基板的一侧；第一导电层，设置在所述平坦层远离所述基板的一侧，所述第一导电层包括：设置在所述非显示区的导电走线和设置在所述显示区的第一电极，所述第一电极与对应的所述像素驱动电路电连接，所述导电走线与所述第一走线电连接；像素定义层，设置于所述第一导电层远离所述基板的一侧，所述像素定义层对应所述第一电极设置有像素开口；发光功能层，设置于所述像素定义层远离所述基板的一侧，所述发光功能层覆盖所述显示区且延伸至所述非显示区，所述发光功能层在所述非显示区中的边界处于所述第二走线子区和所述显示区之间；以及第二导电层，设置于所述发光功能层远离所述基板的一侧，所述第二导电层覆盖所述显示区且延伸至所述非显示区，并与所述导电走线电连接。
进一步的，所述发光功能层在所述非显示区中的边界处于所述第二走线和所述显示区之间。
进一步的，所述导电走线与所述发光功能层之间间隔设置，所述第二导电层还与位于所述导电走线与所述发光功能层之间的平坦层的至少部分上表面直接接触。
进一步的，至少部分所述导电走线远离所述基板一侧表面的粗糙度，大于所述第一电极远离所述基板一侧表面的粗糙度。
进一步的，位于所述导电走线和所述像素定义层之间的所述平坦层的厚度，小于位于所述显示区中所述平坦层的厚度。
进一步的，所述像素定义层在靠近所述非显示区的一侧具有台阶结构，所述发光功能层在所述非显示区中的边界处于所述台阶结构和所述显示区之间。
进一步的，所述第二导电层覆盖所述台阶结构。
进一步的，所述显示面板还包括：第一堤坝，设置在所述平坦层远离所述基板的一侧，且至少部分所述导电走线设置在所述第一堤坝和所述平坦层之间；第二堤坝，设置在所述平坦层远离所述基板的一侧，且位于所述第一堤坝远离所述显示区的一侧，其中，至少部分所述导电走线设置在所述第一堤坝和所述平坦层之间。
进一步的，所述显示面板还包括：封装层，设置在所述第二导电层远离所述基板的一侧，所述封装层包括依次叠设的第一无机封装子层、有机封装子层、第二无机封装子层；所述第一无机封装子层与所述第一堤坝和所述第二堤坝之间的所述导电走线的上表面直接接触。
为了解决上述问题，本发明还提供一种显示装置，其包括本发明所述的显示面板。
本发明的显示面板在窄边框设计时，不对发光功能层的分布范围进行压缩，通过激光刻蚀去除覆盖于非显示区的导电走线、非显示区的平坦层以及部分非显示区的所述像素定义层上的所述发光功能层，使得所述发光功能层在所述非显示区中的边界位于所述第二走线子区和所述显示区之间，进而在窄边框设计时，避免发光功能层覆盖于非显示区的所述导电走线上，避免非显示区的导电走线和第二导电层之间出现电连接异常的现象。
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明的实施例1的显示面板的平面示意图；
图2是图1的A-A截面图；
图3是实施例1像素电极上的发光单元、发光功能层的结构示意图；
图4是本发明实施例1的显示面板的制备步骤图；
图5是本发明实施例1的激光刻蚀导电单元上的发光功能层的示意图；
图6是本发明的实施例2的显示面板的结构示意图；
图7是本发明实施例2的激光刻蚀导电单元上的发光功能层的示意图。
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。
实施例1
本实施例提供了一种显示装置。显示装置包括手机、电脑、MP3、MP4、平板电脑、电视或数码相机等。显示装置包括显示面板100。显示面板100包括显示区101和设置于所述显示区至少一侧的所述显示区101的非显示区102。
如图1所示，本实施例中，显示面板100包括显示区101和包围所述显示区101的非显示区102。
如图2所示，非显示区102包括：依次逐渐靠近所述显示区101设置的第一走线子区1021、栅极驱动子区1022、第二走线子区1023。
如图2所示，显示面板100包括：基板1、驱动电路层2、平坦层3、第一导电层4、像素定义层5、发光功能层6以及第二导电层7。
其中，基板1的材质包括玻璃、聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯以及聚萘二甲酸乙二醇酯等。本实施例中，基板1的材质为聚酰亚胺，由此基板1具有较好的抗冲击能力，可以有效保护显示面板100。
其中，驱动电路层2设置于所述基板1的一侧。所述驱动电路层2包括：像素驱动电路21、第一走线22、栅极驱动电路23、第二走线24以及绝缘层25。
其中，像素驱动电路21设置于所述显示区101的基板1的一侧。多个像素驱动电路21相互间隔设置于所述显示区101的基板1上。其中，像素驱动电路21包括：有源层（图未示）、栅极（图未示）、源漏极（图未示）、栅极绝缘层（图未示）等膜层结构。
其中，第一走线22设置在所述第一走线子区1021的基板1的一侧。本实施例中，第一走线22为低电压电源线。
其中，栅极驱动电路23设置在所述栅极驱动子区1022的基板1的一侧。栅极驱动电路23与对应的所述像素驱动电路21电连接。
其中，第二走线24设置在所述第二走线子区1023的基板1的一侧。本实施例中，第二走线24为复位信号线。第二走线24与对应的所述像素驱动电路21电连接。
其中，绝缘层25设置于相邻两个像素驱动电路21之间的基板1上，还设置于第一走线22与栅极驱动电路23之间的基板1上，还设置于栅极驱动电路23与第二走线24之间的基板1上，还设置于第二走线24与像素驱动电路21之间的基板1上。绝缘层25可以由像素驱动电路21的栅极绝缘层等绝缘膜层延伸形成。
其中，平坦层3设置于所述驱动电路层2远离所述基板1的一侧所述平坦层3的材质可为SiOx或SiNx或SiNOx或SiNx与SiOx的组合结构等。平坦层3主要是为其远离基板1的一侧的膜层的制备提供平整的表面。
其中，第一导电层4设置在所述平坦层3远离所述基板1的一侧。所述第一导电层4包括：设置在所述非显示区102的导电走线41和设置在所述显示区101的第一电极42。所述第一电极42与对应的所述像素驱动电路21电连接，所述导电走线41与所述第一走线22电连接。具体的，每一第一电极42穿过所述平坦层3对应电连接至一个所述像素驱动电路21的漏极。本实施例中，所述第一电极42的材质与所述导电走线41的材质相同，由此可以采用同一工序制备形成第一电极42和导电走线41。在其他实施例中，所述第一电极42的材质可以与所述导电走线41的材质不同。
其中，像素定义层5设置于所述第一导电层4远离所述基板1的一侧，所述像素定义层5对应所述第一电极42设置有像素开口。值得注意的是，本实施例中，显示区101和非显示区102的交界线为像素定义层5的最外面的一个像素开口在基板1上的投影的边界。
其中，发光功能层6设置于所述像素定义层5远离所述基板1的一侧，所述发光功能层6覆盖所述显示区101且延伸至所述非显示区102。
其中，所述发光功能层6在所述非显示区102中的边界处于所述第二走线子区1023和所述显示区101之间。具体的，所述发光功能层6在所述非显示区102中的边界处于所述第二走线24和所述显示区101之间。由此，显示面板100在窄边框设计时，不对发光功能层6的分布范围进行压缩，通过激光刻蚀去除覆盖于非显示区102的导电走线41、非显示区102的平坦层3以及部分非显示区102的所述像素定义层5上的所述发光功能层6，使得发光功能层6在所述非显示区102中的边界处于所述第二走线24和所述显示区101之间，进而在窄边框设计时，避免发光功能层6覆盖于非显示区102的所述导电走线41上，避免非显示区102的导电走线41和第二导电层7之间出现电连接异常的现象。
其中，第二导电层7设置于所述发光功能层6远离所述基板1的一侧，所述第二导电层7覆盖所述显示区101且延伸至所述非显示区102，并与所述导电走线41电连接。
其中，所述导电走线41与所述发光功能层6之间间隔设置，所述第二导电层7还与位于所述导电走线41与所述发光功能层6之间的平坦层3的至少部分上表面直接接触。
为了实现窄边框设计，需要对非显示区102的结构进行压缩。本实施例中，显示面板100还包括第一堤坝8和第二堤坝9。
其中，第一堤坝8设置在所述平坦层3远离所述基板1的一侧，且至少部分所述导电走线设41置在所述第一堤坝8和所述平坦层3之间。
其中，第二堤坝9设置在所述平坦层3远离所述基板1的一侧，且位于所述第一堤坝8远离所述显示区101的一侧，其中，至少部分所述导电走线41设置在所述第一堤坝8和所述平坦层3之间。
如图3所示，显示面板100还包括多个发光单元10。发光单元10一一对应设置于所述像素定义层5的像素开口内。
如图3所示，发光功能层6包括第一发光功能层61和第二发光功能层62。
其中，第一发光功能层61设置于所述发光单元10与所述第一电极42之间，且延伸覆盖于所述像素定义层5远离所述基板1的一侧的表面上。具体的，第一发光功能层61包括空穴注入层、空穴传输层、电子阻挡层等膜层结构。
其中，第二发光功能层62设置于所述发光单元10远离所述基板1的一侧，且延伸覆盖于所述第一发光功能层61上。具体的，第二发光功能层62包括电子传输层、电子注入层、空穴阻挡层等膜层结构。
其中，所述显示面板100还包括：封装层（图未示），设置在所述第二导电层7远离所述基板1的一侧，所述封装层包括依次叠设的第一无机封装子层、有机封装子层、第二无机封装子层；所述第一无机封装子层与所述第一堤坝8和所述第二堤坝9之间的所述导电走线41的上表面直接接触。
如图4所示，本实施例还提供了本实施例的显示面板100的制备方法，包括以下步骤：S1，提供一基板1，在所述基板1上定义出显示区101和设置于所述显示区101至少一侧的非显示区102，非显示区102包括：依次逐渐靠近所述显示区101设置的第一走线子区1021、栅极驱动子区1022、第二走线子区1023；S2，在所述非显示区102内的所述基板1上制备驱动电路层2，所述驱动电路层2包括：设置于所述显示区101的像素驱动电路21、设置在所述第一走线子区1021的第一走线22、设置在所述栅极驱动子区1022的栅极驱动电路23、设置在所述第二走线子区1023的第二走线24，所述栅极驱动电路23与对应的所述像素驱动电路21电连接，所述第二走线24与对应的所述像素驱动电路21电连接；S3，在所述驱动电路层2远离所述基板1的一侧制备平坦层3；S4，在所述平坦层3远离所述基板1的一侧制备第一导电层4，所述第一导电层4包括：设置在所述非显示区102的导电走线41和设置在所述显示区101的第一电极42，所述第一电极42与对应的所述像素驱动电路21电连接，所述导电走线41与所述第一走线22电连接S5，在所述第一导电层4远离所述基板1的一侧制备像素定义层5，所述像素定义层5对应所述第一电极42设置有像素开口；S6，在所述像素定义层5远离所述基板1的一侧制备发光功能层6，所述发光功能层6覆盖所述显示区101且延伸至所述非显示区102，所述发光功能层6在所述非显示区102中的边界处于所述第二走线子区1023和所述显示区101之间；S7，在所述发光功能层6远离所述基板1的一侧制备第二导电层7，所述第二导电层7覆盖所述显示区101且延伸至所述非显示区102，并与所述导电走线41电连接。
本实施例中，采用同一工序制备形成导电走线41和第一电极42，在其他实施例中，也可以分开制备导电走线41和第一电极42。
如图5所示，步骤S6中，在进行窄边框设计时，由于不对发光功能层6的分布范围进行压缩，会导致发光功能层6覆盖于非显示区的平坦层3和导电走线41上，通过激光刻蚀工艺去除覆盖于非显示区102的导电走线41、非显示区102的平坦层3以及部分非显示区102的所述像素定义层5上的所述发光功能层6，使得发光功能层6在所述非显示区102中的边界处于所述第二走线24和所述显示区101之间，进而在窄边框设计时，避免发光功能层6覆盖于非显示区102的所述导电走线41上，避免非显示区102的导电走线41和第二导电层7之间出现电连接异常的现象。
在激光刻蚀去除发光功能层6时，受限于目前的激光刻蚀工艺的精度，部分所述导电走线41远离所述基板1一侧表面为粗糙面。至少部分所述导电走线41远离所述基板1一侧表面的粗糙度，大于所述第一电极42远离所述基板1的一侧表面的粗糙度。
在激光刻蚀去除发光功能层6时，受限于目前的激光刻蚀工艺的精度，位于所述导电走线41和所述像素定义层5之间的所述平坦层3的厚度，小于位于所述显示区101中所述平坦层3的厚度。
实施例2
如图6所示，本实施例包括了实施例1的大部分技术特征，本实施例与实施例1的区别在于：本实施例中，非显示区的像素定义层5在靠近所述非显示区102的一侧设有至少一个台阶结构51。其中，所述发光功能层6在所述非显示区102中的边界处于所述台阶结构51和所述显示区102之间。第二导电层7覆盖所述台阶结构51。其中，台阶结构51的形状包括直角、圆角中的至少一种。本实施例中，台阶结构51的形状为直角。具体的，本实施例中，在激光刻蚀去除发光功能层6之前，就在非显示区的像素定义层5在靠近所述非显示区102的一侧形成至少一个台阶结构51。在其他实施例中，可以在激光刻蚀去除发光功能层6的过程中，在非显示区102的像素定义层5在靠近所述非显示区102的一侧形成至少一个台阶结构51。
如图7所示，在进行窄边框设计时，由于不对发光功能层的分布范围进行压缩，会导致发光功能层6覆盖于非显示区102的平坦层3和导电走线41上，通过激光刻蚀工艺去除覆盖于非显示区102的导电走线41、非显示区102的平坦层3以及部分非显示区102的所述像素定义层5上的所述发光功能层6，使得发光功能层6在所述非显示区102中的边界处于所述第二走线24和所述显示区101之间，进而在窄边框设计时，避免发光功能层6覆盖于非显示区102的所述导电走线41上，避免非显示区102的导电走线41和第二导电层7之间出现电连接异常的现象。
以上对本申请所提供的一种显示面板及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。
Claims (20)
- 一种显示面板，包括：显示区和设置于所述显示区至少一侧的非显示区，所述非显示区包括：依次逐渐靠近所述显示区设置的第一走线子区、栅极驱动子区、第二走线子区；所述显示面板还包括：基板；驱动电路层，设置于所述基板的一侧；所述驱动电路层包括：设置于所述显示区的像素驱动电路、设置在所述第一走线子区的第一走线、设置在所述栅极驱动子区的栅极驱动电路、设置在所述第二走线子区的第二走线，所述栅极驱动电路与对应的所述像素驱动电路电连接，所述第二走线与对应的所述像素驱动电路电连接；平坦层，设置于所述驱动电路层远离所述基板的一侧；第一导电层，设置在所述平坦层远离所述基板的一侧，所述第一导电层包括：设置在所述非显示区的导电走线和设置在所述显示区的第一电极，所述第一电极与对应的所述像素驱动电路电连接，所述导电走线与所述第一走线电连接；像素定义层，设置于所述第一导电层远离所述基板的一侧，所述像素定义层对应所述第一电极设置有像素开口；发光功能层，设置于所述像素定义层远离所述基板的一侧，所述发光功能层覆盖所述显示区且延伸至所述非显示区，所述发光功能层在所述非显示区中的边界处于所述第二走线子区和所述显示区之间；以及第二导电层，设置于所述发光功能层远离所述基板的一侧，所述第二导电层覆盖所述显示区且延伸至所述非显示区，并与所述导电走线电连接。
- 根据权利要求1所述的显示面板，所述发光功能层在所述非显示区中的边界处于所述第二走线和所述显示区之间。
- 根据权利要求2所述的显示面板，所述导电走线与所述发光功能层之间间隔设置，所述第二导电层还与位于所述导电走线与所述发光功能层之间的平坦层的至少部分上表面直接接触。
- 根据权利要求3所述的显示面板，至少部分所述导电走线远离所述基板一侧表面的粗糙度，大于所述第一电极远离所述基板一侧表面的粗糙度。
- 根据权利要求3所述的显示面板，位于所述导电走线和所述像素定义层之间的所述平坦层的厚度，小于位于所述显示区中所述平坦层的厚度。
- 根据权利要求2所述的显示面板，所述像素定义层在靠近所述非显示区的一侧具有台阶结构，所述发光功能层在所述非显示区中的边界处于所述台阶结构和所述显示区之间。
- 根据权利要求6所述的显示面板，所述第二导电层覆盖所述台阶结构。
- 根据权利要求1所述的显示面板，所述显示面板还包括：第一堤坝，设置在所述平坦层远离所述基板的一侧，且至少部分所述导电走线设置在所述第一堤坝和所述平坦层之间；第二堤坝，设置在所述平坦层远离所述基板的一侧，且位于所述第一堤坝远离所述显示区的一侧，其中，至少部分所述导电走线设置在所述第一堤坝和所述平坦层之间。
- 根据权利要求8所述的显示面板，所述显示面板还包括：封装层，设置在所述第二导电层远离所述基板的一侧，所述封装层包括依次叠设的第一无机封装子层、有机封装子层、第二无机封装子层。
- 根据权利要求9所述的显示面板，所述第一无机封装子层与所述第一堤坝和所述第二堤坝之间的所述导电走线的上表面直接接触。
- 一种显示装置，包括显示面板，所述显示面板包括：显示区和设置于所述显示区至少一侧的非显示区，所述非显示区包括：依次逐渐靠近所述显示区设置的第一走线子区、栅极驱动子区、第二走线子区；所述显示面板还包括：基板；驱动电路层，设置于所述基板的一侧；所述驱动电路层包括：设置于所述显示区的像素驱动电路、设置在所述第一走线子区的第一走线、设置在所述栅极驱动子区的栅极驱动电路、设置在所述第二走线子区的第二走线，所述栅极驱动电路与对应的所述像素驱动电路电连接，所述第二走线与对应的所述像素驱动电路电连接；平坦层，设置于所述驱动电路层远离所述基板的一侧；第一导电层，设置在所述平坦层远离所述基板的一侧，所述第一导电层包括：设置在所述非显示区的导电走线和设置在所述显示区的第一电极，所述第一电极与对应的所述像素驱动电路电连接，所述导电走线与所述第一走线电连接；像素定义层，设置于所述第一导电层远离所述基板的一侧，所述像素定义层对应所述第一电极设置有像素开口；发光功能层，设置于所述像素定义层远离所述基板的一侧，所述发光功能层覆盖所述显示区且延伸至所述非显示区，所述发光功能层在所述非显示区中的边界处于所述第二走线子区和所述显示区之间；以及第二导电层，设置于所述发光功能层远离所述基板的一侧，所述第二导电层覆盖所述显示区且延伸至所述非显示区，并与所述导电走线电连接。
- 根据权利要求11所述的显示装置，所述发光功能层在所述非显示区中的边界处于所述第二走线和所述显示区之间。
- 根据权利要求12所述的显示装置，所述导电走线与所述发光功能层之间间隔设置，所述第二导电层还与位于所述导电走线与所述发光功能层之间的平坦层的至少部分上表面直接接触。
- 根据权利要求13所述的显示装置，至少部分所述导电走线远离所述基板一侧表面的粗糙度，大于所述第一电极远离所述基板一侧表面的粗糙度。
- 根据权利要求13所述的显示装置，位于所述导电走线和所述像素定义层之间的所述平坦层的厚度，小于位于所述显示区中所述平坦层的厚度。
- 根据权利要求12所述的显示装置，所述像素定义层在靠近所述非显示区的一侧具有台阶结构，所述发光功能层在所述非显示区中的边界处于所述台阶结构和所述显示区之间。
- 根据权利要求16所述的显示装置，所述第二导电层覆盖所述台阶结构。
- 根据权利要求11所述的显示装置，所述显示面板还包括：第一堤坝，设置在所述平坦层远离所述基板的一侧，且至少部分所述导电走线设置在所述第一堤坝和所述平坦层之间；第二堤坝，设置在所述平坦层远离所述基板的一侧，且位于所述第一堤坝远离所述显示区的一侧，其中，至少部分所述导电走线设置在所述第一堤坝和所述平坦层之间。
- 根据权利要求18所述的显示装置，所述显示面板还包括：封装层，设置在所述第二导电层远离所述基板的一侧，所述封装层包括依次叠设的第一无机封装子层、有机封装子层、第二无机封装子层。
- 根据权利要求19所述的显示装置，所述第一无机封装子层与所述第一堤坝和所述第二堤坝之间的所述导电走线的上表面直接接触。
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