WO2024103252A1

WO2024103252A1 - Nitride-based semiconductor ic chip and method for manufacturing the same

Info

Publication number: WO2024103252A1
Application number: PCT/CN2022/131946
Authority: WO
Inventors: Hui Yan; Sichao LI
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-11-15
Filing date: 2022-11-15
Publication date: 2024-05-23
Also published as: CN115997287A; CN115997287B

Abstract

The present disclosure provides a nitride-based semiconductor integrated circuit (IC) chip including at least one transistor and a built-in bypass diode configured for bypassing reverse current flowing through the transistor. The built-in bypass diode includes a n-type doped region electrically connected to the drain electrode of the transistor and a p-type doped region electrically connected to the source electrode of the transistor. The built-in bypass diode can function as a source-to-drain body diode to realize low turn-on voltage drop in reverse conduction. Therefore, the reverse current can be bypassed and the dead time losses can be reduced without increasing PCB area or causing extra parasitic effects.

Description

NITRIDE-BASED SEMICONDUCTOR IC CHIP AND METHOD FOR MANUFACTURING THE SAME

Field of the Invention:

The present invention generally relates to a nitride-based semiconductor integrated circuit (IC) chip. More specifically, the present invention relates to a nitride-based semiconductor with capability of by-passing reverse current.

Background of the Invention:

Wide bandgap materials, such as gallium nitride (GaN) have been widely used for high frequency electrical energy conversion systems because of low power losses and fast switching transition. In comparison with silicon metal oxide semiconductor field effect transistor (MOSFET) , GaN high-electron-mobility transistor (HEMT) has a much better figure of merit and more promising performance for high-power and high-frequency applications. The nitride-based HEMT utilizes a heterojunction interface between two nitride-based materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Conventionally, in half-bridge rectifier circuit of power converter, there are high-side (HS) and low-side (LS) power transistors, which are switched between on and off states alternatively as shown in FIGS. 1A and 1C. To avoid direct conduction between power source and ground, a deadtime state is implemented during state transition, in which both HS and LS transistors are turned off as shown in FIG. 1B. During this deadtime state, a current is induced by energy stored in the inductor and passes through the LS transistor from source to drain, that is the LS transistor is in reverse conduction. Unlike Si MOS transistor which typically has a body diode with turn-on voltage drop of around 0.7V, GaN lateral HEMT has no body diode. Therefore, the reverse current has to flow through the 2DEG channel in GaN HEMT, which has a voltage drop much high than that of body diode in the case of Si MOS transistor. As a result, power dissipation due to reverse conduction (or so-called dead-time loss) is much higher for GaN HEMT than Si MOS transistor. One approach to address this issue is to add an antiparallel diode with the GaN FET to conduct the reverse current. However, such approach not only require greater printed circuit board (PCB) area but also add output capacitance and increase switching losses.

Summary of the Invention:

In accordance with a first aspect of the present disclosure, a nitride-based semiconductor integrated circuit chip including at least one transistor and a built-in bypass diode configured for bypassing reverse current flowing through the transistor is provided. The transistor is formed on a stacked semiconductor structure including: a substrate; a first nitride-based semiconductor layer disposed above the epitaxial body layer; and a second nitride-based semiconductor layer disposed above the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer such that a two-dimensional electron gas (2DEG) layer is formed adjacent to a heterojunction between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer. The transistor includes at least one pair of drain electrode and source electrode disposed above the second nitride-based semiconductor layer; and at least one gate structure disposed between the at least one pair of drain electrode and source electrode. The built-in bypass diode includes a n-type doped region electrically connected to the drain electrode of the transistor and a p-type doped region electrically connected to the source electrode of the transistor.

In accordance with a second aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor integrated circuit chip is provided. The method comprises: providing a main substrate; disposing a first nitride-based semiconductor layer above the epitaxial body layer; disposing a second nitride-based semiconductor layer on the first nitride-based semiconductor layer, the second nitride-based semiconductor layer having a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The method further comprises constructing one or more transistors by: forming one or more gate structures and one or more source/drain electrodes above the second nitride-based semiconductor layer, wherein each of the transistors includes at least one gate structure and at least one pair of source/drain electrodes. The method further comprises constructing one or more bypass diodes corresponding to the one or more transistors respectively, wherein each of the bypass diode includes a n-type doped region electrically connected to a drain electrode of a corresponding transistor and a p-type doped region electrically connected to a source electrode of the corresponding transistor.

The built-in bypass diode can function as a source-to-drain body diode to realize low turn-on voltage drop in reverse conduction. Therefore, the reverse current can be bypassed and the dead time losses can be reduced without increasing PCB area or causing extra parasitic effects.

Brief Description of the Drawings:

Aspects of the present disclosure may be readily understood from the following detailed description with reference to the accompanying figures. The illustrations may not necessarily be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Common reference numerals may be used throughout the drawings and the detailed description to indicate the same or similar components.

FIGS. 1A to 1C depict operation mechanism of a half-bridge rectifier circuit of a conventional power converter;

FIG. 2 depicts a simplified cross-sectional view of a nitride-based semiconductor integrated circuit chip according to some embodiments of the present invention;

FIGS. 3A-3G depict different stages of a method for manufacturing a semiconductor chip according to the present invention;

FIG. 4 depicts a simplified cross-sectional view of a nitride-based semiconductor integrated circuit chip according to some other embodiments of the present invention; and

FIGS. 5A-5F depict different stages of a method for manufacturing a semiconductor chip according to the present invention.

Detailed Description:

In the following description, preferred examples of the present disclosure will be set forth as embodiments which are to be regarded as illustrative rather than restrictive. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 2 depicts a simplified cross-sectional view of a nitride-based semiconductor integrated circuit chip 100 according to various embodiments of the present invention.

Referring to FIG. 2, the semiconductor chip 100 may include one or more transistors. The semiconductor chip 100 may include a substrate 102. The semiconductor chip 100 may include an epitaxial body layer 108 disposed over the substrate 102. In some embodiments, the epitaxial body layer 108 and the substrate 102 may be formed of same material.

The substrate 102 may be a semiconductor substrate. Exemplary materials of the substrate 102 and the epitaxial body layer 108 may include, for example but are not limited to, Si, p-doped Si, n-doped Si, SiC, GaN, Sapphire, or other suitable semiconductor materials.

The semiconductor chip 100 may further include a first nitride-based semiconductor layer 104 disposed above the epitaxial body layer 108. The semiconductor chip 100 may further include a second nitride-based semiconductor layer 106 disposed on the first nitride-based semiconductor layer 104. In some embodiments, the second nitride-based semiconductor layer 106 may have a bandgap greater than a bandgap of the first nitride-based semiconductor layer 104.

Exemplary materials of the nitride-based

semiconductor layers

104 and 106 are selected such that the nitride-based semiconductor layer 106 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 104, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 104 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 106 may be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based

semiconductor layers

104 and 106 may serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor chip is available to include one or more GaN-based high-electron-mobility transistors (HEMT) .

The exemplary materials of the nitride-based semiconductor layer 104 may include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1. The exemplary structures of the nitride-based semiconductor layer 104 may include, for example but are not limited to, multilayered structure, superlattice structure and composition-gradient structures.

The exemplary materials of the nitride-based semiconductor layer 106 may include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

In some embodiments, the semiconductor chip 100 may further include a buffer layer and a nucleation layer (not illustrated) , or a combination thereof. The buffer layer and the nucleation layer may be disposed between the epitaxial body layer 108 and the nitride-based semiconductor layer 104. The buffer layer and the nucleation layer may be configured to reduce lattice and thermal mismatches between the epitaxial body layer 108 and the nitride-based semiconductor layer 104, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound may include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer may further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof. The exemplary material of the nucleation layer may include, for example but is not limited to AlN or any of its alloys.

Each of the transistors may include at least one gate structure 110 and at least one pair of source/drain electrodes 116 disposed on/over/above the second nitride-based semiconductor layer 106. Each of the S/D electrodes 116 may serve as a source electrode or a drain electrode, depending on the device design. The S/D electrodes 116 may be located at two opposite sides of the corresponding gate structure 110 although other configurations may be used, particularly when plural source, drain, or gate electrodes are employed in the device. Each of the gate structure 110 may be arranged such that each of the gate structure 110 is located between at least two of the S/D electrodes 116.

In the exemplary illustration, for each of the transistors, the adjacent S/D electrodes 116 are symmetrical about the gate structure 110 therebetween. In some embodiments, the adjacent S/D electrodes 116 may be optionally asymmetrical about the gate structure 110 therebetween. That is, one of the S/D electrodes 116 may be closer to the gate structure 110 than another one of the S/D electrodes 116.

In some embodiments, each of the gate structures 110 may include an optional gate semiconductor layer and a gate metal layer. The gate semiconductor layer and the gate metal layer are stacked on the nitride-based semiconductor layer 106. The gate semiconductor layer is between the nitride-based semiconductor layer 106 and the gate metal layer. The gate semiconductor layer and the gate metal layer may form a Schottky barrier. In some embodiments, the transistor may further include an optional dielectric layer (not illustrated) between the p-type doped III-V compound semiconductor layer and the gate metal layer.

Specifically, the gate semiconductor layer may be a p-type doped III-V compound semiconductor layer. The p-type doped III-V compound semiconductor layer may create at least one p-n junction with the nitride-based semiconductor layer 106 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding gate structure 110 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked. Due to such mechanism, the transistor may have a normally-off characteristic for forming enhancement mode devices, which are in a normally-off state when their gate electrodes are at approximately zero bias. In other words, when no voltage is applied to the gate electrodes or a voltage applied to the gate electrodes is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate structures 110) , the zone of the 2DEG region below the gate structures 110 is kept blocked, and thus no current flows therethrough. Moreover, by providing the p-type doped III-V compound semiconductor layers, gate leakage current is reduced and an increase in the threshold voltage during the off-state is achieved.

In some embodiments, the p-type doped III-V compound semiconductor layers may be omitted, such that the transistor is a depletion-mode device, which means the transistor is in a normally-on state at zero gate-source voltage.

The exemplary materials of the p-type doped III-V compound semiconductor layers may include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.

In some embodiments, the gate electrodes may include metals or metal compounds. The gate electrodes may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds may include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the exemplary materials of the gate electrodes may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof.

In some embodiments, the optional dielectric layer may be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials may include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

In some embodiments, the S/D electrodes 116 may include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the S/D electrodes 116 may include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The S/D electrodes 116 may be a single layer, or plural layers of the same or different composition. In some embodiments, the S/D electrodes 116 may form ohmic contacts with the nitride-based semiconductor layer 106. The ohmic contact may be achieved by applying Ti, Al, or other suitable materials to the S/D electrodes 116. In some embodiments, each of the S/D electrodes 116 is formed by at least one conformal layer and a conductive filling. The conformal layer may wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling may include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The semiconductor chip 100 may further include one or more diode structures 150. Each diode structure 150 may include a first doped region 151 formed in the substrate 102 and a second doped region 152 formed in the epitaxial body layer 108. In some embodiments, the second doped region 152 may have a doping polarity opposite to a doping polarity of the first doped region 151.

In some embodiments, the first doped region 151 may be doped with n-type dopants and electrically connected to a drain electrode D of the transistor; the second doped region may be doped with p-type dopants and electrically connected to a source electrode S of the transistor.

The exemplary materials of the n-type dopants may be any Group V materials including, for example but are not limited to, phosphorus, antimony, and arsenic. The exemplary materials of the p-type dopants may be any Group III materials including, for example but are not limited to, boron, indium, gallium, and aluminum.

The first doped region 151 may be electrically connected to the drain electrode of the transistor through a first conductive via 181 extending from the first doped region 151 to a top surface of the second nitride-based semiconductor layer 106. The second doped region 152 may be electrically connected to the source electrode of the transistor through a second conductive via 182 extending from the second doped region 152 to a top surface of the second nitride-based semiconductor layer 106. As such, the diode structure 150 can function as a built-in bypass diode 150 for bypassing a reverse current) flowing from the source to the drain of the transistor.

Different stages of a method for manufacturing the semiconductor chip 100 according to the present invention are shown in FIGS. 3A-3G and described below. In the following, deposition techniques may include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes. The process for forming the passivation layers serving as a planarization layer generally includes a chemical mechanical polish (CMP) process. The process for forming the conductive vias generally includes forming vias in a passivation layer and filling the vias with conductive materials. The process for forming the conductive traces generally includes photolithography, exposure and development, etching, other suitable processes, or combinations thereof.

Referring to FIG. 3A, a substrate 102 (with typical thickness about 0.7 to 1.2 mm) is provided. The substrate 102 may be a p-doped Si substrate.

Referring to FIG. 3B, a doped region 151 is implanted in a surface of the substrate 102. The doped region 151 may be formed by performing a Si oxidation on substrate 102, developing a photo-resist pattern definition over substrate 102 using photo lithography, exposing substrate 102 to a p-type dopant, such as high energy boron atoms, using an implanter, stripping away the remaining photo-resist, annealing the wafer at high temperatures (e.g., 1100℃. ) for an appropriate duration (e.g., 3 hours) , and then stripping any surface oxide by immersion in hydrogen-fluoride containing acid.

Referring to FIG. 3C, an epitaxial body layer 108 may be formed above the substrate 102 using nucleation and growth processes. The epitaxial body layer 108 may be composed of one or more sublayers of Si materials and may have a thickness in a range of about 2 μm to about 7 μm.

Referring to FIG. 3D, a doped region 152 is implanted in the epitaxial body layer 108 and adjacent to the doped region 151. The process for forming the doped region 152 is similar to that for forming the doped region 151 except for that n-type dopants, such as high energy phosphorous atoms are used.

Referring to FIG. 3E. Two nitride-based semiconductor layers 104 and 106 may then be formed on the epitaxial body layer 108 using the above-mentioned deposition techniques. The nitride-based semiconductor layer 104 serves as a primary current channel and the nitride-based semiconductor layer 106 serves as a barrier layer. As a result, A 2DEG region is formed adjacent to a heterojunction interface between the nitride-based semiconductor layer 104 and the nitride-based semiconductor layer 106. Formation of nitride-based semiconductor layers 104 and 106 may include depositing a layer of GaN or InGaN material typically about 0.01 to about 0.5 μm in thickness to form current conducting region, and depositing a layer of material composed of AlGaN where the Al fraction (which is the content of Al such that Al fraction plus Ga fraction equals 1) is in a range of about 0.1 to about 1.0 and the thickness is in a range between about 0.01 and about 0.03 μm to form barrier layer.

One or more gate structure 110 and S/D electrodes 116 are then formed over the nitride-based semiconductor layer 106. Gate structure 110 may be formed, for example, by depositing p-type GaN material on a surface of nitride-based semiconductor layer 106, etching the gate structure 110 from the p-type GaN material, and forming a refractory metal contact such as tantalum (Ta) , titanium (Ti) , titanium nitride (TiN) , tungsten (W) , or tungsten silicide (WSi ₂) over the GaN material. It should be understood that other known methods and materials for providing a gate structure 110 may also be used. S/D electrodes 116 may be formed from any known ohmic contact metals, such as Ti and/or Al, along with a capping metal such as Ni, Au, Ti or TiN. The metal and gate layer are each preferably about 0.01 to about 1.0 μm in thickness, and then annealed at high temperature, such as 800℃ for 60 seconds.

Referring to FIG. 3F. A conductive via 181 are then formed to extend from the nitride-based semiconductor layer 106 to the doped region 152 in the epitaxial body layer 108. Openings may be fabricated by covering nitride-based semiconductor layer 106 with SiO ₂ and a photo-resist everywhere except at the site of the via 181, and then exposing the covered device to a high energy plasma in an etch chamber. The high energy plasma typically contains chlorine-based gases, such as BCl ₃ or Cl ₂, and is generated through high frequency oscillating fields produced within the etch chamber. After etching through from the nitride-based semiconductor layer 106 to the doped region 152, the photo-resist is stripped off using chemical strippers, oxygen plasma, or combinations of these techniques. TiN and Al may be deposited into the openings to form the conductive via 181, with the TiN material forming an outer layer along the walls of openings with a thickness in a range of about

and the Al material forming the interior of via 181 having a thickness in a range of about 1-5 um. The TiN outer layer promotes adhesion of an Al material.

Referring to FIG. 3G. A conductive vias 182 are then formed to extend from the nitride-based semiconductor layer 106 to the doped region 151. The process for forming vias 182 is similar to that for forming via 181 except for that the opens are etched through from the nitride-based semiconductor layer 106 to the doped region 151 in the substrate 102.

Although it is demonstrated in this embodiment that conductive via 181 is formed before conductive vias 182, it should be understood that conductive vias 182 may also be formed before conductive via 181, depending on the actual fabrication procedures.

It should also be understood that passivation layers and routing (conductive) layers may then be deposited and etched to form connections between the conductive vias, gate structures and electrodes with external circuits.

FIG. 4 depicts a simplified cross-sectional view of a nitride-based semiconductor integrated circuit chip 200 according to various embodiments of the present invention.

Referring to FIG. 4, the semiconductor chip 200 may include one or more transistors. The semiconductor chip 200 may include a main substrate 202. The selection of materials for main substrate 202 is similar to that for substrate 102 and will not be further described in details.

The semiconductor chip 200 may further include a first nitride-based semiconductor layer 204 disposed above the main substrate 202. The semiconductor chip 200 may further include a second nitride-based semiconductor layer 206 disposed on the first nitride-based semiconductor layer 204. In some embodiments, the second nitride-based semiconductor layer 206 may have a bandgap greater than a bandgap of the first nitride-based semiconductor layer 204. The selection of materials for nitride-based semiconductor layers 204 and 206 are similar to that for nitride-based semiconductor layers 104 and 106 and will not be further described in details.

The semiconductor chip 200 may further include one or more isolation layers 230 positioned on the second nitride-based semiconductor layer. The isolation layer 230 layer may be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials may include, for example but are not limited to, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof. In some embodiments, the isolation layer 230 may be made of silicon nitride (SiN) .

In some embodiments, the semiconductor chip 200 may further include one or more bonding layers (not shown) on the isolation layers 230. Each of the bonding layers may be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials may include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof. In some embodiments, the bonding layer may be made of silicon dioxide (SiO2) .

The semiconductor chip 202 may further include one or more diode body layers 250 deposited on the one or more isolation structures 230 respectively. Each diode body layer 250 may include a first doped region 251 having a first doping polarity. The diode body layer 250 may further include a second doped region 252 having a second doping polarity opposite to the first doping polarity. In some embodiments, the first doped region 251 is doped with n-type dopants and the second doped region 252 is doped with p-type dopants.

The semiconductor chip 202 may further include one or more gate structures 210 and one or more source/drain electrodes 216 disposed above the second nitride-based semiconductor layer 206, wherein each of the transistors includes at least one gate structure and at least one pair of source/drain electrodes.

In some embodiments, the n-type doped region 251 may be positioned adjacent to a drain electrode D of a corresponding transistor and electrically connected to the drain electrode D. The p-type doped region 252 may be positioned adjacent to a source electrode S of the corresponding transistor and electrically connected to the source electrode S.

Different stages of a method for manufacturing the semiconductor chip 200 according to the present invention are shown in FIGS. 5A-5F and described below. Some stages are similar to the method for manufacturing the semiconductor chip 100 and will not be discussed in details.

Referring to FIG. 5A, a Si main substrate 202 is provided. Two nitride-based semiconductor layers 204 and 206 may then be formed on the main substrate 202 using the above-mentioned deposition techniques such that a 2DEG region is formed adjacent to a heterojunction interface between the nitride-based semiconductor layers 204 and 206.

An isolation layer 230 may then be formed on the second nitride-based semiconductor layer 206. The isolation layer 230 may be formed, for example, by deposing a layer of silicon nitride (SiN) film on top of the second nitride-based semiconductor layer 206. The isolation layer may then be pre-processed to form a pre-processed layer 271. The pre-processed layer 271may be formed, for example, by depositing a silicon dioxide (SiO ₂) layer on top of the isolation layer 231.

Referring to FIG. 5B. A diode substrate 502 is prepared. The diode substrate 502 may be a Si substrate. The diode substrate 502 may be pre-processed to form a pre-processed layer 272. The pre-processed layer 272 may be made of same material as the first pre-processed layer 271. The second pre-processed layer 272 may be formed, for example, by depositing a SiO ₂ layer on the surface of the diode substrate 502.

Referring to FIG. 5C. The diode substrate 502 may then be attached to the isolation layer 230 on the main substrate 202 to form the diode body layer 250. The attachment of the diode substrate 502 to the isolation layer 230 may be performed, for example, by direct bonding of the

pre-processed layers

271 and 272. In some embodiment, the direct bonding process may include aligning and contacting the

pre-processed layers

271 and 272, and then annealing the contacted surfaces at elevated temperatures.

Referring to FIG. 5D. A first section of the diode body layer 250 is doped with n-type dopants to form a n-type doped region 251. The process for forming the n-type doped regions 251 is similar to that for forming the n-type doped region 151 and will not be further described in details.

Referring to FIG. 5E. A second section of the diode body layer 250 is doped with p-type dopants to form a p-type doped region 252. The process for forming the p-type doped regions 252 is similar to that for forming the p-type doped region 152 and will not be further described in details.

Referring to FIG. 5F. One or more gate structures 210 and S/D electrodes 216 are then formed over the nitride-based semiconductor layer 206. The process for forming the gate structures 210 is similar to that for forming the gate structures 110 and will not be further described in details. The process for forming the S/D electrodes 216 is similar to that for forming the S/D electrodes 116 and will not be further described in details.

The n-type doped region 251 is then electrically connected to the drain electrode of the transistor. And the p-type doped region 252 is then electrically connected to the source electrode of the transistor.

Although it is demonstrated in this embodiment that the n-type doped region 251 is formed before the p-type doped region 252, it should be understood that the p-type doped region 252 may also be formed before n-type doped region 251, depending on the actual fabrication procedures.

It should also be understood that passivation layers and routing (conductive) layers may then be deposited and etched to form electrical connections among the doped regions, gate structures and electrodes as well as with external circuits.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations. While the apparatuses disclosed herein have been described with reference to particular structures, shapes, materials, composition of matter and relationships…etc., these descriptions and illustrations are not limiting. Modifications may be made to adapt a particular situation to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto.

Claims

A nitride-based semiconductor integrated circuit chip including at least one transistor and a built-in bypass diode configured for bypassing reverse current flowing through the transistor,

wherein the transistor is formed on a stacked semiconductor structure including:

a substrate;

a first nitride-based semiconductor layer disposed above the substrate; and

a second nitride-based semiconductor layer disposed above the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer such that a two-dimensional electron gas (2DEG) layer is formed adjacent to a heterojunction between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer;

wherein the transistor includes:

at least one pair of drain electrode and source electrode disposed above the second nitride-based semiconductor layer; and

at least one gate structure disposed between the at least one pair of drain electrode and source electrode; and

wherein the bypass diode includes a n-type doped region electrically connected to the drain electrode of the transistor and a p-type doped region electrically connected to the source electrode of the transistor.
The nitride-based semiconductor integrated circuit chip according to claim 1, wherein

the stacked semiconductor structure further includes an epitaxial body layer disposed between the substrate and the first nitride-based semiconductor layer;

the n-type doped region of the bypass diode is formed in the substrate and the p-type doped region is formed in the epitaxial body layer.
The nitride-based semiconductor integrated circuit chip according to claim 2, wherein the n-type doped region is electrically connected to the drain electrode through a first conductive vias extending from the n-type doped region to a top surface of the second nitride-based semiconductor layer.
The nitride-based semiconductor integrated circuit chip according to claim 3, wherein the p-type doped region is electrically connected to the source electrode through a second conductive vias extending from the p-type doped region to a top surface of the second nitride-based semiconductor layer.
The nitride-based semiconductor integrated circuit chip according to any one of claims 2 to 4, wherein, the substrate and the epitaxial body layer are made of same material.
The nitride-based semiconductor integrated circuit chip according to claim 5, wherein, the substrate and the epitaxial body layer are made of silicon.
The nitride-based semiconductor integrated circuit chip according to claim 6, wherein the transistor is a nitride-based high-electron-mobility transistor (HEMT) .
The nitride-based semiconductor integrated circuit chip according to claim 7, wherein the nitride-based HEMT is a AlGaN/GaN HEMT.
The nitride-based semiconductor integrated circuit chip according to claim 8, wherein the AlGaN/GaN HEMT is an enhancement-mode AlGaN/GaN HEMT.
The nitride-based semiconductor integrated circuit chip according to claim 8, wherein the AlGaN/GaN HEMT is a depletion-mode AlGaN/GaN HEMT.
The nitride-based semiconductor integrated circuit chip according to claim 1, wherein the stacked semiconductor structure further includes:

an isolation layer deposited above the second nitride-based semiconductor layer; and

a diode body layer deposited above the isolation layer; and

the n-type doped region and the p-type doped region of the bypass diode are formed in the diode body layer.
The nitride-based semiconductor integrated circuit chip according to claim 11, wherein, the substrate and the diode body layer are made of same material.
The nitride-based semiconductor integrated circuit chip according to claim 12, wherein, the substrate and the diode body layer are made of silicon.
The nitride-based semiconductor integrated circuit chip according to claim 13, wherein the transistor is a nitride-based high-electron-mobility transistor (HEMT) .
The nitride-based semiconductor integrated circuit chip according to claim 14, wherein the nitride-based HEMT is a AlGaN/GaN HEMT.
The nitride-based semiconductor integrated circuit chip according to claim 15, wherein the AlGaN/GaN HEMT is an enhancement-mode AlGaN/GaN HEMT.
The nitride-based semiconductor integrated circuit chip according to claim 15, wherein the AlGaN/GaN HEMT is a depletion-mode AlGaN/GaN HEMT.
A method for manufacturing a nitride-based semiconductor integrated circuit chip, comprising:

providing a main substrate;

disposing a first nitride-based semiconductor layer above the epitaxial body layer;

disposing a second nitride-based semiconductor layer on the first nitride-based semiconductor layer, the second nitride-based semiconductor layer having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

constructing one or more transistors by: forming one or more gate structures and one or more source/drain electrodes above the second nitride-based semiconductor layer, wherein each of the transistors includes at least one gate structure and at least one pair of source/drain electrodes; and

constructing one or more bypass diodes corresponding to the one or more transistors respectively, wherein each of the bypass diode includes a n-type doped region electrically connected to a drain electrode of a corresponding transistor and a p-type doped region electrically connected to a source electrode of the corresponding transistor.
The method according to claim 18, further comprising:

forming the one or more n-type doped regions in a surface of the main substrate;

disposing an epitaxial body layer over the main substrate; and

forming the one or more p-type doped regions in the epitaxial body layer;
The method according to claim 19, further comprising electrically connecting each of the n-type doped regions to a drain electrode of a corresponding transistor by forming a first conductive vias extending from the n-type doped region to a top surface of the second nitride-based semiconductor layer.
The method according to claim 13, further comprising electrically connecting each of the p-type doped regions to a source electrode of a corresponding transistor by forming a second conductive vias extending from the p-type doped region to a top surface of the second nitride-based semiconductor layer.
The method according to claim 18, further comprising:

disposing one or more isolation layers above the second nitride-based semiconductor layer;

disposing one or more diode body layers above the one or more isolation layers respectively;

forming a n-type doped regions in each of one or more diode body layers; and

forming a p-type doped regions in each of one or more diode body layers.
The method according to claim 22, further comprising electrically connecting each of the n-type doped regions to a drain electrode of a corresponding transistor.
The method according to claim 23, further comprising electrically connecting each of the p-type doped regions to a source electrode of a corresponding transistor.
The method according to claim 22, wherein the one or more diode body layers are formed by:

pre-processing surfaces of the one or more isolation layers to form one or more first pre-processed layers;

pre-processing surface of one or more diode substrates to form one or more second pre-processed layers; and

attaching the one or more diode substrates on the one or more isolation layer respectively by directly bonding each of the one or more first pre-processed layer to a corresponding second pre-processed layer.