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WO2024092863A1 - 连续时间带通Sigma-Delta调制器及电子设备 - Google Patents

连续时间带通Sigma-Delta调制器及电子设备 Download PDF

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Publication number
WO2024092863A1
WO2024092863A1 PCT/CN2022/130870 CN2022130870W WO2024092863A1 WO 2024092863 A1 WO2024092863 A1 WO 2024092863A1 CN 2022130870 W CN2022130870 W CN 2022130870W WO 2024092863 A1 WO2024092863 A1 WO 2024092863A1
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Prior art keywords
voltage
output
operational amplifier
resistor
feedback
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PCT/CN2022/130870
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English (en)
French (fr)
Inventor
罗永双
杨南
万贤杰
王友华
朱璨
付东兵
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重庆吉芯科技有限公司
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Publication of WO2024092863A1 publication Critical patent/WO2024092863A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators

Definitions

  • the present invention relates to the technical field of integrated circuits, and in particular to a continuous-time bandpass Sigma-Delta modulator and electronic equipment.
  • the continuous-time Sigma-Delta modulator has the characteristics of low power consumption and high speed, and also has its own anti-aliasing characteristics, which greatly reduces the design requirements for the anti-aliasing filter of the previous stage, and effectively reduces the chip area. These characteristics make the continuous-time Sigma-Delta modulator widely used. Among them, the bandpass continuous-time Sigma-Delta modulator can directly digitize the intermediate frequency signal while having the aforementioned characteristics, greatly simplifying the complexity of the receiver system.
  • the loop filter in the bandpass continuous-time Sigma-Delta modulator is usually composed of a resonator composed of an active RC integrator or a resonator composed of an inductor and capacitor.
  • the inductor-capacitor resonator is a passive device and is ideally only an energy storage device, there is no power consumption. At the same time, the inductor-capacitor resonator can achieve a higher quality factor and provide earlier gain, which makes its noise performance better than the resonator composed of an active RC integrator.
  • the existing continuous-time bandpass Sigma-Delta modulator technology based on the LC resonator has only one current signal as feedback of the modulator output for an LC second-order resonator.
  • the lack of a feedback degree of freedom makes it impossible to realize any bandpass Sigma-Delta modulator noise transfer function. This limits the selection of loop parameters in the design of the continuous-time bandpass Sigma-Delta modulator based on the LC resonator, which directly affects the performance of the entire modulator.
  • the purpose of the present invention is to provide a continuous-time bandpass Sigma-Delta modulator based on an LC resonator, which adds a voltage feedback on the basis of current feedback to make up for the missing degree of freedom and solve the limitation of the missing degree of freedom on the system performance of the continuous-time bandpass Sigma-Delta modulator based on the LC resonator.
  • a continuous-time bandpass Sigma-Delta modulator comprising:
  • a transconductance operational amplifier receives an input voltage signal and converts the input voltage signal to obtain and output a current signal
  • a passive resonator as a loop filter, is connected to the output end of the transconductance operational amplifier, converts the current signal, obtains and outputs an intermediate voltage signal;
  • thermometer code connected to the output end of the passive resonator, sampling and quantizing the intermediate voltage signal to obtain and output a thermometer code
  • a current feedback module whose input end is connected to the output end of the sampling quantizer, whose output end is connected to the passive resonator, and provides a feedback current for the passive resonator under the control of the thermometer code;
  • a voltage feedback module whose input end is connected to the output end of the sampling quantizer and whose output end is connected to the passive resonator, provides a feedback voltage for the passive resonator under the control of the thermometer code.
  • the passive resonator includes a capacitor and an inductor, one end of the capacitor is connected to the output end of the transconductance operational amplifier, the other end of the capacitor is grounded, one end of the inductor is connected to the output end of the transconductance operational amplifier, the other end of the inductor is connected to the output end of the sampling quantizer via the voltage feedback module connected in series, and one end of the inductor is connected to the output end of the transconductance operational amplifier to output the intermediate voltage signal.
  • the thermometer code includes a four-bit thermometer code
  • the current feedback module includes a first current source, a second current source, a third current source, a fourth current source, a fifth current source, a first switch, a second switch, a third switch and a fourth switch
  • the working voltage is connected to ground after being connected in series with the first current source, the first switch and the second current source in sequence
  • the working voltage is also connected to ground after being connected in series with the first current source, the second switch and the third current source in sequence
  • the working voltage is also connected to ground after being connected in series with the first current source, the third switch and the fourth current source in sequence
  • the working voltage is also connected to ground after being connected in series with the first current source, the fourth switch and the fifth current source in sequence
  • the control end of the first switch is connected to the first bit of the four-bit thermometer code
  • the control end of the second switch is connected to the second bit of the four-bit thermometer code
  • the control end of the third switch is connected to the third bit of
  • the voltage feedback module includes an output voltage regulating unit, a voltage dividing unit and a selection output unit, the output voltage regulating unit outputs an adjustable initial voltage, the input end of the voltage dividing unit is connected to the output end of the output voltage regulating unit, the voltage dividing unit combines the ground, the working voltage and the initial voltage to perform voltage dividing processing to obtain and output multiple initial feedback voltages of different sizes, the multiple input ends of the selection output unit are connected to the multiple initial feedback voltages in a one-to-one correspondence, the control end of the selection output unit is connected to the thermometer code, under the control of the thermometer code, the selection output unit selects one of the multiple initial feedback voltages as the feedback voltage and outputs it, and the output end of the selection output unit is connected to an end of the inductor away from the transconductance operational amplifier.
  • the output voltage regulating unit includes N reference current sources, N digitally controlled switches, a first resistor, a first operational amplifier and an NMOS tube.
  • the N reference current sources and the N digitally controlled switches form N parallel current branches.
  • Each current branch includes a reference current source and a digitally controlled switch connected in series in sequence.
  • One end of each reference current source away from the digitally controlled switch is connected to the working voltage.
  • the control ends of the N digitally controlled switches are connected one-to-one with the N bits of the N-bit digital code.
  • One end of the N digitally controlled switches away from the reference current source is short-circuited and connected to one end of the first resistor. The other end of the first resistor is grounded.
  • the non-inverting input end of the first operational amplifier is connected to the common end of the N digitally controlled switches.
  • the inverting input end of the first operational amplifier is connected to the source of the NMOS tube.
  • the output end of the first operational amplifier is connected to the gate of the NMOS tube.
  • the source of the NMOS tube outputs the initial voltage.
  • N is an integer greater than or equal to 2.
  • the voltage dividing unit includes a second resistor and four third resistors
  • the working voltage is connected to the drain of the NMOS tube after passing through the first third resistor, the second third resistor, the third third resistor and the fourth third resistor connected in series in sequence
  • the source of the NMOS tube is grounded after passing through the second resistor connected in series
  • the first third resistor outputs an initial feedback voltage at one end close to the working voltage
  • the first third resistor and the second third resistor have a common end that outputs an initial feedback voltage
  • the second third resistor and the third resistor have a common end that outputs an initial feedback voltage
  • the third third resistor and the fourth third resistor have a common end that outputs an initial feedback voltage
  • the fourth third resistor has a common end that outputs an initial feedback voltage at one end close to the NMOS tube.
  • the selection output unit includes a data selector and a second operational amplifier, the five input terminals of the data selector are connected one-to-one with the five initial feedback voltages, the control terminal of the data selector is connected to the thermometer code, the output terminal of the data selector is connected to the non-inverting input terminal of the second operational amplifier, the inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier outputs the feedback voltage.
  • the voltage feedback module further includes an output common mode adjustment unit, an output terminal of the output common mode adjustment unit is connected to the voltage dividing unit, and the output common mode adjustment unit stably clamps the common mode value of the feedback voltage.
  • the output common-mode adjustment unit includes a third operational amplifier and a PMOS tube, the source of the PMOS tube is connected to the operating voltage, the gate of the PMOS tube is connected to the output end of the third operational amplifier, the inverting input end of the third operational amplifier is connected to the reference voltage, the non-inverting input end of the third operational amplifier is connected to the common end of the second third resistor and the third third resistor, and the drain of the PMOS tube is connected to an end of the first third resistor away from the second third resistor.
  • An electronic device comprises a continuous-time bandpass Sigma-Delta modulator as described in any one of the above items.
  • the continuous-time bandpass Sigma-Delta modulator and electronic device of the present invention have at least the following beneficial effects:
  • a continuous-time bandpass Sigma-Delta modulator is designed by combining a transconductance operational amplifier, a passive resonator, a sampling quantizer, a current feedback module and a voltage feedback module. Voltage feedback is added on the basis of conventional current feedback, which can realize current feedback and voltage feedback at the same time, and increases the feedback freedom.
  • the entire modulator can realize any bandpass Sigma-Delta modulator noise transfer function, which effectively solves the limitation on the performance of the continuous-time bandpass Sigma-Delta modulator system based on the inductor-capacitor resonator due to the lack of feedback freedom, and improves the performance of the modulator.
  • FIG. 1 is a block diagram showing a continuous-time bandpass Sigma-Delta modulator according to the present invention.
  • FIG. 2 is a circuit diagram of the current feedback module 4 in FIG. 1 .
  • FIG. 3 is a circuit diagram of the voltage feedback module 5 in FIG. 1 .
  • FIG. 4 shows a block diagram of a continuous-time bandpass Sigma-Delta modulator of a CRFB structure.
  • the inventors have found that in the existing continuous-time bandpass Sigma-Delta modulator technology based on the LC resonator, for an LC second-order resonator, the feedback of the modulator output is only a current signal based on the current feedback module.
  • the feedback freedom is small, resulting in the inability of the prior art to realize any bandpass Sigma-Delta modulator noise transfer function, which in turn limits the selection of loop parameters in the design of the continuous-time bandpass Sigma-Delta modulator based on the LC resonator, directly affecting the performance of the entire modulator.
  • the present invention proposes a continuous-time bandpass Sigma-Delta modulator, which comprises:
  • the transconductance operational amplifier 1 receives the input voltage signal u and converts the input voltage signal u to obtain and output a current signal I 0 ;
  • the passive resonator 2 as a loop filter, is connected to the output terminal of the transconductance operational amplifier 1, converts the current signal I0 , obtains and outputs the intermediate voltage signal x1;
  • the sampling quantizer 3 is connected to the output end of the passive resonator 2, samples and quantizes the intermediate voltage signal x1, obtains and outputs the thermometer code DN;
  • a current feedback module 4 whose input terminal is connected to the output terminal of the sampling quantizer 3 and whose output terminal is connected to the passive resonator 2, provides a feedback current I OUT for the passive resonator 2 under the control of the thermometer code DN;
  • the voltage feedback module 5 has an input terminal connected to the output terminal of the sampling quantizer 3 and an output terminal connected to the passive resonator 2 , and provides a feedback voltage V OUT for the passive resonator 2 under the control of the thermometer code DN.
  • the passive resonator 2 is an inductor-capacitor type resonator, which includes a capacitor C and an inductor L.
  • One end of the capacitor C is connected to the output end of the transconductance operational amplifier 1, and the other end of the capacitor C is grounded.
  • One end of the inductor L is connected to the output end of the transconductance operational amplifier 1, and the other end of the inductor L is connected to the output end of the sampling quantizer 3 after being connected in series with a voltage feedback module 5.
  • One end of the inductor L is connected to the output end of the transconductance operational amplifier 1 to output an intermediate voltage signal x1, and the intermediate voltage signal x1 is the voltage on the capacitor C.
  • the sampling quantizer 3 can be a 5-level parallel comparison type analog-to-digital converter, which samples and quantizes the intermediate voltage signal x1 on the passive resonator 2 at a sampling frequency fs, and obtains a 4-bit thermometer code DN by analog-to-digital conversion, namely IN ⁇ 0>, IN ⁇ 1>, IN ⁇ 2> and IN ⁇ 3> shown in FIG2, and the corresponding digital voltage is recorded as v.
  • the sampling quantizer 3 can also be an analog-to-digital converter with other structures and other bit numbers, which is not limited here.
  • the current feedback module 4 includes a first current source I1, a second current source I2, a third current source I3, a fourth current source I4, a fifth current source I5, a first switch K1, a second switch K2, a third switch K3 and a fourth switch K4.
  • the operating voltage VDD is connected to the ground via the first current source I1, the first switch K1 and the second current source I2 connected in series in sequence.
  • the operating voltage VDD is also connected to the ground via the first current source I1, the second switch K2 and the third current source I3 connected in series in sequence.
  • the operating voltage VDD is also connected to the ground via the first current source I1, the third switch K2 and the third current source I3 connected in series in sequence.
  • the operating voltage VDD is further connected to ground via the first current source I1, the fourth switch K4 and the fifth current source I5 which are connected in series in sequence.
  • the control end of the first switch K1 is connected to the first bit IN ⁇ 0> of the four-bit thermometer code DN
  • the control end of the second switch K2 is connected to the second bit IN ⁇ 1> of the four-bit thermometer code DN
  • the control end of the third switch K3 is connected to the third bit IN ⁇ 2> of the four-bit thermometer code DN
  • the control end of the fourth switch K4 is connected to the fourth bit IN ⁇ 3> of the four-bit thermometer code DN.
  • a common end of the first switch K1, the second switch K2, the third switch K3 and the fourth switch K4 outputs a feedback current I OUT
  • the feedback current I OUT is connected to the output end of the transconductance operational amplifier 1.
  • the output current of the first current source I1 is I 1
  • the output currents of the second current source I2, the third current source I3, the fourth current source I4, and the fifth current source I5 are equal, denoted as I 2
  • I 1 2I 2
  • the magnitude of the output feedback current I OUT can be adjusted by gating control of IN ⁇ 0>, IN ⁇ 1>, IN ⁇ 2>, and IN ⁇ 3>.
  • the output current magnitudes of the first current source I1, the second current source I2, the third current source I3, the fourth current source I4, and the fifth current source I5 can be arbitrarily set, and are not limited thereto.
  • the voltage feedback module 5 includes an output voltage regulating unit 51, a voltage dividing unit 52 and a selection output unit 53.
  • the output voltage regulating unit 51 outputs an adjustable initial voltage V0.
  • the input end of the voltage dividing unit 52 is connected to the output end of the output voltage regulating unit 51.
  • the voltage dividing unit 52 combines the ground, the working voltage VDD and the initial voltage V0 for voltage dividing processing to obtain and output multiple initial feedback voltages of different sizes, such as VF1 ⁇ VF5.
  • the multiple input ends of the selection output unit 53 are connected to the multiple initial feedback voltages in a one-to-one correspondence.
  • the control end of the selection output unit 53 is connected to the thermometer code DN.
  • the selection output unit 53 selects one of the multiple initial feedback voltages as the feedback voltage V OUT and outputs it.
  • the output end of the selection output unit 53 is connected to an end of the inductor L away from the transconductance operational amplifier 1.
  • the output voltage regulating unit 51 includes N reference current sources I 0 , N digitally controlled switches K 0 , a first resistor R 1 , a first operational amplifier A1 and an NMOS tube M1 .
  • the N reference current sources I 0 and the N digitally controlled switches K 0 form N parallel current branches.
  • Each current branch includes a reference current source I 0 and a digitally controlled switch K 0 connected in series in sequence.
  • One end of each reference current source I 0 away from the digitally controlled switch K 0 is connected to the working voltage VDD.
  • the control ends of the N digitally controlled switches K 0 are connected to the N bits of the N-bit digital code in a one-to-one correspondence, such as the 8-bit digital code shown in I_ADJ ⁇ 0:7> in the figure.
  • One end of the N digitally controlled switches K 0 away from the reference current source I 0 is short-circuited and connected to one end of the first resistor R 1 .
  • the other end of the first resistor R 1 is grounded.
  • the non-inverting input end of the first operational amplifier A1 is connected to the N digitally controlled switches K 0 , the inverting input terminal of the first operational amplifier A1 is connected to the source of the NMOS tube M1, the output terminal of the first operational amplifier A1 is connected to the gate of the NMOS tube M1, and the source of the NMOS tube M1 outputs an initial voltage V0, wherein N is an integer greater than or equal to 2.
  • the digital code used for the on-off control of the digital control switch K0 is 8-bit I_ADJ ⁇ 0:7>, corresponding to 8 current branches, and the value of N is 8; it should be noted that the digital code used for the on-off control of the digital control switch K0 is not limited to the 8-bit I_ADJ ⁇ 0:7> shown in Figure 1, and can also be a digital code of any other number of bits, which is specifically determined by the value of N and is not limited here.
  • the on-off of the N current branches in the output voltage regulating unit 51 is controlled by regulating the N-bit digital code to regulate the current flowing through the first resistor R1 , thereby regulating the voltage at the non-inverting input terminal of the first operational amplifier A1.
  • the first operational amplifier A1 combines with the NMOS tube M1 to follow and output the voltage at the non-inverting input terminal of the first operational amplifier A1, and an initial voltage V0 is obtained at the source of the NMOS tube M1.
  • the initial voltage V0 can be regulated by the N-bit digital code, and the least significant bit (LSB) or resolution of the voltage feedback module 5 can be reconfigured. Assuming that the current flowing through the first resistor R1 is n ⁇ I0 , and n is an integer from 0 to N, then one LSB of the voltage feedback module 5 can be expressed as:
  • the voltage dividing unit 52 includes a second resistor R 2 and four third resistors R 0 .
  • the working voltage VDD is connected to the drain of the NMOS tube M1 after passing through the first third resistor R 0 , the second third resistor R 0 , the third third resistor R 0 and the fourth third resistor R 0 which are connected in series in sequence.
  • the source of the NMOS tube M1 is grounded after passing through the second resistor R 2 which is connected in series.
  • the first third resistor R 0 outputs an initial feedback voltage VF1 at one end close to the working voltage VDD
  • the first third resistor R 0 and the second third resistor R 0 output an initial feedback voltage VF2 at a common end
  • the second third resistor R 0 and the third third resistor R 0 output an initial feedback voltage VF3 at a common end
  • the third third resistor R 0 and the fourth third resistor R 0 output an initial feedback voltage VF4 at a common end
  • the fourth third resistor R 0 outputs an initial feedback voltage VF5 at one end close to the NMOS tube M1.
  • the voltage divider unit 52 performs voltage division processing on the ground, the operating voltage VDD and the initial voltage V0 to obtain and output five initial feedback voltages VF1 to VF5 of different sizes; wherein, the number and resistance of the voltage divider resistors in the voltage divider unit 52 can be selected according to actual needs and are not limited here.
  • the five initial feedback voltages VF1 to VF5 in FIG3 just correspond to the 4-bit thermometer code DN.
  • the selection output unit 53 includes a data selector MUX and a second operational amplifier A2, the five input terminals of the data selector MUX are connected to the five initial feedback voltages VF1 to VF5 in one-to-one correspondence, the control terminal of the data selector MUX is connected to the thermometer code DN, the output terminal of the data selector MUX is connected to the non-inverting input terminal of the second operational amplifier A2, the inverting input terminal of the second operational amplifier A2 is connected to the output terminal of the second operational amplifier A2, and the output terminal of the second operational amplifier A2 outputs the feedback voltage V OUT .
  • the data selector MUX selects and outputs each input initial feedback voltage, and its control method is that, if there are i high levels in the input thermometer code DN, then the data selector MUX outputs the i-th initial feedback voltage; the initial feedback voltage is processed by the follower output of the second operational amplifier A2 to obtain the feedback voltage V OUT .
  • the voltage feedback module 5 further includes an output common mode adjustment unit 54 , the output terminal of the output common mode adjustment unit 54 is connected to the voltage divider unit 52 , and the output common mode adjustment unit 54 stably clamps the common mode value of the feedback voltage V OUT .
  • the output common-mode adjustment unit 54 includes a third operational amplifier A3 and a PMOS tube M2, the source of the PMOS tube M2 is connected to the working voltage VDD, the gate of the PMOS tube M2 is connected to the output end of the third operational amplifier A3, the inverting input end of the third operational amplifier A3 is connected to the reference voltage VREF, the non-inverting input end of the third operational amplifier A3 is connected to the common end of the second third resistor R 0 and the third third resistor R 0 , and the drain of the PMOS tube M2 is connected to an end of the first third resistor R 0 away from the second third resistor R 0 .
  • the voltage value of the initial feedback voltage VF3 is stabilized at the reference voltage VREF, and the initial feedback voltage VF3 is the middle voltage of the entire voltage divider unit 52 , thereby stably clamping the common mode value of the feedback voltage V OUT at VREF.
  • the continuous-time bandpass Sigma-Delta modulator shown in FIG1 is a cascade resonator feedback (CRFB) structure, and its working principle is as follows:
  • the loop filter in the continuous-time bandpass Sigma-Delta modulator is composed of an inductor-capacitor resonator. Unlike the active RC resonator, the two integral state quantities of the resonator are a voltage signal and a current signal, which are the voltage x 1 on the capacitor C and the current x 2 on the inductor L. Therefore, the state equation of the loop filter is:
  • K1 is the current amplification factor of the current feedback module 4
  • K2 is the voltage amplification factor of the voltage feedback module 5
  • y is the input of the sampling quantizer 3
  • v is the output of the sampling quantizer 3 .
  • FIG4 the general system block diagram of the continuous-time bandpass Sigma-Delta modulator of the cascade resonator feedback structure is shown in FIG4 , and its detailed structural parameters can be referred to the prior art, which will not be repeated here, and its sampling clock frequency is generally normalized to 1 Hz.
  • the Laplace transform of the modulator state equation of the cascade resonator feedback structure is as follows:
  • the continuous-time bandpass sigma-delta modulator based on the inductor-capacitor resonator of the present invention can realize any bandpass sigma-delta modulator noise transfer function.
  • a continuous-time bandpass Sigma-Delta modulator is designed by combining a transconductance operational amplifier, a passive resonator, a sampling quantizer, a current feedback module and a voltage feedback module.
  • Voltage feedback is added on the basis of conventional current feedback, and current feedback and voltage feedback can be realized simultaneously, thereby increasing the feedback freedom, so that the entire modulator can realize any bandpass Sigma-Delta modulator noise transfer function.
  • the present invention is also applicable to other quantizers of different levels or other continuous-time bandpass Sigma-Delta modulators of multiple inductor-capacitor resonators.
  • the present invention also provides an electronic device, which includes the above-mentioned continuous-time bandpass Sigma-Delta modulator.
  • the feedback freedom is increased, so that the entire modulator can realize any bandpass Sigma-Delta modulator noise transfer function, which effectively solves the limitation on the system performance of the continuous-time bandpass Sigma-Delta modulator based on the inductor-capacitor resonator due to the lack of feedback freedom, improves the performance of the modulator, and improves the performance of the entire electronic device.
  • a continuous-time bandpass Sigma-Delta modulator is designed in combination with a transconductance operational amplifier, a passive resonator, a sampling quantizer, a current feedback module and a voltage feedback module.
  • Voltage feedback is added on the basis of conventional current feedback, and current feedback and voltage feedback can be realized simultaneously, thereby increasing the feedback freedom, so that the entire modulator can realize any bandpass Sigma-Delta modulator noise transfer function.

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Abstract

本发明提供一种连续时间带通Sigma-Delta调制器及电子设备，所述连续时间带通Sigma-Delta调制器包括跨导运算放大器、无源谐振器、采样量化器、电流反馈模块及电压反馈模块。在本发明中，结合跨导运算放大器、无源谐振器、采样量化器、电流反馈模块及电压反馈模块设计了连续时间带通Sigma-Delta调制器，在常规电流反馈的基础上增加了电压反馈，能同时实现电流反馈与电压反馈，增加了反馈自由度，使得整个调制器可以实现任意的带通Sigma-Delta调制器噪声传递函数，这有效地解决了由于反馈自由度缺失对基于电感电容谐振器的连续时间带通Sigma-Delta调制器系统性能的限制，提升了调制器的性能。

Description

连续时间带通Sigma-Delta调制器及电子设备 技术领域
本发明涉及集成电路技术领域，特别是涉及一种连续时间带通Sigma-Delta调制器及电子设备。
背景技术
连续时间Sigma-Delta调制器有着低功耗、高速的特点外，还有着自身的抗混叠特性，大大减轻了对前级的抗混叠滤波器设计需求，同时有效的减小了芯片面积。这些特点都使得连续时间Sigma-Delta调制器得到广泛的使用。其中的带通型连续时间Sigma-Delta调制器在有着前述特点的同时，可以直接对中频信号直接数字化，极大的简化了接收机系统的复杂度。带通型连续时间Sigma-Delta调制器中的环路滤波器通常由有源RC积分器构成的谐振器或者电感电容构成的谐振器组成。由于电感电容型谐振器是无源器件，并且理想情况下仅仅是储能器件，所以不存在功耗。同时，电感电容谐振器可以实现更高的品质因数，提供更早的增益，这使得其噪声性能优于由有源RC积分器构成的谐振器。
但是，现有的基于电感电容谐振器的连续时间带通Sigma-Delta调制器技术，由于对于一个电感电容二阶谐振器，调制器输出的反馈仅有一个电流信号。缺失了一个反馈自由度，导致现有技术不能实现任意的带通Sigma-Delta调制器噪声传递函数。这就限制了在基于电感电容谐振器的连续时间带通Sigma-Delta调制器设计中的环路参数的选取，直接影响了整个调制器的性能。
因此，目前亟需一种基于更多反馈自由度的可以实现任意的带通Sigma-Delta调制器噪声传递函数的技术方案。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种基于电感电容谐振器的连续时间带通Sigma-Delta调制器，在电流反馈的基础上增加了一个电压反馈，以弥补缺失的自由度，解决自由度缺失对基于电感电容谐振器的连续时间带通Sigma-Delta调制器系统性能的限制。
为实现上述目的及其他相关目的，本发明提供的技术方案如下。
一种连续时间带通Sigma-Delta调制器，包括：
跨导运算放大器，接输入电压信号并对所述输入电压信号进行转换，得到并输出电流信 号；
无源谐振器，作为环路滤波器，接所述跨导运算放大器的输出端，对所述电流信号进行转换，得到并输出中间电压信号；
采样量化器，接所述无源谐振器的输出端，对所述中间电压信号进行采样量化，得到并输出温度计码；
电流反馈模块，其输入端接所述采样量化器的输出端，其输出端接所述无源谐振器，在所述温度计码的控制下为所述无源谐振器提供反馈电流；
电压反馈模块，其输入端接所述采样量化器的输出端，其输出端接所述无源谐振器，在所述温度计码的控制下为所述无源谐振器提供反馈电压。
可选地，所述无源谐振器包括电容和电感，所述电容的一端接所述跨导运算放大器的输出端，所述电容的另一端接地，所述电感的一端接所述跨导运算放大器的输出端，所述电感的另一端经串接的所述电压反馈模块后接所述采样量化器的输出端，所述电感接所述跨导运算放大器输出端的一端输出所述中间电压信号。
可选地，所述温度计码包括四位温度计码，所述电流反馈模块包括第一电流源、第二电流源、第三电流源、第四电流源、第五电流源、第一开关、第二开关、第三开关及第四开关，工作电压经依次串接的所述第一电流源、所述第一开关及所述第二电流源后接地，所述工作电压还经依次串接的所述第一电流源、所述第二开关及所述第三电流源后接地，所述工作电压还经依次串接的所述第一电流源、所述第三开关及所述第四电流源后接地，所述工作电压还经依次串接的所述第一电流源、所述第四开关及所述第五电流源后接地，所述第一开关的控制端接所述四位温度计码的第一位，所述第二开关的控制端接所述四位温度计码的第二位，所述第三开关的控制端接所述四位温度计码的第三位，所述第四开关的控制端接所述四位温度计码的第四位，所述第一开关、所述第二开关、所述第三开关及所述第四开关的公共端输出所述反馈电流，所述反馈电流接所述跨导运算放大器的输出端。
可选地，所述电压反馈模块包括输出电压调节单元、分压单元及选择输出单元，所述输出电压调节单元输出可调节的初始电压，所述分压单元的输入端接所述输出电压调节单元的输出端，所述分压单元结合地、所述工作电压及所述初始电压进行分压处理，得到并输出多个不同大小的初始反馈电压，所述选择输出单元的多个输入端与多个所述初始反馈电压一一对应连接，所述选择输出单元的控制端接所述温度计码，在所述温度计码的控制下，所述选择输出单元选择多个所述初始反馈电压中的一个作为所述反馈电压并输出，所述选择输出单元的输出端接所述电感远离所述跨导运算放大器的一端。
可选地，所述输出电压调节单元包括N个参考电流源、N个数控开关、第一电阻、第一运算放大器及NMOS管，N个所述参考电流源与N个所述数控开关形成N条并联的电流支路，每条所述电流支路包括依次串接的一个所述参考电流源及一个所述数控开关，每个所述参考电流源远离所述数控开关的一端接所述工作电压，N个所述数控开关的控制端与N位数字码的N位一一对应连接，N个所述数控开关远离所述参考电流源的一端短接并接所述第一电阻的一端，所述第一电阻的另一端接地，所述第一运算放大器的同相输入端接N个所述数控开关的公共端，所述第一运算放大器的反相输入端接所述NMOS管的源极，所述第一运算放大器的输出端接所述NMOS管的栅极，所述NMOS管的源极输出所述初始电压，其中，N为大于等于2的整数。
可选地，所述分压单元包括第二电阻及4个第三电阻，所述工作电压经依次串接的第一个所述第三电阻、第二个所述第三电阻、第三个所述第三电阻及第四个所述第三电阻后接所述NMOS管的漏极，所述NMOS管的源极经串接的所述第二电阻后接地，第一个所述第三电阻靠近所述工作电压的一端输出一个所述初始反馈电压，第一个所述第三电阻与第二个所述第三电阻的公共端输出一个所述初始反馈电压，第二个所述第三电阻与第三个所述第三电阻的公共端输出一个所述初始反馈电压，第三个所述第三电阻与第四个所述第三电阻的公共端输出一个所述初始反馈电压，第四个所述第三电阻靠近所述NMOS管的一端输出一个所述初始反馈电压。
可选地，所述选择输出单元包括数据选择器及第二运算放大器，所述数据选择器的五个输入端与五个所述初始反馈电压一一对应连接，所述数据选择器的控制端接所述温度计码，所述数据选择器的输出端接所述第二运算放大器的同相输入端，所述第二运算放大器的反相输入端接所述第二运算放大器的输出端，所述第二运算放大器的输出端输出所述反馈电压。
可选地，所述电压反馈模块还包括输出共模调节单元，所述输出共模调节单元的输出端接所述分压单元，所述输出共模调节单元对所述反馈电压的共模值进行稳定钳位。
可选地，所述输出共模调节单元包括第三运算放大器及PMOS管，所述PMOS管的源极接所述工作电压，所述PMOS管的栅极接所述第三运算放大器的输出端，所述第三运算放大器的反相输入端接参考电压，所述第三运算放大器的同相输入端接第二个所述第三电阻与第三个所述第三电阻的公共端，所述PMOS管的漏极接第一个所述第三电阻远离第二个所述第三电阻的一端。
一种电子设备，包括如上述任一项所述的连续时间带通Sigma-Delta调制器。
如上所述，本发明的连续时间带通Sigma-Delta调制器及电子设备至少具有以下有益效果：
结合跨导运算放大器、无源谐振器、采样量化器、电流反馈模块及电压反馈模块设计了连续时间带通Sigma-Delta调制器，在常规电流反馈的基础上增加了电压反馈，能同时实现电流反馈与电压反馈，增加了反馈自由度，使得整个调制器可以实现任意的带通Sigma-Delta调制器噪声传递函数，这有效地解决了由于反馈自由度缺失对基于电感电容谐振器的连续时间带通Sigma-Delta调制器系统性能的限制，提升了调制器的性能。
附图说明
图1显示为本发明中连续时间带通Sigma-Delta调制器的结构框图。
图2显示为图1中电流反馈模块4的电路结构图。
图3显示为图1中电压反馈模块5的电路结构图。
图4显示为CRFB结构的连续时间带通Sigma-Delta调制器的结构框图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图4。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
如前述在背景技术中所述，发明人研究发现：在现有的基于电感电容谐振器的连续时间带通Sigma-Delta调制器技术中，对于一个电感电容二阶谐振器，调制器输出的反馈仅有一个基于电流反馈模块的电流信号。反馈自由度较少，导致现有技术不能实现任意的带通Sigma-Delta调制器噪声传递函数，进而限制了在基于电感电容谐振器的连续时间带通Sigma-Delta调制器设计中的环路参数的选取，直接影响了整个调制器的性能。
基于此，如图1所示，本发明提出一种连续时间带通Sigma-Delta调制器，其包括：
跨导运算放大器1，接输入电压信号u并对输入电压信号u进行转换，得到并输出电流信号I 0；
无源谐振器2，作为环路滤波器，接跨导运算放大器1的输出端，对电流信号I 0进行转换，得到并输出中间电压信号x1；
采样量化器3，接无源谐振器2的输出端，对中间电压信号x1进行采样量化，得到并输出温度计码DN；
电流反馈模块4，其输入端接采样量化器3的输出端，其输出端接无源谐振器2，在温度计码DN的控制下为无源谐振器2提供反馈电流I OUT；
电压反馈模块5，其输入端接采样量化器3的输出端，其输出端接无源谐振器2，在温度计码DN的控制下为无源谐振器2提供反馈电压V OUT。
其中，跨导运算放大器1可采用常规的跨导运算放大结构，其对应跨导为g m，其对输入电压信号u进行转换，得到并输出电流信号I 0，有I 0＝g mu。
详细地，如图1所示，无源谐振器2为电感电容型谐振器，其包括电容C和电感L，电容C的一端接跨导运算放大器1的输出端，电容C的另一端接地，电感L的一端接跨导运算放大器1的输出端，电感L的另一端经串接的电压反馈模块5后接采样量化器3的输出端，电感L接跨导运算放大器1输出端的一端输出中间电压信号x1，中间电压信号x1即为电容C上的电压。
详细地，在本发明的一可选实施例中，如图1-图2所示，采样量化器3可以是5-level的并联比较型模数转换器，其将无源谐振器2上的中间电压信号x1以采样频率fs进行采样并量化，由模数转换得到4位的温度计码DN，即图2所示的IN<0>、IN<1>、IN<2>及IN<3>，其对应的数字电压记为v。可以理解的是，采样量化器3还可以是其他结构其他位数的模数转换器，在此不作限定。
详细地，在本发明的一可选实施例中，如图2所示，电流反馈模块4包括第一电流源I1、第二电流源I2、第三电流源I3、第四电流源I4、第五电流源I5、第一开关K1、第二开关K2、第三开关K3及第四开关K4，工作电压VDD经依次串接的第一电流源I1、第一开关K1及第二电流源I2后接地，工作电压VDD还经依次串接的第一电流源I1、第二开关K2及第三电流源I3后接地，工作电压VDD还经依次串接的第一电流源I1、第三开关K3及第四电流源I4后接地，工作电压VDD还经依次串接的第一电流源I1、第四开关K4及第五电流源I5后接地，第一开关K1的控制端接四位温度计码DN的第一位IN<0>，第二开关K2的控制端接四位温度计码DN的第二位IN<1>，第三开关K3的控制端接四位温度计码DN的第三位 IN<2>，第四开关K4的控制端接四位温度计码DN的第四位IN<3>，第一开关K1、第二开关K2、第三开关K3及第四开关K4的公共端输出反馈电流I OUT，反馈电流I OUT接所述跨导运算放大器1的输出端。
其中，第一电流源I1的输出电流为I 1，第二电流源I2、第三电流源I3、第四电流源I4、第五电流源I5的输出电流相等，记为I 2，且I 1＝2I 2，通过IN<0>、IN<1>、IN<2>及IN<3>的选通控制，可调节输出的反馈电流I OUT的大小。此外，第一电流源I1、第二电流源I2、第三电流源I3、第四电流源I4及第五电流源I5的输出电流大小可以任意设置，不限于此。
详细地，在本发明的一可选实施例中，如图3所示，电压反馈模块5包括输出电压调节单元51、分压单元52及选择输出单元53，输出电压调节单元51输出可调节的初始电压V0，分压单元52的输入端接输出电压调节单元51的输出端，分压单元52结合地、工作电压VDD及初始电压V0进行分压处理，得到并输出多个不同大小的初始反馈电压，如VF1～VF5，选择输出单元53的多个输入端与多个初始反馈电压一一对应连接，选择输出单元53的控制端接温度计码DN，在温度计码DN的控制下，选择输出单元53选择多个初始反馈电压中的一个作为反馈电压V OUT并输出，选择输出单元53的输出端接电感L远离跨导运算放大器1的一端。
更详细地，如图3所示，输出电压调节单元51包括N个参考电流源I 0、N个数控开关K 0、第一电阻R 1、第一运算放大器A1及NMOS管M1，N个参考电流源I 0与N个数控开关K 0形成N条并联的电流支路，每条电流支路包括依次串接的一个参考电流源I 0及一个数控开关K 0，每个参考电流源I 0远离数控开关K 0的一端接工作电压VDD，N个数控开关K 0的控制端与N位数字码的N位一一对应连接，如图中的I_ADJ<0:7>所示的8位数字码，N个数控开关K 0远离参考电流源I 0的一端短接并接第一电阻R 1的一端，第一电阻R 1的另一端接地，第一运算放大器A1的同相输入端接N个数控开关K 0的公共端，第一运算放大器A1的反相输入端接NMOS管M1的源极，第一运算放大器A1的输出端接NMOS管M1的栅极，NMOS管M1的源极输出初始电压V0，其中，N为大于等于2的整数。
其中，用于数控开关K 0通断控制的数字码为8位的I_ADJ<0:7>，对应有8个电流支路，N的取值为8；需要说明的是，用于数控开关K 0通断控制的数字码不限于图1所示的8位的I_ADJ<0:7>，还可以是任意其它位数的数字码，具体由N的数值决定，在此不作限定。
更详细地，如图3所示，通过N位数字码的调节控制，对输出电压调节单元51中N条电流支路的通断进行控制，以调节流过第一电阻R 1上的电流，进而对第一运算放大器A1的同相输入端的电压进行调节，第一运算放大器A1结合NMOS管M1对第一运算放大器A1 的同相输入端电压进行跟随输出，在NMOS管M1的源极得到初始电压V0，可通过N位数字码调节控制初始电压V0的大小，同时实现了电压反馈模块5的最低有效位(least significant bit，LSB)或者分辨率可重构，假定流过第一电阻R 1的电流为n×I 0，n为0～N的整数，那么电压反馈模块5的一个LSB可以表示为：
Figure PCTCN2022130870-appb-000001
更详细地，如图3所示，分压单元52包括第二电阻R 2及4个第三电阻R 0，工作电压VDD经依次串接的第一个第三电阻R 0、第二个第三电阻R 0、第三个第三电阻R 0及第四个第三电阻R 0后接NMOS管M1的漏极，NMOS管M1的源极经串接的第二电阻R 2后接地，第一个第三电阻R 0靠近工作电压VDD的一端输出初始反馈电压VF1，第一个第三电阻R 0与第二个第三电阻R 0的公共端输出初始反馈电压VF2，第二个第三电阻R 0与第三个第三电阻R 0的公共端输出初始反馈电压VF3，第三个第三电阻R 0与第四个第三电阻R 0的公共端输出初始反馈电压VF4，第四个第三电阻R 0靠近NMOS管M1的一端输出初始反馈电压VF5。
更详细地，如图3所示，分压单元52结合地、工作电压VDD及初始电压V0进行分压处理，得到并输出5个不同大小的初始反馈电压VF1～VF5；其中，分压单元52中分压电阻的个数与阻值可根据实际需求进行选择，在此不作限定，图3中的5个初始反馈电压VF1～VF5刚好与4位的温度计码DN对应。
更详细地，如图3所示，选择输出单元53包括数据选择器MUX及第二运算放大器A2，数据选择器MUX的五个输入端与五个初始反馈电压VF1～VF5一一对应连接，数据选择器MUX的控制端接温度计码DN，数据选择器MUX的输出端接第二运算放大器A2的同相输入端，第二运算放大器A2的反相输入端接第二运算放大器A2的输出端，第二运算放大器A2的输出端输出反馈电压V OUT。
更详细地，如图3所示，数据选择器MUX对输入的各个初始反馈电压进行选择输出，其控制方式为，如输入的温度计码DN中有i个高电平，那么数据选择器MUX输出为第i路初始反馈电压；该初始反馈电压经过第二运算放大器A2的跟随输出处理，得到反馈电压V OUT。
更详细地，如图3所示，电压反馈模块5还包括输出共模调节单元54，输出共模调节单元54的输出端接分压单元52，输出共模调节单元54对反馈电压V OUT的共模值进行稳定钳位。
更详细地，如图3所示，输出共模调节单元54包括第三运算放大器A3及PMOS管M2，PMOS管M2的源极接工作电压VDD，PMOS管M2的栅极接第三运算放大器A3的输出端，第三运算放大器A3的反相输入端接参考电压VREF，第三运算放大器A3的同相输入端接第 二个第三电阻R 0与第三个第三电阻R 0的公共端，PMOS管M2的漏极接第一个第三电阻R 0远离第二个第三电阻R 0的一端。
更详细地，如图3所示，通过第三运算放大器A3的虚短作用，将初始反馈电压VF3的电压值稳定在在参考电压VREF，而初始反馈电压VF3为整个分压单元52的中位电压，进而将反馈电压V OUT的共模值稳定钳位在VREF。
详细地，图1所示的连续时间带通Sigma-Delta调制器为级联谐振器反馈结构(cascade resonator feedback，CRFB)，其工作原理如下：
连续时间带通Sigma-Delta调制器中的环路滤波器由电感电容谐振器构成，不同于有源RC谐振器，该谐振器的两个积分状态量为一个电压信号和一个电流信号，分别为电容C上的电压x 1和电感L上的电流x 2。于是，对该环路滤波器列出状态方程为：
Figure PCTCN2022130870-appb-000002
其中，K 1为电流反馈模块4的电流放大倍数，K 2为电压反馈模块5的电压放大倍数，y为采样量化器3的输入，v为采样量化器3的输出。
对上述方程组做拉普拉斯变换可以得到：
Figure PCTCN2022130870-appb-000003
于是，该调制器的ABCD矩阵为：
Figure PCTCN2022130870-appb-000004
此外，级联谐振器反馈结构的连续时间带通Sigma-Delta调制器的一般系统框图如图4所示，其详细结构参数可参见现有技术，在此不再赘述，其采样时钟频率一般为归一化的1Hz。该级联谐振器反馈结构的调制器状态方程的拉普拉斯变换如下：
Figure PCTCN2022130870-appb-000005
于是，该调制器的ABCD矩阵为：
Figure PCTCN2022130870-appb-000006
通过比较式(4)表示的本发明的连续时间带通Sigma-Delta调制器的ABCD矩阵和式(6)表示的一般级联谐振器反馈结构的连续时间带通Sigma-Delta调制器的ABCD矩阵，可以看出，通过适当的环路滤波器参数的配置(如电感L的电感值、电感C的电容值、电流反馈模块4的LSB、电压反馈模块5的LSB以及跨导运算放大器的跨导g m等)可以式(4)和式(6)的完全相等。也就是说通过适当的环路滤波器参数的配置，本发明的基于电感电容谐振器的连续时间带通sigma-delta调制器可以实现任意的带通sigma-delta调制器噪声传递函数。
因此，在本发明中，结合跨导运算放大器、无源谐振器、采样量化器、电流反馈模块及电压反馈模块设计了连续时间带通Sigma-Delta调制器，在常规电流反馈的基础上增加了电压反馈，能同时实现电流反馈与电压反馈，增加了反馈自由度，使得整个调制器可以实现任意的带通Sigma-Delta调制器噪声传递函数，这有效地解决了由于反馈自由度缺失对基于电感电容谐振器的连续时间带通Sigma-Delta调制器系统性能的限制，提升了调制器的性能。
本发明同样适用于其他不同level的量化器或者其他多个电感电容谐振器的连续时间带通Sigma-Delta调制器。
此外，本发明还提供一种电子设备，所述电子设备包括如上述连续时间带通Sigma-Delta调制器，基于上述连续时间带通Sigma-Delta调制器中电流反馈加电压反馈的设计，增加了反馈自由度，使得整个调制器可以实现任意的带通Sigma-Delta调制器噪声传递函数，这有效地解决了由于反馈自由度缺失对基于电感电容谐振器的连续时间带通Sigma-Delta调制器系统性能的限制，提升了调制器的性能，提升了整个电子设备的性能。
综上所述，在本发明所提供的连续时间带通Sigma-Delta调制器及电子设备中，结合跨导运算放大器、无源谐振器、采样量化器、电流反馈模块及电压反馈模块设计了连续时间带通Sigma-Delta调制器，在常规电流反馈的基础上增加了电压反馈，能同时实现电流反馈与电压反馈，增加了反馈自由度，使得整个调制器可以实现任意的带通Sigma-Delta调制器噪声传递函数，这有效地解决了由于反馈自由度缺失对基于电感电容谐振器的连续时间带通Sigma-Delta调制器系统性能的限制，提升了调制器的性能。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种连续时间带通Sigma-Delta调制器，其特征在于，包括：
    跨导运算放大器，接输入电压信号并对所述输入电压信号进行转换，得到并输出电流信号；
    无源谐振器，作为环路滤波器，接所述跨导运算放大器的输出端，对所述电流信号进行转换，得到并输出中间电压信号；
    采样量化器，接所述无源谐振器的输出端，对所述中间电压信号进行采样量化，得到并输出温度计码；
    电流反馈模块，其输入端接所述采样量化器的输出端，其输出端接所述无源谐振器，在所述温度计码的控制下为所述无源谐振器提供反馈电流；
    电压反馈模块，其输入端接所述采样量化器的输出端，其输出端接所述无源谐振器，在所述温度计码的控制下为所述无源谐振器提供反馈电压。
  2. 根据权利要求1所述的连续时间带通Sigma-Delta调制器，其特征在于，所述无源谐振器包括电容和电感，所述电容的一端接所述跨导运算放大器的输出端，所述电容的另一端接地，所述电感的一端接所述跨导运算放大器的输出端，所述电感的另一端经串接的所述电压反馈模块后接所述采样量化器的输出端，所述电感接所述跨导运算放大器输出端的一端输出所述中间电压信号。
  3. 根据权利要求2所述的连续时间带通Sigma-Delta调制器，其特征在于，所述温度计码包括四位温度计码，所述电流反馈模块包括第一电流源、第二电流源、第三电流源、第四电流源、第五电流源、第一开关、第二开关、第三开关及第四开关，工作电压经依次串接的所述第一电流源、所述第一开关及所述第二电流源后接地，所述工作电压还经依次串接的所述第一电流源、所述第二开关及所述第三电流源后接地，所述工作电压还经依次串接的所述第一电流源、所述第三开关及所述第四电流源后接地，所述工作电压还经依次串接的所述第一电流源、所述第四开关及所述第五电流源后接地，所述第一开关的控制端接所述四位温度计码的第一位，所述第二开关的控制端接所述四位温度计码的第二位，所述第三开关的控制端接所述四位温度计码的第三位，所述第四开关的控制端接所述四位温度计码的第四位，所述第一开关、所述第二开关、所述第三开关及所述第四开关的公共端输出所述反馈电流，所述反馈电流接所述跨导运算放大器的输出端。
  4. 根据权利要求3所述的连续时间带通Sigma-Delta调制器，其特征在于，所述电压反 馈模块包括输出电压调节单元、分压单元及选择输出单元，所述输出电压调节单元输出可调节的初始电压，所述分压单元的输入端接所述输出电压调节单元的输出端，所述分压单元结合地、所述工作电压及所述初始电压进行分压处理，得到并输出多个不同大小的初始反馈电压，所述选择输出单元的多个输入端与多个所述初始反馈电压一一对应连接，所述选择输出单元的控制端接所述温度计码，在所述温度计码的控制下，所述选择输出单元选择多个所述初始反馈电压中的一个作为所述反馈电压并输出，所述选择输出单元的输出端接所述电感远离所述跨导运算放大器的一端。
  5. 根据权利要求4所述的连续时间带通Sigma-Delta调制器，其特征在于，所述输出电压调节单元包括N个参考电流源、N个数控开关、第一电阻、第一运算放大器及NMOS管，N个所述参考电流源与N个所述数控开关形成N条并联的电流支路，每条所述电流支路包括依次串接的一个所述参考电流源及一个所述数控开关，每个所述参考电流源远离所述数控开关的一端接所述工作电压，N个所述数控开关的控制端与N位数字码的N位一一对应连接，N个所述数控开关远离所述参考电流源的一端短接并接所述第一电阻的一端，所述第一电阻的另一端接地，所述第一运算放大器的同相输入端接N个所述数控开关的公共端，所述第一运算放大器的反相输入端接所述NMOS管的源极，所述第一运算放大器的输出端接所述NMOS管的栅极，所述NMOS管的源极输出所述初始电压，其中，N为大于等于2的整数。
  6. 根据权利要求5所述的连续时间带通Sigma-Delta调制器，其特征在于，所述分压单元包括第二电阻及4个第三电阻，所述工作电压经依次串接的第一个所述第三电阻、第二个所述第三电阻、第三个所述第三电阻及第四个所述第三电阻后接所述NMOS管的漏极，所述NMOS管的源极经串接的所述第二电阻后接地，第一个所述第三电阻靠近所述工作电压的一端输出一个所述初始反馈电压，第一个所述第三电阻与第二个所述第三电阻的公共端输出一个所述初始反馈电压，第二个所述第三电阻与第三个所述第三电阻的公共端输出一个所述初始反馈电压，第三个所述第三电阻与第四个所述第三电阻的公共端输出一个所述初始反馈电压，第四个所述第三电阻靠近所述NMOS管的一端输出一个所述初始反馈电压。
  7. 根据权利要求6所述的连续时间带通Sigma-Delta调制器，其特征在于，所述选择输出单元包括数据选择器及第二运算放大器，所述数据选择器的五个输入端与五个所述初始反馈电压一一对应连接，所述数据选择器的控制端接所述温度计码，所述数据选择器的输出端接所述第二运算放大器的同相输入端，所述第二运算放大器的反相输入端接所述第二运算放 大器的输出端，所述第二运算放大器的输出端输出所述反馈电压。
  8. 根据权利要求6所述的连续时间带通Sigma-Delta调制器，其特征在于，所述电压反馈模块还包括输出共模调节单元，所述输出共模调节单元的输出端接所述分压单元，所述输出共模调节单元对所述反馈电压的共模值进行稳定钳位。
  9. 根据权利要求8所述的连续时间带通Sigma-Delta调制器，其特征在于，所述输出共模调节单元包括第三运算放大器及PMOS管，所述PMOS管的源极接所述工作电压，所述PMOS管的栅极接所述第三运算放大器的输出端，所述第三运算放大器的反相输入端接参考电压，所述第三运算放大器的同相输入端接第二个所述第三电阻与第三个所述第三电阻的公共端，所述PMOS管的漏极接第一个所述第三电阻远离第二个所述第三电阻的一端。
  10. 一种电子设备，其特征在于，包括如权利要求1-9中任一项所述的连续时间带通Sigma-Delta调制器。
PCT/CN2022/130870 2022-10-31 2022-11-09 连续时间带通Sigma-Delta调制器及电子设备 WO2024092863A1 (zh)

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