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WO2024092543A1 - Nitride-based semiconductor device and method for manufacturing the same - Google Patents

Nitride-based semiconductor device and method for manufacturing the same Download PDF

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Publication number
WO2024092543A1
WO2024092543A1 PCT/CN2022/129174 CN2022129174W WO2024092543A1 WO 2024092543 A1 WO2024092543 A1 WO 2024092543A1 CN 2022129174 W CN2022129174 W CN 2022129174W WO 2024092543 A1 WO2024092543 A1 WO 2024092543A1
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WO
WIPO (PCT)
Prior art keywords
layer
nitride
etching stop
based semiconductor
stop layer
Prior art date
Application number
PCT/CN2022/129174
Other languages
French (fr)
Inventor
Kai Hu
King Yuen Wong
Original Assignee
Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Innoscience (suzhou) Semiconductor Co., Ltd. filed Critical Innoscience (suzhou) Semiconductor Co., Ltd.
Priority to CN202280086143.1A priority Critical patent/CN118451554A/en
Priority to PCT/CN2022/129174 priority patent/WO2024092543A1/en
Publication of WO2024092543A1 publication Critical patent/WO2024092543A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane

Definitions

  • the present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having etching stop layers to improve the device reliability.
  • III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices.
  • devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
  • a nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first etching stop layer, a gate electrode, and a gate isolation layer.
  • the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer.
  • the first etching stop layer is disposed over the second nitride-based semiconductor layer and has inner sidewalls facing each other.
  • the gate electrode is disposed over the first etching stop layer.
  • the gate isolation layer is disposed over the second nitride-based semiconductor layer and located between the first etching stop layer and the gate electrode. The gate isolation layer has first corners abutting against the inner sidewalls of the first etching stop layer.
  • a method for manufacturing a nitride-based semiconductor device has steps as follows; forming a first nitride-based semiconductor layer; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer; forming a first etching stop layer over the second nitride-based semiconductor layer; forming a first dielectric layer over the first etching stop layer; removing a portion of the first dielectric layer to expose the first etching stop layer; removing the exposed portion of the first etching stop layer to form an opening; forming a gate isolation layer over the second nitride-based semiconductor layer and extending to the opening; forming a gate electrode over the gate isolation layer.
  • a nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first etching stop layer, a second etching stop layer, a gate isolation layer, and a gate electrode.
  • the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer.
  • the first etching stop layer is disposed over the second nitride-based semiconductor layer.
  • the second etching stop layer is disposed over the first etching stop layer.
  • the gate isolation layer is disposed over the second nitride-based semiconductor layer and extends from the first etching stop layer to the second etching stop layer.
  • the gate electrode is disposed over the first etching stop layer and the second etching stop layer and separated from the first etching stop layer and the second etching stop layer by the gate isolation layer.
  • the etching stop layer extending from the gate isolation layer to other component can be electrically isolated from the gate electrode, which results in block of leakage current from the gate electrode.
  • FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 2A, FIG. 2B, FIG. 2C, FIG 2D, FIG. 2E, FIG. 2F, FIG. 2G, FIG. 2H, FIG. 2I, FIG. 2J, and FIG. 2K show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure.
  • FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure.
  • the nitride-based semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14, etching stop layer 20, 24, 27, a gate dielectric layer 22, dielectric layers 26, 28, 30, 32, 34, 36, an isolation structure 38, electrodes 40, 42, a conductive layer 44, a gate isolation layer 50, a gate electrode 52, patterned conductive layers 60, 66, contact vias 62, 64, 68, and pads 70.
  • the substrate 10 may be a semiconductor substrate.
  • the exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials.
  • the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) .
  • the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
  • the nitride-based semiconductor device 1A may further include a buffer layer (not illustrated) .
  • the buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12.
  • the buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference.
  • the buffer layer may include a III-V compound.
  • the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof.
  • the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
  • the semiconductor device 1A may further include a nucleation layer (not shown) .
  • the nucleation layer may be formed between the substrate 10 and a buffer layer.
  • the nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer.
  • the exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
  • the nitride-based semiconductor layer 12 can be disposed on/over/above the buffer layer.
  • the nitride-based semiconductor layer 14 can be disposed on/over/above the nitride-based semiconductor layer 12.
  • the exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al x Ga (1–x) N where x ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.
  • the nitride-based semiconductor layer 12 is an undoped GaN layer having a bandgap of approximately 3.4 eV
  • the nitride-based semiconductor layer 14 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.
  • the nitride-based semiconductor layers 12 and 14 can serve as a channel layer and a barrier layer, respectively.
  • a triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
  • the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
  • HEMT high-electron-mobility transistor
  • the etching stop layer 20 is disposed over the nitride-based semiconductor layer 14.
  • the etching stop layer 20 can cover the nitride-based semiconductor layer 14.
  • the gate dielectric layer 22 is disposed over the etching stop layer 20.
  • the gate dielectric layer 22 covers the etching stop layer 20.
  • the etching stop layer 20 can keep stable at an etching stage of the gate dielectric layer 22.
  • the etching stop layer 20 and the gate dielectric layer 22 have different materials.
  • the etching stop layer 20 includes AlN and the gate dielectric layer 22 includes SiN.
  • the etching stop layer 20 is an aluminum nitride layer and the gate dielectric layer 22 is a silicon nitride layer.
  • the etching stop layer 20 is thinner than the gate dielectric layer 22.
  • the etching stop layer 20 has a thickness in a range from about 1 nm to 3 nm.
  • the gate dielectric layer 22 has a thickness in a range from about 25 nm to about 35 nm.
  • the etching stop layer 24 is disposed over the nitride-based semiconductor layer 14.
  • the etching stop layer 24 is disposed over the etching stop layer 20 and the gate dielectric layer 22.
  • the etching stop layer 24 has inner sidewalls facing each other.
  • the dielectric layer 26 is disposed over the etching stop layer 24.
  • the dielectric layer 26 has inner sidewalls facing each other.
  • the dielectric layer 26 covers the etching stop layer 24.
  • the etching stop layer 24 can keep stable at an etching stage of the dielectric layer 26.
  • the etching stop layer 24 and the dielectric layer 26 have different materials.
  • the etching stop layer 24 includes AlN and the dielectric layer 26 includes oxide compound, such as SiO x .
  • the etching stop layer 24 is an aluminum nitride layer and the dielectric layer 26 is a silicon oxide layer.
  • the etching stop layer 24 is thinner than the dielectric layer 26.
  • the etching stop layer 24 has a thickness in a range from about 1 nm to 3 nm.
  • the gate dielectric layer 22 has a thickness in a range from about 15 nm to about 25 nm.
  • the etching stop layer 27 is disposed over the nitride-based semiconductor layer 14.
  • the etching stop layer 27 is disposed over the etching stop layer 24 and the dielectric layer 26.
  • the etching stop layer 27 has inner sidewalls facing each other. A distance between the inner sidewalls of the etching stop layer 27 is greater than a distance between the inner sidewalls of the etching stop layer 24. A distance between the inner sidewalls of the etching stop layer 27 is greater than a distance between the inner sidewalls of the dielectric layer 26.
  • the dielectric layer 28 is disposed over the etching stop layer 27.
  • the dielectric layer 28 has inner sidewalls facing each other.
  • the dielectric layer 28 covers the etching stop layer 27.
  • a distance between the inner sidewalls of the dielectric layer 28 is greater than a distance between the inner sidewalls of the etching stop layer 24.
  • a distance between the inner sidewalls of the dielectric layer 28 is greater than a distance between the inner sidewalls of the dielectric layer 26.
  • the etching stop layer 27 can keep stable at an etching stage of the dielectric layer 28.
  • the etching stop layer 27 and the dielectric layer 28 have different materials.
  • the etching stop layer 27 includes AlN and the dielectric layer 28 includes oxide compound, such as SiO x .
  • the etching stop layer 27 is an aluminum nitride layer and the dielectric layer 28 is a silicon oxide layer.
  • the etching stop layer 27 is thinner than the dielectric layer 28.
  • the etching stop layer 27 has a thickness in a range from about 1 nm to 3 nm.
  • the dielectric layer 28 has a thickness in a range from about 50 nm to about 70 nm.
  • the etching stop layers 20, 24, 27 are parallel with each other. In some embodiments, the etching stop layers 20, 24, 27 have the same material or compound, which is different than those of the gate dielectric layer 22, the dielectric layer 26, and the dielectric layer 28. In some embodiments, the dielectric layer 26 and the dielectric layer 28 have the same material or compound, which is different than that of the gate dielectric layer 22.
  • the dielectric layer 30 is disposed over the dielectric layer 28.
  • the dielectric layer 30 covers the dielectric layer 28.
  • the dielectric layer 30 has inner sidewalls facing each other. A distance between the inner sidewalls of the dielectric layer 30 is substantially the same as a distance between the inner sidewalls of the dielectric layer 28.
  • the dielectric layer 28 includes oxide compound, such as SiO x .
  • the dielectric layer 30 is a silicon oxide layer.
  • the electrodes 40 and 42 are disposed over the nitride-based semiconductor layer 14.
  • the electrode 40 can be covered by the dielectric layer 30.
  • the electrode 40 can penetrate the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, the etching stop layer 24, the gate dielectric layer 22, and the etching stop layer 20 in sequence to make contact with the nitride-based semiconductor layer 14.
  • the electrode 42 can be covered by the dielectric layer 30.
  • the electrode 42 can penetrate the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, the etching stop layer 24, the gate dielectric layer 22, and the etching stop layer 20 in sequence to make contact with the nitride-based semiconductor layer 14.
  • Each of the electrodes 40 and 42 can serve as a source electrode or a drain electrode. In some embodiments, the electrodes 40 and 42 can be called ohmic electrodes.
  • the conductive layer 44 is located between the dielectric layer 28 and the electrode 40 and located between the dielectric layer 28 and the electrode 42.
  • the electrodes 40 and 42 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
  • the exemplary materials of the electrodes 40 and 42 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof.
  • the electrodes 40 and 42 may be a single layer, or plural layers of the same or different composition.
  • the electrodes 40 and 42 can form ohmic contact with the nitride-based semiconductor layer 14. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the electrodes 40 and 42.
  • each of the electrodes 40 and 42 is formed by at least one conformal layer and a conductive filling.
  • the conformal layer can wrap the conductive filling.
  • the exemplary materials of the conformal layer for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof.
  • the exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.
  • a gate isolation layer 50 is disposed over the nitride-based semiconductor layer 14.
  • the gate isolation layer 50 is located between the electrodes 40 and 42.
  • the gate isolation layer 50 is located over the etching stop layer 20 and the gate dielectric layer 22, such that the etching stop layer 20 and the gate dielectric layer 22 are between nitride-based semiconductor layer 14 and the gate isolation layer 50.
  • the gate isolation layer 50 can make contact with a top surface of the gate dielectric layer 22.
  • the gate isolation layer 50 can make contact with a top surface and the inner sidewalls of the dielectric layer 26.
  • the gate isolation layer 50 can extend from the etching stop layer 24 to the etching stop layer 27.
  • the gate isolation layer 50 can extend from the top surface of the gate dielectric layer 22 to a top surface of the dielectric layer 30.
  • the gate isolation layer 50 can extend along the inner sidewalls of the dielectric layer 30, the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, the etching stop layer 24.
  • the inner sidewalls of the etching stop layers 24 and 27 are in contact with the gate isolation layer 50.
  • the gate isolation layer 50 has a stepwise profile.
  • the material of the gate isolation layer 50 can include, for example but are not limited to, dielectric materials.
  • the gate isolation layer 50 can include SiN x , SiO x , SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof.
  • the gate electrode 52 is disposed over the dielectric layer 30, the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, the etching stop layer 24, the gate dielectric layer 22, and the etching stop layer 20.
  • the gate isolation layer 50 is located between the etching stop layer 24 and the gate electrode 52.
  • the gate isolation layer 50 is located between the etching stop layer 27 and the gate electrode 52.
  • the gate electrode 52 may be formed as a single layer, or plural layers of the same or different compositions.
  • the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
  • the electrodes 40, 42, and the gate electrode 52 can constitute a depletion mode GaN-based HEMT.
  • the gate electrode 52 has portions 522, 524, 526.
  • the portion 524 is located over the portion 522.
  • the portion 524 is wider than the portion 522.
  • the portion 526 is located over the portion 524.
  • the portion 526 is wider than the portion 524.
  • the different widths of the gate electrode 52 is able to function as a multiple field plates configuration. For example, ends of the portion 524 which are out of the portion 522 can serve as a field plate. Similarly, ends of the portion 526 which are out of portion 524 can serve as a field plate.
  • the etching stop layers 24 and 27 are applied thereto.
  • a device applying at least one etching stop layer to its structure may result in leakage current because the etching stop layer is possible to become a leakage current path in the structure.
  • the configuration of the gate isolation layer 50 and the gate electrode 52 is adapted thereto.
  • the gate isolation layer 50 can at least wrap a bottom surface of the gate electrode 52. Accordingly, the gate electrode 52 can get separated from the etching stop layers 24 and 27 by the gate isolation layer 50.
  • the gate isolation layer 50 can have bottom corners abutting against the inner sidewalls of the etching stop layer 24.
  • the gate isolation layer 50 has a bottom surface connecting one to another of the bottom corners.
  • the gate isolation layer 50 can have middle corners abutting against the inner sidewalls of the etching stop layer 27.
  • the reason to such the configuration is that the inner sidewalls of the etching stop layer 24 and 27 are potential to become a leakage current entrance so the gate isolation layer 50 can cover the entrance and isolate the entrance from the gate electrode 52.
  • the etching stop layer 24 extending from the gate isolation layer 50 to the electrode 40 or 42 is electrically isolated from the gate electrode 52, which results in block of potential leakage current from the gate electrode 52.
  • the etching stop layer 27 extending from the gate isolation layer 50 to the electrode 40 or 42 is electrically isolated from the gate electrode 52, which results in block of potential leakage current from the gate electrode 52. Accordingly, a multiple field plates configuration is achieved by a single gate electrode and reduction of the device reliability is avoided.
  • the dielectric layer 32 is disposed over the dielectric layer 30.
  • the dielectric layer 32 is disposed over the gate electrode 52.
  • the dielectric layer 32 covers the dielectric layer 30 and the gate electrode 52.
  • the material of the dielectric layer 32 can include, for example but are not limited to, dielectric materials.
  • the dielectric layer 32 can include SiN x , SiO x , SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof.
  • the dielectric layer 34 is disposed over the dielectric layer 32.
  • the material of the dielectric layer 34 can include, for example but are not limited to, dielectric materials.
  • the dielectric layer 34 can include SiN x , SiO x , SiON, SiC, SiBN, SiCBN, oxides, nitrides, PEOX, or combinations thereof.
  • the dielectric layer 36 is disposed over the dielectric layer 34.
  • the material of the dielectric layer 34 can include, for example but are not limited to, dielectric materials.
  • the dielectric layer 34 can include SiN x , SiO x , SiON, SiC, SiBN, SiCBN, oxides, nitrides, PEOX, or combinations thereof.
  • the isolation structure 38 is disposed over the nitride-based semiconductor layer 12.
  • the isolation structure 38 can extend from the nitride-based semiconductor layer 12 to the dielectric layer 32 and further to a bottom surface of the dielectric layer 34.
  • the isolation structure 38 can be doped with ions to achieve the electrically isolating purpose.
  • the ions can include, for example but are not limited to, nitrogen ion, fluorine ion, oxygen ion, argon atom, aluminum atom, or combinations thereof. These dopants can make the isolation structure 38 have a high resistivity and thus act as an electrically isolating region.
  • the patterned conductive layer 60 is disposed on the dielectric layer 32.
  • the patterned conductive layer 60 is covered by the dielectric layer 34.
  • the patterned conductive layer 60 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 60 can form at least one circuit.
  • the patterned conductive layer 60 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.
  • the contact vias 62 are disposed within the dielectric layers 32 and 34.
  • the contact vias 62 extend longitudinally so as to electrically connect the electrodes 40 and 42.
  • the exemplary materials of the contact vias 62 can include, but are not limited to, conductive materials, for example, metal or alloys.
  • the contact vias 64 are disposed within the dielectric layer 34.
  • the contact vias 64 extend longitudinally so as to electrically connect the patterned conductive layer 60.
  • the exemplary materials of the contact vias 64 can include, but are not limited to, conductive materials, for example, metal or alloys.
  • the patterned conductive layer 66 is disposed on the dielectric layer 34.
  • the patterned conductive layer 66 is covered by the dielectric layer 36.
  • the patterned conductive layer 66 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 66 can form at least one circuit.
  • the patterned conductive layer 66 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.
  • the contact vias 68 are disposed within the dielectric layer 36.
  • the contact vias 68 extend longitudinally so as to electrically connect the patterned conductive layer 66.
  • the exemplary materials of the contact vias 66 can include, but are not limited to, conductive materials, for example, metal or alloys.
  • the pads 70 are disposed on the contact vias 68.
  • the pads 70 are disposed within the dielectric layer 36.
  • the pads 70 can have regions free from coverage from the dielectric layer 36.
  • the pads 70 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.
  • deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • MOCVD metal organic CVD
  • PECVD plasma enhanced CVD
  • LPCVD low-pressure CVD
  • plasma-assisted vapor deposition epitaxial growth, or other suitable processes.
  • a substrate 10 is provided.
  • a nitride-based semiconductor layer 12 is formed on the substrate 10.
  • a nitride-based semiconductor layer 14 is formed on the nitride-based semiconductor layer 12.
  • An etching stop layer 20 is formed on the nitride-based semiconductor layer 14.
  • a gate dielectric layer 22 is formed on the etching stop layer 20.
  • an etching stop layer 24 is formed on the gate dielectric layer 22.
  • a dielectric layer 26 is formed on the etching stop layer 24.
  • An etching stop layer 27 is formed on the dielectric layer 26.
  • a dielectric layer 28 is formed on the etching stop layer 27.
  • a conductive layer 44 is formed on the dielectric layer 28.
  • the conductive layer 44 is patterned. Electrodes 40 and 42 are formed over the conductive layer 44. The electrodes 40 and 42 are formed to penetrate the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, the etching stop layer 24, the gate dielectric layer 22, and the etching stop layer 20 in sequence to make contact with the nitride-based semiconductor layer 14. Prior to the formation of the electrodes 40 and 42, multiple etching stages are performed. In the etching stages, the etching stop layers 20, 24, 27 can function. For example, during the etching stage of the gate dielectric layer 22, the etching stop layer 20 can keep stable so the nitride-based semiconductor layer 14 can be away from damage at the etching stage of the gate dielectric layer 22.
  • a dielectric layer 30 is formed on the dielectric layer 28.
  • the dielectric layer 30 covers the electrodes 40 and 42.
  • some portions of the dielectric layers 28 and 30 are removed. After the removal, a portion of the etching stop layer 27 is exposed.
  • the removal of the dielectric layers 28 and 30 can be achieved by using an etching stage.
  • the etching stop layer 27 can serve as an etching stop function during the etching stage of the dielectric layers 28 and 30.
  • the etching stop layer 27 and the dielectric layers 28 and 30 have different etching rates with respect to the same etchant applied to the etching stage.
  • some portions of the dielectric layers 28 and 30 are removed. After the removal, a portion of the etching stop layer 27 is exposed.
  • the removal of the dielectric layers 28 and 30 can be achieved by using an etching stage.
  • the etching stop layer 27 can serve as an etching stop function during the etching stage of the dielectric layers 28 and 30.
  • the etching stop layer 27 and the dielectric layers 28 and 30 have different etching rates with respect to the same etchant applied to the etching stage.
  • the exposed portion of the etching stop layer 27 is removed to form an opening such that a portion of the dielectric layer 26 is exposed from the opening.
  • the removal of the etching stop layer 27 can be achieved by using an etching stage. Removing the portions of the dielectric layers 28 and 30 as described in FIG. 2E and removing the exposed portion of the etching stop layer 27 as described in FIG. 2F are performed by using different etchants. Furthermore, the dielectric layer 26 can almost keep free from damage during the etching stage due to a high etching selectivity.
  • a portion of the dielectric layer 26 is removed. After the removal, a portion of the etching stop layer 24 is exposed.
  • the removal of the dielectric layer 26 can be achieved by using an etching stage.
  • the etching stop layer 24 can serve as an etching stop function during the etching stage of the dielectric layer 26.
  • the etching stop layer 24 and the dielectric layer 26 have different etching rates with respect to the same etchant applied to the etching stage of the dielectric layer 26.
  • the exposed portion of the etching stop layer 24 is removed to form an opening such that a portion of the gate dielectric layer 22 is exposed from the opening.
  • the removal of the etching stop layer 24 can be achieved by using an etching stage.
  • Removing the portion of the dielectric layer 26 and removing the exposed portion of the etching stop layer 24 are performed by using different etchants. Furthermore, the gate dielectric layer 22 can almost keep free from damage during the etching stage of the etching stop layer 24 due to a high etching selectivity.
  • a stepwise profile can be formed.
  • a gate isolation layer 50 is formed over the nitride-based semiconductor layer 14.
  • the gate isolation layer 50 is formed to extend into the openings of the etching stop layers 24 and 27.
  • the gate isolation layer 50 can be formed to extend from the dielectric layer 30 to the gate dielectric layer 22 through the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, and the etching stop layer 24.
  • a gate electrode 52 is formed over the gate isolation layer 50.
  • the gate electrode 52 is physically separated from the etching stop layers 24 and 27 by the gate isolation layer 52.
  • a dielectric layer 32 is formed over the gate electrode 52.
  • a patterned conductive layer 60 is formed on the dielectric layer 32.
  • An isolation structure 38 is formed by doping ions into the structure.
  • a dielectric layer 34 is formed over the dielectric layer 32.
  • Contact vias 62 and 64 are formed within the dielectric layer 34.
  • a conductive layer 66 is formed on the dielectric layer 34. The conductive layer 66 can be patterned after the formation thereof. Thereafter, a dielectric layer, contact vias, and pads are formed over the dielectric layer 34 to obtain the structure as described in FIG. 1.
  • the terms “substantially, “ “substantial, “ “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
  • the terms when used in conjunction with a numerical value, can encompass a range of variation of less than or equal to ⁇ 10%of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
  • substantially coplanar can refer to two surfaces within micrometers of lying along a same plane, such as within 40 ⁇ m, within 30 ⁇ m, within 20 ⁇ m, within 10 ⁇ m, or within 1 ⁇ m of lying along the same plane.
  • a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

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  • Junction Field-Effect Transistors (AREA)

Abstract

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first etching stop layer, a gate electrode, and a gate isolation layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The first etching stop layer is disposed over the second nitride-based semiconductor layer and has inner sidewalls facing each other. The gate electrode is disposed over the first etching stop layer. The gate isolation layer is disposed over the second nitride-based semiconductor layer and located between the first etching stop layer and the gate electrode. The gate isolation layer has first corners abutting against the inner sidewalls of the first etching stop layer.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Inventors: Kai HU; King Yuen WONG
Field of the Disclosure:
The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having etching stop layers to improve the device reliability.
Background of the Disclosure:
In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
Summary of the Disclosure:
In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first etching stop layer, a gate electrode, and a gate isolation layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The first etching stop layer is disposed over the second nitride-based semiconductor layer and has inner sidewalls facing each other. The gate electrode is disposed over the first etching stop layer. The gate isolation layer is disposed over the second nitride-based semiconductor layer and located between the first etching stop layer and the gate electrode. The gate isolation layer has first corners abutting against the inner sidewalls of the first etching stop layer.
In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. The method has steps as follows; forming a first nitride-based semiconductor layer; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer; forming a first etching stop layer over the second nitride-based semiconductor layer; forming a first dielectric layer over the first etching stop layer; removing a  portion of the first dielectric layer to expose the first etching stop layer; removing the exposed portion of the first etching stop layer to form an opening; forming a gate isolation layer over the second nitride-based semiconductor layer and extending to the opening; forming a gate electrode over the gate isolation layer.
In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first etching stop layer, a second etching stop layer, a gate isolation layer, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The first etching stop layer is disposed over the second nitride-based semiconductor layer. The second etching stop layer is disposed over the first etching stop layer. The gate isolation layer is disposed over the second nitride-based semiconductor layer and extends from the first etching stop layer to the second etching stop layer. The gate electrode is disposed over the first etching stop layer and the second etching stop layer and separated from the first etching stop layer and the second etching stop layer by the gate isolation layer.
By the above configuration, the etching stop layer extending from the gate isolation layer to other component can be electrically isolated from the gate electrode, which results in block of leakage current from the gate electrode.
Brief Description of the Drawings:
Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:
FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and
FIG. 2A, FIG. 2B, FIG. 2C, FIG 2D, FIG. 2E, FIG. 2F, FIG. 2G, FIG. 2H, FIG. 2I, FIG. 2J, and FIG. 2K show different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present disclosure.
Detailed Description:
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure  will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.
Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.
In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. The nitride-based semiconductor device 1A includes a substrate 10, nitride-based  semiconductor layers  12, 14,  etching stop layer  20, 24, 27, a gate dielectric layer 22,  dielectric layers  26, 28, 30, 32, 34, 36, an isolation structure 38,  electrodes  40, 42, a conductive layer 44, a gate isolation layer 50, a gate electrode 52, patterned  conductive layers  60, 66,  contact vias  62, 64, 68, and pads 70.
The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.
In some embodiments, the nitride-based semiconductor device 1A may further include a buffer layer (not illustrated) . The buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.
The nitride-based semiconductor layer 12 can be disposed on/over/above the buffer layer. The nitride-based semiconductor layer 14 can be disposed on/over/above the nitride-based semiconductor layer 12. The exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In xAl yGa  (1–x–y) N where x+y ≤ 1, Al xGa  (1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In xAl yGa  (1–x–y) N where x+y ≤ 1, Al yGa  (1–y) N where y ≤ 1.
The exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 12 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 14 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 12 and 14 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
The etching stop layer 20 is disposed over the nitride-based semiconductor layer 14. The etching stop layer 20 can cover the nitride-based semiconductor layer 14.
The gate dielectric layer 22 is disposed over the etching stop layer 20. The gate dielectric layer 22 covers the etching stop layer 20.
The etching stop layer 20 can keep stable at an etching stage of the gate dielectric layer 22. The etching stop layer 20 and the gate dielectric layer 22 have different materials. In some embodiments, the etching stop layer 20 includes AlN and the gate dielectric layer 22 includes SiN. In some embodiments, the etching stop layer 20 is an aluminum nitride layer and the gate dielectric layer 22 is a silicon nitride layer. The etching stop layer 20 is thinner than the gate dielectric layer 22. In some embodiments, the etching stop layer 20 has a thickness in a range from about 1 nm to 3 nm. In some embodiments, the gate dielectric layer 22 has a thickness in a range from about 25 nm to about 35 nm.
The etching stop layer 24 is disposed over the nitride-based semiconductor layer 14. The etching stop layer 24 is disposed over the etching stop layer 20 and the gate dielectric layer 22. The etching stop layer 24 has inner sidewalls facing each other.
The dielectric layer 26 is disposed over the etching stop layer 24. The dielectric layer 26 has inner sidewalls facing each other. The dielectric layer 26 covers the etching stop layer 24.
The etching stop layer 24 can keep stable at an etching stage of the dielectric layer 26. The etching stop layer 24 and the dielectric layer 26 have different materials. In some embodiments, the etching stop layer 24 includes AlN and the dielectric layer 26 includes oxide compound, such as SiO x. In some embodiments, the etching stop layer 24 is an aluminum nitride layer and the dielectric layer 26 is a silicon oxide layer. The etching stop layer 24 is thinner than the dielectric layer 26. In some embodiments, the etching stop layer 24 has a thickness in a range from about 1 nm to 3 nm. In some embodiments, the gate dielectric layer 22 has a thickness in a range from about 15 nm to about 25 nm.
The etching stop layer 27 is disposed over the nitride-based semiconductor layer 14. The etching stop layer 27 is disposed over the etching stop layer 24 and the dielectric layer 26. The etching stop layer 27 has inner sidewalls facing each other. A distance between the inner sidewalls of the etching stop layer 27 is greater than a distance between the inner sidewalls of the etching stop layer 24. A distance between the inner sidewalls of the etching stop layer 27 is greater than a distance between the inner sidewalls of the dielectric layer 26.
The dielectric layer 28 is disposed over the etching stop layer 27. The dielectric layer 28 has inner sidewalls facing each other. The dielectric layer 28 covers the etching stop layer 27. A distance between the inner sidewalls of the dielectric layer 28 is greater than a distance between  the inner sidewalls of the etching stop layer 24. A distance between the inner sidewalls of the dielectric layer 28 is greater than a distance between the inner sidewalls of the dielectric layer 26.
The etching stop layer 27 can keep stable at an etching stage of the dielectric layer 28. The etching stop layer 27 and the dielectric layer 28 have different materials. In some embodiments, the etching stop layer 27 includes AlN and the dielectric layer 28 includes oxide compound, such as SiO x. In some embodiments, the etching stop layer 27 is an aluminum nitride layer and the dielectric layer 28 is a silicon oxide layer. The etching stop layer 27 is thinner than the dielectric layer 28. In some embodiments, the etching stop layer 27 has a thickness in a range from about 1 nm to 3 nm. In some embodiments, the dielectric layer 28 has a thickness in a range from about 50 nm to about 70 nm.
In some embodiments, the etching stop layers 20, 24, 27 are parallel with each other. In some embodiments, the etching stop layers 20, 24, 27 have the same material or compound, which is different than those of the gate dielectric layer 22, the dielectric layer 26, and the dielectric layer 28. In some embodiments, the dielectric layer 26 and the dielectric layer 28 have the same material or compound, which is different than that of the gate dielectric layer 22.
The dielectric layer 30 is disposed over the dielectric layer 28. The dielectric layer 30 covers the dielectric layer 28. The dielectric layer 30 has inner sidewalls facing each other. A distance between the inner sidewalls of the dielectric layer 30 is substantially the same as a distance between the inner sidewalls of the dielectric layer 28. In some embodiments, the dielectric layer 28 includes oxide compound, such as SiO x. In some embodiments, the dielectric layer 30 is a silicon oxide layer.
The  electrodes  40 and 42 are disposed over the nitride-based semiconductor layer 14. The electrode 40 can be covered by the dielectric layer 30. The electrode 40 can penetrate the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, the etching stop layer 24, the gate dielectric layer 22, and the etching stop layer 20 in sequence to make contact with the nitride-based semiconductor layer 14. The electrode 42 can be covered by the dielectric layer 30. The electrode 42 can penetrate the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, the etching stop layer 24, the gate dielectric layer 22, and the etching stop layer 20 in sequence to make contact with the nitride-based semiconductor layer 14. Each of the  electrodes  40 and 42 can serve as a source electrode or a drain electrode. In some embodiments, the  electrodes  40 and 42 can be called ohmic electrodes. The conductive layer 44 is located between the dielectric layer 28 and the electrode 40 and located between the dielectric layer 28 and the electrode 42. The conductive layer 44 include TiN.
In some embodiments, the  electrodes  40 and 42 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) ,  compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the  electrodes  40 and 42 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The  electrodes  40 and 42 may be a single layer, or plural layers of the same or different composition. In some embodiments, the  electrodes  40 and 42 can form ohmic contact with the nitride-based semiconductor layer 14. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the  electrodes  40 and 42.
In some embodiments, each of the  electrodes  40 and 42 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.
A gate isolation layer 50 is disposed over the nitride-based semiconductor layer 14. The gate isolation layer 50 is located between the  electrodes  40 and 42. The gate isolation layer 50 is located over the etching stop layer 20 and the gate dielectric layer 22, such that the etching stop layer 20 and the gate dielectric layer 22 are between nitride-based semiconductor layer 14 and the gate isolation layer 50. The gate isolation layer 50 can make contact with a top surface of the gate dielectric layer 22. The gate isolation layer 50 can make contact with a top surface and the inner sidewalls of the dielectric layer 26. The gate isolation layer 50 can extend from the etching stop layer 24 to the etching stop layer 27. More specifically, the gate isolation layer 50 can extend from the top surface of the gate dielectric layer 22 to a top surface of the dielectric layer 30. The gate isolation layer 50 can extend along the inner sidewalls of the dielectric layer 30, the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, the etching stop layer 24. The inner sidewalls of the etching stop layers 24 and 27 are in contact with the gate isolation layer 50. The gate isolation layer 50 has a stepwise profile. In some embodiments, the material of the gate isolation layer 50 can include, for example but are not limited to, dielectric materials. For example, the gate isolation layer 50 can include SiN x, SiO x, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof.
The gate electrode 52 is disposed over the dielectric layer 30, the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, the etching stop layer 24, the gate dielectric layer 22, and the etching stop layer 20. The gate isolation layer 50 is located between the etching stop layer 24 and the gate electrode 52. The gate isolation layer 50 is located between the etching stop layer 27 and the gate electrode 52. The gate electrode 52 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo,  TiN, TaN, metal alloys or compounds thereof, or other metallic compounds. The  electrodes  40, 42, and the gate electrode 52 can constitute a depletion mode GaN-based HEMT.
The gate electrode 52 has  portions  522, 524, 526. The portion 524 is located over the portion 522. The portion 524 is wider than the portion 522. The portion 526 is located over the portion 524. The portion 526 is wider than the portion 524. The different widths of the gate electrode 52 is able to function as a multiple field plates configuration. For example, ends of the portion 524 which are out of the portion 522 can serve as a field plate. Similarly, ends of the portion 526 which are out of portion 524 can serve as a field plate.
To achieve such the profile of the gate electrode 52, multiple etching stages are performed prior to the formation of the gate electrode 52. Accordingly, the etching stop layers 24 and 27 are applied thereto. In this regard, a device applying at least one etching stop layer to its structure may result in leakage current because the etching stop layer is possible to become a leakage current path in the structure. To improve such the defect, the configuration of the gate isolation layer 50 and the gate electrode 52 is adapted thereto.
More specifically, the gate isolation layer 50 can at least wrap a bottom surface of the gate electrode 52. Accordingly, the gate electrode 52 can get separated from the etching stop layers 24 and 27 by the gate isolation layer 50. The gate isolation layer 50 can have bottom corners abutting against the inner sidewalls of the etching stop layer 24. The gate isolation layer 50 has a bottom surface connecting one to another of the bottom corners. The gate isolation layer 50 can have middle corners abutting against the inner sidewalls of the etching stop layer 27.
The reason to such the configuration is that the inner sidewalls of the  etching stop layer  24 and 27 are potential to become a leakage current entrance so the gate isolation layer 50 can cover the entrance and isolate the entrance from the gate electrode 52. As such, the etching stop layer 24 extending from the gate isolation layer 50 to the  electrode  40 or 42 is electrically isolated from the gate electrode 52, which results in block of potential leakage current from the gate electrode 52. Similarly, the etching stop layer 27 extending from the gate isolation layer 50 to the  electrode  40 or 42 is electrically isolated from the gate electrode 52, which results in block of potential leakage current from the gate electrode 52. Accordingly, a multiple field plates configuration is achieved by a single gate electrode and reduction of the device reliability is avoided.
The dielectric layer 32 is disposed over the dielectric layer 30. The dielectric layer 32 is disposed over the gate electrode 52. The dielectric layer 32 covers the dielectric layer 30 and the gate electrode 52. In some embodiments, the material of the dielectric layer 32 can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 32 can  include SiN x, SiO x, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof.
The dielectric layer 34 is disposed over the dielectric layer 32. In some embodiments, the material of the dielectric layer 34 can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 34 can include SiN x, SiO x, SiON, SiC, SiBN, SiCBN, oxides, nitrides, PEOX, or combinations thereof.
The dielectric layer 36 is disposed over the dielectric layer 34. In some embodiments, the material of the dielectric layer 34 can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 34 can include SiN x, SiO x, SiON, SiC, SiBN, SiCBN, oxides, nitrides, PEOX, or combinations thereof.
The isolation structure 38 is disposed over the nitride-based semiconductor layer 12. The isolation structure 38 can extend from the nitride-based semiconductor layer 12 to the dielectric layer 32 and further to a bottom surface of the dielectric layer 34. The isolation structure 38 can be doped with ions to achieve the electrically isolating purpose. The ions can include, for example but are not limited to, nitrogen ion, fluorine ion, oxygen ion, argon atom, aluminum atom, or combinations thereof. These dopants can make the isolation structure 38 have a high resistivity and thus act as an electrically isolating region.
The patterned conductive layer 60 is disposed on the dielectric layer 32. The patterned conductive layer 60 is covered by the dielectric layer 34. The patterned conductive layer 60 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 60 can form at least one circuit. The patterned conductive layer 60 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.
The contact vias 62 are disposed within the  dielectric layers  32 and 34. The contact vias 62 extend longitudinally so as to electrically connect the  electrodes  40 and 42. The exemplary materials of the contact vias 62 can include, but are not limited to, conductive materials, for example, metal or alloys.
The contact vias 64 are disposed within the dielectric layer 34. The contact vias 64 extend longitudinally so as to electrically connect the patterned conductive layer 60. The exemplary materials of the contact vias 64 can include, but are not limited to, conductive materials, for example, metal or alloys.
The patterned conductive layer 66 is disposed on the dielectric layer 34. The patterned conductive layer 66 is covered by the dielectric layer 36. The patterned conductive layer 66 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 66 can form at least one circuit. The patterned conductive layer 66 may include a single film or  multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.
The contact vias 68 are disposed within the dielectric layer 36. The contact vias 68 extend longitudinally so as to electrically connect the patterned conductive layer 66. The exemplary materials of the contact vias 66 can include, but are not limited to, conductive materials, for example, metal or alloys.
The pads 70 are disposed on the contact vias 68. The pads 70 are disposed within the dielectric layer 36. The pads 70 can have regions free from coverage from the dielectric layer 36. The pads 70 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.
Different stages of a method for manufacturing the semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG 2D, FIG. 2E, FIG. 2F, FIG. 2G, FIG. 2H, FIG. 2I, FIG. 2J, and FIG. 2K, as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
Referring to FIG. 2A, a substrate 10 is provided. A nitride-based semiconductor layer 12 is formed on the substrate 10. A nitride-based semiconductor layer 14 is formed on the nitride-based semiconductor layer 12. An etching stop layer 20 is formed on the nitride-based semiconductor layer 14. A gate dielectric layer 22 is formed on the etching stop layer 20.
Referring to FIG. 2B, an etching stop layer 24 is formed on the gate dielectric layer 22. A dielectric layer 26 is formed on the etching stop layer 24. An etching stop layer 27 is formed on the dielectric layer 26. A dielectric layer 28 is formed on the etching stop layer 27. A conductive layer 44 is formed on the dielectric layer 28.
Referring to FIG. 2C, the conductive layer 44 is patterned.  Electrodes  40 and 42 are formed over the conductive layer 44. The  electrodes  40 and 42 are formed to penetrate the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, the etching stop layer 24, the gate dielectric layer 22, and the etching stop layer 20 in sequence to make contact with the nitride-based semiconductor layer 14. Prior to the formation of the  electrodes  40 and 42, multiple etching stages are performed. In the etching stages, the etching stop layers 20, 24, 27 can function. For example, during the etching stage of the gate dielectric layer 22, the etching stop layer 20 can keep stable so the nitride-based semiconductor layer 14 can be away from damage at the etching stage of the gate dielectric layer 22.
Referring to FIG. 2D, a dielectric layer 30 is formed on the dielectric layer 28. The dielectric layer 30 covers the  electrodes  40 and 42.
Referring to FIG. 2E, some portions of the  dielectric layers  28 and 30 are removed. After the removal, a portion of the etching stop layer 27 is exposed. The removal of the  dielectric layers  28 and 30 can be achieved by using an etching stage. The etching stop layer 27 can serve as an etching stop function during the etching stage of the  dielectric layers  28 and 30. For example, the etching stop layer 27 and the  dielectric layers  28 and 30 have different etching rates with respect to the same etchant applied to the etching stage.
Referring to FIG. 2E, some portions of the  dielectric layers  28 and 30 are removed. After the removal, a portion of the etching stop layer 27 is exposed. The removal of the  dielectric layers  28 and 30 can be achieved by using an etching stage. The etching stop layer 27 can serve as an etching stop function during the etching stage of the  dielectric layers  28 and 30. For example, the etching stop layer 27 and the  dielectric layers  28 and 30 have different etching rates with respect to the same etchant applied to the etching stage.
Referring to FIG. 2F, the exposed portion of the etching stop layer 27 is removed to form an opening such that a portion of the dielectric layer 26 is exposed from the opening. The removal of the etching stop layer 27 can be achieved by using an etching stage. Removing the portions of the  dielectric layers  28 and 30 as described in FIG. 2E and removing the exposed portion of the etching stop layer 27 as described in FIG. 2F are performed by using different etchants. Furthermore, the dielectric layer 26 can almost keep free from damage during the etching stage due to a high etching selectivity.
Referring to FIG. 2G, a portion of the dielectric layer 26 is removed. After the removal, a portion of the etching stop layer 24 is exposed. The removal of the dielectric layer 26 can be achieved by using an etching stage. The etching stop layer 24 can serve as an etching stop function during the etching stage of the dielectric layer 26. For example, the etching stop layer 24 and the dielectric layer 26 have different etching rates with respect to the same etchant applied to the etching stage of the dielectric layer 26. Thereafter, the exposed portion of the etching stop layer 24 is removed to form an opening such that a portion of the gate dielectric layer 22 is exposed from the opening. The removal of the etching stop layer 24 can be achieved by using an etching stage. Removing the portion of the dielectric layer 26 and removing the exposed portion of the etching stop layer 24 are performed by using different etchants. Furthermore, the gate dielectric layer 22 can almost keep free from damage during the etching stage of the etching stop layer 24 due to a high etching selectivity.
By the multiple etching stages, a stepwise profile can be formed.
Referring to FIG. 2H, a gate isolation layer 50 is formed over the nitride-based semiconductor layer 14. The gate isolation layer 50 is formed to extend into the openings of the etching stop layers 24 and 27. The gate isolation layer 50 can be formed to extend from the dielectric layer 30 to the gate dielectric layer 22 through the dielectric layer 28, the etching stop layer 27, the dielectric layer 26, and the etching stop layer 24.
Referring to FIG. 2I, a gate electrode 52 is formed over the gate isolation layer 50. The gate electrode 52 is physically separated from the etching stop layers 24 and 27 by the gate isolation layer 52.
Referring to FIG. 2J, a dielectric layer 32 is formed over the gate electrode 52. A patterned conductive layer 60 is formed on the dielectric layer 32. An isolation structure 38 is formed by doping ions into the structure.
Referring to FIG. 2K, a dielectric layer 34 is formed over the dielectric layer 32. Contact vias 62 and 64 are formed within the dielectric layer 34. A conductive layer 66 is formed on the dielectric layer 34. The conductive layer 66 can be patterned after the formation thereof. Thereafter, a dielectric layer, contact vias, and pads are formed over the dielectric layer 34 to obtain the structure as described in FIG. 1.
The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.
As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.
As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases  where one or more intervening components are located between the former component and the latter component.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims (25)

  1. A nitride-based semiconductor device, comprising:
    a first nitride-based semiconductor layer;
    a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;
    a first etching stop layer disposed over the second nitride-based semiconductor layer and having inner sidewalls facing each other;
    a gate electrode disposed over the first etching stop layer; and
    a gate isolation layer disposed over the second nitride-based semiconductor layer and located between the first etching stop layer and the gate electrode, wherein the gate isolation layer has first corners abutting against the inner sidewalls of the first etching stop layer.
  2. The nitride-based semiconductor device according to any one of the preceding claims, wherein the gate isolation layer has a bottom surface connecting one to another of the first corners.
  3. The nitride-based semiconductor device according to any one of the preceding claims, further comprising:
    a second etching stop layer disposed over the first etching stop layer and having inner sidewalls facing each other, wherein the gate isolation layer has second corners abutting against the inner sidewalls of the second etching stop layer.
  4. The nitride-based semiconductor device according to any one of the preceding claims, wherein a distance between the inner sidewalls of the second etching stop layer is greater than a distance between the inner sidewalls of the first etching stop layer.
  5. The nitride-based semiconductor device according to any one of the preceding claims, further comprising:
    a first dielectric layer disposed between the first etching stop layer and the second etching stop layer and comprising at least one material which is different than the first etching stop layer and the second etching stop layer.
  6. The nitride-based semiconductor device according to any one of the preceding claims, wherein the first dielectric layer has a top surface in contact with the gate isolation layer.
  7. The nitride-based semiconductor device according to any one of the preceding claims, wherein the first dielectric layer has inner sidewalls in contact with the gate isolation layer.
  8. The nitride-based semiconductor device according to any one of the preceding claims, wherein the gate isolation layer has a stepwise profile.
  9. The nitride-based semiconductor device according to any one of the preceding claims, wherein the gate electrode has a first portion and a second portion over the first portion and wider than the first portion.
  10. The nitride-based semiconductor device according to any one of the preceding claims, further comprising a gate dielectric layer disposed between the second nitride-based semiconductor layer and the gate isolation layer.
  11. The nitride-based semiconductor device according to any one of the preceding claims0, further comprising a third etching stop layer disposed between the second nitride-based semiconductor layer and the gate isolation layer.
  12. The nitride-based semiconductor device according to any one of the preceding claims, further comprising:
    a source electrode disposed over the second nitride-based semiconductor layer and penetrating the first etching stop layer
  13. The nitride-based semiconductor device according to any one of the preceding claims, wherein the first etching stop layer extends from the gate isolation layer to the source electrode.
  14. The nitride-based semiconductor device according to any one of the preceding claims, wherein the gate isolation layer at least wraps a bottom surface of the gate electrode.
  15. The nitride-based semiconductor device according to any one of the preceding claims, wherein the first etching stop layer comprises an aluminum nitride layer.
  16. A method for manufacturing a nitride-based semiconductor device, comprising:
    forming a first nitride-based semiconductor layer;
    forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;
    forming a first etching stop layer over the second nitride-based semiconductor layer;
    forming a first dielectric layer over the first etching stop layer;
    removing a portion of the first dielectric layer to expose the first etching stop layer;
    removing the exposed portion of the first etching stop layer to form an opening;
    forming a gate isolation layer over the second nitride-based semiconductor layer and extending to the opening; and
    forming a gate electrode over the gate isolation layer.
  17. The method according to any one of the preceding claims, wherein the first etching stop layer and the first dielectric layer have different etching rates with respect to the same etchant.
  18. The method according to any one of the preceding claims, wherein the gate electrode is physically separated from the first etching stop layer by the gate isolation layer.
  19. The method according to any one of the preceding claims, further comprising forming a source electrode prior to removing the portion of the first dielectric layer.
  20. The method according to any one of the preceding claims, wherein removing the portion of the first dielectric layer and removing the exposed portion of the first etching stop layer are performed by using different etchants.
  21. A nitride-based semiconductor device, comprising:
    a first nitride-based semiconductor layer;
    a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;
    a first etching stop layer disposed over the second nitride-based semiconductor layer;
    a second etching stop layer disposed over the first etching stop layer;
    a gate isolation layer disposed over the second nitride-based semiconductor layer and extending from the first etching stop layer to the second etching stop layer; and
    a gate electrode disposed over the first etching stop layer and the second etching stop layer and separated from the first etching stop layer and the second etching stop layer by the gate isolation layer.
  22. The nitride-based semiconductor device according to any one of the preceding claims, wherein the first etching stop layer and the second etching stop layer are parallel with each other.
  23. The nitride-based semiconductor device according to any one of the preceding claims, further comprising:
    a source electrode disposed over the second nitride-based semiconductor layer and penetrating the first etching stop layer and the second etching stop layer.
  24. The nitride-based semiconductor device according to any one of the preceding claims, wherein the first etching stop layer and the second etching stop layer extend from the gate isolation layer to the source electrode.
  25. The nitride-based semiconductor device according to any one of the preceding claims, wherein the first etching stop layer and the second etching stop layer comprise the same compound.
PCT/CN2022/129174 2022-11-02 2022-11-02 Nitride-based semiconductor device and method for manufacturing the same WO2024092543A1 (en)

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US20170271492A1 (en) * 2016-03-17 2017-09-21 Taiwan Semiconductor Manufacturing Company Ltd. High-electron-mobility transistor (hemt) capable of protecting iii-v compound layer
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US20110049526A1 (en) * 2009-08-28 2011-03-03 Transphorm Inc. Semiconductor Devices with Field Plates
US20170271492A1 (en) * 2016-03-17 2017-09-21 Taiwan Semiconductor Manufacturing Company Ltd. High-electron-mobility transistor (hemt) capable of protecting iii-v compound layer
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CN111952366A (en) * 2020-08-19 2020-11-17 深圳方正微电子有限公司 Field effect transistor and method of making the same

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