WO2024082363A1 - Semiconductor structure and manufacturing method therefor - Google Patents

Abstract

The embodiments of the present disclosure relate to the technical field of semiconductors. Provided are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, the direction perpendicular to a surface of the substrate being a first direction; a distribution layer, which is located in the substrate and comprises a capacitor region, wherein the distribution layer in the capacitor region comprises at least one electrically conductive structure, the electrically conductive structure comprises a plurality of first electrically conductive layers and a plurality of second electrically conductive layers, and the first electrically conductive layers and the second electrically conductive layers are alternately arranged spaced apart in a plane perpendicular to the first direction; a first capacitor electrode, which comprises at least the plurality of first electrically conductive layers in one electrically conductive structure; a second capacitor electrode, which comprises at least the plurality of second electrically conductive layers in one electrically conductive structure; and a dielectric layer, which is at least located in a gap between the first capacitor electrode and the second capacitor electrode that are adjacent to each other, wherein the first capacitor electrode, the second capacitor electrode and the dielectric layer form a capacitor structure. The embodiments of the present disclosure are at least conducive to increasing the depth of the capacitor structure in the first direction and increasing the capacitance of the capacitor structure.

Description

Semiconductor structure and method for manufacturing the same

cross reference

This application claims priority to the Chinese patent application entitled “Semiconductor Structure and Manufacturing Method Thereof” and application number 202211269069.5, filed on October 17, 2022, which is incorporated herein by reference in its entirety.

Technical Field

The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same.

Background technique

Traditional 2.5D integrated circuit packaging integrates storage/logic/chipsets in a single package structure, with better performance and lower power consumption. Among them, the silicon adapter plays the role of interconnection between various chips, substrates and printed circuit boards (PCBs). Therefore, the silicon adapter has multiple through-silicon vias (TSVs) and multiple redistribution layers (RDLs).

However, with the increase in the integration density of integrated circuits, there is a large electrical interference between the TSV and RDL in the silicon adapter board, so an anti-interference structure is set in the silicon adapter board, for example, a trench capacitor structure used as a decoupling capacitor or a bypass capacitor. The capacitance of the trench capacitor structure is a key factor in improving the anti-interference capability of the anti-interference structure.

Summary of the invention

The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial for increasing the depth of the capacitor structure along the first direction and increasing the capacitance of the capacitor structure.

According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a substrate, a direction perpendicular to the surface of the substrate is a first direction; a wiring layer located in the substrate, the wiring layer includes a capacitor area, the wiring layer in the capacitor area includes at least one conductive structure, the conductive structure includes multiple first conductive layers and multiple second conductive layers, the first conductive layers and the second conductive layers are spaced and alternately arranged on a plane perpendicular to the first direction; at least one first capacitor electrode of the first conductive layer in the conductive structure; at least one second capacitor electrode of the second conductive layer in the conductive structure; a dielectric layer, at least located in the gap between adjacent first capacitor electrodes and second capacitor electrodes, the first capacitor electrode, the second capacitor electrode and the dielectric layer constitute a capacitor structure.

In some embodiments, the wiring layer of the capacitor region includes a plurality of the conductive structures arranged at intervals, and one of the conductive structures corresponds to one of the capacitor structures.

In some embodiments, a plane perpendicular to the first direction is a reference plane, the first conductive layer and the second conductive layer each have a reference point in a corresponding area, and the connecting lines formed by the multiple reference points on the reference plane serve as capacitor electrode row wiring, and the capacitor electrode row wiring is a straight line or a broken line.

In some embodiments, the conductive structure further includes a third conductive layer and a fourth conductive layer; wherein the third conductive layer is electrically connected to multiple first conductive layers in the conductive structure, and the third conductive layer and multiple first conductive layers in one of the conductive structures constitute the first capacitor electrode; the fourth conductive layer is electrically connected to multiple second conductive layers in the conductive structure, and the fourth conductive layer and multiple second conductive layers in one of the conductive structures constitute the second capacitor electrode.

In some embodiments, the wiring layer of the capacitor region includes a plurality of contact-connected sub-wiring layers stacked along the first direction, the sub-wiring layer includes at least one sub-conductive structure, the sub-conductive structure includes a first sub-conductive layer and a second sub-conductive layer, the first sub-conductive layer and the second sub-conductive layer are spaced and alternately arranged on a plane perpendicular to the first direction; wherein, in the conductive structure, the first capacitor electrode includes a plurality of the first sub-conductive layers stacked along the first direction, and the second capacitor electrode includes a plurality of the second sub-conductive layers stacked along the first direction.

In some embodiments, the third conductive layer includes: multiple third sub-conductive layers, one third sub-conductive layer is in contact and connected with one first conductive layer; wherein the multiple third sub-conductive layers are arranged in the same layer, or the multiple third sub-conductive layers are respectively in contact and connected with the first sub-conductive layers in different layers among the multiple first conductive layers; and at least one first electrical connection layer, the first electrical connection layer is in contact and connected with two adjacent third sub-conductive layers.

In some embodiments, the fourth conductive layer includes: multiple fourth sub-conductive layers, one fourth sub-conductive layer is in contact and connected with one second conductive layer; wherein the multiple fourth sub-conductive layers are arranged in the same layer; or, the multiple fourth sub-conductive layers are respectively in contact and connected with multiple second sub-conductive layers in different layers of the second conductive layer; and at least one second electrical connection layer, the second electrical connection layer is in contact and connected with two adjacent fourth sub-conductive layers.

In some embodiments, a direction perpendicular to at least a portion of the capacitor electrode array wiring is a first reference direction; among the multiple first sub-conductive layers stacked along the first direction, the lengths of the multiple first sub-conductive layers in the first reference direction are equal or unequal; among the multiple second sub-conductive layers stacked along the first direction, the lengths of the multiple second sub-conductive layers in the first reference direction are equal or unequal.

In some embodiments, a direction parallel to at least a portion of the capacitor electrode array wiring is a second reference direction; among the multiple first sub-conductive layers stacked along the first direction, the widths of the multiple first sub-conductive layers in the second reference direction are equal or unequal; among the multiple second sub-conductive layers stacked along the first direction, the widths of the multiple second sub-conductive layers in the second reference direction are equal or unequal.

In some embodiments, among the multiple first sub-conductive layers stacked along the first direction, the heights of the multiple first sub-conductive layers in the first direction are equal or different; among the multiple second sub-conductive layers stacked along the first direction, the heights of the multiple second sub-conductive layers in the first direction are equal or different.

In some embodiments, the wiring layer further includes a first lead-out structure and a second lead-out structure, wherein the first lead-out structure is electrically connected to one of the first capacitor electrode and the second capacitor electrode, and the second lead-out structure is electrically connected to the other of the first capacitor electrode and the second capacitor electrode.

In some embodiments, the first lead-out structure includes a first lead line at least partially located on the surface of the substrate, and the second lead-out structure includes a second lead line at least partially located on the surface of the substrate.

According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, comprising: providing a substrate, wherein a direction perpendicular to a surface of the substrate is a first direction; forming a wiring layer and an initial interlayer dielectric layer in the substrate that at least surrounds a sidewall of the wiring layer extending along the first direction, wherein the wiring layer includes a capacitor region, the wiring layer in the capacitor region includes at least one conductive structure, the conductive structure includes a plurality of first conductive layers and a plurality of second conductive layers, the first conductive layers and the second conductive layers are spaced and alternately arranged on a plane perpendicular to the first direction, the first capacitor electrode includes a plurality of the first conductive layers in the conductive structure, and the second capacitor electrode includes a plurality of the second conductive layers in the conductive structure; removing the initial interlayer dielectric layer in the capacitor region to form a gap between the first capacitor electrode and the second capacitor electrode; and forming a dielectric layer that fills the gap.

In some embodiments, the first capacitor electrode, the second capacitor electrode and the dielectric layer constitute a capacitor junction; the step of forming the wiring layer includes: forming a plurality of the conductive structures arranged at intervals in the capacitor region, one conductive structure corresponding to one capacitor structure.

In some embodiments, the forming of the first capacitor electrode and the second capacitor electrode further includes: forming a third conductive layer in the substrate, the third conductive layer being electrically connected to multiple first conductive layers in the conductive structure, and the third conductive layer and multiple first conductive layers in the conductive structure constitute the first capacitor electrode; forming a fourth conductive layer in the substrate, the fourth conductive layer being electrically connected to multiple second conductive layers in the conductive structure, and the fourth conductive layer and multiple second conductive layers in the conductive structure constitute the second capacitor electrode.

In some embodiments, the steps of forming the first conductive layer and the second conductive layer include: forming a plurality of first sub-conductive layers stacked along the first direction in the capacitor region to form the first conductive layer; forming a plurality of second sub-conductive layers stacked along the first direction in the capacitor region to form the second conductive layer; wherein the first sub-conductive layers and the second sub-conductive layers spaced and alternately arranged on a plane perpendicular to the first direction constitute a sub-conductive structure, and the plurality of sub-conductive structures stacked along the first direction constitute the conductive structure.

In some embodiments, the step of forming the third conductive layer includes: forming multiple third sub-conductive layers, wherein one third sub-conductive layer is in contact and connected with one first conductive layer; wherein the multiple third sub-conductive layers are arranged in the same layer; or, the multiple third sub-conductive layers are respectively in contact and connected with multiple first sub-conductive layers in different layers of the first conductive layer; forming at least one first electrical connection layer, wherein the first electrical connection layer is in contact and connected with two adjacent third sub-conductive layers.

In some embodiments, the step of forming the fourth conductive layer includes: forming multiple fourth sub-conductive layers, wherein one fourth sub-conductive layer is in contact and connected with one second conductive layer; wherein the multiple fourth sub-conductive layers are arranged in the same layer; or, the multiple fourth sub-conductive layers are respectively in contact and connected with multiple second sub-conductive layers in different layers of the second conductive layer; forming at least one second electrical connection layer, wherein the second electrical connection layer is in contact and connected with two adjacent fourth sub-conductive layers.

In some embodiments, the step of forming the wiring layer also includes: forming a first lead-out structure, the first lead-out structure is electrically connected to one of the first capacitor electrode and the second capacitor electrode; forming a second lead-out structure, the second lead-out structure is electrically connected to the other of the first capacitor electrode and the second capacitor electrode.

In some embodiments, the step of forming the first lead-out structure includes: forming a first lead at least partially located on the surface of the substrate; the step of forming the second lead-out structure includes: forming a second lead at least partially located on the surface of the substrate.

The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

Using the wiring layer located in the capacitor region of the substrate, i.e., RDL, as the first capacitor electrode and the second capacitor electrode of the capacitor structure is conducive to simplifying the process steps of preparing the capacitor structure and reducing the number of required masks. Moreover, by virtue of the characteristics of the wiring layer, it is conducive to increasing the depth of the capacitor structure in the first direction, and designing the staggered arrangement of the first capacitor electrode and the second capacitor electrode, thereby increasing the facing area of the first capacitor electrode and the second capacitor electrode to increase the capacitance of the capacitor structure. It is understandable that the capacitor structure located in the substrate can be used as a decoupling capacitor or a bypass capacitor to reduce the electrical interference between the electrical connection layers in the substrate, thereby facilitating the improvement of the signal-to-noise ratio of the semiconductor structure by increasing the capacitance of the capacitor structure, thereby improving the anti-interference ability of the circuit structure composed of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

1 and 2 are schematic diagrams of two partial cross-sectional structures of a semiconductor structure provided by an embodiment of the present disclosure;

3 to 5 are schematic diagrams of three top views of the first conductive layer and the second conductive layer in the semiconductor structure provided in an embodiment of the present disclosure;

6 and 7 are schematic diagrams of two partial three-dimensional structures of a capacitor structure in a semiconductor structure provided in an embodiment of the present disclosure;

FIG8 is a schematic diagram of a top view of the structure shown in FIG6 or FIG7;

9 and 10 are schematic diagrams of two other partial three-dimensional structures of a capacitor structure in a semiconductor structure provided in an embodiment of the present disclosure;

FIG11 is a schematic diagram of another partial three-dimensional structure of a capacitor structure in a semiconductor structure provided by an embodiment of the present disclosure;

FIG12 is a partial cross-sectional view of a capacitor structure in a semiconductor structure provided by an embodiment of the present disclosure;

13 and 14 are schematic diagrams of two partial three-dimensional structures of a wiring layer in a semiconductor structure provided in an embodiment of the present disclosure;

15 and 16 are schematic partial cross-sectional views corresponding to the steps of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure.

Detailed ways

The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the semiconductor structure, the wiring layer located in the capacitor region of the substrate, that is, RDL, is used as the first capacitor electrode and the second capacitor electrode of the capacitor structure, which is conducive to simplifying the process steps of preparing the capacitor structure and reducing the number of required masks. Moreover, by virtue of the characteristics of the wiring layer, it is conducive to increasing the depth of the capacitor structure in the first direction, and designing the staggered arrangement of the first capacitor electrode and the second capacitor electrode, thereby increasing the facing area of the first capacitor electrode and the second capacitor electrode to increase the capacitance of the capacitor structure. It can be understood that the capacitor structure located in the substrate can be used as a decoupling capacitor or a bypass capacitor to reduce the electrical interference between the electrical connection layers in the substrate, which is conducive to improving the signal-to-noise ratio of the semiconductor structure by increasing the capacitance of the capacitor structure, thereby improving the anti-interference ability of the circuit structure composed of the semiconductor structure.

The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

An embodiment of the present disclosure provides a semiconductor structure, and the semiconductor structure provided by an embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Figures 1 and 2 are schematic diagrams of two partial cross-sectional structures of the semiconductor structure provided by an embodiment of the present disclosure; Figures 3 to 5 are schematic diagrams of three top-view structures of the first conductive layer and the second conductive layer in the semiconductor structure provided by an embodiment of the present disclosure; Figures 6 and 7 are schematic diagrams of two partial three-dimensional structures of the capacitor structure in the semiconductor structure provided by an embodiment of the present disclosure; Figure 8 is a schematic diagram of the top-view structure of the structure shown in Figure 6 or Figure 7; Figures 9 and 10 are schematic diagrams of two other partial three-dimensional structures of the capacitor structure in the semiconductor structure provided by an embodiment of the present disclosure; Figure 11 is another partial three-dimensional structure schematic diagram of the capacitor structure in the semiconductor structure provided by an embodiment of the present disclosure; Figure 12 is a partial cross-sectional view of the capacitor structure in the semiconductor structure provided by an embodiment of the present disclosure; Figures 13 and 14 are schematic diagrams of two partial three-dimensional structures of the wiring layer in the semiconductor structure provided by an embodiment of the present disclosure.

It should be noted that, for the convenience of illustration, the dielectric layer and other film layers in the semiconductor structure except the wiring layer are not shown in FIGS. 6 to 14 .

1 to 14 , the semiconductor structure includes: a substrate 100, wherein a direction perpendicular to the surface of the substrate 100 is a first direction X; a wiring layer 101 located in the substrate 100, wherein the wiring layer 101 includes a capacitor region 111, wherein the wiring layer 101 in the capacitor region 111 includes at least one conductive structure 121, wherein the conductive structure 121 includes a plurality of first conductive layers 131 and a plurality of second conductive layers 141, wherein the first conductive layers 131 and the second conductive layers 141 are spaced apart and alternately arranged on a plane perpendicular to the first direction X; a first capacitor electrode 151 including at least a plurality of first conductive layers 131 in one conductive structure 121; a second capacitor electrode 161 including at least a plurality of second conductive layers 141 in one conductive structure 121; and a dielectric layer 102 located at least in the interval between adjacent first capacitor electrodes 151 and second capacitor electrodes 161, wherein the first capacitor electrode 151, the second capacitor electrode 161 and the dielectric layer 102 constitute a capacitor structure 103.

It is understandable that when designing the wiring layer 101, designing the wiring layer 101 in a certain area as the wiring layer 101 of the capacitor region 111, and using the wiring layer 101 of the capacitor region 111 as the first capacitor electrode 151 and the second capacitor electrode 161 of the capacitor structure 103 is conducive to simplifying the process steps of preparing the capacitor structure 103. Among them, one of the first capacitor electrode 151 and the second capacitor electrode 161 is used as the upper electrode of the capacitor structure 103, and the other is used as the lower electrode of the capacitor structure 103.

It should be noted that the wiring layer 101 may include a layer of conductive structure 121, and may also include a multi-layer conductive structure 121 stacked along the first direction X. Moreover, the conductive structure 121 includes multiple first conductive layers 131 and multiple second conductive layers 141. The first conductive layers 131 and the second conductive layers 141 are spaced and alternately arranged on a plane perpendicular to the first direction X, that is, the second conductive layers 141 are spaced between adjacent first conductive layers 131, and the first conductive layers 131 are spaced between adjacent second conductive layers 141. Thus, on the one hand, when the plurality of first conductive layers 131 are used as the first capacitor electrode 151 and the plurality of second conductive layers 141 are used as the second capacitor electrode 161, the first capacitor electrode 151 at least includes the plurality of first conductive layers 131 in the conductive structure 121, and the second capacitor electrode 161 at least includes the plurality of second conductive layers 141 in the conductive structure 121, which is conducive to designing the staggered arrangement of the first capacitor electrode 151 and the second capacitor electrode 161, thereby facilitating the increase of the facing area of the first capacitor electrode 151 and the second capacitor electrode 161; on the other hand, by means of the characteristics of the wiring layer 101, it is conducive to increase the depth of the first capacitor electrode 151 and the second capacitor electrode 161 in the first direction X, so as to increase the depth of the capacitor structure 103 in the first direction X. Therefore, it is conducive to increase the capacitance of the capacitor structure 103 by increasing the facing area of the first capacitor electrode 151 and the second capacitor electrode 161 and the depth of the capacitor structure 103 in the first direction X.

In some embodiments, the capacitor structure 103 located in the substrate 100 can be used as a decoupling capacitor or a bypass capacitor to reduce the electrical interference between the electrical connection layers in the substrate 100, so as to improve the signal-to-noise ratio of the semiconductor structure by increasing the capacitance of the capacitor structure 103, thereby improving the anti-interference ability of the circuit structure composed of the semiconductor structure. In one example, the substrate 100 can be a silicon interposer in a packaging structure, and the capacitor structure 103 is used as a decoupling capacitor or a bypass capacitor in the silicon interposer to improve the signal-to-noise ratio in the silicon interposer.

An embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

In some embodiments, referring to FIG1 , the conductive structure 121 in the wiring layer 101 of the capacitor region 111 is a single film layer structure, and the wiring layer 101 of the capacitor region 111 is also a single film layer structure. In other embodiments, referring to FIG2 , the conductive structure 121 in the wiring layer 101 of the capacitor region 111 is a multi-film layer structure stacked along the first direction X, and the conductive structure 121 is the wiring layer 101, and the wiring layer 101 of the capacitor region 111 is also a multi-film layer structure, and the conductive structure 121 being a multi-film layer structure will be described in detail later.

In some embodiments, the first conductive layer 131 and the second conductive layer 141 are arranged at intervals along the second direction Y and extend along the third direction Z. In one example, the first direction X, the second direction Y and the third direction Z are perpendicular to each other. In practical applications, it is sufficient that the first direction X, the second direction Y and the third direction Z intersect each other.

In some embodiments, referring to FIG. 3 to FIG. 5, the plane perpendicular to the first direction X is the reference plane, the first conductive layer 131 and the second conductive layer 141 each have a reference point p in the corresponding area, and the connection line formed by the multiple reference points p on the reference plane is used as the capacitor electrode array wiring 191, and the capacitor electrode array wiring 191 is a straight line or a broken line. In this way, it is beneficial to improve the diversity of the capacitor structure morphology within a limited layout space. For example, when it is necessary to avoid the device keep-out zone in the semiconductor structure, by adjusting the morphology of the capacitor electrode array wiring 191, it is beneficial to make the capacitor structure and the device keep-out zone not interfere with each other, and not affect the capacitance of the capacitor structure, that is, to improve the compatibility between the capacitor structure and other devices in the semiconductor structure, reduce unnecessary waste of layout space, and thus help to further improve the overall integration of the semiconductor structure.

It should be noted that the first conductive layer 131 and the second conductive layer 141 each have a reference point p in a corresponding region, which means that a reference point p corresponds to a first conductive layer 131 or a second conductive layer 141, and the relative positional relationship between the reference point p corresponding to the first conductive layer 131 and the first conductive layer 131 is the same as the relative positional relationship between the reference point p corresponding to the second conductive layer 141 and the second conductive layer 141. In an example, the reference point p corresponding to the first conductive layer 131 is located at the center of the first conductive layer 131, and the reference point p corresponding to the second conductive layer 141 is located at the center of the second conductive layer 141.

In one example, referring to FIG3 , the capacitor electrode array wiring 191 formed by multiple reference points p on the reference plane is a straight line; in another example, referring to FIG4 and FIG5 , the capacitor electrode array wiring 191 formed by multiple reference points p on the reference plane is a broken line. It can be understood that when the number of first conductive layers 131 and second conductive layers 141 is large, the capacitor electrode array wiring 191 shown in FIG5 can be regarded as a smooth curve.

It should be noted that an embodiment of the present disclosure does not limit the specific presentation form of the capacitor electrode array wiring 191, that is, it does not limit the size of the area facing each other in the second direction Y between the adjacent first conductive layer 131 and the second conductive layer 141. In practical applications, it can be adjusted according to actual needs.

In some embodiments, referring to Figures 2 and 6 to 12, the wiring layer 101 of the capacitor region 111 includes a plurality of sub-wiring layers 113 stacked along the first direction X, the sub-wiring layer 113 includes at least one sub-conductive structure 123, the sub-conductive structure 123 includes a first sub-conductive layer 133 and a second sub-conductive layer 143, the first sub-conductive layer 133 and the second sub-conductive layer 143 are spaced and alternately arranged on a plane perpendicular to the first direction X; wherein, in the conductive structure 121, the first capacitor electrode 151 includes a plurality of first sub-conductive layers 133 stacked along the first direction X, and the second capacitor electrode 161 includes a plurality of second sub-conductive layers 143 stacked along the first direction X.

It can be understood that the first conductive layer 131 may include a plurality of first sub-conductive layers 133 stacked along the first direction X, and the second conductive layer 141 may include a plurality of second sub-conductive layers 143 stacked along the first direction X, and the plurality of first sub-conductive layers 133 in a first conductive layer 131 correspond to the same reference point p (refer to FIG. 3 ) in the capacitor electrode array wiring 191 (refer to FIG. 3 ). In addition, the conductive structure 121 includes first sub-conductive layers 133 and second sub-conductive layers 143 spaced and alternately arranged along the second direction Y, and includes a plurality of first sub-conductive layers 133 stacked along the first direction X and a plurality of second sub-conductive layers 143 stacked along the first direction X.

In addition, the number of layers of the sub-wiring layer 113 is consistent with the number of layers of the sub-conductive structure 123. It should be noted that, in FIGS. 2 to 12 , the wiring layer 101 includes 3 layers of sub-wiring layers 113 stacked along the first direction X as an example. In practical applications, there is no restriction on the number of layers of the sub-wiring layer 113 stacked along the first direction X. For example, the wiring layer 101 may include 2 layers, 5 layers, or 8 layers of sub-wiring layers 113 stacked along the first direction X. In addition, the wiring layer 101 of the capacitor region 111 framed in the dotted frame in FIG. 2 is the sub-wiring layer 113.

The first sub-conductive layer 133 and the second sub-conductive layer 143 are described in detail below.

In some embodiments, referring to Figure 6, a direction perpendicular to at least the local capacitor electrode array wiring 191 (refer to Figure 3) is a first reference direction; among the multiple first sub-conductive layers 133 stacked along the first direction X, the multiple first sub-conductive layers 133 have equal lengths in the first reference direction; among the multiple second sub-conductive layers 143 stacked along the first direction X, the multiple second sub-conductive layers 143 have equal lengths in the first reference direction.

In practical applications, among the multiple first sub-conductive layers 133 stacked along the first direction X, the lengths of the multiple first sub-conductive layers 133 in the first reference direction may be unequal; among the multiple second sub-conductive layers 143 stacked along the first direction X, the lengths of the multiple second sub-conductive layers 143 in the first reference direction may also be unequal. Alternatively, the lengths of the multiple first sub-conductive layers 133 stacked along the first direction X or the multiple second sub-conductive layers 143 stacked along the first direction X in the first reference direction are unequal, and the lengths of the other in the first reference direction are equal. It can be understood that an embodiment of the present disclosure does not limit the size relationship between the lengths of the multiple first sub-conductive layers 133 stacked along the first direction X in the first reference direction, and does not limit the size relationship between the lengths of the multiple second sub-conductive layers 143 stacked along the first direction X in the first reference direction, and can be adjusted according to actual needs.

In one example, referring to FIG6 , the capacitor electrode array wiring 191 is a straight line, and the direction perpendicular to the capacitor electrode array wiring 191 is the first reference direction, that is, the first reference direction is the third direction Z; among the multiple first sub-conductive layers 133 stacked along the first direction X, the multiple first sub-conductive layers 133 have the same length in the third direction Z; among the multiple second sub-conductive layers 143 stacked along the first direction X, the multiple second sub-conductive layers 143 have the same length in the third direction Z. It should be noted that in actual applications, when the capacitor electrode array wiring 191 is a folded line, the first reference directions corresponding to different regions of the conductive structure 121 may be different.

In another example, continuing to refer to Figure 6, on the basis that the lengths of multiple first sub-conductive layers 133 stacked along the first direction X in the third direction Z are equal, and the lengths of multiple second sub-conductive layers 143 stacked along the first direction X in the third direction Z are equal, the length of the first sub-conductive layer 133 in the third direction Z is equal to the length of the second sub-conductive layer 143 in the third direction Z.

In another example, referring to FIG7 , the capacitor electrode array wiring 191 is a straight line, and the direction perpendicular to the capacitor electrode array wiring 191 is the first reference direction, that is, the first reference direction is the third direction Z; among the multiple first sub-conductive layers 133 stacked along the first direction X, the first sub-conductive layers 133 located at the bottom layer and the top layer are equal in length in the third direction Z, and the first sub-conductive layer 133 located at the bottom layer is longer in length in the third direction Z than the first sub-conductive layer 133 located in the middle; among the multiple second sub-conductive layers 143 stacked along the first direction X, the second sub-conductive layers 143 located at the bottom layer and the top layer are equal in length in the third direction Z, and the second sub-conductive layer 143 located at the bottom layer is longer in length in the third direction Z than the second sub-conductive layer 143 located in the middle.

In some embodiments, referring to Figures 6 and 7, the direction parallel to at least the local capacitor electrode array wiring 191 is the second reference direction; among the multiple first sub-conductive layers 133 stacked along the first direction X, the widths of the multiple first sub-conductive layers 133 in the second reference direction are equal; among the multiple second sub-conductive layers 143 stacked along the first direction X, the widths of the multiple second sub-conductive layers 143 in the second reference direction are equal.

In practical applications, among the multiple first sub-conductive layers 133 stacked along the first direction X, the widths of the multiple first sub-conductive layers 133 in the second reference direction may be unequal; among the multiple second sub-conductive layers 143 stacked along the first direction X, the widths of the multiple second sub-conductive layers 143 in the second reference direction may also be unequal. Alternatively, the lengths of the multiple first sub-conductive layers 133 stacked along the first direction X or one of the multiple second sub-conductive layers 143 stacked along the first direction X in the second reference direction are unequal, and the lengths of the other in the second reference direction are equal. It can be understood that an embodiment of the present disclosure does not limit the size relationship between the lengths of the multiple first sub-conductive layers 133 stacked along the first direction X in the second reference direction, and does not limit the size relationship between the lengths of the multiple second sub-conductive layers 143 stacked along the first direction X in the second reference direction, and can be adjusted according to actual needs.

In one example, referring to FIG6 , the capacitor electrode array wiring 191 is a straight line, and the direction parallel to the capacitor electrode array wiring 191 is the second reference direction, that is, the second reference direction is the second direction Y; among the multiple first sub-conductive layers 133 stacked along the first direction X, the multiple first sub-conductive layers 133 have the same width in the second direction Y; among the multiple second sub-conductive layers 143 stacked along the first direction X, the multiple second sub-conductive layers 143 have the same width in the second direction Y. It should be noted that in actual applications, when the capacitor electrode array wiring 191 is a folded line, the second reference directions corresponding to different regions of the conductive structure 121 may be different.

In another example, with continued reference to FIGS. 6 and 7 , on the basis that the widths of the plurality of first sub-conductive layers 133 stacked along the first direction X in the second direction Y are equal, and the widths of the plurality of second sub-conductive layers 143 stacked along the first direction X in the second direction Y are equal, the width of the first sub-conductive layer 133 in the second direction Y is equal to the width of the second sub-conductive layer 143 in the second direction Y.

In some embodiments, among the multiple first sub-conductive layers 133 stacked along the first direction X, the heights of the multiple first sub-conductive layers 133 in the first direction X are equal; among the multiple second sub-conductive layers 143 stacked along the first direction X, the heights of the multiple second sub-conductive layers 143 in the first direction X are equal.

In practical applications, among the multiple first sub-conductive layers 133 stacked along the first direction X, the heights of the multiple first sub-conductive layers 133 in the first direction X may be different; among the multiple second sub-conductive layers 143 stacked along the first direction X, the heights of the multiple second sub-conductive layers 143 in the first direction X may also be different. Alternatively, the heights of the multiple first sub-conductive layers 133 stacked along the first direction X or one of the multiple second sub-conductive layers 143 stacked along the first direction X are different in the first direction X, and the height of the other in the first direction X is equal. It can be understood that an embodiment of the present disclosure does not limit the size relationship between the heights of the multiple first sub-conductive layers 133 stacked along the first direction X in the first direction X, and does not limit the size relationship between the heights of the multiple second sub-conductive layers 143 stacked along the first direction X in the first direction X, and can be adjusted according to actual needs.

In one example, referring to Figures 6 and 7, the capacitor electrode array wiring 191 is a straight line, and among the multiple first sub-conductive layers 133 stacked along the first direction X, the multiple first sub-conductive layers 133 have the same height in the first direction X; among the multiple second sub-conductive layers 143 stacked along the first direction X, the multiple second sub-conductive layers 143 have the same height in the first direction X.

In another example, continuing to refer to Figures 6 and 7, on the basis that the heights of multiple first sub-conductive layers 133 stacked along the first direction X are equal in the first direction X, and the heights of multiple second sub-conductive layers 143 stacked along the first direction X are equal in the first direction X, the height of the first sub-conductive layer 133 in the first direction X is equal to the height of the second sub-conductive layer 143 in the first direction X.

It can be understood that in the above embodiment, when the multiple first sub-conductive layers 133 stacked along the first direction X have equal lengths, equal widths and equal heights, it is conducive to forming a regular first conductive layer 131, and it is convenient to subsequently form the dielectric layer 102 on the surface of the first conductive layer 131. Similarly, when the multiple second sub-conductive layers 143 stacked along the first direction X have equal lengths, equal widths and equal heights, it is conducive to forming a regular second conductive layer 141, and it is convenient to subsequently form the dielectric layer 102 on the surface of the second conductive layer 141.

In some embodiments, referring to Figures 6 to 12, the conductive structure 121 also includes a third conductive layer 171 and a fourth conductive layer 181; wherein the third conductive layer 171 is electrically connected to multiple first conductive layers 131 in the conductive structure 121, and the third conductive layer 171 and multiple first conductive layers 131 in a conductive structure 121 constitute a first capacitor electrode 151; the fourth conductive layer 181 is electrically connected to multiple second conductive layers 141 in the conductive structure 121, and the fourth conductive layer 181 and multiple second conductive layers 141 in a conductive structure 121 constitute a second capacitor electrode 161.

It can be understood that the first capacitor electrode 151 includes multiple first conductive layers 131 and a third conductive layer 171 electrically connecting the multiple first conductive layers 131. The multiple first conductive layers 131 and the third conductive layer 171 can both be part of the wiring layer 101, that is, the multiple first conductive layers 131 and the third conductive layer 171 can be an integrally formed structure. In this way, on the one hand, it is beneficial to simplify the steps of forming the first conductive layer 131 and the third conductive layer 171; on the other hand, it is beneficial to avoid having a clear dividing line between the first conductive layer 131 and the third conductive layer 171, thereby reducing the lattice difference and contact resistance between the first conductive layer 131 and the third conductive layer 171, so as to improve the overall conductivity of the first conductive layer 131 and the third conductive layer 171 and improve the connection strength between the first conductive layer 131 and the third conductive layer 171.

In addition, the second capacitor electrode 161 includes a plurality of second conductive layers 141 and a fourth conductive layer 181 electrically connecting the plurality of second conductive layers 141. The plurality of second conductive layers 141 and the fourth conductive layer 181 can both be part of the wiring layer 101, that is, the plurality of second conductive layers 141 and the fourth conductive layer 181 can be an integrally formed structure. In this way, on the one hand, it is helpful to simplify the steps of forming the second conductive layer 141 and the fourth conductive layer 181; on the other hand, it is helpful to avoid having a clear dividing line between the second conductive layer 141 and the fourth conductive layer 181, thereby helping to reduce the lattice difference and contact resistance between the second conductive layer 141 and the fourth conductive layer 181, so as to improve the overall conductivity of the second conductive layer 141 and the fourth conductive layer 181 and improve the connection strength between the second conductive layer 141 and the fourth conductive layer 181.

In some embodiments, referring to Figures 6 to 9, the third conductive layer 171 and the fourth conductive layer 181 may be respectively located on two opposite sides of the wiring layer 101 (refer to Figure 2) in the third direction Z; in other embodiments, referring to Figure 10, the third conductive layer 171 is respectively located on two opposite sides of the wiring layer 101 in the third direction Z, and the fourth conductive layer 181 is respectively located on two opposite sides of the wiring layer 101 in the third direction Z; in still other embodiments, referring to Figures 11 and 12, the third conductive layer 171 and the fourth conductive layer 181 may be respectively located on two opposite sides of the wiring layer 101 (refer to Figure 2) in the first direction X.

In some embodiments, the third conductive layer 171 includes: a plurality of third sub-conductive layers 173 , wherein a third sub-conductive layer 173 is in contact with a first conductive layer 131 ; and at least one first electrical connection layer 114 , wherein the first electrical connection layer 114 is in contact with and connects two adjacent third sub-conductive layers 173 .

In some embodiments, referring to FIG7 , a plurality of third sub-conductive layers 173 are arranged in the same layer, so that the third conductive layer 171 as a whole extends along the second direction Y; in other embodiments, referring to FIG6 , FIG9 and FIG10 , a plurality of third sub-conductive layers 173 are respectively in contact with and connected to first sub-conductive layers 133 in different layers among a plurality of first conductive layers 131; wherein, in one example, referring to FIG6 , a plurality of third sub-conductive layers 173 are all located on the same side, and one third sub-conductive layer 173 corresponds to one first conductive layer 131, and at least two third sub-conductive layers 173 are respectively in contact with and connected to two first sub-conductive layers 133 in different layers; in another example, referring to FIG. 9, the plurality of third sub-conductive layers 173 are all located on the same side, and the two third sub-conductive layers 173 are respectively in contact with and connected to the two first sub-conductive layers 133 in different layers in the same first conductive layer 131; in another example, referring to FIG10, the plurality of third sub-conductive layers 173 are respectively located on the two opposite sides of the wiring layer 101 in the third direction Z, and the two third sub-conductive layers 173 are respectively in contact with and connected to the two first sub-conductive layers 133 in different layers in the same first conductive layer 131, one third sub-conductive layer 173 is located on one side of the first conductive layer 131 along the third direction Z, and the other third sub-conductive layer 173 is located on the other side of the first conductive layer 131 along the third direction Z.

It should be noted that, in an embodiment of the present disclosure, examples of “multiple third sub-conductive layers 173 are respectively in contact and connected with first sub-conductive layers 133 in different layers among multiple first conductive layers 131 ” include but are not limited to the three embodiments shown in FIG. 6 , FIG. 9 and FIG. 10 .

It can be understood that, for the third conductive layer 171, the plurality of third sub-conductive layers 173 and the at least one first electrical connection layer 114 can be an integrally formed structure. In addition, referring to FIG. 7 , the plurality of third sub-conductive layers 173, the at least one first electrical connection layer 114, and the plurality of first sub-conductive layers 133 respectively contacting and connected with the plurality of third sub-conductive layers 173 can all be an integrally formed structure, so as to simplify the formation steps of the conductive structure 121 and improve the conductive performance and structural stability of the first capacitor electrode 151 formed by the plurality of first conductive layers 131 and the third conductive layer 171.

In some embodiments, referring to Figures 6 to 10, the fourth conductive layer 181 includes: multiple fourth sub-conductive layers 183, a fourth sub-conductive layer 183 is in contact and connected with a second conductive layer 141; at least one second electrical connection layer 124, the second electrical connection layer 124 is in contact and connected with two adjacent fourth sub-conductive layers 183.

In some embodiments, referring to Figure 6, multiple fourth sub-conductive layers 183 are arranged in the same layer, so that the fourth conductive layer 181 as a whole extends along the second direction Y; in other embodiments, referring to Figures 7, 9 and 10, the multiple fourth sub-conductive layers 183 are respectively contacted and connected with multiple second sub-conductive layers 143 in different layers in the second conductive layer 141. In one example, referring to FIG7 , a plurality of fourth sub-conductive layers 183 are all located on the same side, and one fourth sub-conductive layer 183 corresponds to one second conductive layer 141, and at least two fourth sub-conductive layers 183 are respectively in contact and connected with two second sub-conductive layers 143 in different layers; in another example, referring to FIG9 , a plurality of fourth sub-conductive layers 183 are all located on the same side, and two fourth sub-conductive layers 183 are respectively in contact and connected with two second sub-conductive layers 143 in different layers in the same second conductive layer 141; in yet another example, referring to FIG10 , a plurality of fourth sub-conductive layers 183 are respectively located on opposite sides of the wiring layer 101 in the third direction Z, and two fourth sub-conductive layers 183 are respectively in contact and connected with two second sub-conductive layers 143 in different layers in the same second conductive layer 141, one fourth sub-conductive layer 183 is located on one side of the second conductive layer 141 along the third direction Z, and the other fourth sub-conductive layer 183 is located on the other side of the second conductive layer 141 along the third direction Z.

It should be noted that, in an embodiment of the present disclosure, examples of “multiple fourth sub-conductive layers 183 are respectively in contact and connected with multiple second sub-conductive layers 143 in different layers of the second conductive layer 141 ” include but are not limited to the three embodiments shown in FIGS. 7 , 9 and 10 .

It can be understood that, for the fourth conductive layer 181, the plurality of fourth sub-conductive layers 183 and the at least one second electrical connection layer 124 can be an integrally formed structure. In addition, referring to FIG6 , the plurality of fourth sub-conductive layers 183, the at least one second electrical connection layer 124, and the plurality of second sub-conductive layers 143 respectively contacting and connected with the plurality of fourth sub-conductive layers 183 can all be an integrally formed structure, so as to simplify the formation steps of the conductive structure 121 and improve the conductive performance and structural stability of the second capacitor electrode 161 formed by the plurality of second conductive layers 141 and the fourth conductive layer 181.

In practical applications, while multiple third sub-conductive layers 173 are arranged on the same layer, multiple fourth sub-conductive layers 183 can also be arranged on the same layer; or, while multiple third sub-conductive layers 173 are respectively contacted and connected with multiple first sub-conductive layers 133 in different layers among the multiple first conductive layers 131, multiple fourth sub-conductive layers 183 can also be respectively contacted and connected with multiple second sub-conductive layers 143 in different layers among the second conductive layers 141.

It should be noted that, in FIGS. 1 to 11 , the wiring layer 101 includes one conductive structure 121, that is, only one capacitor structure 103 is illustrated as an example. In practical applications, referring to FIG. 12 , the wiring layer 101 of the capacitor region 111 (refer to FIG. 2 ) may include a plurality of conductive structures 121 arranged at intervals, and one conductive structure 121 corresponds to one capacitor structure 103.

It can be understood that, referring to FIG12, the wiring layer 101 of the capacitor region 111 includes a plurality of sub-wiring layers 113 stacked along the first direction X, and the sub-wiring layer 113 includes at least one sub-conductive structure 123. FIG10 takes the example that the wiring layer 101 includes two conductive structures 121 arranged at intervals along the second direction Y, that is, the semiconductor structure includes two capacitor structures 103. In practical applications, there is no restriction on the number of conductive structures 121 arranged at intervals included in the wiring layer 101, and there is no restriction on the arrangement of the plurality of conductive structures 121, and both can be adjusted according to actual needs.

In the above embodiments, referring to FIG. 6, FIG. 13 or FIG. 14, the wiring layer 101 further includes a first lead-out structure 115 and a second lead-out structure 125, the first lead-out structure 115 is electrically connected to one of the first capacitor electrode 151 and the second capacitor electrode 161, and the second lead-out structure 125 is electrically connected to the other of the first capacitor electrode 151 and the second capacitor electrode 161. In some embodiments, the first lead-out structure 115 is electrically connected to the first capacitor electrode 151, and the second lead-out structure 125 is electrically connected to the second capacitor electrode 161; in other embodiments, the first lead-out structure 115 is electrically connected to the second capacitor electrode 161, and the second lead-out structure 125 is electrically connected to the first capacitor electrode 151.

In some embodiments, referring to Figure 6, the first capacitor electrode 151 includes multiple first conductive layers 131 and a third conductive layer 171, the first lead-out structure 115 is in contact with the third conductive layer 171 in the first capacitor electrode 151, the second capacitor electrode 161 includes multiple second conductive layers 141 and a fourth conductive layer 181, and the second lead-out structure 125 is in contact with the fourth conductive layer 181 in the second capacitor electrode 161.

In other embodiments, referring to Figures 13 and 14, the first capacitor electrode 151 includes multiple first conductive layers 131, the first lead-out structure 115 is in contact with and connected to a first sub-conductive layer 133 in the first conductive layer 131, and the second capacitor electrode 161 includes multiple second conductive layers 141, and the second lead-out structure 125 is in contact with and connected to a second sub-conductive layer 143 in the second conductive layer 141.

In one example, referring to FIG13, the first lead-out structure 115 and the second lead-out structure 125 may be located on opposite sides of the wiring layer 101 (refer to FIG2) along the third direction Z; in another example, referring to FIG12, the first lead-out structure 115 and the second lead-out structure 125 may be located on the same side of the wiring layer 101 (refer to FIG2), and the first lead-out structure 115 and the second lead-out structure 125 are spaced from each other; in another example, the first lead-out structure 115 and the second lead-out structure 125 may also be located on opposite sides of the wiring layer 101 (refer to FIG2) along the first direction X. It should be noted that an embodiment of the present disclosure does not impose too many restrictions on the positional relationship between the first lead-out structure 115 and the second lead-out structure 125 and the wiring layer 101, as long as the first lead-out structure 115 is electrically connected to one of the first capacitor electrode 151 and the second capacitor electrode 161, and the second lead-out structure 125 is electrically connected to the other of the first capacitor electrode 151 and the second capacitor electrode 161.

In some embodiments, referring to FIG14 , the first lead-out structure 115 includes a first lead 135 at least partially located on the surface of the substrate 100, and the second lead-out structure 125 includes a second lead 145 at least partially located on the surface of the substrate 100. It can be understood that, on the basis that the first lead-out structure 115 is electrically connected to the first conductive layer 131, and the second lead-out structure 125 is electrically connected to the second conductive layer 141, there is a gap between the first lead 135 and the second conductive layer 141, and there is a gap between the second lead 145 and the first conductive layer 131.

In some embodiments, with continued reference to FIG. 14 , the first lead structure 115 includes a plurality of first conductive pillars 155, wherein a first conductive pillar 155 is in contact with and connected to a first conductive layer 131; and a first lead 135 is in contact with and connected to all of the first conductive pillars 155. In practical applications, the plurality of first conductive pillars 155 and the first lead 135 may be an integrally formed structure; the second lead structure 125 includes a plurality of second conductive pillars 165, wherein a second conductive pillar 165 is in contact with and connected to a second conductive layer 141; and a second lead 145 is in contact with and connected to all of the second conductive pillars 165. In practical applications, the plurality of second conductive pillars 165 and the second lead 145 may be an integrally formed structure.

In one example, the material of the first lead 135 and the material of the second lead 145 may both be aluminum.

In one example, along the first direction X, the thickness of the first lead 135 and the thickness of the second lead 145 may both be in the range of 3 um to 7 um. This is beneficial to improving the electrical performance of the first lead-out structure 115 and the second lead-out structure 125 .

In some embodiments, referring to FIG. 1 and FIG. 2 , the semiconductor structure may further include: a peripheral structure surrounding the capacitor region 111 to achieve insulation between the wiring layer 101 of the capacitor region 111 and other electrical structures in the substrate 100 .

In one example, with continued reference to FIG. 1 and FIG. 2 , the peripheral structure includes: a first interlayer dielectric layer 116, a first insulating layer 117, a second interlayer dielectric layer 126, a second insulating layer 127, a third interlayer dielectric layer 136, a third insulating layer 137, and a fourth interlayer dielectric layer 146 stacked in sequence along a first direction X. It should be noted that FIG. 1 and FIG. 2 only illustrate a specific case of the peripheral structure. In practical applications, there is no restriction on the number of interlayer dielectric layers and the number of insulating layers included in the peripheral structure. Among them, the material of the first interlayer dielectric layer 116, the material of the second interlayer dielectric layer 126, the material of the third interlayer dielectric layer 136, and the material of the fourth interlayer dielectric layer 146 all include silicon nitride; the material of the first insulating layer 117, the material of the second insulating layer 127, and the material of the third insulating layer 137 all include silicon oxide.

In one example, in the first direction X, the thickness of the first interlayer dielectric layer 116 , the thickness of the second interlayer dielectric layer 126 , the thickness of the third interlayer dielectric layer 136 , and the thickness of the fourth interlayer dielectric layer 146 may all range from 0.5 um to 1 um.

In some embodiments, referring to Figures 1 and 2, the dielectric layer 102 may include a first dielectric layer 112 and a second dielectric layer 122, the first dielectric layer 112 conformally covers most of the surface of the first capacitor electrode 151, the first capacitor electrode 151 exposed by the first dielectric layer 112 is in contact with the first lead-out structure 115, the first dielectric layer 112 also conformally covers most of the surface of the second capacitor electrode 161, the second capacitor electrode 161 exposed by the first dielectric layer 112 is in contact with the second lead-out structure 125, and the first dielectric layer 112 and the second dielectric layer 122 together fill the gap between the first capacitor electrode 151 and the second capacitor electrode 161.

In one example, the width of the first dielectric layer 112 in the second direction Y is

In some embodiments, in combination with reference Figures 2 and 6, the first conductive layer 131 and the second conductive layer 141 have equal sizes in the first direction X, the second direction Y, and the third direction Z, and the widths of multiple intervals between the first conductive layer 131 and the second conductive layer 141 in the second direction Y are equal, and the pitch of a interval and the first conductive layer 131 as a whole in the second direction Y ranges from 0.2um to 0.4um.

In some embodiments, along the first direction X, the height of the first conductive layer 131 and the height of the second conductive layer 141 may both range from 1 um to 2 um.

In some embodiments, the capacitance per unit area of the capacitor structure 103 may be in the range of 3 fF/mm ² to 8 fF/mm ² . For example, the capacitance per unit area of the capacitor structure 103 may be greater than or equal to 5 fF/mm ² .

In summary, using the wiring layer 101 located in the capacitor region 111 of the substrate 100 as the first capacitor electrode 151 and the second capacitor electrode 161 of the capacitor structure 103 is conducive to simplifying the process steps of preparing the capacitor structure 103. Moreover, by virtue of the characteristics of the wiring layer 101, it is conducive to increasing the depth of the capacitor structure 103 in the first direction X, and designing the staggered arrangement of the first capacitor electrode 151 and the second capacitor electrode 161, thereby increasing the facing area of the first capacitor electrode 151 and the second capacitor electrode 161, so as to increase the capacitance of the capacitor structure 103. It can be understood that the capacitor structure 103 located in the substrate 100 can be used as a decoupling capacitor or a bypass capacitor to reduce the electrical interference between the electrical connection layers in the substrate 100, so as to improve the signal-to-noise ratio of the semiconductor structure by increasing the capacitance of the capacitor structure 103, thereby improving the anti-interference ability of the circuit structure composed of the semiconductor structure.

Another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which is used to prepare the semiconductor structure provided by the aforementioned embodiment. The method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described in detail below in conjunction with Figures 1 to 16. Figures 15 and 16 are partial cross-sectional schematic diagrams corresponding to each step of the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. It should be noted that the parts that are the same or corresponding to the aforementioned embodiments are not repeated here.

1 to 16 , a method for manufacturing a semiconductor structure includes: providing a substrate 100, wherein a direction perpendicular to a surface of the substrate 100 is a first direction X; forming a wiring layer 101 and an initial interlayer dielectric layer at least surrounding a sidewall of the wiring layer 101 extending along the first direction in the substrate 100, wherein the wiring layer 101 includes a capacitor region 111, the wiring layer 101 in the capacitor region 111 includes at least one conductive structure 121, the conductive structure 121 includes a plurality of first conductive layers 131 and a plurality of second conductive layers 141, the first conductive layers 131 and the second conductive layers 141 are spaced and alternately arranged on a plane perpendicular to the first direction X, the first capacitor electrode 151 includes a plurality of first conductive layers 131 in a conductive structure 121, and the second capacitor electrode 161 includes a plurality of second conductive layers 141 in a conductive structure 121; removing the initial interlayer dielectric layer in the capacitor region 111 to form a gap 108 between the first capacitor electrode 151 and the second capacitor electrode 161; and forming a dielectric layer 102 that fills the gap 108.

Another embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

In some embodiments, the step of forming the wiring layer 101 in the substrate 100 further includes: referring to FIG. 13 , forming an initial first interlayer dielectric layer 156, an initial first insulating layer 147, an initial second interlayer dielectric layer 166, an initial second insulating layer 157, an initial third interlayer dielectric layer 176, an initial third insulating layer 167, and an initial fourth interlayer dielectric layer 186 stacked in sequence along the first direction X. The wiring layer 101 is located in the initial first interlayer dielectric layer 156, the initial first insulating layer 147, the initial second interlayer dielectric layer 166, the initial second insulating layer 157, the initial third interlayer dielectric layer 176, and the initial third insulating layer 167, that is, the initial first interlayer dielectric layer 156, the initial first insulating layer 147, the initial second interlayer dielectric layer 166, the initial second insulating layer 157, the initial third interlayer dielectric layer 176, and the initial third insulating layer 167 are also provided in the gap between the first conductive layer 131 and the second conductive layer 141. Moreover, the thickness of the wiring layer 101 in the first direction X is the first thickness, the thickness of the film layer formed by the initial first interlayer dielectric layer 156, the initial first insulating layer 147, the initial second interlayer dielectric layer 166, the initial second insulating layer 157, the initial third interlayer dielectric layer 176 and the initial third insulating layer 167 in the first direction X is the second thickness, and the first thickness runs through the second thickness. The initial fourth interlayer dielectric layer 186 is also located on the top surface of the wiring layer 101 away from the substrate 100.

It should be noted that when the wiring layer 101 includes three sub-wiring layers 113 stacked along the first direction X, in the step of preparing the wiring layer 101, an initial first interlayer dielectric layer 156, an initial first insulating layer 147, an initial second interlayer dielectric layer 166, an initial second insulating layer 157, an initial third interlayer dielectric layer 176, an initial third insulating layer 167, and an initial fourth interlayer dielectric layer 186 are formed. It can be understood that the initial interlayer dielectric layer can include an initial first interlayer dielectric layer 156, an initial first insulating layer 147, an initial second interlayer dielectric layer 166, an initial second insulating layer 157, an initial third interlayer dielectric layer 176, an initial third insulating layer 167, and an initial fourth interlayer dielectric layer 186. In practical applications, there is no restriction on the film layer structure of the initial interlayer dielectric layer that wraps the wiring layer 101, that is, there is no restriction on the number of dielectric layers and the number of insulating layers included in the initial interlayer dielectric layer.

In some embodiments, referring to Figure 14, the steps of forming the first conductive layer 131 and the second conductive layer 141 include: forming a plurality of first sub-conductive layers 133 stacked along the first direction X in the capacitor region 111 to form the first conductive layer 131; forming a plurality of second sub-conductive layers 143 stacked along the first direction X in the capacitor region 111 to form the second conductive layer 141; wherein the first sub-conductive layers 133 and the second sub-conductive layers 143 spaced and alternately arranged on a plane perpendicular to the first direction X constitute a sub-conductive structure 123, and the plurality of sub-conductive structures 123 stacked along the first direction X constitute a conductive structure 121 (refer to Figure 10).

It should be noted that adjacent first sub-conductive layers 133 stacked along the first direction X are in contact and connected, adjacent second sub-conductive layers 143 stacked along the first direction X are in contact and connected, the multiple sub-conductive structures 123 stacked along the first direction X constitute a sub-wiring layer 113, and the multiple sub-wiring layers 113 stacked along the first direction X constitute a wiring layer 101.

It can be understood that the capacitor region 111 is designed when forming the wiring layer 101, and the wiring layer 101 in the prepared capacitor region 111 is used as the first capacitor electrode 151 and the second capacitor electrode 161, so as to facilitate the subsequent formation of the capacitor structure 103. In this way, it is beneficial to form the first capacitor electrode 151 and the second capacitor electrode 161 in the capacitor structure 103 in the step of forming the wiring layer 101, thereby simplifying the preparation steps of forming the capacitor structure 103 and reducing the preparation cost of the capacitor structure 103.

In some embodiments, removing the initial interlayer dielectric layer in the capacitor region 111 to form a gap 108 between the first capacitor electrode 151 and the second capacitor electrode 161 to form the dielectric layer 102 includes the following steps:

In combination with reference figures 13 and 14, the initial first interlayer dielectric layer 156, the initial first insulating layer 147, the initial second interlayer dielectric layer 166, the initial second insulating layer 157, the initial third interlayer dielectric layer 176, the initial third insulating layer 167 and the initial fourth interlayer dielectric layer 186 located in the capacitor region 111 are removed to form a gap 108 between the adjacent first conductive layer 131 and the second conductive layer 141, and the remaining initial first interlayer dielectric layer 156 serves as the first interlayer dielectric layer 116, the remaining initial first insulating layer 147 serves as the first insulating layer 117, the remaining initial second interlayer dielectric layer 166 serves as the second interlayer dielectric layer 126, the remaining initial second insulating layer 157 serves as the second insulating layer 127, the remaining initial third interlayer dielectric layer 176 serves as the third interlayer dielectric layer 136, the remaining initial third insulating layer 167 serves as the third insulating layer 137, and the remaining initial fourth interlayer dielectric layer 186 serves as the fourth interlayer dielectric layer 146.

It can be understood that in the aforementioned step of forming the wiring layer 101, the first capacitor electrode 151 and the second capacitor electrode 161 have been formed, and there is no need to use an additional mask to form the first capacitor electrode 151 and the second capacitor electrode 161 separately, which is conducive to simplifying the process steps of forming the first capacitor electrode 151 and the second capacitor electrode 161, so as to reduce the probability of a decrease in the yield of the semiconductor structure caused by process errors, and reduce the cost of forming the first capacitor electrode 151 and the second capacitor electrode 161. Moreover, in the step of forming the final capacitor structure, only one mask is needed to remove the initial interlayer dielectric layer in the capacitor region 111 to form the gap 108, and then the dielectric layer 102 filling the gap 108 is formed. In this way, in the step of forming the capacitor structure, only one mask is needed to etch the initial interlayer dielectric layer, which is conducive to saving the number of masks required for preparing the capacitor structure, so as to reduce the preparation cost of forming the capacitor structure. In addition, the desired capacitor structure can be formed by directly forming the dielectric layer 102 in the gap 108.

16 and 2, a dielectric layer 102 is formed in the space 108. In some embodiments, the step of forming the dielectric layer 102 includes: forming a first dielectric layer 112, the first dielectric layer 112 conformally covers the bottom and sidewalls of the space 108; forming a second dielectric layer 122, the first dielectric layer 112 and the second dielectric layer 122 together fill the space 108.

It can be understood that the first dielectric layer 112 can serve as a diffusion barrier layer to prevent the conductive elements in the first conductive layer 131 or the second conductive layer 141 from diffusing into the second dielectric layer 122, to prevent the insulation performance of the second dielectric layer 122 from being reduced, and to avoid short circuits between adjacent first conductive layers 131 and second conductive layers 141.

In some embodiments, the step of forming the first capacitor electrode 151 and the second capacitor electrode 161 may also include: referring to Figures 6 to 10, forming a third conductive layer 171 in the substrate 100, the third conductive layer 171 is electrically connected to multiple first conductive layers 131 in the conductive structure 121, and the third conductive layer 171 and multiple first conductive layers 131 in a conductive structure 121 constitute the first capacitor electrode 151; forming a fourth conductive layer 181 in the substrate 100, the fourth conductive layer 181 is electrically connected to multiple second conductive layers 141 in the conductive structure 121, and the fourth conductive layer 181 and multiple second conductive layers 141 in a conductive structure 121 constitute the second capacitor electrode 161.

It should be noted that, in conjunction with reference to FIG. 15 and FIG. 6 , the initial first interlayer dielectric layer 156, the initial first insulating layer 147, the initial second interlayer dielectric layer 166, the initial second insulating layer 157, the initial third interlayer dielectric layer 176, the initial third insulating layer 167 and the initial fourth interlayer dielectric layer 186 constitute a combined film layer, and before forming the third conductive layer 171, it also includes: etching the combined film layer to form a first groove (not shown in the figure), forming the third conductive layer 171 in the first groove; etching the combined film layer to form a second groove (not shown in the figure), forming the fourth conductive layer 181 in the second groove. Another embodiment of the present disclosure does not limit the specific preparation method of how to form the third conductive layer 171 and the fourth conductive layer 181.

In some embodiments, the step of forming the third conductive layer 171 includes: forming multiple third sub-conductive layers 173, and a third sub-conductive layer 173 is in contact and connected with a first conductive layer 131; wherein the multiple third sub-conductive layers 173 are arranged in the same layer; or, the multiple third sub-conductive layers 173 are respectively in contact and connected with multiple first sub-conductive layers 133 in different layers in the first conductive layer 131; and forming at least one first electrical connection layer 114, and the first electrical connection layer 114 is in contact and connected with two adjacent third sub-conductive layers 173.

It should be noted that another embodiment of the present disclosure does not limit the specific preparation method of how to form the third sub-conductive layer 173 and the first electrical connection layer 114.

In some embodiments, the step of forming the fourth conductive layer 181 includes: forming multiple fourth sub-conductive layers 183, a fourth sub-conductive layer 183 is in contact and connected with a second conductive layer 141; wherein the multiple fourth sub-conductive layers 183 are arranged in the same layer; or, the multiple fourth sub-conductive layers 183 are respectively in contact and connected with multiple second sub-conductive layers 143 in different layers in the second conductive layer 141; forming at least one second electrical connection layer, and the second electrical connection layer 124 is in contact and connected with two adjacent fourth sub-conductive layers 183.

It should be noted that another embodiment of the present disclosure does not limit the specific preparation method of how to form the fourth sub-conductive layer 183 and the second electrical connection layer 124 .

In some embodiments, referring to Figures 2 and 12, the first capacitor electrode 151, the second capacitor electrode 161 and the dielectric layer 102 constitute a capacitor structure 103; the step of forming the wiring layer 101 includes: forming a plurality of spaced apart conductive structures 121 in the capacitor region 111, and one conductive structure 121 corresponds to one capacitor structure 103.

In some embodiments, the step of forming the wiring layer 101 also includes: referring to Figures 13 and 14, forming a first lead-out structure 115, the first lead-out structure 115 is electrically connected to one of the first capacitor electrode 151 and the second capacitor electrode 161; forming a second lead-out structure 125, the second lead-out structure 125 is electrically connected to the other of the first capacitor electrode 151 and the second capacitor electrode 161.

It should be noted that, referring to FIG. 15 , FIG. 13 and FIG. 14 , the initial first interlayer dielectric layer 156, the initial first insulating layer 147, the initial second interlayer dielectric layer 166, the initial second insulating layer 157, the initial third interlayer dielectric layer 176, the initial third insulating layer 167 and the initial fourth interlayer dielectric layer 186 constitute a combined film layer, and before forming the third conductive layer 171, it also includes: etching the combined film layer to form a third groove (not shown in the figure), forming a first lead-out structure 115 in the third groove; etching the combined film layer to form a fourth groove (not shown in the figure), forming a second lead-out structure 125 in the second groove. Another embodiment of the present disclosure does not limit the specific preparation method of how to form the first lead-out structure 115 and the second lead-out structure 125.

In some embodiments, the step of forming the first lead structure 115 includes: referring to FIG. 14 , forming a first lead 135 at least partially located on the surface of the substrate 100 ; the step of forming the second lead structure 125 includes: forming a second lead 145 at least partially located on the surface of the substrate 100 .

In some embodiments, the third groove is used to form the first lead 135 and the first conductive column 155. After etching the combined film layer to form the third groove, aluminum material is deposited in the third groove to form an integrated structure of the first lead 135 and the first conductive column 155. The fourth groove is used to form the second lead 145 and the second conductive column 165. After etching the combined film layer to form the fourth groove, aluminum material is deposited in the fourth groove to form an integrated structure of the second lead 145 and the second conductive column 165.

In summary, the manufacturing method provided by another embodiment of the present disclosure forms the first capacitor electrode 151 and the second capacitor electrode 161 in the capacitor structure 103 while forming the wiring layer 101, so as to simplify the preparation steps of forming the capacitor structure 103 and reduce the preparation cost of the capacitor structure 103. In addition, by means of the characteristics of the wiring layer 101, it is beneficial to increase the depth of the capacitor structure 103 in the first direction X, and design the staggered arrangement of the first capacitor electrode 151 and the second capacitor electrode 161, so as to increase the facing area of the first capacitor electrode 151 and the second capacitor electrode 161, so as to increase the capacitance of the capacitor structure 103. It can be understood that the capacitor structure 103 located in the substrate 100 can be used as a decoupling capacitor or a bypass capacitor to reduce the electrical interference between the electrical connection layers in the substrate 100, so as to improve the signal-to-noise ratio of the semiconductor structure by increasing the capacitance of the capacitor structure 103, thereby improving the anti-interference ability of the circuit structure composed of the semiconductor structure.

Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims (20)

A semiconductor structure comprising: A substrate, wherein a direction perpendicular to a surface of the substrate is a first direction; A wiring layer in the substrate, the wiring layer comprising a capacitor region, the wiring layer in the capacitor region comprising at least one conductive structure, the conductive structure comprising a plurality of first conductive layers and a plurality of second conductive layers, the first conductive layers and the second conductive layers being spaced and alternately arranged on a plane perpendicular to the first direction; At least one first capacitor electrode of the first conductive layer in the conductive structure; At least one second capacitor electrode of the second conductive layer in the conductive structure; The dielectric layer is at least located in the interval between the first capacitor electrode and the second capacitor electrode. The first capacitor electrode, the second capacitor electrode and the dielectric layer constitute a capacitor structure. The semiconductor structure according to claim 1, wherein the wiring layer of the capacitor region comprises a plurality of the conductive structures arranged at intervals, and one of the conductive structures corresponds to one of the capacitor structures. The semiconductor structure according to any one of claims 1 or 2, wherein a plane perpendicular to the first direction is a reference plane, the first conductive layer and the second conductive layer each have a reference point in a corresponding area, and a connection line formed by a plurality of the reference points on the reference plane serves as a capacitor electrode row wiring, and the capacitor electrode row wiring is a straight line or a fold line. The semiconductor structure as claimed in claim 3, wherein the conductive structure further comprises a third conductive layer and a fourth conductive layer; wherein the third conductive layer is electrically connected to a plurality of the first conductive layers in the conductive structure, and the third conductive layer and a plurality of the first conductive layers in the conductive structure constitute the first capacitor electrode; the fourth conductive layer is electrically connected to a plurality of the second conductive layers in the conductive structure, and the fourth conductive layer and a plurality of the second conductive layers in the conductive structure constitute the second capacitor electrode. The semiconductor structure according to claim 4, wherein the wiring layer of the capacitor region comprises a plurality of contact-connected sub-wiring layers stacked along the first direction, the sub-wiring layer comprises at least one sub-conductive structure, the sub-conductive structure comprises a first sub-conductive layer and a second sub-conductive layer, the first sub-conductive layer and the second sub-conductive layer are spaced and alternately arranged on a plane perpendicular to the first direction; Wherein, in the conductive structure, the first capacitor electrode includes a plurality of the first sub-conductive layers stacked along the first direction, and the second capacitor electrode includes a plurality of the second sub-conductive layers stacked along the first direction. The semiconductor structure according to claim 5, wherein the third conductive layer comprises: A plurality of third sub-conductive layers, wherein one of the third sub-conductive layers is in contact with and connected to one of the first conductive layers; Wherein, the plurality of third sub-conductive layers are arranged in the same layer, or the plurality of third sub-conductive layers are respectively in contact with and connected to the first sub-conductive layers in different layers among the plurality of first conductive layers; At least one first electrical connection layer, wherein the first electrical connection layer contacts and connects two adjacent third sub-conductive layers. The semiconductor structure according to claim 5, wherein the fourth conductive layer comprises: A plurality of fourth sub-conductive layers, wherein one of the fourth sub-conductive layers is in contact with and connected to one of the second conductive layers; Wherein, the plurality of fourth sub-conductive layers are arranged in the same layer; or the plurality of fourth sub-conductive layers are respectively in contact with and connected to the plurality of second sub-conductive layers in different layers of the second conductive layer; At least one second electrical connection layer, wherein the second electrical connection layer contacts and connects two adjacent fourth sub-conductive layers. The semiconductor structure as described in claim 5, wherein the direction perpendicular to at least part of the capacitor electrode array wiring is a first reference direction; among the multiple first sub-conductive layers stacked along the first direction, the lengths of the multiple first sub-conductive layers in the first reference direction are equal or unequal; among the multiple second sub-conductive layers stacked along the first direction, the lengths of the multiple second sub-conductive layers in the first reference direction are equal or unequal. The semiconductor structure as described in claim 5, wherein the direction parallel to at least part of the capacitor electrode row wiring is a second reference direction; among the multiple first sub-conductive layers stacked along the first direction, the widths of the multiple first sub-conductive layers in the second reference direction are equal or unequal; among the multiple second sub-conductive layers stacked along the first direction, the widths of the multiple second sub-conductive layers in the second reference direction are equal or unequal. The semiconductor structure as described in claim 5, wherein, among the multiple first sub-conductive layers stacked along the first direction, the heights of the multiple first sub-conductive layers in the first direction are equal or unequal; among the multiple second sub-conductive layers stacked along the first direction, the heights of the multiple second sub-conductive layers in the first direction are equal or unequal. The semiconductor structure according to any one of claims 1 or 4, wherein the wiring layer further comprises a first lead-out structure and a second lead-out structure, the first lead-out structure is electrically connected to one of the first capacitor electrode and the second capacitor electrode, and the second lead-out structure is electrically connected to the other of the first capacitor electrode and the second capacitor electrode. The semiconductor structure of claim 11, wherein the first lead structure comprises a first lead at least partially located on the surface of the substrate, and the second lead structure comprises a second lead at least partially located on the surface of the substrate. A method for manufacturing a semiconductor structure, comprising: Providing a substrate, wherein a direction perpendicular to a surface of the substrate is a first direction; A wiring layer and an initial interlayer dielectric layer at least surrounding a sidewall of the wiring layer extending in a first direction are formed in the substrate, wherein the wiring layer includes a capacitor region, the wiring layer in the capacitor region includes at least one conductive structure, the conductive structure includes a plurality of first conductive layers and a plurality of second conductive layers, the first conductive layers and the second conductive layers are spaced and alternately arranged on a plane perpendicular to the first direction, the first capacitor electrode includes a plurality of the first conductive layers in the conductive structure, and the second capacitor electrode includes a plurality of the second conductive layers in the conductive structure; Removing the initial interlayer dielectric layer in the capacitor region to form a gap between the first capacitor electrode and the second capacitor electrode; A dielectric layer is formed to fill the space. The manufacturing method as claimed in claim 13, wherein the first capacitor electrode, the second capacitor electrode and the dielectric layer constitute a capacitor junction; the step of forming the wiring layer comprises: forming a plurality of the conductive structures arranged at intervals in the capacitor region, one of the conductive structures corresponding to one of the capacitor structures. The manufacturing method according to any one of claims 13 or 14, wherein the forming of the first capacitor electrode and the second capacitor electrode further comprises: forming a third conductive layer in the substrate, wherein the third conductive layer is electrically connected to the plurality of first conductive layers in the conductive structure, and the third conductive layer and the plurality of first conductive layers in the conductive structure constitute the first capacitor electrode; A fourth conductive layer is formed in the substrate, the fourth conductive layer is electrically connected to a plurality of the second conductive layers in the conductive structure, and the fourth conductive layer and a plurality of the second conductive layers in the conductive structure constitute the second capacitor electrode. The manufacturing method according to claim 15, wherein the step of forming the first conductive layer and the second conductive layer comprises: forming a plurality of first sub-conductive layers stacked along the first direction in the capacitor region to form the first conductive layer; forming a plurality of second sub-conductive layers stacked along the first direction in the capacitor region to form the second conductive layer; The first sub-conductive layers and the second sub-conductive layers that are spaced apart and alternately arranged on a plane perpendicular to the first direction constitute a sub-conductive structure, and a plurality of the sub-conductive structures stacked along the first direction constitute the conductive structure. The manufacturing method according to claim 16, wherein the step of forming the third conductive layer comprises: forming a plurality of third sub-conductive layers, wherein one of the third sub-conductive layers is in contact with and connected to one of the first conductive layers; Wherein, the plurality of third sub-conductive layers are arranged in the same layer; or the plurality of third sub-conductive layers are respectively in contact with and connected to the plurality of first sub-conductive layers in different layers of the first conductive layer; At least one first electrical connection layer is formed, wherein the first electrical connection layer contacts and connects two adjacent third sub-conductive layers. The manufacturing method according to claim 16, wherein the step of forming the fourth conductive layer comprises: forming a plurality of fourth sub-conductive layers, wherein a fourth sub-conductive layer is in contact with and connected to a second conductive layer; Wherein, the plurality of fourth sub-conductive layers are arranged in the same layer; or the plurality of fourth sub-conductive layers are respectively in contact with and connected to the plurality of second sub-conductive layers in different layers of the second conductive layer; At least one second electrical connection layer is formed, wherein the second electrical connection layer contacts and connects two adjacent fourth sub-conductive layers. The manufacturing method according to claim 13, wherein the step of forming the wiring layer further comprises: forming a first lead-out structure, wherein the first lead-out structure is electrically connected to one of the first capacitor electrode and the second capacitor electrode; A second lead-out structure is formed, wherein the second lead-out structure is electrically connected to the other of the first capacitor electrode and the second capacitor electrode. The manufacturing method according to claim 19, wherein the step of forming the first lead structure comprises: forming a first lead at least partially located on the surface of the substrate; The step of forming the second lead-out structure includes: forming a second lead line at least partially located on the surface of the substrate.

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