WO2024066745A1 - Hemt device and manufacturing method therefor - Google Patents

Abstract

A HEMT device, comprising a semiconductor layer, at least one gate structure, a first insulating layer (210), a dotted drain contact through hole (211), an annular source contact through hole (212), a drain ohmic contact metal layer (215), and a source ohmic contact metal layer (216). The gate structure is divided into a gate bus region (207), four gate ring regions (208), and four connection regions (209); the four gate ring regions (208) are uniformly distributed around the gate bus region (207); each gate ring region (208) is connected to the gate bus region (207) by means of a connection region (209). Gate control units use an annular cellular structure, so that very small source-drain series resistance can be achieved, and optimization of the area ratio of an active region can be achieved by means of a double-layer interconnection technology; the four gate control units are uniformly distributed around one gate bus region, thereby improving the layout design efficiency. Also disclosed is a manufacturing method for the HEMT device.

Description

HEMT device and manufacturing method thereof

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to a Chinese patent application filed with the Chinese Patent Office on September 29, 2022, with application number 202211200078.9 and invention name “A HEMT device and its manufacturing method”, the entire contents of which are incorporated by reference into this application.

Technical Field

The present invention belongs to the technical field of semiconductor power devices and relates to a HEMT device and a manufacturing method thereof.

Background technique

In the field of power electronics, GaN devices are mainly high electron mobility devices based on AlGaN/GaN (AlGaN/GaN HEMT). Thanks to the high concentration of two-dimensional electron gas (2DGE) in the AlGaN/GaN heterojunction, AlGaN/GaN HEMT can achieve extremely high power density and switching speed.

Please refer to Figure 1, which is a schematic diagram of the cross-sectional structure of an AlGaN/GaN high electron mobility device, including a substrate 101, a GaN layer 102, an AlGaN layer 103, a gate dielectric layer 104, a gate 105, a source 106, a drain 107 and a passivation layer 108, wherein a two-dimensional electron gas layer 109 is formed at the interface between the GaN layer 102 and the AlGaN layer 103.

In terms of design, AlGaN/GaN HEMT devices are mainly based on the lateral two-dimensional electron gas (2DEG) channel to achieve conduction. Therefore, unlike traditional power electronic devices such as silicon-based vertical double diffused metal oxide semiconductor field effect transistors (Si VDMOS) and silicon-based insulated gate bipolar transistors (Si IGBT), AlGaN/GaN HEMT has a lateral device structure. Therefore, all the source, drain, and gate electrodes of the device need to be arranged directly above the GaN wafer to achieve function.

Traditional AlGaN/GaN HEMT lateral devices are mainly interdigitated finger structures. As the most common lateral power device structure, the interdigitated finger structure has the characteristics of large active area ratio and simple connection. However, due to the long single interdigitated finger of the traditional interdigitated finger structure, the source-drain series resistance will be large, and the electromigration of the metal will be more obvious when it is turned on, which affects the reliability of the device. The island structure or bridge structure shrinks the entire interdigitated finger in the interdigitated finger structure into an island unit. This type of structure can reduce parasitic resistance and alleviate the problem of metal electromigration. At the same time, the flip-chip package also optimizes the heat dissipation performance of the device. However, the biggest problem of this type of structure is that the metal electrode occupies a large area and the active area ratio is small, which affects the usage ratio of the effective area.

Therefore, how to improve the structure and manufacturing method of HEMT devices to reduce the source-drain series resistance and improve the device The current density can be increased and the functional units can be more flexible in the overall layout of the device, which has become an important technical problem to be solved by technicians in this field.

It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application.

Summary of the invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a HEMT device and a method for manufacturing the same, so as to solve the problems of low utilization ratio of effective area, large source-drain series resistance, inflexible layout, etc. of the prior HEMT device.

To achieve the above-mentioned object and other related objects, the present invention provides a HEMT device, comprising:

A semiconductor layer, the semiconductor layer comprising a first material layer and a second material layer stacked in sequence from bottom to top, wherein a two-dimensional electron gas is contained at an interface between the first material layer and the second material layer;

At least one gate structure is located on the second material layer, the gate structure includes a gate material layer and a gate metal layer stacked in sequence from bottom to top, the gate structure is divided into a gate bus region, four gate ring regions and four connection regions, the four gate ring regions are evenly distributed around the gate bus region, and each of the gate ring regions is connected to the gate bus region through one of the connection regions;

A first insulating layer, located on the second material layer and covering the gate structure;

a point-shaped drain contact through hole, located in the area surrounded by the gate ring area and penetrating the first insulating layer to expose the second material layer;

an annular source contact through hole, which is arranged around the gate ring area and penetrates the first insulating layer to expose the second material layer, and the source contact through hole is also provided with a gap to allow the connection area to pass through;

A drain ohmic contact metal layer is located in the drain contact through hole;

The source ohmic contact metal layer is located in the source contact through hole.

Optionally, it also includes:

A second insulating layer, covering the drain ohmic contact metal layer, the source ohmic contact metal layer and the first insulating layer;

A source through hole, a drain through hole and a gate through hole, wherein the source through hole is located above the source ohmic contact metal layer and penetrates the second insulating layer to expose the source ohmic contact metal layer, the drain through hole is located above the drain ohmic contact metal layer and penetrates the second insulating layer to expose the drain ohmic contact metal layer, and the gate through hole is located above the gate bus region and penetrates the first insulating layer and the second insulating layer to expose the gate metal layer;

The source interconnection line, the drain interconnection line and the gate interconnection line extend in the X direction and are spaced apart in the Y direction, the X direction and the Y direction are parallel to the plane where the semiconductor layer is located and perpendicular to each other, the source interconnection line is also filled into the source through hole to be connected to the source ohmic contact metal layer, the drain interconnection line is also filled into the drain through hole to be connected to the drain ohmic contact metal layer, and the gate interconnection line is also filled into the gate through hole to be connected to the gate metal layer.

Optionally, one gate ring area in the HEMT device corresponds to one gate control unit, four gate control units corresponding to each gate structure constitute a functional unit, the four gate control units of one functional unit are arranged in two rows and two columns, and the gate control units in different rows are distributed on different drain interconnection lines, wherein the direction of the row is the X direction, and the direction of the column is the Y direction.

Optionally, the HEMT device includes a plurality of the functional units arranged in at least two rows and at least two columns, and the source interconnection line is located between two adjacent rows of the functional units.

Optionally, the HEMT device further includes a drain pad, a source pad, a gate pad and a substrate pad located above the source interconnection line, the drain interconnection line and the gate interconnection line, the drain pad is electrically connected to the drain interconnection line, the source pad is electrically connected to the source interconnection line, the gate pad is electrically connected to the gate interconnection line, and the substrate pad is electrically connected to the semiconductor layer.

Optionally, the semiconductor layer further includes a substrate layer and a buffer layer located on the substrate layer, and the first material layer is located on the buffer layer.

Optionally, the material of the first material layer includes intrinsic GaN, and the material of the second material layer includes AlGaN.

Optionally, the gate structure further includes a protection layer covering an upper surface of the gate metal layer.

Optionally, the drain ohmic contact metal layer further extends to an upper surface of the first insulating layer, and the source ohmic contact metal layer further extends to an upper surface of the first insulating layer.

The present invention also provides a method for manufacturing a HEMT device, comprising the following steps:

Providing a semiconductor layer, the semiconductor layer comprising a first material layer and a second material layer stacked in sequence from bottom to top, wherein a two-dimensional electron gas is contained at an interface between the first material layer and the second material layer;

Forming at least one gate structure on the second material layer, the gate structure comprising a gate material layer and a gate metal layer stacked in sequence from bottom to top, the gate structure being divided into a gate bus region, four gate ring regions and four connection regions, the four gate ring regions being evenly distributed around the gate bus region, and each of the gate ring regions being connected to the gate bus region through one of the connection regions;

A first insulating layer covering the gate structure is formed on the second material layer, and a point-shaped drain contact through hole and a ring-shaped source contact through hole are formed through the first insulating layer to expose the second material layer, wherein the drain contact through hole is located in the area surrounded by the gate ring area, and the source contact through hole is arranged around the gate ring area and has a space allowing a gap through which the connecting region passes;

A drain ohmic contact metal layer is formed in the drain contact through hole, and a source ohmic contact metal layer is formed in the source contact through hole.

Optionally, the method further comprises the following steps:

forming a second insulating layer covering the drain ohmic contact metal layer, the source ohmic contact metal layer and the first insulating layer;

forming a source through hole, a drain through hole and a gate through hole, wherein the source through hole is located above the source ohmic contact metal layer and penetrates the second insulating layer to expose the source ohmic contact metal layer, the drain through hole is located above the drain ohmic contact metal layer and penetrates the second insulating layer to expose the drain ohmic contact metal layer, and the gate through hole is located above the gate bus region and penetrates the first insulating layer and the second insulating layer to expose the gate metal layer;

A source interconnection line, a drain interconnection line and a gate interconnection line extending in the X direction and spaced apart in the Y direction are formed, wherein the X direction and the Y direction are parallel to the plane where the semiconductor layer is located and perpendicular to each other, the source interconnection line is also filled into the source through hole to be connected to the source ohmic contact metal layer, the drain interconnection line is also filled into the drain through hole to be connected to the drain ohmic contact metal layer, and the gate interconnection line is also filled into the gate through hole to be connected to the gate metal layer.

Optionally, the method further includes the steps of making a drain pad, a source pad, a gate pad and a substrate pad above the source interconnection line, the drain interconnection line and the gate interconnection line, wherein the drain pad is electrically connected to the drain interconnection line, the source pad is electrically connected to the source interconnection line, the gate pad is electrically connected to the gate interconnection line, and the substrate pad is electrically connected to the semiconductor layer.

As described above, in the HEMT device of the present invention, the gate control unit adopts a ring cell structure, which can achieve a very small source-drain series resistance. In the actual application of low-voltage GaN power devices, combined with the double-layer interconnection technology, the active area ratio can be optimized, and the current density of the device can be effectively improved. The HEMT device design of the present invention is conducive to the mass production of low-voltage and high-current GaN HEMT devices. In addition, in the HEMT device of the present invention, four gate control units are evenly distributed around a gate confluence area. This four-in-one functional unit is more flexible and changeable than the interdigital structure when the overall layout of the device is in the overall layout of the device, which is conducive to improving the efficiency of the layout design.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a cross-sectional structure of an AlGaN/GaN high electron mobility device.

FIG. 2 is a process flow chart showing a method for manufacturing a HEMT device according to the present invention.

FIG. 3 is a schematic diagram showing a cross-sectional structure of a semiconductor layer provided by the method for manufacturing a HEMT device of the present invention.

FIG. 4 is a partial cross-sectional view of a structure obtained after forming a gate structure on the second material layer according to the method for manufacturing a HEMT device of the present invention.

FIG. 5 is a partial plan layout diagram of a structure obtained after a gate structure is formed on the second material layer according to the method for manufacturing a HEMT device of the present invention.

6 is a partial cross-sectional view of a structure obtained after forming a first insulating layer and a point-shaped drain contact through hole and a ring-shaped source contact through hole penetrating the first insulating layer according to the manufacturing method of the HEMT device of the present invention.

7 is a partial plan layout diagram of a structure obtained after forming a first insulating layer and a point-shaped drain contact through hole and a ring-shaped source contact through hole penetrating the first insulating layer according to the manufacturing method of the HEMT device of the present invention.

FIG8 is a partial cross-sectional view of a structure obtained after forming a drain ohmic contact metal layer and a source ohmic contact metal layer according to the method for manufacturing a HEMT device of the present invention.

FIG. 9 is a partial planar layout diagram of a structure obtained after forming a drain ohmic contact metal layer and a source ohmic contact metal layer according to the manufacturing method of the HEMT device of the present invention.

FIG. 10 is a partial cross-sectional view of a structure obtained after forming a second insulating layer, a source through hole, a drain through hole, and a gate through hole in the method for manufacturing a HEMT device of the present invention.

FIG. 11 is a partial plan layout diagram of a structure obtained after forming a second insulating layer, a source through hole, a drain through hole, and a gate through hole in the method for manufacturing a HEMT device of the present invention.

FIG. 12 is a partial planar layout diagram of the structure obtained after the method for manufacturing the HEMT device of the present invention further forms source interconnection lines, drain interconnection lines and gate interconnection lines extending in the X direction and spaced apart in the Y direction.

FIG. 13 is a partial plan layout diagram of the structure obtained after forming source interconnection lines, drain interconnection lines, gate interconnection lines, gate common connection lines and substrate connection lines according to the method for manufacturing a HEMT device of the present invention.

FIG. 14 is a partial planar layout diagram of a structure obtained after forming a drain pad, a source pad, a gate pad and a substrate pad according to the manufacturing method of the HEMT device of the present invention.

Component number description
101 Substrate
102 GaN layer
103 AlGaN layer
104 gate dielectric layer
105 Gate
106 Source
107 Drain
108 Passivation layer
109 Two-dimensional electron gas
Steps S1 to S4
201 First Material Layer
202 Second material layer
203 substrate layer
204 Buffer layer
205 gate material layer
206 Gate metal layer
207 Gate bus area
208 Gate Ring Area
209 Connection Zone
210 First insulation layer
211 Drain contact via
212 Source contact via
213 Gap
214 Protective layer
215 Drain ohmic contact metal layer
216 Source ohmic contact metal layer
217 Second insulation layer
218 Source Via
219 Drain via
220 Gate Via
221 Source Interconnect
222 Drain interconnect
223 Gate Interconnect
224 Drain pad
225 Source pad
226 Gate pad
227 Substrate pad
228 Gate common connection line
229 substrate connection line

Detailed ways

The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figures 2 to 14. It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

Embodiment 1

In this embodiment, a method for manufacturing a HEMT device is provided. Please refer to FIG. 2 , which is a process flow chart of the method, and includes the following steps:

S1: providing a semiconductor layer, wherein the semiconductor layer comprises a first material layer and a second material layer stacked in sequence from bottom to top, and an interface between the first material layer and the second material layer contains a two-dimensional electron gas;

S2: forming at least one gate structure on the second material layer, the gate structure comprising a gate material layer and a gate metal layer stacked sequentially from bottom to top, the gate structure being divided into a gate bus region, four gate ring regions and four connection regions, the four gate ring regions being evenly distributed around the gate bus region, and each of the gate ring regions being connected to the gate bus region through one of the connection regions;

S3: forming a first insulating layer covering the gate structure on the second material layer, and forming a point-shaped drain contact through-hole and a ring-shaped source contact through-hole penetrating the first insulating layer to expose the second material layer, wherein the drain contact through-hole is located in the area surrounded by the gate ring area, and the source contact through-hole is arranged around the gate ring area and has a gap to allow the connection area to pass through;

S4: forming a drain ohmic contact metal layer in the drain contact through hole, and forming a source ohmic contact metal layer in the source contact through hole.

As an example, please refer to FIG. 3 , and perform step S1 : providing a semiconductor layer, wherein the semiconductor layer includes a first material layer 201 and a second material layer 202 stacked in sequence from bottom to top, and a two-dimensional electron gas is contained at an interface between the first material layer 201 and the second material layer 202 .

As an example, the material of the first material layer 201 includes intrinsic GaN, and the material of the second material layer 202 includes AlGaN.

As an example, the semiconductor layer further includes a substrate layer 203 and a buffer layer 204 located on the substrate layer 203, and the first material layer 201 is located on the buffer layer 204. In this embodiment, the substrate layer 203 is made of Si, and the buffer layer 204 is made of GaN.

Referring to FIG. 4 and FIG. 5 , step S2 is performed: at least one gate structure is formed on the second material layer 202, the gate structure includes a gate material layer 205 and a gate metal layer 206 stacked sequentially from bottom to top, the gate structure is divided into a gate bus region 207, four gate ring regions 208 and four connection regions 209, the four gate ring regions 208 are evenly distributed around the gate bus region 207, and each gate ring region 208 is connected to the gate bus region 207 through a connection region 209. FIG. 4 is a partial cross-sectional view of the structure obtained after performing this step, and FIG. 5 is a partial plan layout view of the structure obtained after performing this step. In this embodiment, FIG. 4 is a cross-sectional view at the section line (dashed line) in FIG. 5 .

As an example, the material of the gate material layer 205 includes P-type GaN. In this embodiment, the gate structure further includes a protective layer 214 covering the upper surface of the gate metal layer 206. The material of the protective layer 214 may include at least one of _SiO2 and SiON or other suitable materials, and is used as a hard mask to protect the gate metal layer 206 during the subsequent acid cleaning process after the ohmic contact hole is opened, so as to prevent the gate metal layer 206 from being damaged during the ohmic contact hole cleaning process.

Specifically, one gate ring area 208 in the HEMT device corresponds to one gate control unit, and four gate control units corresponding to each gate structure constitute a functional unit, wherein FIG. 4 shows an area where a functional unit is located. In this embodiment, four gate control units of a functional unit are arranged in two rows and two columns.

As an example, the HEMT device includes a plurality of the functional units arranged in at least two rows and at least two columns.

Referring to FIG. 6 and FIG. 7 , the step S3 is performed: forming a first insulating layer 210 covering the gate structure on the second material layer 202, and forming a point-shaped drain contact through hole 211 and a ring-shaped source contact through hole 212 penetrating the first insulating layer 210 to expose the second material layer 202, wherein the drain contact through hole 211 is located in the area surrounded by the gate ring area 208, and the source contact through hole 212 is arranged around the gate ring area 208 and has a notch 213 to allow the connection area 209 to pass through. FIG. 6 shows a partial cross-sectional view of the structure obtained after performing this step, and FIG. 7 shows a partial plan layout view of the structure obtained after performing this step.

As an example, the material of the first insulating layer 210 may include silicon dioxide, silicon nitride or other suitable insulating Material.

As an example, the first insulating layer 210 can be patterned by semiconductor processes such as photolithography and etching to obtain the drain contact through hole 211 and the source contact through hole 212, and the outer edge of the drain contact through hole 211 is spaced a certain distance from the inner edge of the gate ring area 208, and the inner edge of the source contact through hole 212 is spaced a certain distance from the outer edge of the gate ring area 208.

Referring again to FIG. 8 and FIG. 9 , the step S4 is performed: forming a drain ohmic contact metal layer 215 in the drain contact through hole 211, and forming a source ohmic contact metal layer 216 in the source contact through hole 212. FIG. 8 is a partial cross-sectional view of the structure obtained after performing this step, and FIG. 9 is a partial plan layout view of the structure obtained after performing this step.

As an example, the coverage area of the drain ohmic contact metal layer 215 is larger than the opening area of the drain contact through hole 211 , that is, the drain ohmic contact metal layer 215 also extends to the upper surface of the first insulating layer 210 .

As an example, the coverage area of the source ohmic contact metal layer 216 is larger than the opening area of the source contact through hole 212, that is, the source ohmic contact metal layer 216 also extends to the upper surface of the first insulating layer 210. In this embodiment, the source ohmic contact metal layers 216 of different gate control units are connected into one piece, and further, the source ohmic contact metal layers 216 of different functional units are connected into one piece.

Referring to FIG. 10 and FIG. 11 , a second insulating layer 217 is further formed to cover the drain ohmic contact metal layer 215, the source ohmic contact metal layer 216 and the first insulating layer 210, and a source through hole 218, a drain through hole 219 and a gate through hole 220 are formed. The source through hole 218 is located above the source ohmic contact metal layer 216 and penetrates the second insulating layer 217 to expose the source ohmic contact metal layer 216. The drain through hole 219 is located above the drain ohmic contact metal layer 215 and penetrates the second insulating layer 217 to expose the drain ohmic contact metal layer 215. The gate through hole 220 is located above the gate bus region 207 and penetrates the first insulating layer 210 and the second insulating layer 217 to expose the gate metal layer 206. FIG. 10 is a partial cross-sectional view of the structure obtained after performing this step, and FIG. 11 is a partial plan layout view of the structure obtained after performing this step.

As an example, the material of the second insulating layer 217 may include silicon dioxide, silicon nitride or other suitable insulating materials.

Referring again to FIG. 12 , a source interconnection line 221, a drain interconnection line 222, and a gate interconnection line 223 are further formed, extending in the X direction and spaced apart in the Y direction. The X direction and the Y direction are parallel to the plane where the semiconductor layer is located and perpendicular to each other. The source interconnection line 221 is also filled into the source through hole 218 to be connected to the source ohmic contact metal layer 216. The drain interconnection line 222 is also filled into the drain through hole 219 to be connected to the drain ohmic contact metal layer 215. The gate interconnection line 223 is also filled into the gate through hole 220 to be connected to the gate metal layer 206.

Specifically, in the description that the four gate control units of the functional unit are arranged in two rows and two columns and the HEMT device includes a plurality of functional units arranged in at least two rows and at least two columns, the direction of the row is the X direction, and the direction of the column is the Y direction. In this embodiment, the source interconnection line 221 is located between two adjacent rows of the functional units, and the gate control units located in different rows are distributed on different drain interconnection lines 222.

As an example, please refer to Figure 13. When the source interconnection line 221, the drain interconnection line 222 and the gate interconnection line 223 are formed, the gate common connection line 228 and the substrate connection line 229 are formed simultaneously. In this embodiment, the gate common connection line 228 is in the shape of a rectangular ring. The plurality of source interconnections 221, the drain interconnections 222 and the gate interconnections 223 are all located in the area surrounded by the gate common connection line 228, and both ends of the gate interconnection line 223 are connected to the gate common connection line 228. The substrate connection line 229 is in the shape of a rectangular ring and is arranged around the periphery of the gate common connection line 228. The substrate connection line 229 is electrically connected to the substrate layer 203 from the front side of the semiconductor layer.

Please refer to Figure 14 again, a drain pad 224, a source pad 225, a gate pad 226 and a substrate pad 227 are further made above the source interconnection line 221, the drain interconnection line 222 and the gate interconnection line 223, the drain pad 224 is electrically connected to the drain interconnection line 222, the source pad 225 is electrically connected to the source interconnection line 221, the gate pad 226 is electrically connected to the gate interconnection line 223, and the substrate pad 227 is electrically connected to the semiconductor layer.

As an example, the drain pad 224 and the source pad 225 are both located in the area surrounded by the gate common connection line 228, the drain pad 224 and the drain interconnection line 222 are directly electrically connected through a contact hole, and the source pad 225 and the source interconnection line 221 are directly electrically connected through a contact hole.

As an example, most of the gate pad 226 and most of the substrate pad 227 are located in the area surrounded by the gate common connection line 228, the gate pad 226 is connected to the gate common connection line 228 through a contact hole to achieve electrical connection between the gate pad 226 and the gate interconnection line 223, and the substrate pad 227 is connected to the substrate connection line 229 through a contact hole to achieve electrical connection between the substrate pad 227 and the substrate layer 203 in the semiconductor layer.

It should be noted that the specific layout of the drain pad 224 , the source pad 225 , the gate pad 226 and the substrate pad 227 can also be adjusted according to actual needs and is not limited to the example presented in FIG. 13 .

The manufacturing method of the HEMT device of this embodiment manufactures the gate control unit into a ring cellular structure, which can achieve a very small source-drain series resistance. In the actual application of low-voltage GaN power devices, in conjunction with the double-layer interconnection technology, the active area ratio can be optimized, and the current density of the device can be effectively improved. The manufacturing method of the HEMT device of this embodiment is conducive to the mass production of low-voltage and high-current GaN HEMT devices. In addition, the manufacturing method of the HEMT device of this embodiment adopts a layout in which four gate control units are evenly distributed around a gate confluence area. This four-in-one functional unit is more flexible and changeable than the interdigital structure when the overall layout of the device is in the overall layout, which is conducive to improving the efficiency of layout design.

Embodiment 2

In the present embodiment, a HEMT device is provided. Please refer to FIG. 10 and FIG. 11 , which respectively show a partial cross-sectional view and a partial planar layout view of the HEMT device, including a semiconductor layer, at least one gate structure, a first insulating layer 210 , a dot-shaped drain contact through hole 211 , a ring-shaped source contact through hole 212 , a drain ohmic contact metal layer 215 , and a source ohmic contact metal layer 216 .

Specifically, the semiconductor layer includes a first material layer 201 and a second material layer 202 stacked in sequence from bottom to top, and a two-dimensional electron gas is contained at an interface between the first material layer 201 and the second material layer 202 .

As an example, the material of the first material layer 201 includes intrinsic GaN, and the material of the second material layer 202 includes AlGaN.

As an example, the semiconductor layer further includes a substrate layer 203 and a buffer layer 204 located on the substrate layer 203, and the first material layer 201 is located on the buffer layer 204. In this embodiment, the substrate layer 203 is made of Si, and the buffer layer 204 is made of GaN.

Specifically, the gate structure is located on the second material layer 202, and the gate structure includes a gate material layer 205 and a gate metal layer 206 stacked in sequence from bottom to top. The gate structure is divided into a gate bus area 207, four gate ring areas 208 and four connection areas 209. The four gate ring areas 208 are evenly distributed around the gate bus area 207, and each of the gate ring areas 208 is connected to the gate bus area 207 through a connection area 209.

As an example, the gate material layer 205 is made of P-type GaN. In this embodiment, the gate structure further includes a protection layer 214 covering the upper surface of the gate metal layer 206. The material of the protection layer 214 may include at least one of SiO ₂ and SiON or other suitable materials.

Specifically, the first insulating layer 210 is located on the second material layer 202 and covers the gate structure. The material of the first insulating layer 210 may include silicon dioxide, silicon nitride or other suitable insulating materials.

Specifically, the drain contact through hole 211 is located in the area surrounded by the gate ring area 208, and the source contact through hole 212 is arranged around the gate ring area 208 and has a gap 213 for allowing the connection area to pass through. In this embodiment, the outer edge of the drain contact through hole 211 is spaced a certain distance from the inner edge of the gate ring area 208, and the inner edge of the source contact through hole 212 is spaced a certain distance from the outer edge of the gate ring area 208.

Specifically, the drain ohmic contact metal layer 215 is located in the drain contact through hole 211 ; the source ohmic contact metal layer 216 is located in the source contact through hole 212 .

As an example, the coverage area of the drain ohmic contact metal layer 215 is larger than the opening area of the drain contact through hole 211 , that is, the drain ohmic contact metal layer 215 also extends to the upper surface of the first insulating layer 210 .

As an example, the coverage area of the source ohmic contact metal layer 216 is larger than the opening of the source contact through hole 212. The hole area, that is, the source ohmic contact metal layer 216 also extends to the upper surface of the first insulating layer 210. In this embodiment, the source ohmic contact metal layers 216 of different gate control units are connected into one piece, and further, the source ohmic contact metal layers 216 of different functional units are connected into one piece.

As an example, the HEMT device also includes a second insulating layer 217 covering the drain ohmic contact metal layer 215, the source ohmic contact metal layer 216 and the first insulating layer 210, and includes a source through hole 218, a drain through hole 219 and a gate through hole 220, the source through hole 218 is located above the source ohmic contact metal layer 216 and penetrates the second insulating layer 217 to expose the source ohmic contact metal layer 216, the drain through hole 219 is located above the drain ohmic contact metal layer 215 and penetrates the second insulating layer 217 to expose the drain ohmic contact metal layer 215, and the gate through hole 220 is located above the gate bus region 207 and penetrates the first insulating layer 210 and the second insulating layer 217 to expose the gate metal layer 206.

As an example, referring to FIG. 12 , the HEMT device further includes a source interconnection line 221, a drain interconnection line 222, and a gate interconnection line 223 extending in the X direction and spaced apart in the Y direction. The X direction and the Y direction are parallel to the plane where the semiconductor layer is located and perpendicular to each other. The source interconnection line 221 is also filled into the source through hole 218 to be connected to the source ohmic contact metal layer 216. The drain interconnection line 222 is also filled into the drain through hole 219 to be connected to the drain ohmic contact metal layer 215. The gate interconnection line 223 is also filled into the gate through hole 220 to be connected to the gate metal layer 206.

As an example, the four gate control units of one functional unit in the HEMT device are arranged in two rows and two columns, and the HEMT device includes a plurality of functional units arranged in at least two rows and at least two columns. In this embodiment, the source interconnection line 221 is located between two adjacent rows of the functional units, and the gate control units located in different rows are distributed on different drain interconnection lines 222, wherein the direction of the row is the X direction, and the direction of the column is the Y direction.

As an example, please refer to FIG. 13 , the HEMT device further includes a gate common connection line 228 and a substrate connection line 229. In the present embodiment, the gate common connection line 228 is in a rectangular ring shape, and the plurality of source interconnection lines 221, the drain interconnection lines 222 and the gate interconnection lines 223 are all located in the area surrounded by the gate common connection line 228, and both ends of the gate interconnection line 223 are connected to the gate common connection line 228. The substrate connection line 229 is in a rectangular ring shape and is arranged around the periphery of the gate common connection line 228. The substrate connection line 229 is electrically connected to the substrate layer 203 from the front side of the semiconductor layer.

As an example, referring to FIG. 14 , the HEMT device further includes a drain pad 224, a source pad 225, a gate pad 226, and a substrate pad 227 located above the source interconnection line 221, the drain interconnection line 222, and the gate interconnection line 223, wherein the drain pad 224 is electrically connected to the drain interconnection line 222, the source pad 225 is electrically connected to the source interconnection line 221, the gate pad 226 is electrically connected to the gate interconnection line 223, and the substrate pad 227 is electrically connected to the drain interconnection line 222. The pad 227 is electrically connected to the semiconductor layer.

As an example, the drain pad 224 and the source pad 225 are both located in the area surrounded by the gate common connection line 228, the drain pad 224 and the drain interconnection line 222 are directly electrically connected through a contact hole, and the source pad 225 and the source interconnection line 221 are directly electrically connected through a contact hole.

As an example, most of the gate pad 226 and most of the substrate pad 227 are located in the area surrounded by the gate common connection line 228, the gate pad 226 is connected to the gate common connection line 228 through a contact hole to achieve electrical connection between the gate pad 226 and the gate interconnection line 223, and the substrate pad 227 is connected to the substrate connection line 229 through a contact hole to achieve electrical connection between the substrate pad 227 and the substrate layer 203 in the semiconductor layer.

It should be noted that the specific layout of the drain pad 224 , the source pad 225 , the gate pad 226 and the substrate pad 227 can also be adjusted according to actual needs and is not limited to the layout shown in FIG. 13 .

In summary, in the HEMT device of the present invention, the gate control unit adopts a ring cellular structure, which can achieve a very small source-drain series resistance. In the actual application of low-voltage GaN power devices, combined with the double-layer interconnection technology, the active area ratio can be optimized, and the current density of the device can be effectively improved. The HEMT device design of the present invention is conducive to the mass production of low-voltage and high-current GaN HEMT devices. In addition, in the HEMT device of the present invention, four gate control units are evenly distributed around a gate confluence area. This four-in-one functional unit is more flexible and changeable than the interdigital structure when the device is laid out as a whole, which is conducive to improving the efficiency of the layout design. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims (15)

A HEMT device, comprising: A semiconductor layer, the semiconductor layer comprising a first material layer and a second material layer stacked in sequence from bottom to top, wherein a two-dimensional electron gas is contained at an interface between the first material layer and the second material layer; At least one gate structure is located on the second material layer, the gate structure includes a gate material layer and a gate metal layer stacked in sequence from bottom to top, the gate structure is divided into a gate bus region, four gate ring regions and four connection regions, the four gate ring regions are evenly distributed around the gate bus region, and each of the gate ring regions is connected to the gate bus region through one of the connection regions; A first insulating layer, located on the second material layer and covering the gate structure; a point-shaped drain contact through hole, located in the area surrounded by the gate ring area and penetrating the first insulating layer to expose the second material layer; an annular source contact through hole, which is arranged around the gate ring area and penetrates the first insulating layer to expose the second material layer, and the source contact through hole is also provided with a gap to allow the connection area to pass through; A drain ohmic contact metal layer is located in the drain contact through hole; The source ohmic contact metal layer is located in the source contact through hole. The HEMT device according to claim 1, further comprising: A second insulating layer, covering the drain ohmic contact metal layer, the source ohmic contact metal layer and the first insulating layer; A source through hole, a drain through hole and a gate through hole, wherein the source through hole is located above the source ohmic contact metal layer and penetrates the second insulating layer to expose the source ohmic contact metal layer, the drain through hole is located above the drain ohmic contact metal layer and penetrates the second insulating layer to expose the drain ohmic contact metal layer, and the gate through hole is located above the gate bus region and penetrates the first insulating layer and the second insulating layer to expose the gate metal layer; The source interconnection line, the drain interconnection line and the gate interconnection line extend in the X direction and are spaced apart in the Y direction, the X direction and the Y direction are parallel to the plane where the semiconductor layer is located and perpendicular to each other, the source interconnection line is also filled into the source through hole to be connected to the source ohmic contact metal layer, the drain interconnection line is also filled into the drain through hole to be connected to the drain ohmic contact metal layer, and the gate interconnection line is also filled into the gate through hole to be connected to the gate metal layer. The HEMT device according to claim 2 is characterized in that: one gate ring region in the HEMT device corresponds to one gate control unit, and four gate control units corresponding to each gate structure form a functional unit. The four gate control units of a functional unit are arranged in two rows and two columns, and the gate control units in different rows are distributed on different drain interconnection lines, wherein the direction of the row is the X direction, and the direction of the column is the Y direction. The HEMT device according to claim 3, characterized in that: the HEMT device comprises a plurality of the functional units arranged in at least two rows and at least two columns, and the source interconnection line is located between two adjacent rows of the functional units. The HEMT device according to claim 2 is characterized in that: the HEMT device further comprises a drain pad, a source pad, a gate pad and a substrate pad located above the source interconnection line, the drain interconnection line and the gate interconnection line, the drain pad is electrically connected to the drain interconnection line, the source pad is electrically connected to the source interconnection line, the gate pad is electrically connected to the gate interconnection line, and the substrate pad is electrically connected to the semiconductor layer. The HEMT device according to claim 1 is characterized in that: the semiconductor layer further comprises a substrate layer and a buffer layer located on the substrate layer, and the first material layer is located on the buffer layer. The HEMT device according to claim 1, wherein the material of the first material layer comprises intrinsic GaN, and the material of the second material layer comprises AlGaN. The HEMT device according to claim 1, wherein the gate structure further comprises a protective layer covering an upper surface of the gate metal layer. The HEMT device according to claim 1, characterized in that: the drain ohmic contact metal layer also extends to the upper surface of the first insulating layer, and the source ohmic contact metal layer also extends to the upper surface of the first insulating layer. The HEMT device according to claim 1 is characterized in that: the HEMT device further comprises a gate common connection line and a substrate connection line, the gate common connection line is in a rectangular ring shape, a plurality of the source interconnection lines, the drain interconnection lines and the gate interconnection lines are all located in an area surrounded by the gate common connection line, and the substrate connection line is in a rectangular ring shape and is arranged around the periphery of the gate common connection line. The HEMT device according to claim 1, characterized in that: a certain distance is between the outer edge of the drain contact through hole and the inner edge of the gate ring area, and a certain distance is between the inner edge of the source contact through hole and the outer edge of the gate ring area. A method for manufacturing a HEMT device, characterized by comprising the following steps: Providing a semiconductor layer, the semiconductor layer comprising a first material layer and a second material layer stacked in sequence from bottom to top, wherein a two-dimensional electron gas is contained at an interface between the first material layer and the second material layer; Forming at least one gate structure on the second material layer, the gate structure comprising a gate material layer and a gate metal layer stacked in sequence from bottom to top, the gate structure being divided into a gate bus region, four gate ring regions and four connection regions, the four gate ring regions being evenly distributed around the gate bus region, and each of the gate ring regions being connected to the gate bus region through one of the connection regions; Forming a first insulating layer covering the gate structure on the second material layer, and forming a point-shaped drain contact through-hole and a ring-shaped source contact through-hole penetrating the first insulating layer to expose the second material layer, wherein the drain contact through-hole is located in the area surrounded by the gate ring area, and the source contact through-hole is arranged around the gate ring area and has a gap to allow the connection area to pass through; A drain ohmic contact metal layer is formed in the drain contact through hole, and a source ohmic contact metal layer is formed in the source contact through hole. The method for manufacturing a HEMT device according to claim 12, further comprising the following steps: forming a second insulating layer covering the drain ohmic contact metal layer, the source ohmic contact metal layer and the first insulating layer; forming a source through hole, a drain through hole and a gate through hole, wherein the source through hole is located above the source ohmic contact metal layer and penetrates the second insulating layer to expose the source ohmic contact metal layer, the drain through hole is located above the drain ohmic contact metal layer and penetrates the second insulating layer to expose the drain ohmic contact metal layer, and the gate through hole is located above the gate bus region and penetrates the first insulating layer and the second insulating layer to expose the gate metal layer; A source interconnection line, a drain interconnection line and a gate interconnection line extending in the X direction and spaced apart in the Y direction are formed, wherein the X direction and the Y direction are parallel to the plane where the semiconductor layer is located and perpendicular to each other, the source interconnection line is also filled into the source through hole to be connected to the source ohmic contact metal layer, the drain interconnection line is also filled into the drain through hole to be connected to the drain ohmic contact metal layer, and the gate interconnection line is also filled into the gate through hole to be connected to the gate metal layer. The method for manufacturing a HEMT device according to claim 13 is characterized in that: it also includes the step of manufacturing a drain pad, a source pad, a gate pad and a substrate pad above the source interconnection line, the drain interconnection line and the gate interconnection line, the drain pad is electrically connected to the drain interconnection line, the source pad is electrically connected to the source interconnection line, the gate pad is electrically connected to the gate interconnection line, and the substrate pad is electrically connected to the semiconductor layer. The method for manufacturing a HEMT device according to claim 13 is characterized in that: it also includes forming a gate common connection line and a substrate connection line simultaneously when forming the source interconnection line, the drain interconnection line and the gate interconnection line, the gate common connection line is in a rectangular ring shape, and a plurality of the source interconnection lines, the drain interconnection lines and the gate interconnection lines are all located in the area surrounded by the gate common connection line, and the substrate connection line is in a rectangular ring shape and is arranged around the periphery of the gate common connection line.