WO2024026597A1

WO2024026597A1 - Nitride-based semiconductordevice and method for manufacturing the same

Info

Publication number: WO2024026597A1
Application number: PCT/CN2022/109336
Authority: WO
Inventors: Junhui Ma; Jheng-Sheng You; Ming-Hong Chang
Original assignee: Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date: 2022-07-31
Filing date: 2022-07-31
Publication date: 2024-02-08
Also published as: CN118103991A

Abstract

A nitride-based semiconductor deviceincludes a first and a second nitride-based semiconductor layers, a source and a drain electrodes, a doped nitride-based semiconductor layer, and a gate electrode. The source electrode is disposed over the second nitride-based semiconductor layer and includes a first and a second conductive layers. The drain electrode is disposed over the second nitride-based semiconductor layer and includes a third and a fourth conductive layers. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer and between the source electrode and the drain electrode. The gate electrode is disposed over the doped nitride-based semiconductor layer and between the source electrode and the drain electrode and includes a fifth and a sixth conductive layers. The second, fourth, and sixth conductive layers have the same material.

Description

NITRIDE-BASED SEMICONDUCTORDEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Junhui MA, Jheng-Sheng YOU, Ming-Hong CHANG

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to anitride-based semiconductor packaged device having a nitride-based conductive layer.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a doped nitride-based semiconductor layer, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The source electrode is disposed over the second nitride-based semiconductor layer and includes a first conductive layer and a second conductive layer stacked on the first conductive layer. The drain electrode is disposed over the second nitride-based semiconductor layer and includes a third conductive layer and a fourth conductive layer stacked on the third conductive layer. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer and between the source electrode and the drain electrode. The gate electrode is disposed over the doped nitride-based semiconductor layer and between the source electrode and the drain electrode and includes a fifth conductive layer and a sixth conductive layer stacked on the fifth conductive layer. The second, fourth, and sixth conductive layers have the same material.

In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor device is provided. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A doped nitride-based semiconductor layer is formed over the second nitride-based semiconductor layer. A nitride-based conductive layer is formed over the doped nitride-based semiconductor layer. A protection layer is formed to cover the doped nitride-based semiconductor layer and the nitride-based conductive layer. A first hole and a second hole are formed in the protection layer to expose a portion of the second nitride-based semiconductor layer and a portion of the nitride-based conductive layer, respectively. A source electrode is formed in the first hole and a gate electrode is formed in the second hole in the same photolithography process.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, a protection layer, a source electrode, a drain electrode, and a gate electrode. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer. The protection layer is disposed over the second nitride-based semiconductor layer and covers the doped nitride-based semiconductor layer. The source electrode and the drain electrode are disposed over the second nitride-based semiconductor layer and penetrate the protection layer to make contact with the second nitride-based semiconductor layer. The gate electrode is disposed over the doped nitride-based semiconductor layer and between the source electrode and the drain electrode. End portions of the source electrode, the drain electrode, and the gate electrode are located on a top surface of the protection layer and have substantially the same thickness.

By the above configuration, in the present disclosure, a nitride-based conductive layer is formed on a doped nitride-based semiconductor layerto form a Schottky contact therebetween prior to the formation of the source, drain and the gate electrodes. The nitride-based conductive layer can avoid affectionof the ohmic conductive layerto the Schottky contact, such that the electrical property of the Schottky contactcan be maintained. Thus, the source, drain and the gate electrodes can be formed in the same manufacturing stages; and therefore, the source, drain and the gate electrodes can have the similar or the same electrode structure. Hence, the nitride-based semiconductor device can have low manufacturing costs.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a vertical cross-sectional view of anitride-based semiconductor device according to some embodiments of the present disclosure;

FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2Dshow different stages of a method for manufacturing anitride-based semiconductor deviceaccording to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and

FIG. 4 is a vertical cross-sectional view of anitride-based semiconductor deviceaccording to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor packaged devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure.

Referring to FIG. 1, the nitride-based semiconductor device 1Aincludes a substrate 10, a buffer layer 12, nitride-based

semiconductor layers

14, 16, a source electrode 20, a drain electrode 22, a dopednitride-based semiconductor layer30, a nitride-based conductive layer 32, a gate electrode 34, and a protection layer 40.

The substrate 10 may be a semiconductor substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

The buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 14. The buffer layer 12 can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 14, thereby curing defects due to the mismatches/difference. The buffer layer 12 may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer 12 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 10 and a buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 14 can be disposed on/over/above the buffer layer 12. The nitride-based semiconductor layer 16 can be disposed on/over/above the nitride-based semiconductor layer 14. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 16 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the nitride-based semiconductor layer 16 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 14, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 16 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 14 and 16 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

Generally, the source/drain electrode is requiredto have low contact resistance to avoid low efficiency of the device, and thusa contact between the source/drain electrode and the nitride-based semiconductor layer thereunder is optionally selected asan ohmic contact. The gate electrode is required to have a relatively high contact resistance to avoidexcessive on-state current, and thus a contact between the gate electrode and the nitride-based semiconductor layer thereunder is optionally selected as aSchottky contact.

In order to achieve different electrical contacts, thegate electrode and the source/drain electrode should be manufacturedin different manufacturing stages, which resultingin a high manufacturing cost.

At least to avoid the aforesaid issue, the present disclosure provides a novel structure. The detailed configuration and the manufacturing method thereof would be fully described as follows.

First of all, prior to the formation of the gate, source, and the

drain electrodes

34, 20, and 22, the doped nitride-based semiconductor layer 30 andthenitride-based conductive layer 32 for bringing the device to the desired status (e.g., enhancement mode) are formed in sequence on/over/above the nitride-based semiconductor layer 16.

The formed doped nitride-based semiconductor layer 30 is disposed on/over/above the nitride-based semiconductor layer 16. The doped nitride-based semiconductor layer 30 makes contact with the nitride-based semiconductor layer 16.

The formed nitride-based conductive layer 32 is disposed on/over/above the nitride-based semiconductor layer 30. The nitride-based conductive layer 32 makes contact with the doped nitride-based semiconductor layer 30. The nitride-based conductive layer 32 can be formed to become narrower than the doped nitride-based semiconductor layer 30.

In some embodiments, the doped nitride-based semiconductor layer 30 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 30 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based conductive layer 32 can be titanium nitride (TiN) . Thus, a Schottky contact SC (or a Schottky diode) can be formed therebetween.

Then, an intermediate protection layer is formed to cover the resulted structure. A patterning process is performed on the intermediate protection layer to form holes H1-H3, thereby forming aprotection layer 40 with the holes H1-H3. The holes H1, H3 are preset to accommodate the source and drain electrodes20, 22, respectively. The holes H1, H3 expose different parts of a top surface 162 of the nitride-based semiconductor layer 16. The location of the hole H1 can be viewed as a source region. The location of the hole H3 can be viewed as a drain region. The hole H1 is defined by side surfaces SS1 of the protection layer 40. The hole H3 is defined by side surfaces SS3 of the protection layer 40. The holes H1, H3 can have substantially the same depth.

It should be noted thatnot only a portion of the intermediate protection layer but also a portion of the nitride-based conductive layer 32 are removed during the aforesaid patterning process, such that the nitride-based conductive layer 32 can have a recessed top surface RS and a side surface SS21 connected to the recessed top surface RS. The recessed top surface RS faces away from the doped nitride-based semiconductor layer30. The recessed top surface RS of the nitride-based conductive layer 32 is formed from an etching process. The nitride-based conductive layer 32 can serve as protection for the doped nitride-based semiconductor layer 30. Since the nitride-based conductive layer 32 provide a function simpler than that of the nitride-based conductive layer 32, slight damage on the nitride-based conductive layer 32 is acceptable than which occurs on the doped nitride-based semiconductor layer 30. Damage to the doped nitride-based semiconductor layer 30 may result in unwanted leakage current.

The hole H2, which is preset to accommodate the gate electrode 34, is collectively defined by the recessed top surface RS and side surfaces SS21 of the nitride-based conductive layer 32 and the side surfaces SS22the protection layer 40. The hole H2 exposes the recessed top surface RS of the nitride-based conductive layer 32. The location of the hole H2 can beviewed as a gate region. The depth of the hole H2 is formed to be shallower than those of the holesH1, H3 due to configuration of the nitride-based conductive layer 32 and the doped nitride-based semiconductor layer 30.

In some embodiments, theformedside surfacesSS21, SS1, SS22, SS3 of the nitride-based conductive layer 32 and the protection layer 40 can be oblique/inclined side surfaces.

In some embodiments, each of the source, drain, and the gate electrodes, 20, 22, and 34, for example but not limited thereto, is to designed to formed to have a composite electrode structure, which means that each of the source, drain, and the gate electrodes, 20, 22, and 34 has a plurality of stacked conductive layers (for example, two stacked conductive layers in the FIG. 1) .

To form such the composite electrode structure, a plurality of single blanket conductive layers can be formed in sequence on the resulted structure by deposition techniques. Then, a deposition process is performed for depositing two single blanket conductive layers on the resulted structure. It should be noted that the bottom-most single blanket conductive layer, which is formed to make contact with the top surface 162 the nitride-based semiconductor layer 16 and the recessed top surface RS of the nitride-based conductive layer 32, should include an ohmic conductive layerto form ohmic contact, thereby meeting the electrical requirements of the source and drain

electrodes

20, 22.

In some embodiments, the ohmic conductive layercan include, for example but are not limited to, titanium (Ti) . The electrical property of the Schottky contact SC can be maintained instead of affecting by the ohmic conductive layer due to the obstruction/block of the nitride-based conductive layer 32. The top-most single blanket conductive layer can include a metal alloy. In some embodiments, the metal alloy of the top-most single blanket conductive layer can include Al-Cu alloy, titanium (Ti) , and titanium nitride (TiN) . In some embodiments, the metal alloy of the top-most single blanket conductive layer can include Al-Si alloy, titanium (Ti) , and titanium nitride (TiN) .

After the deposition process, portions of the single blanket conductive layers can be formed to fill into the holes H1-H3. Portions of the single blanket conductive layerscover the top surface 402 of the protection layer40. Then, the single blanket conductive layers can bepatterned in the same photolithography process, such that the excess portions thereof are removed. The remaining portions of the single blanket conductive layerscan serve as the source, drain, and the gate electrodes, 20, 22, and 34. Thus, the source, drain, and the gate electrodes, 20, 22, and 34 can be obtained.

Referring the FIG. 1 again, the formed source electrode 20 and the formed drain electrode 22 are disposed on/over/above the nitride-based semiconductor layer 16. The source and drain electrodes20, 22 penetrate the protection layer 40 to make contact with the nitride-based semiconductor layer16. The source electrode 20 includes a plurality

conductive layers

202, 204. The drain electrode 22 includes

conductive layers

222, 224. The formed gate electrode 34 is disposed on/over/above the doped nitride-based semiconductor layer 30 and the nitride-based conductive layer 32. The nitride-based conductive layer 32 is disposed between the doped nitride-based semiconductor layer 30 and the gate electrode 34. The gate electrode 34 is located between the source and the

drain electrodes

20, 22. The gate electrode 34 penetrates the protection layer 40 and extends into a thickness of the nitride-based conductive layer 32. The gate electrode 34 makes contact with the protection layer 40 and the nitride-based conductive layer 32. It should be noted that the

conductive layers

202, 222, 342 are the remaining portions of the bottom-most conductive layer, and the

conductive layers

204, 224, 344 are the remaining portions of the top-most conductive layer.

With respect to the source electrode 20, the conductive layer 202 makes contact with a top and side surfaces 402, SS1 of the protection layer 40 and the top surface 162 of the nitride-based semiconductor layer 16, such that the conductive layer 202 can have a U-shaped profile. The conductive layer 202 has twoend portions extending along the top surface 402 of the protection layer 40, and has two end oblique extending portions abutting against the protection layer 40. The conductive layer 204 is conformally stacked/disposed on the conductive layer 202, such that the conductive layer 204 can also have a U-shaped profile. The conductive layer 204 makes contact with the conductive layer 202. The conductive layer 204 can be thicker than the conductive layer 202.

With respect to the drain electrode 22, the conductive layer 222 makes contact with the top and side surfaces 402, SS3 of the protection layer 40 and the top surface 162 of the nitride-based semiconductor layer 16, such that the conductive layer 222 can have a U-shaped profile. The conductive layer 222 has two end portions extending along the top surface 402 of the protection layer 40, and has two oblique extending portions abutting against the protection layer 40. The conductive layer 224 is conformally stacked/disposed on the conductive layer 222, such that the conductive layer 224 can also have a U-shaped profile. The conductive layer 224 makes contact with the conductive layer 222. The conductive layer 224 can be thicker than the conductive layer 222.

With respect to the gate electrode 34, the conductive layer 342 makes contact with side surfaces SS22 of the protection layer 40, and side surfaces SS21, the recessed top surface RS of the nitride-based conductive layer 32, such that the conductive layer 342 can have a U-shaped profile. The conductive layer 342 has two end portions extending along the top surface 402 of the protection layer 40, and has two oblique extending portions abutting against the protection layer 40 and the nitride-based conductive layer 32. The conductive layer 344 is conformally stacked/disposed on the conductive layer 342, such that the conductive layer 344 can also have a U-shaped profile. The conductive layer 344 makes contact with the conductive layer 342. The conductive layer 344 can be thicker than the conductive layer 342. The oblique extending portions of theconductive layer 344 is thicker than that of theoblique extending portions of theconductive layers204, 224.

With respect to the source, drain, and the

gate electrodes

20, 22, 34, since they are manufactured in the same manufacturing stages, they can own the same or the similar electrode structures (i.e., they are manufactured in the same deposition process and the same photolithography process) . More specifically, the formation of the source, drain, and the

gate electrodes

20, 22, 34 starts at the same time point and is terminated as the same time point as well, which can be called simultaneity.

For example, the conductive layer 202 of the source electrode 20, the conductive layer 342 of the gate electrode 34, and the conductive layer 222 of the drain electrode 22 are made from the same bottom-most single conductive layer including ohmic metal (for example, titanium) . Thus, the

conductive layers

202, 222, 342 can have the same conductive material (for example, titanium) . The

conductive layers

202, 222, 342can have substantially the same thickness.

On the other hand, the conductive layer 204 of the source electrode 20, the conductive layer 344 of the gate electrode 34, and the conductive layer 224 of the drain electrode 22 are made from the same top-most single conductive layer (for example, Al-Cu alloy, titanium (Ti) , and titanium nitride (TiN) ) . Similarly, the

conductive layers

204, 224, 344 can have the same conductive material (for example, Al-Cu alloy, titanium (Ti) , and titanium nitride (TiN) ) different from those of the

conductive layers

202, 222, 342. The

conductive layers

204, 224, 344 can have substantially the same thickness. The thickness of the

conductive layers

204, 224, 344 is thicker than those of the

conductive layers

202, 222, 342.

Moreover, end portions of the source, drain, and the gate electrodes20, 22, 34 are located on/over/above the top surface 402 of the protection layer 40. These end portions of the source, drain, and the

gate electrodes

20, 22, 34can have substantially the same thickness. These end portions of the source, drain, and the

gate electrodes

20, 22, 34are located at the same level of height.

In some embodiments, the two end portions of the source electrode 20 can have substantially the same width/extending length. The two end portions of the drain electrode 22 can have substantially the same width/extending length. The two end portions of the gate electrode 34 can have substantially the same width/extending length.

In addition, due to the depth relationship of the holes H1-H3, the gate electrode 34 has an outline different than those of the source electrode 20 and the drain electrode22. Abottom-most portion of the gate electrode 34 is at a position higher than bottom-most portions of the source electrode 20 and the drain electrode 22.

Based on the above, in the present disclosure, prior to the formation of the source, gate and the

drain electrodes

20, 34, 22, anitride-based conductive layer 32is formed on the doped nitride-based semiconductor layer30 to form a Schottky contact SC. The nitride-based conductive layer 32 can prevent the ohmic conductive layer to affect the electrical property of the Schottky contact SC. Thus, the source, gate and the

drain electrodes

20, 34, 22 can be manufactured in the same manufacturing stages. Therefore, the nitride-based semiconductor device 1A manufactured by aforesaid manufacturing method can have a lower manufacturing cost and a higher manufacturing efficiency.

The formed protection layer 40 is disposed on/over/above the nitride-based semiconductor layer 16. The protection layer 40 makes a contact with the nitride-based semiconductor layer 16. The protection layer 40covers the doped nitride-based semiconductor layer30 and the nitride-based conductive layer 32.

The exemplary materials of the protection layer 40 can include, for example but are not limited to, dielectric materials. For example, the protection layer 40 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the protection layer 40 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

In the exemplary illustration of FIG. 1A, the nitride-based semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrode 34 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 30 may create at least one p-n junction with the nitride-based semiconductor layer 16 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 34 has different characteristics (e.g., different electron concentrations) than the remaining portion of the 2DEG region and thus is blocked.

Due to such mechanism, the nitride-based semiconductor device 1A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 34 or a voltage applied to the gate electrode 34 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 34) , the zone of the 2DEG region below the gate electrode 34 is kept blocked, and thus no current flows therethrough.

In some embodiments, the nitride-based semiconductor layer 14 includes undoped GaN and the nitride-based semiconductor layer 16 includes AlGaN, and the doped nitride-based semiconductor layer 30 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the nitride-based semiconductor device 1A into an off-state condition.

Different stages of a method for manufacturing the semiconductor packaged device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, and FIG 2D, described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a substrate 10 is provided. A buffer layer 12 is formed on/over/above the substrate 10. A nitride-based semiconductor layer 14 is formed on the buffer layer 12. A nitride-based semiconductor layer 16 is formed on the nitride-based semiconductor layer 14. A doped nitride-based semiconductor layer30 is formed on/over/abovethe nitride-based semiconductor layer 16. An intermediate nitride-based conductive layer 42 is formed over the doped nitride-based semiconductor layer30. The intermediate nitride-based conductive layer 42 is formed narrower than the doped nitride-based semiconductor layer 30.

The formation of the doped nitride-based semiconductor layer 30 and the intermediate nitride-based conductive layer 42includes deposition techniques and a patterning process. In some embodiments, the deposition techniques can be performed for forming a blanket layer, and the patterning process can be performed for removing excess portions thereof. In some embodiments, the patterning process can include photolithography, exposure and development, etching, other suitable processes, or combinations thereof.

Referring to FIG. 2B, an intermediate protection layer 44 is formed to cover the doped nitride-based semiconductor layer30, the intermediate nitride-based conductive layer 42, and a top surface of the nitride-based conductive layer 16.

Referring to FIG. 2C, holes H1-H3 are formed in the intermediate protection layer 44. During the formation of the holes H1-H3, portions of the intermediate protection layer 44 and a portion of the intermediate nitride-based conductive layer42 are removed. The protection layer 40 with holes H1-H3 is thus formed. The nitride-based conductive layer 32 has a recessed top surface RS after the formation of the hole H2. The intermediate nitride-based conductive layer 42can serve as protection to the nitride-based semiconductor layer 30 during the formation of the hole H2.

Referring to FIG. 2D, a plurality of the single blanket

conductive layers

46, 48 are deposited on the resulted structure of FIG. 2C in sequence. Specifically, asingle blanket conductive layer 46 is formed to cover the resulted structure in the FIG. 2C, such that the single blanket conductive layer 46 can make contact with the inner side surfaces of the protection layer 40. Portions of the single blanket conductive layer 46 fills into the holes H1-H3. Another blanket conductive layer 48 is formed to cover the single blanket conductive layer 46. The blanket conductive layer 48 makes contact with the blanket conductive layer 46. Portions of the single blanket conductive layer 48 fills into the holes H1-H3.

Then, single blanket

conductive layers

46, 48 are patterned to form source electrode 20, drain electrode 22, and the gate electrode 34are formed in the holes H1, H3, H2, respectively, in the same photolithography process. The formed source electrode 20, drain electrode 22, and the gate electrode 34 are formed to be separated from each other. Thereafter, the nitride-based semiconductor device 1A in the FIG. 1A can be obtained.

FIG. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to the semiconductor packaged device 1A as described and illustrated with reference to FIG. 1, except that the source electrode 20B has

conductive layers

202, 204, 206; the drain electrode 22Bhas

conductive layers

222, 224, 226; and the gate electrode 34B has

conductive layers

342, 344, 346. Furthermore, the nitride-based semiconductor device 1B has a protection layer 50, a plurality of conductive vias 52 (or contact vias) , and a patterned circuit layer 54.

At least for achieving abetter connection to between the source/gate/drain electrode 20B/34B/22B and the corresponding conductive via 52, in some embodiments, conductive fillings can be formed to connect with the source, gate,

drain electrode

20B, 34B, 22B.

To be more specific, the source electrode 20Bin the FIG. 3 has an additional conductive layer 206. The conductive layer 206 is disposed/stacked on the conductive layer 204. The conductive layer 206 makes contact with the conductive layer 204. The conductive layer 206 fills up a recess formed by the

conductive layers

202, 204, such that a top surface of the source electrode 20B is a flat top surface. The total area of the top flat surface of the source electrode 20B is greater than that of the source electrode 20.

The drain electrode 22Bin the FIG. 3 has an additional conductive layer 226. The conductive layer 226 is disposed/stacked on the conductive layer 224. The conductive layer 226 makes contact with the conductive layer 224. The conductive layer 226 fills up a recess formed by the

conductive layers

222, 224, such that a top surface of the drain electrode 22B is a flat top surface. The total area of the top flat surface of the drain electrode 22B is greater than that of the drain electrode 20.

thegate electrode 34Bin the FIG. 3 has an additional conductive layer 346. The conductive layer 346 is disposed/stacked on the conductive layer 344. The conductive layer 346 makes contact with the conductive layer 344. The conductive layer 346 fills up a recess formed by the

conductive layers

342, 344, such that a top surface of the gate electrode 34B is a flat top surface. The total area of the top flat surface of the gate electrode 34B is greater than that of the gate electrode 34.

It should be noted that the

conductive layers

206, 226, 346 are made ofthe same single blanket conductive layer, such that the

conductive layers

206, 226, 346 can have the same material. In some embodiments, the material of the

conductive layers

206, 226, 346 is different from those of the

conductive layers

202, 222, 342 (or the

conductive layers

204, 224, 344) so an etching back process is available to be applied to the formation of the

conductive layers

206, 226, 346.

Each of the source, drain and the

gate electrodes

20B, 22B, 34B in the FIG. 3 can have a conductive filling to create top flat surface area, which is advantageous to form the conductive vias 52 in the subsequent manufacturing stages. Such a configuration can enhance/improve the manufacturing yield of the nitride-based semiconductor device 1B.

The conductive vias 52 are disposed within the protection layer 50. The conductive vias 52 penetrate the protection layer 50. The conductive vias 52 extend longitudinally to electrically couple with the patterned circuit layer 54. The conductive vias 52 are disposed on/over/above top flat surfaces of the source, drain and the

gate electrodes

20B, 22B, 34B, respectively. The conductive vias 52 makecontact with a top surface of the source, drain and the

gate electrodes

20B, 22B, 34B, respectively. The exemplary materials of the conductive vias 52 can include, for example, but are not limited to, conductive materials, such as metals or alloy.

The protection layer 50 covers the source, drain and the

gate electrodes

20B, 22B, 34B and the protection layer 40. Top surfaces of the conductive vias 52 are free from coverage of the protection layer 50. The exemplary materials of the protection layer 50 can be the same or similar to that of the protection layer 40.

The patterned circuit layer 54 is disposed on/over/above the top surfaces of the conductive vias 52. The patterned circuit layer 54 is electrically connected to the source, drain and the

gate electrodes

20B, 22B and 34B through the conductive vias 52. The patterned conductive layer 54 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 54 can form at least one circuit. The exemplary materials of the patterned conductive layer 54 can include, for example but are not limited to, conductive materials. The patterned conductive layer 54 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

FIG. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to the semiconductor packaged device 1A as described and illustrated with reference to FIG. 1, except that each of the source, drain and the

gate electrodes

20C, 22C, 34Cis formed to have two end portions extends along the top surface 402 of the protection layer 40.

In the present embodiment, the occupation area of the source, drain and the

gate electrodes

20C, 22C, 34C is increased/enlarged to further form top flat surfaces by opposite end portions, in which one of the end portions is formed to have a greater extending length/width than that of the other one of the end portions.

Each of the source, drain and the

gate electrodes

20C, 22C, 34C in the FIG. 4can have an increased/enlargedtop surface area, which is advantageous to form the conductive vias 52 in the subsequentmanufacturing stages. Such a configuration can enhance the manufacturing yield of the nitride-based semiconductor device 1C.

In addition, the protection layer 50Cfills up a recess formed by the

conductive layers

202C, 204C of the source electrode 20C, a recess formed by the

conductive layers

222C, 224C of the drain electrode 22C, and a recess formed by the

conductive layers

342C, 344C. The protection layer 50C extends into a thickness of the protection layer 40. The exemplary materials of the protection layer 50C can be the same or similar to that of the protection layer 40.

Based on above, in the present disclosure, prior to the formation of the source, drain and the gate electrodes, a nitride-based conductive layer is formed on a doped nitride-based semiconductor layer to form a Schottky contact therebetween. The configuration of the nitride-based conductive layer can avoid the influence of the ohmic conductive layer, such that the electrical property of the Schottky contactfor the gate can be maintained. Thus, the source, drain and the gate electrodes can be formed in the same metal deposition process and the same photolithography process. Hence, the formed nitride-based semiconductor device can have low manufacturing costs.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a source electrode disposed over the second nitride-based semiconductor layer and comprising a first conductive layer and a second conductive layer stacked on the first conductive layer;

a drain electrode disposed over the second nitride-based semiconductor layer and comprising a third conductive layer and a fourth conductive layer stacked on the third conductive layer;

a doped nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer and between the source electrode and the drain electrode; and

a gate electrode disposed over the doped nitride-based semiconductor layer and between the source electrode and the drain electrode and comprising a fifth conductive layer and a sixth conductive layer stacked on the fifth conductive layer, wherein the second, fourth, and sixth conductive layers have the same material.
The nitride-based semiconductor device of claim 1, wherein the first, third, and fifth conductive layers have the same material.
The nitride-based semiconductor device of claim 2, wherein the second, fourth, and sixth conductive layers comprise the same material that is different than those of the first, third, and fifth conductive layers.
The nitride-based semiconductor device of claim 2, wherein the second, fourth, and sixth conductive layers comprise aluminum (Al) .
The nitride-based semiconductor device of claim 1, wherein the first, third, and fifth conductive layers comprise titanium (Ti) .
The nitride-based semiconductor device of claim 1, wherein each of the first, third, and fifth conductive layers has a U-shaped profile.
The nitride-based semiconductor device of claim 6, wherein each of the second, fourth, and sixth conductive layers has a U-shaped profile.
The nitride-based semiconductor device of claim 1, further comprising:

a protection layer disposed over the second nitride-based semiconductor layer and covering the doped nitride-based semiconductor layer, wherein the first, third, and fifth conductive layers extend horizontally along a top surface of the protection layer.
The nitride-based semiconductor device of claim 8, wherein the first, third, and fifth conductive layers have oblique extending portions, respectively, which abut against the protection layer.
The nitride-based semiconductor device of claim 9, wherein the oblique extending portion of the sixth conductive layer is thicker than the oblique extending portions of the second and fourth conductive layers.
The nitride-based semiconductor device of claim 1, wherein the sixth conductive layer is thicker than the fifth conductive layer.
The nitride-based semiconductor device of claim 1, further comprising:

a nitride-based conductive layer disposed between the doped nitride-based semiconductor layer and the gate electrode.
The nitride-based semiconductor device of claim 12, wherein the nitride-based conductive layer has a recessed top surface facing away from the doped nitride-based semiconductor layer.
The nitride-based semiconductor device of claim 1, wherein the source electrode further comprises a seventh conductive layer stacked on the second conductive layer, the drain electrode further comprises aneighth conductive layer stacked on the fourth conductive layer, and the gate electrode further comprises a ninth conductive layer stacked on the sixth conductive layer,

wherein the seventh, eighth, and ninth conductive layers have the same material.
The nitride-based semiconductor device of claim 14, wherein the ninth conductive layer has at least one material different than the materials of the fifth and sixth conductive layers.
A method for manufacturing a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

forming a doped nitride-based semiconductor layer over the second nitride-based semiconductor layer;

forming a nitride-based conductive layer over the doped nitride-based semiconductor layer;

forming a protection layer covering the doped nitride-based semiconductor layer and the nitride-based conductive layer;

forming a first hole and a second hole in the protection layer to expose a portion of the second nitride-based semiconductor layer and a portion of the nitride-based conductive layer, respectively; and

forming a source electrode in the first hole and a gate electrode in the second hole in the same photolithography process.
The method of claim 16, wherein forming a first hole and a second hole comprises removing a portion of the nitride-based conductive layer.
The method of claim 17, wherein the nitride-based conductive layer has a recessed top surface after the formation of the second hole.
The method of claim 16, wherein forming the source electrode and the gate electrode comprises:

patterning a single blanket conductive layer to form the source electrode and the gate electrode which are separated from each other.
The method of claim 19, wherein the single blanket conductive layer fills into the first hole and the second hole.
A nitride-based semiconductor device comprising:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;

a doped nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer;

a protection layer disposed over the second nitride-based semiconductor layer and covering the doped nitride-based semiconductor layer;

a source electrode and a drain electrode disposed over the second nitride-based semiconductor layer and penetrating the protection layer to make contact with the second nitride-based semiconductor layer; and

a gate electrode disposed over the doped nitride-based semiconductor layer and between the source electrode and the drain electrode, wherein end portions of the source electrode, the drain electrode, and the gate electrode are located on a top surface of the protection layer and have substantially the same thickness.
The nitride-based semiconductor device of claim 21, wherein the end portions of the source electrode, the drain electrode, and the gate electrode are located at the same level of height.
The nitride-based semiconductor device of claim 21, wherein each of the source electrode, the drain electrode, and the gate electrode is in a U-shaped profile.
The nitride-based semiconductor device of claim 23, wherein the gate electrode has an outline different than those of the source electrode and the drain electrode.
The nitride-based semiconductor device of claim 21, wherein the gate electrode has a bottom-most portion at a position higher than bottom-most portions of the source electrode and the drain electrode.