WO2023238755A1 - Field effect transistor - Google Patents

Abstract

The present invention provides a field effect transistor 1 which is provided with: an n-type first semiconductor layer 10 that is formed of a gallium oxide semiconductor; a second semiconductor layer 11 that is formed of Si and is arranged on the first semiconductor layer 10; first and second p-type semiconductor parts 13a, 13b that are respectively buried in first and second trenches 12a, 12b; a gate electrode 16 that is covered by a gate insulating film 15 and is buried in a third trench 14 which is configured such that one lateral surface and a part of the bottom surface thereof are formed of the first p-type semiconductor part 13a; an n-type region 111 that is provided on at least a part of the surface layer of the second semiconductor layer 11 in a region between trenches, the part being on the third trench 14 side; and a p-type region 112 that is provided in a region between the n-type region 111 and the first semiconductor layer 10 in the region between trenches.

Description

field effect transistor

The present invention relates to field effect transistors.

Conventionally, a field effect transistor having a trench gate structure and using β-Ga ₂ O ₃ and Si as a semiconductor layer is known (see Patent Document 1). In the field effect transistor described in Patent Document 1, the bottom of the trench where the electric field is concentrated is provided in the β-Ga ₂ O ₃ layer with high dielectric breakdown electric field strength, so that dielectric breakdown of the semiconductor layer can be suppressed. can.

Also, conventionally, a field effect transistor having a trench gate structure is known in which a p-type region overlapping a gate oxide film region is provided in a semiconductor layer made of SiC (see Non-Patent Document 1). In the field effect transistor described in Non-Patent Document 1, concentration of the electric field at the bottom of the trench can be alleviated by the p-type region overlapping the gate oxide film region.

Patent No. 6873516

D. Peters et, al., “CoolSiC Trench MOSFET Combining SiC Performance with Silicon Ruggedness”, Issue 3 Power electronics Europe 2017.

In order to obtain a field effect transistor with particularly excellent reliability, a p-type region overlapping the gate oxide film region described in Non-Patent Document 1 is applied to the field effect transistor described in Patent Document 1, and a p-type region overlapping the gate oxide film region described in Non-Patent Document 1 is applied to the field effect transistor described in Patent Document 1. Ideally, the concentration of the electric field should be alleviated. In this case, not only the dielectric breakdown of the semiconductor layer around the bottom of the trench but also the dielectric breakdown of the gate insulating film is suppressed, and further improvement in the reliability of the field effect transistor can be expected.

However, since p-type β-Ga ₂ O ₃ with good conductivity does not exist, the electric field described in Patent Document 1, like the p-type region in SiC in the field effect transistor described in Non-Patent Document 1, A p-type region cannot be formed by converting a part of β-Ga ₂ O ₃ in an effect transistor into a p-type. Therefore, the p-type region overlapping the gate oxide film region described in Non-Patent Document 1 cannot be applied to the field effect transistor described in Patent Document 1.

An object of the present invention is to provide a field effect transistor having a trench gate structure and having higher reliability.

In order to achieve the above object, one embodiment of the present invention provides the following field effect transistors [1] to [5].

[1] An n-type first semiconductor layer made of a gallium oxide-based semiconductor, a second semiconductor layer made of Si provided on the first semiconductor layer, and a top surface of the second semiconductor layer. First and second p-type semiconductor parts embedded in the first and second trenches reaching the first semiconductor layer, respectively, and one side surface and a part of the bottom surface of the first p-type semiconductor a gate electrode covered with a gate insulating film and buried in a third trench extending from the upper surface of the second semiconductor layer to the first semiconductor layer; In the surface layer of the inter-trench region between the second trench and the third trench of the second semiconductor layer, an n-type region provided at least in a part of the third trench side, and the inter-trench region. a p-type region provided in a region between the first semiconductor layer and the n-type region so as to isolate the first semiconductor layer and the n-type region; and a p-type region connected to the n-type region. A field effect transistor comprising a source electrode and a drain electrode connected to the first semiconductor layer.
[2] The field effect transistor according to [1] above, wherein a second n-type region is provided in a region between the first semiconductor layer and the p-type region in the inter-trench region.
[3] The field effect transistor according to [1] above, wherein a second p-type region is provided in a region between the n-type region and the second trench in a surface layer of the inter-trench region.
[4] The field effect transistor according to any one of [1] to [3] above, wherein the p-type semiconductor portion is made of a p-type oxide semiconductor.
[5] The field effect transistor according to [4] above, wherein the p-type oxide semiconductor is p-type NiO, CuO, or Cu ₂ O.

According to the present invention, it is possible to provide a field effect transistor having a trench gate structure and having higher reliability.

FIG. 1 is a vertical cross-sectional view of a field effect transistor according to an embodiment of the invention. FIG. 2A is a vertical cross-sectional view showing an example of a manufacturing process of a field effect transistor. FIG. 2B is a vertical cross-sectional view showing an example of the manufacturing process of a field effect transistor. FIG. 2C is a vertical cross-sectional view showing an example of a manufacturing process of a field effect transistor. FIG. 3A is a vertical cross-sectional view showing an example of a manufacturing process of a field effect transistor. FIG. 3B is a vertical cross-sectional view showing an example of the manufacturing process of a field effect transistor. FIG. 3C is a vertical cross-sectional view showing an example of the manufacturing process of a field effect transistor. FIG. 4A is a graph showing off-breakdown voltage characteristics of a field effect transistor. FIG. 4B is a graph showing gate characteristics of a field effect transistor. FIG. 4C is a graph showing the on-characteristics of a field effect transistor.

(Configuration of field effect transistor)
FIG. 1 is a vertical cross-sectional view of a field effect transistor 1 according to an embodiment of the invention. The field effect transistor 1 is a vertical field effect transistor having a trench gate structure.

The field effect transistor 1 includes an n-type first semiconductor layer 10 made of a gallium oxide-based semiconductor, a second semiconductor layer 11 made of Si provided on the first semiconductor layer 10, and a second semiconductor layer 11 made of Si. A first p-type semiconductor section 13a and a second p-type semiconductor section 13b are respectively embedded in a first trench 12a and a second trench 12b reaching from the upper surface of the layer 11 to the first semiconductor layer 10; In the third trench 14 extending from the upper surface of the second semiconductor layer 11 to the first semiconductor layer 10, the side surface and part of the bottom surface are formed by the first p-type semiconductor part 13a. , the gate electrode 16 covered and buried in the gate insulating film 15 and the region between the second trench 12b and the third trench 14 of the second semiconductor layer 11 (hereinafter referred to as the inter-trench region). In the surface layer, a first semiconductor layer is formed in an n-type region 111 provided at least in a part of the third trench 14 side, and in a region between the first semiconductor layer 10 and the n-type region 111 in the inter-trench region. 10 and an n-type region 111, a source electrode 17 connected to the n-type region 111, and a drain electrode 18 connected to the first semiconductor layer 10. Note that the gate electrode 16 on the left side shown in FIG. 1 is used for a field effect transistor adjacent to the left side of the field effect transistor 1.

The field effect transistor 1 may be of a normally-off type or a normally-on type, but when used as a power device, it is usually manufactured as a normally-off type from the viewpoint of safety. This is to prevent conduction between the source electrode 17 and the drain electrode 18 when the gate becomes uncontrollable due to disconnection of the gate circuit or the like.

In the normally-off field effect transistor 1, by applying a voltage equal to or higher than the gate threshold voltage between the gate electrode 16 and the source electrode 17, the gate insulating film 15 side of the p-type region 112 in the inter-trench region is A vertical channel is formed in the region, allowing current to flow between the source electrode 17 and the drain electrode 18.

The first semiconductor layer 10 is made of a single crystal of a gallium oxide semiconductor having a β-type crystal structure. Here, the gallium oxide semiconductor refers to Ga ₂ O ₃ or Ga ₂ O ₃ to which elements such as Al and In are added. For example, a gallium oxide semiconductor has a composition expressed as (Ga _x Al _y In _(1-x-y) ) ₂ O ₃ (0<x≦1, 0≦y≦1, 0<x+y≦1). have When Al is added to Ga ₂ O ₃ , the band gap is widened, and when In is added, the band gap is narrowed. Furthermore, the first semiconductor layer 10, which is n-type, contains donor impurities such as Si and Sn.

Further, the first semiconductor layer 10 typically includes a layer 101 with a high donor concentration for ohmic connection to the drain electrode 18 and a layer 102 thereon, as shown in FIG. For example, layer 101 has a donor concentration of 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less, and layer 102 has a donor concentration of 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁷ cm ⁻³ or less. It has a donor concentration. Further, for example, the thickness of the layer 101 is 30 μm or more and 600 μm or less, and the thickness of the layer 102 is 5 μm or more and 50 μm or less.

The layer 101 of the first semiconductor layer 10 is typically made of a gallium oxide semiconductor substrate. The substrate in this case is, for example, a bulk gallium oxide single crystal grown by a melt growth method such as the FZ (Floating Zone) method or the EFG (Edge Defined Film Fed Growth) method, sliced, and the surface polished. formed by. Further, the layer 102 of the first semiconductor layer 10 is typically an epitaxial film formed using the upper surface of the layer 101 as a base surface.

The second semiconductor layer 11 is a layer made of single crystal Si. The n-type region 111 and the p-type region 112 formed in the second semiconductor layer 11 are formed, for example, by implanting donor impurities and acceptor impurities into the second semiconductor layer 11.

The n-type region 111 formed in the second semiconductor layer 11 is the source of the field effect transistor 1. The n-type region 111 contains a donor impurity such as arsenic, and has a high donor concentration of, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less in order to ohmically connect the source electrode 17.

The p-type region 112 formed in the second semiconductor layer 11 contains an acceptor impurity such as boron, and has an acceptor concentration of, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less.

If the second semiconductor layer 11 is too thin, it becomes difficult to form the n-type region 111 and the p-type region 112, and if it is too thick, the first trench 12a, the second trench 12b, and the third trench 14 are formed deeply. I will have to. Therefore, it is preferable that the thickness D1 of the second semiconductor layer 11 is, for example, 0.6 μm or more and 1.2 μm or less.

The method for forming the second semiconductor layer 11 is not particularly limited. For example, a Si single crystal may be epitaxially grown using the upper surface of the first semiconductor layer 10 as a base surface. In order to form a silicon substrate, a Si substrate is bonded to the first semiconductor layer 10 using a substrate bonding technique such as a surface activated bonding method, and the Si substrate thinned by a thinning technique such as a smart cut method is bonded to a second semiconductor layer 10. Layer 11 is preferred.

Note that in a field effect transistor having a trench gate structure, for its operation, it is necessary for an n-type semiconductor layer and a p-type semiconductor layer to form a pn junction. When the semiconductor layer is composed of a layer made of a gallium oxide-based semiconductor and a layer made of Si, it is difficult to form a pn junction between them, which are different materials. For example, a layer of SiGa or Ga metal is formed at the interface between an n-type semiconductor layer and a p-type semiconductor layer, or because Si acts as a donor in a gallium oxide semiconductor, Si is removed from the p-type semiconductor layer. A pn junction may not be obtained due to the formation of a layer with extremely high donor concentration near the interface of the n-type semiconductor layer due to diffusion.

Therefore, as shown in FIG. 1, a second n-type region 113 is provided in the region between the n-type first semiconductor layer 10 and the p-type region 112 in the inter-trench region of the second semiconductor layer 11. It is preferable that the In this case, the p-n junction is not between the first semiconductor layer 10 made of a gallium oxide semiconductor and the p-type region 112 made of Si, but between the second n-type region 113 and the p-type region 112, both made of Si. Therefore, it is only necessary to form an interface that makes ohmic contact, and the interface does not need to be flat or steep. That is, a pn junction can be easily formed. The second n-type region 113 contains a donor impurity such as phosphorus, and has a donor concentration of, for example, 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁷ cm ⁻³ or less.

Further, as shown in FIG. 1, a second p-type region 114 is provided in a region between the n-type region 111 and the second trench 12b in the surface layer of the inter-trench region of the second semiconductor layer 11. It is preferable that the Thereby, the bulk of the field effect transistor 1 in the p-type region 112 in the inter-trench region can be fixed to the ground potential together with the source potential using the second p-type region 114. Second p-type region 114 contains an acceptor impurity such as boron. The acceptor concentration of the second p-type region 114 is higher than that of the p-type region 112, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less.

The first trench 12a and the second trench 12b reach from the upper surface of the second semiconductor layer 11 (the surface opposite to the first semiconductor layer 10) to the first semiconductor layer 10. That is, the bottoms of the first trench 12a, the second trench 12b, and the first p-type semiconductor part 13a and the second p-type semiconductor part 13b buried therein are located above the upper surface of the first semiconductor layer 10 (the second trench 12b). (the surface on the semiconductor layer 11 side).

The first p-type semiconductor section 13a and the second p-type semiconductor section 13b are made of p-type semiconductors such as NiO, CuO, and _Cu2O , which do not easily react with the gallium oxide semiconductor that constitutes the first semiconductor layer 10. It is preferable that it is made of a p-type oxide semiconductor such as. When NiO is used as the material for the first p-type semiconductor section 13a and the second p-type semiconductor section 13b, a high breakdown voltage can be obtained due to the large band gap of 3.7 eV that NiO has. When CuO or Cu ₂ O is used, the breakdown voltage is lower than that of NiO, but the material cost can be reduced compared to NiO. Note that these materials may be amorphous, polycrystalline, or single crystal, or may be a composite of two or more of these materials.

By providing the first p-type semiconductor section 13a and the second p-type semiconductor section 13b, when applying a reverse bias between the gate electrode 16 and the source electrode 17 of the field effect transistor 1 (when off), The electric field is concentrated at the bottoms of the first p-type semiconductor section 13a and the second p-type semiconductor section 13b. Since the bottoms of the first p-type semiconductor part 13a and the second p-type semiconductor part 13b are located in the first semiconductor layer 10 made of a gallium oxide semiconductor with high dielectric breakdown field strength, the semiconductor layer 10 is formed by electric field concentration. dielectric breakdown is suppressed, and the withstand voltage of the field effect transistor 1 is increased. Then, by providing the first p-type semiconductor part 13a and the second p-type semiconductor part 13b and concentrating the electric field in the first semiconductor layer 10, the material of the second semiconductor layer 11 in which the channel is formed is changed. Si, which has a lower dielectric breakdown field strength and higher electron mobility than a gallium oxide-based semiconductor, can be used to reduce the channel resistance and the on-resistance of the device. Furthermore, Ga ₂ O ₃ and Si are cheaper than SiC, and Ga ₂ O ₃ has lower loss performance that exceeds that of SiC.

Further, one side surface and a part of the bottom surface of the third trench 14 are formed by the first p-type semiconductor part 13a, and the gate electrode 16 covered with the gate insulating film 15 in the third trench 14 is formed by the first p-type semiconductor part 13a. A portion of the bottom surface, for example, about half of the cross section shown in FIG. 1, is covered by the first p-type semiconductor portion 13a. Therefore, the electric field can be concentrated at the bottom of the first p-type semiconductor section 13a, and the electric field at the bottom of the third trench 14 can be reduced. Thereby, dielectric breakdown of the first semiconductor layer 10 and the gate insulating film 15 around the bottom of the third trench 14 can be suppressed, and the reliability of the field effect transistor 1 can be improved. Note that it is not preferable that the entire bottom surface of the gate electrode 16 covered with the gate insulating film 15 be covered with the first p-type semiconductor portion 13a, since there is a concern that the resistance will increase due to a phenomenon called parasitic JFET.

In order to cause a spatial modulation effect of the electric field by narrowing the n-type layer 102, the distance between the first p-type semiconductor part 13a and the second p-type semiconductor part 13b, that is, the width D10 of the inter-trench region, is set to 1. It is preferably .2 μm or more and 2.0 μm or less.

Further, in order to shield the electric field to the end of the gate electrode due to the spatial modulation effect, the depth D7 of the first trench 12a from the interface between the first semiconductor layer 10 and the second semiconductor layer 11 is set to be 1.6 μm or more. , preferably 3.0 μm or less.

Further, in order to achieve electric field relaxation due to the further spatial modulation effect of the n-type layer 102, the horizontal distance D14 between the second trench 12b and the third trench 14 is set to 0.8 μm or more and 1.2 μm or less. It is preferable that

The gate electrode 16 is made of, for example, polycrystalline Si to which a donor is added at a high concentration, tungsten, or tungsten silicide, which is a compound of tungsten and Si. The gate electrode 16 has its side and bottom surfaces covered with a gate insulating film 15 and its top surface covered with an insulating film 19 .

The gate insulating film 15 insulates the gate electrode 16 from the first semiconductor layer 10 and the second semiconductor layer 11, and the insulating film 19 insulates the gate electrode 16 from the source electrode 17. The gate insulating film 15 and the insulating film 19 are made of, for example, HfO ₂ , Al ₂ O ₃ , or SiO ₂ . The thickness of the gate insulating film 15 is, for example, 30 nm or more and 100 nm or less. The thickness of the insulating film 19 is, for example, 30 nm or more and 100 nm or less.

The source electrode 17 is made of a metal such as aluminum, and is ohmically connected to the n-type region 111 of the second semiconductor layer 11. Further, the drain electrode 18 is made of a metal such as titanium or aluminum, and is ohmically connected to the first semiconductor layer 10 .

The horizontal pattern of the first p-type semiconductor part 13a and the second p-type semiconductor part 13b (that is, the horizontal pattern of the first trench 12a and the second trench 12b), the gate insulating film 15, and the gate electrode 16 The horizontal pattern (that is, the horizontal pattern of the third trench 14) and the horizontal pattern of the n-type region 111 and the second p-type region 114 are not particularly limited. For example, the first trench 12a and the second trench 12b may be connected at a portion that does not appear in the vertical cross section of FIG.

(Manufacture of field effect transistors)
2A to 2C and FIGS. 3A to 3C are vertical cross-sectional views showing an example of the manufacturing process of the field effect transistor 1. The manufacturing steps shown in FIGS. 2A to 2C and 3A to 3C will be described below.

First, as shown in FIG. 2A, an n-type first semiconductor layer 10, which is a substrate made of a gallium oxide semiconductor, and an n-type Si substrate 20 containing donor impurities such as phosphorus are prepared, and the surface Paste together using the activation bonding method.

Here, a planar ion implantation region 21 is formed in the Si substrate 20 at a predetermined depth from the junction surface with the first semiconductor layer 10 by ion implantation of hydrogen ions. As will be described later, the Si substrate 20 is divided using the ion implantation region 21 as a division plane, and the film separated from the Si substrate 20 becomes the second semiconductor layer 11. Therefore, the ion implantation region from the bonding surface of the Si substrate 20 The depth of 21 is determined depending on the desired thickness of the second semiconductor layer 11.

The dose of hydrogen ions implanted to form the ion implantation region 21 is, for example, 2×10 ¹⁶ to 8×10 ¹⁶ /cm ² . In addition, the implantation energy of ion implantation is determined by the depth of the ion implantation region 21 from the junction surface. For example, when forming the ion implantation region 21 at a depth of about 950 nm from the junction surface, the energy of approximately 110 keV is determined. ion implantation of hydrogen ions.

In the surface activated bonding method, the first semiconductor layer 10 is planarized by a planarization process such as CMP (chemical mechanical polishing) in an ultra-high vacuum chamber under a pressure of about 5×10 ⁻⁶ Pa, for example. The outermost surfaces of the bonding surfaces of the substrate and the Si substrate 20 are removed by irradiation with an Ar atom beam accelerated with an energy of 1.5 keV, and the newly exposed surfaces are brought into contact and bonded.

Next, as shown in FIG. 2B, heat treatment is applied to the bonded first semiconductor layer 10 and Si substrate 20 to cause hydrogen embrittlement in the ion implantation region 21 and divide the Si substrate 20 (smart cut ), leaving the second semiconductor layer 11 on the first semiconductor layer 10.

The heat treatment in Smart Cut is performed, for example, in an N ₂ or Ar atmosphere for 1 to 10 minutes. Note that the heat treatment may be performed in a vacuum chamber under reduced pressure, or may be performed in a furnace other than the vacuum chamber. After the smart cut, heat treatment is performed again to recover the damage to the second semiconductor layer 11 caused by the ion implantation and the smart cut. Thereafter, the surface of the second semiconductor layer 11 may be subjected to a planarization process such as CMP.

Next, as shown in FIG. 2C, an acceptor impurity such as boron is ion-implanted into the second semiconductor layer 11 to form a p-type region 112 and a second p-type region 114, and the second semiconductor layer An n-type region 111 is formed by ion-implanting a donor impurity such as arsenic into the region 11 . A region of the n-type second semiconductor layer 11 into which impurities are not implanted is defined as a second n-type region 113.

Next, as shown in FIG. 3A, a first trench 12a and a second trench 12b are formed in the stacked body of the first semiconductor layer 10 and the second semiconductor layer 11, and the first trench 12a and the second trench 12b are A first p-type semiconductor section 13a and a second p-type semiconductor section 13b are formed in the two trenches 12b, respectively.

The first trench 12a and the second trench 12b are formed by, for example, photolithography and dry etching. The first p-type semiconductor part 13a and the second p-type semiconductor part 13b are formed by depositing a material into the first trench 12a and the second trench 12b by, for example, CVD (Chemical Vapor Deposition), vacuum evaporation, sputtering, or the like. Let it form.

Next, as shown in FIG. 3B, a third trench 14 is formed in the stack of the first semiconductor layer 10 and the second semiconductor layer 11. The third trench 14 is formed so as to partially overlap the first trench 12a in the width direction. The third trench 14 is formed by, for example, photolithography and dry etching.

Next, as shown in FIG. 3C, a gate insulating film 15 and a gate electrode 16 are formed in the third trench 14. The gate insulating film 15 and the gate electrode 16 are formed by depositing a material in the third trench 14 by, for example, CVD, vacuum deposition, sputtering, or the like.

Thereafter, an insulating film 19, a source electrode 17, and a drain electrode 18 are formed to obtain a field effect transistor 1. The insulating film 19 is formed by depositing a material on the gate electrode 16 by, for example, CVD, vacuum deposition, sputtering, or the like. The source electrode 17 and the drain electrode 18 are formed by depositing materials on the upper surface of the second semiconductor layer 11 and the lower surface of the first semiconductor layer 10, respectively, by sputtering or the like, for example.

(Characteristics of field effect transistor)
Below, simulation results of the electric field distribution, OFF breakdown voltage characteristics, gate characteristics, and ON characteristics when a reverse bias is applied to the gate electrode 16 of the field effect transistor 1 (when off) will be described.

Table 1 below shows the dimensions D1 to D18 (see FIG. 1) of each part of the field effect transistor 1 used in this simulation.

Further, the material of the first semiconductor layer 10 is Ga ₂ O ₃ , the material of the first p-type semiconductor part 13a and the second p-type semiconductor part 13b is NiO, the material of the gate electrode 16 is polycrystalline Si, and the gate insulation material is The material of the film 15 was SiO ₂ .

Further, the thickness of the gate insulating film 15 is 50 nm, the thickness of the first semiconductor layer 10 is 5 μm, and the interface trap level density between the first semiconductor layer 10 and the second semiconductor layer 11 is 2×10 ¹² cm ^{− 2} /eV, the radius of curvature of the corners at both ends of the bottom of the first trench 12a, second trench 12b, and third trench 14 shown in the cross section of FIG. The rate was set at 3.9.

Table 2 below shows the donor concentration or acceptor concentration of each part of the field effect transistor 1 used in this simulation.

When a voltage of 1400 V is applied to the drain electrode 18 of the above field effect transistor 1 (the source electrode 17 is grounded), the electric field strengths at points P1, P2, and P3 (see FIG. 1) are respectively They were approximately 6MV/cm, 4MV/cm, and 0.3MV/cm. Here, point P1 is a point in the first semiconductor layer 10 around the bottom of the first trench 12a, and point P2 is a point in the gate insulating film 15 around the bottom of the third trench 14. , point P3 is a point on the interface between p-type region 112 and second n-type region 113.

The electric field at point P1 was the strongest inside the field effect transistor 1, and the electric field strength at points P2 and P3 was kept low as described above. From this, when a reverse bias is applied to the gate electrode 16 of the field effect transistor 1, the electric field is concentrated at the bottom of the first p-type semiconductor part 13a, and the electric field is concentrated around the bottom of the third trench 14 and the first semiconductor layer. It was confirmed that the electric field around the interface between the semiconductor layer 10 and the second semiconductor layer 11 was relaxed. Therefore, it is possible to suppress dielectric breakdown of the first semiconductor layer 10 and the gate insulating film 15 around the bottom of the third trench 14 where the electric field tends to concentrate.

FIG. 4A is a graph showing the off-breakdown voltage characteristics of the field effect transistor 1. The graph in FIG. 4A shows the change in drain current when the gate voltage applied to the gate electrode 16 is fixed at -5V and the drain voltage applied to the drain electrode 18 is changed. FIG. 4A shows that avalanche breakdown occurs when the drain voltage exceeds approximately 1400V.

FIG. 4B is a graph showing the gate characteristics of the field effect transistor 1. The graph in FIG. 4B shows the change in drain current when the drain voltage applied to the drain electrode 18 is fixed at 1V and the gate voltage applied to the gate electrode 16 is changed. FIG. 4B shows that the gate threshold voltage is approximately 2V.

FIG. 4C is a graph showing the on-characteristics of the field effect transistor 1. The graph in FIG. 4C shows the change in drain current when the gate voltage applied to the gate electrode 16 is fixed at 15 V and the drain voltage applied to the drain electrode 18 is changed. According to FIG. 4C, for example, the on-resistance when the gate voltage is 15 V and the drain voltage is 1 V is approximately 3.2 mΩcm ² .

(Effects of embodiment)
According to the embodiment of the present invention, the bottom of the third trench 14 in which the gate electrode 16 is embedded is placed in the n-type first semiconductor layer 10 made of a gallium oxide semiconductor with high dielectric breakdown field strength. Furthermore, by relaxing the electric field around the bottom of the third trench 14 by the first p-type semiconductor part 13a, the insulation of the first semiconductor layer 10 and the gate insulating film 15 around the bottom of the third trench 14 is reduced. Destruction can be suppressed and reliability of the field effect transistor 1 can be improved.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. Furthermore, the constituent elements of the embodiments described above can be arbitrarily combined without departing from the spirit of the invention.

Furthermore, the embodiments described above do not limit the claimed invention. Furthermore, it should be noted that not all combinations of features described in the embodiments are essential for solving the problems of the invention.

A field effect transistor having a trench gate structure and having higher reliability is provided.

DESCRIPTION OF SYMBOLS 1... Field effect transistor, 10... First semiconductor layer, 11... Second semiconductor layer, 111... N type region, 112... P type region, 113... Second n type region, 114... Second p type Region, 12a...first trench, 12b...second trench, 13a...first p-type semiconductor section, 13b...second p-type semiconductor section, 14...third trench, 15...gate insulating film, 16 ...gate electrode, 17...source electrode, 18...drain electrode

Claims (5)

an n-type first semiconductor layer made of a gallium oxide-based semiconductor;
a second semiconductor layer made of Si provided on the first semiconductor layer;
first and second p-type semiconductor parts respectively embedded in first and second trenches reaching from the top surface of the second semiconductor layer to the first semiconductor layer;
A third trench extending from the top surface of the second semiconductor layer to the first semiconductor layer, which is provided so that one side surface and a part of the bottom surface are formed by the first p-type semiconductor part. a gate electrode covered with a gate insulating film and buried;
an n-type region provided in at least a part of the third trench side in a surface layer of an inter-trench region between the second trench and the third trench of the second semiconductor layer;
a p-type region provided in a region between the first semiconductor layer and the n-type region in the inter-trench region so as to isolate the first semiconductor layer and the n-type region;
a source electrode connected to the n-type region;
a drain electrode connected to the first semiconductor layer;
A field effect transistor with. a second n-type region is provided in a region between the first semiconductor layer and the p-type region in the inter-trench region;
A field effect transistor according to claim 1. a second p-type region is provided in a surface layer of the inter-trench region between the n-type region and the second trench;
A field effect transistor according to claim 1. The p-type semiconductor portion is made of a p-type oxide semiconductor,
The field effect transistor according to any one of claims 1 to 3. the p-type oxide semiconductor is p-type NiO, CuO, or Cu ₂ O;
The field effect transistor according to claim 4.

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