WO2023213080A1 - Method for realizing network node time synchronization based on fpga - Google Patents

Abstract

The present invention particularly relates to a method for realizing network node time synchronization based on an FPGA, comprising the following steps: constructing a local clock module; designing a pulse synchronization module on the basis of constructing the local clock module; on the basis of designing the pulse synchronization module, encapsulating Ethernet message frames in a path delay measurement process and a time synchronization process; on the basis of encapsulating the Ethernet message frames in the path delay measurement process and the time synchronization process, recording a timestamp value of a moment when a message is sent at node i and a timestamp value of a moment when the message is received at node i+1; on the basis of recording the timestamp value of the moment when the message is sent at node i and the timestamp value of the moment when the message is received at node i+1, calculating the obtained timestamp values to obtain a path delay measurement result; and on the basis of calculating the obtained timestamp values to obtain the path delay measurement result, sending a time synchronization message. Provided is a time synchronization method having low cost, high precision and stability, which meets accurate scheduling and various communication requirements.

Description

Method to realize network node time synchronization based on FPGA Technical field

The present invention relates to the technical field of communication, and in particular to a method for realizing time synchronization of network nodes based on FPGA.

Background technique

The development of new applications such as the Industrial Internet of Things and autonomous driving has placed higher requirements on communication network performance. Ethernet technology has been introduced into the above applications with its advantages of high bandwidth and low cost. However, traditional Ethernet cannot meet the deterministic and low-latency transmission requirements of the above applications, and time-sensitive network technology (Time Sensitive Networking (TSN) provides an effective way to solve this problem through business scheduling and resource management and other initiatives. In the TSN standards set, IEEE The time synchronization technology provided by the 802.1 AS protocol can enable the nodes in the network that implement this protocol to achieve final time synchronization through signaling interaction, thus providing the possibility for TSN deterministic, low-latency service scheduling and resource management.

Currently, the IEEE 802.1 AS protocol is mostly implemented through the software layer. A protocol implementation method based on Linux environment has been disclosed. It is driven by Intel I210 network card to obtain soft timestamps and measure the time delay when the network is under different loads. However, during the test, it was found that the measured delay value was quite different from the theoretical value. One of the reasons is that the soft timestamp is susceptible to network fluctuations, and its accuracy cannot be guaranteed. At the software level, a state machine function related to path delay measurement and time synchronization is designed, and the interaction and analysis of packets in the network are realized by calling the function. However, this solution is prone to packet loss when network congestion occurs, causing problems for the network. Time synchronization brings uncertainty. Although the software implementation is low-cost and self-adaptive, the soft clock has low accuracy, weak stability, and is greatly affected by network fluctuations, which greatly reduces the synchronization accuracy and affects the quality of TSN communication services. The use of hardware to achieve clock synchronization will provide the network with high-precision (us-level synchronization error) synchronization clocks, thereby meeting more precise communication needs such as scheduling and resource management, as well as new application scenario needs (such as multi-sensor information synchronization analysis, etc.). Current hardware research on synchronization applications mostly uses software to process messages, and also calls Nios The II embedded soft core processes gPTP messages. Since its network data transmission and real-time clock use the system's own IP core, its measurement accuracy will have a large deviation. For obtaining timestamps, the above method generates timestamps at the MAC layer through the corresponding network card driver. However, the processing time of the timestamps in the MAC layer is difficult to determine, which will affect its accuracy to a certain extent.

technical problem

For hardware research on synchronization applications, most of the message processing is implemented in software, and the Nios II embedded soft core is called to process gPTP messages. Since its network data transmission and real-time clock use the system's own ip core, The measurement accuracy will have a large deviation.

Technical solutions

Based on this, it is necessary to address the above technical issues and provide a method that implements message interaction and timestamp acquisition in the system on the FPGA hardware circuit and can correctly forward the messages in the path delay measurement and time synchronization process and generate high-precision A method of realizing network node time synchronization based on FPGA with hardware timestamp.

A method for realizing time synchronization of network nodes based on FPGA, the method includes:

Build a local clock module;

Based on the above-mentioned construction of the local clock module, the pulse synchronization module is designed;

Based on the designed pulse synchronization module, the Ethernet message frame of the path delay measurement process and time synchronization process is encapsulated;

Based on the Ethernet message frame of the encapsulation path delay measurement process and time synchronization process, record the timestamp value of the moment when the message is sent at the i node and the timestamp value of the moment when the message is received at the i+1 node;

Based on the timestamp value of the time when the recorded message is sent at the i node and the timestamp value of the time when the message is received at the i+1 node, calculate the obtained timestamp value to obtain the path delay measurement result;

Calculate the path delay measurement result based on the obtained timestamp value, and send a time synchronization message.

Further, the steps of building a local clock module include:

Use the FPGA onboard crystal oscillator to generate a stable clock signal to control the generation of an 80-bit counter as the master clock or slave clock in the network;

Select the appropriate clock frequency through the FPGA onboard crystal oscillator.

Further, the designed pulse synchronization module includes:

The pulse synchronization module is designed according to the number of bits of data sent or received in the network;

FPGA circuits at different nodes use different pulse synchronization methods to synchronize clock signals.

Further, the Ethernet message frame encapsulating the path delay measurement process and the time synchronization process includes:

The message type value specified by the protocol is added to the Ethernet data frame header to distinguish the message.

Further, the timestamp value of the time when the message was sent at the i node and the timestamp value of the time when the message was received at the i+1 node are recorded, including:

Encapsulate the timestamp value into a designated empty field of the Ethernet message frame for transmission;

The correctness of the data frames sent or received is checked through the CRC check module.

Further, the sending time synchronization message includes:

Record the timestamp of the moment when the message is sent from the master node and the timestamp of the moment when the message is received by the slave node;

The time synchronization offset is calculated based on the path delay measurement results.

Further, the method also includes: when implementing time synchronization of any two nodes and testing its time synchronization performance,

FPGAs realize full-duplex Ethernet link communication by sending data packets point-to-point;

Test whether the Ethernet link communication is normal by using network packet capture software.

Further, the FPGAs realize full-duplex Ethernet link communication by sending data packets point-to-point, and then include:

Two FPGA development boards record the timestamp value of the corresponding moment by sending and receiving corresponding messages;

Correct the time deviation of the two nodes to achieve time synchronization.

Further, correcting the time deviation of the two nodes to achieve time synchronization includes:

Output the corrected time deviation to the PC through the serial port;

Time synchronization accuracy is obtained through base conversion.

The above-mentioned method for realizing network node time synchronization based on FPGA is used to implement the Ethernet network node synchronization algorithm, including the following steps: building a local clock module. Based on building the local clock module, the pulse synchronization module is designed. Based on the designed pulse synchronization module, the Ethernet message frame of the path delay measurement process and time synchronization process is encapsulated. Based on the Ethernet message frame encapsulated path delay measurement process and time synchronization process, the timestamp value of the moment when the message is sent at the i node and the timestamp value of the moment when the message is received at the i+1 node are recorded. Based on the timestamp value of the time when the message was sent at node i and the timestamp value of the time when the message was received at node i+1, the obtained timestamp value is calculated to obtain the path delay measurement result. Based on the calculated timestamp value, the path delay measurement result is obtained, and a time synchronization message is sent.

beneficial effects

The method of the present invention implements link delay measurement and time error correction based on FPGA devices, and provides a stable clock source to obtain a hard timestamp that is highly accurate and not affected by network fluctuations, and can provide a high-precision synchronization clock for the network. It avoids the disadvantages caused by the software layer and provides a low-cost, high-precision and stable time synchronization method for Ethernet, thereby meeting the communication needs of more accurate scheduling and resource management as well as the needs of new application scenarios.

Description of the drawings

Figure 1 is a flow chart of a method for realizing time synchronization of network nodes based on FPGA according to an embodiment of the present invention.

Figure 2 is an overall design diagram of the system in this embodiment.

Figure 3 is a state machine jump flow chart of the FPGA message sending module in this embodiment.

Figure 4 is a state machine jump flow chart of the FPGA message receiving module in this embodiment.

Figure 5 is a flow chart of the master node obtaining timestamp state machine in this embodiment.

Figure 6 is a flow chart of a state machine for obtaining a timestamp from a node in this embodiment.

Figure 7 is a topology diagram of communication capabilities established by the FPGA in this embodiment.

Embodiments of the invention

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

As shown in Figures 1 to 2, in one embodiment, a method for realizing time synchronization of network nodes based on FPGA includes the following steps:

Step S110: Build a local clock module. The FPGA onboard crystal oscillator is used to generate a stable clock signal to control the generation of an 80-bit counter, which serves as a local clock module in the network, including a master clock or a slave clock, to provide a stable clock source for the network. The master clock serves as the time base and sends time information for time correction. The slave clock maintains synchronization with the master clock through the received time information.

Step S120: Design a pulse module based on building a local clock module. The single-bit signal is shot twice in different clock domains to synchronize the asynchronous clock, so that the data can be sampled and transmitted correctly when each clock edge arrives.

Step S130: Based on the designed pulse module, encapsulate the Ethernet message frame of the path delay measurement process and the time synchronization process. Enable packets to interact between the measured nodes, and use the packet type value specified by the protocol to add it to the Ethernet data frame header to distinguish the packets transmitted in the network.

Step S140: Based on the Ethernet message frame encapsulating the path delay measurement process and the time synchronization process, record the timestamp value of the time when the message is sent by the i node and the timestamp value of the time when the message is received by the i+1 node. The timestamp value is encapsulated into the designated empty field of the Ethernet message frame for transmission, and the correctness of the sent or received data frame is verified through the CRC check module.

S150: Based on the timestamp value of the time when the message was sent at the i node and the timestamp value of the time when the message was received at the i+1 node, calculate the obtained timestamp value to obtain the path delay measurement result. Parse the timestamp field in the data packet, calculate the deviation of the timestamp value obtained, and obtain the path delay measurement result.

S160: Calculate the obtained timestamp value to obtain the path delay measurement result, and send the time synchronization message. And record the timestamp of the time when the message is sent from the master node and the timestamp of the time when the message is received by the slave node. Based on the path delay measurement results, the time synchronization deviation is calculated.

When it is necessary to implement time synchronization of any two nodes and test its time synchronization performance, the following steps are included:

FPGAs realize full-duplex Ethernet link communication by sending data packets point-to-point. Use network packet capture software to test whether the communication is normal. If the communication is normal, perform the relevant operations from steps S110 to S160 in sequence.

Based on step S140, it also includes: two FPGA development boards correct the time deviation of the two nodes by sending and receiving corresponding messages and recording the timestamp value of the corresponding moment to achieve time synchronization.

Based on step S160, it also includes: outputting the corrected time deviation to the PC through the serial port, and obtaining the time synchronization accuracy through hexadecimal conversion.

In this embodiment, the local clock is an 80-bit counter, which is used to record the timestamp value of the moment when a message is sent or received later. The pulse synchronization module handles the issue of single-bit signals crossing clock domains and generates the reception completion signal Rec_done in the receive data clock domain. This signal controls the jump of the message sending state machine in the sending clock domain. The above functional modules are all programmed through the hardware programming language Verilog HDL is comprehensively implemented on FPGA devices. The Verilog pseudo code of this module is as follows:

//Module input and output signals//

(1): input tx_clk; //Send data clock//

input rx_clk; //Receive data clock//

input rst_n; //Reset signal//

input Rec_done; //Receive data completion signal//

output tx_start_en; //State machine trigger signal//

//Receive data completion signal and perform two-beat operation in the sending data clock domain//

(2): always @(posedge tx_clk or negedge rst_n) //Triggered by the rising edge of the clock or the falling edge of the reset signal//

          Rec_done _0 <= Rec_done;

          Rec_done _1 <= Rec_done _0; // Beat the Rec_done signal //

          Rec_done _2 <= Rec_done _1; // Beat the Rec_done signal twice //

//Exclusive OR operation is performed on the beat signal to obtain the sending data state machine trigger signal tx_start_en//

(3): assign tx_start_en = Rec_done _1 ^ Rec_done _2;

Among them, posedge means triggering on the rising edge of the clock, and negedge means triggering on the falling edge of reset.

As shown in Figure 3, in this embodiment, the message sending module adopts a three-stage state machine design to send data messages, which includes the preamble of the message, the frame start delimiter, and the Ethernet frame header. , IP header, UDP header, sent message type header, sent message data segment and CRC check, etc. The types of messages sent are: Pdelay_Resp, Pdelay_Resp_Follow_Up, and Sync. The Pdelay_Resp and Sync messages are event type messages. The reception and sending of such messages will trigger the MAC layer to sample the local clock; the Pdelay_Resp_Follow_Up message is general. Type message, used only to carry information. The module design Verilog pseudo code is as follows:

//Main input and output signals of the module//

1.input tx_clk; //Send data clock//

input rst_n; //Reset signal//

input tx_start_en; //State machine trigger signal//

input data; //Input data//

output txdata; //Data to be sent//

output txdone; //Send data completion signal//

//State machine jump//

2.always @(*) begin//Conditional judgment for jumping between state machines//

case(cur_state) //Select state machine//

idle : begin

If(skip_en) //When the skip signal skip_en is high level, jump to the next state //

Next_state = Send_preamble+SFD;

else

                                                                                  next_state =                        

end

……..                 //The middle state machines are the same as the above jump methods//

……..

……..

Send_ PDResp_data or SendPDResp_Fup_data or Send_Sync_data：begin//Send data field//

if(skip_en)

        next_state = Send_CRC;

else

next_state=Send_PDResp_head or SendPDResp_Fup_data or Send_Sync_data end

3.always @(posedge tx_clk or negedge rst_n)begin//Execute each state machine function//

(1) Initial state:

if(tx_start_en)//State machine trigger signal//

skip_en <= 1’b1;

(2) Send_preamble+SFD: //Send preamble and frame start delimiter//

preamble = 55-55-55-55-55-55-55;

SFD = 0xd5;

(3) Send_eth_head://Send Ethernet header//

D_MAC = FF_FF_FF_FF_FF_FF;//Destination MAC address//

S_MAC= 00_11_22_33_44_55;//Source MAC address//

Lenth/Type = 0x0800;//length/type//

(4) Send_ip_head//Send IP header//

(5) Send_udp_head//Send UDP header//

(6)Send_PDResp_head :0x3; //Send Pdelay_Resp message header, the header type value is 0x3//

or SendPDResp_Fup_head: 0xA; //Send Pdelay_Resp_Follow_Up message header, the header type value is 0xA//

or Send_Sync_head: 0x0; //Send Sync message header, the header type value is 0x0//

(7)Send_ PDResp_data: TimeStamp; //Send Pdelay_Resp data field, which is the timestamp value //

or SendPDResp_Fup_data: TimeStamp; //Send Pdelay_Resp_Follow_Up data field, which is the timestamp value //

or Send_Sync_data: TimeStamp; //Send Sync data field, which is the timestamp value //

(8) Send_CRC: //CRC check//

if(txdone)//Send completion signal and perform CRC check//

txdata <= crc_data;

end

As shown in Figure 4, in this embodiment, the message receiving module is used to receive the preamble and frame start delimiter (Recv_Preamble+SFD), Ethernet frame header (Recv_eth_head), IP header (Recv_ip_head), UDP header (Recv_udp_head), sending message type header (Recv_PDReq_head), sending message data segment (Recv_PDReq_data) and CRC check (Recv_CRC), etc. The type of received message is Pdelay_Req, and Pdelay_Req is an event type message. The signal rx_start_en is used as the trigger signal of this module to control the state machine to perform operations. In the process, the jump between each state machine is controlled by the signal Skip_en.

Assume that there are master-slave nodes in the system, as shown in Figure 5. In this embodiment, the timestamp values t ₁ , t ₂ , t ₃ , and t ₄ are all cleared in the reset state, and the signal that controls the reading of the timestamp is rd_t_m is set low. In the S1 state, when the message receiving module receives the Pdelay_Req message, it pulls the rd_t_m control signal high to read the timestamp value t ₂ of the reception moment from the local clock module. In the S2 state, after sending the Pdelay_Resp message, the rd_t_m control signal is pulled high to read the timestamp value t ₃ of the sending time from the local clock module. Then in the S3 state machine, the Pdelay_Resp_Follow_Up message will be sent carrying the timestamp t ₃ . When the path delay measurement operation is completed, in the S4 state machine, the main module sends a Sync message. At this time, the rd_t_m control signal will be pulled high to read the source timestamp value t _s of the sending time from the local clock module. Any error in the state machine execution during reading the timestamp value will jump back to the reset state.

As shown in Figure 6, in this embodiment, in the reset state, the timestamp values _t1 , _t2 , _t3 , and _t4 are all cleared, and the signal rd_t_s that controls the read timestamp is set to low level. In the S1 state machine, after the message sending module sends the Pdelay_Req message, the rd_t_s control signal is pulled high to read the timestamp value t ₁ of the sending time from the local clock module; in the S2 state machine, it is pulled high after receiving the Pdelay_Resp message. The rd_t_s control signal reads the timestamp value t ₄ of the reception time from the local clock module, and parses the timestamp value t ₂ carried in the Pdelay_Resp message; after receiving the Pdelay_Resp_Follow_Up message in the S3 state machine, it will parse the timestamp carried in the message. t ₃ ; In S4 state, calculate the path delay PathDelay through the formula after obtaining four timestamps. For example, formula (1) is as follows:

(1),

In formula (1), t ₁ indicates that the rd_t_s control signal is raised to read the timestamp value of the sending moment from the local clock module; t ₂ indicates the timestamp value carried in the Pdelay_Resp message; t ₃ indicates that the time stamp value is received in the S3 state machine After the Pdelay_Resp_Follow_Up message, the message will be parsed and carry a timestamp; t ₄ means that after receiving the Pdelay_Resp message in the S2 state machine, the rd_t_s control signal is raised to read the timestamp value of the reception moment from the local clock module.

After obtaining the path delay result, the Sync message sent by the master node in the S5 state is received by the slave node, and the timestamp value _tr of the reception moment is recorded in the S6 state, and the time carried in the Sync message is parsed. Stamp value t _s , and finally use the formula to calculate the time synchronization offset Offset in the S7 state and correct it. The formula is as follows:

(2),

In equation (2), t _r represents the timestamp value of the reception moment recorded in the S6 state; t _s represents the timestamp value of that moment carried in the Sync message; PathDelay represents the PathDelay value obtained by equation (1).

In order to facilitate calculation, in the time deviation correction module, the present invention uses a 320-bit registration signal rce_time[319:0] to encapsulate the recorded timestamps t ₁ , t ₂ , t ₃ and t ₄ . Each time The stamp is 80 bits, and from high to low it is t ₁ , t ₂ , t ₃ , t ₄ .

As shown in Figure 7, in this embodiment, when sending messages between nodes, it is necessary to ensure that the nodes can communicate normally. First, set the corresponding source MAC address, source IP address, destination MAC address, and destination IP address on the FPGA development board. Secondly, send messages to each other between nodes. Finally, use network packet capture software to capture the sent data packets and test Communication link connectivity.

The method proposed by the present invention to test the time synchronization accuracy is: first, the time deviation module calculates and obtains the time synchronization deviation Offset, and secondly, outputs the binary value to the PC through the serial port module, and the serial port debugging assistant on the PC displays the binary value, that is, the time For synchronization accuracy, the results obtained each time are collected, processed and analyzed by MATLAB software, and a time synchronization accuracy chart is drawn.

In the above-mentioned FPGA-based method for realizing network node time synchronization, the 80-bit counter generated by clock signal control serves as a local clock module to provide a stable clock source for the network. The Ethernet data frame is encapsulated through the message sending module and the message is sent from the i node to i+1 node, and records the timestamp of the message sending moment, and encapsulates the value into a data frame for sending. The message receiving module receives the corresponding data frame and records the timestamp value of the reception moment. Verify messages before receiving or sending them, and set up a synchronization module to handle cross-clock domain issues. Finally, the timestamp value obtained by parsing the message is corrected for deviation and time synchronized, and the time synchronization accuracy is output to the PC through the serial port. This solution implements link delay measurement and time error correction based on FPGA hardware circuits. The hard timestamp obtained by the stable clock source provided by the hardware has high accuracy and is not affected by network fluctuations, and can provide high accuracy for the network (us level synchronization error) synchronizes the clock, avoiding the disadvantages caused by the software layer, and provides a low-cost, high-precision, and stable time synchronization method for Ethernet, thereby meeting the communication needs of more accurate scheduling and resource management, and New application scenarios are needed.

The above-mentioned embodiments only express several implementation modes of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the patent scope of the present invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the patent of the present invention should be determined by the appended claims.

Industrial applicability

The present invention provides a low-cost, high-precision and stable time synchronization method for Ethernet, thereby meeting the communication needs of more accurate scheduling and resource management and the needs of new application scenarios.

Claims (9)

A method for realizing time synchronization of network nodes based on FPGA is characterized in that the method includes: Build a local clock module; Based on the above-mentioned construction of the local clock module, the pulse synchronization module is designed; Based on the designed pulse synchronization module, the Ethernet message frame of the path delay measurement process and time synchronization process is encapsulated; Based on the Ethernet message frame of the encapsulation path delay measurement process and time synchronization process, record the timestamp value of the time when the message is sent at the i node and the timestamp value of the time when the message is received at the i+1 node; Based on the timestamp value of the time when the recorded message is sent at the i node and the timestamp value of the time when the message is received at the i+1 node, calculate the obtained timestamp value to obtain the path delay measurement result; Calculate the path delay measurement result based on the obtained timestamp value, and send a time synchronization message. The method according to claim 1, characterized in that said building a local clock module includes: Use the FPGA onboard crystal oscillator to generate a stable clock signal to control the generation of an 80-bit counter as the master clock or slave clock in the network; Select the appropriate clock frequency through the FPGA onboard crystal oscillator. The method according to claim 1, characterized in that the designed pulse synchronization module includes: The pulse synchronization module is designed according to the number of bits of data sent or received in the network; FPGA circuits at different nodes use different pulse synchronization methods to synchronize clock signals. The method according to claim 1, characterized in that the Ethernet message frame encapsulating the path delay measurement process and the time synchronization process includes: The message type value specified by the protocol is added to the Ethernet data frame header to distinguish the message. The method according to claim 1, characterized in that the timestamp value of the time when the message is sent at the i node and the timestamp value of the time when the message is received at the i+1 node include: Encapsulate the timestamp value into a designated empty field of the Ethernet message frame for transmission; The correctness of the data frames sent or received is checked through the CRC check module. The method according to claim 1, characterized in that said sending a time synchronization message includes: Record the timestamp of the moment when the message is sent from the master node and the timestamp of the moment when the message is received by the slave node; The time synchronization offset is calculated based on the path delay measurement results. The method according to claim 1, characterized in that the method further includes: when implementing time synchronization of any two nodes and testing its time synchronization performance, FPGAs realize full-duplex Ethernet link communication by sending data packets point-to-point; Test whether the Ethernet link communication is normal by using network packet capture software. The method of claim 7, wherein the FPGAs implement full-duplex Ethernet link communication by sending data packets point-to-point, and then further includes: Two FPGA development boards record the timestamp value of the corresponding moment by sending and receiving corresponding messages; Correct the time deviation of the two nodes to achieve time synchronization. The method according to claim 8, characterized in that, correcting the time deviation of the two nodes to achieve time synchronization, then includes: Output the corrected time deviation to the PC through the serial port; Time synchronization accuracy is obtained through base conversion.