WO2023159649A1 - Phased array apparatus, communication device and control method - Google Patents

Abstract

The present application relates to the technical field of communication, and provides a phased array apparatus and a communication device, for use in realizing the phase synchronization of a plurality of chips when the plurality of chips are stitched to form a phased array, and reducing a phase error among the plurality of chips while reducing costs. The apparatus comprises a first power divider, a first chip, a second chip, a third chip and a fourth chip; a local oscillator output end of the first chip is coupled with an input end of the first power divider; two output ends of the first power divider are respectively coupled with a local oscillator input end of the second chip and a local oscillator input end of the third chip; a local oscillator output end of the second chip is coupled with a local oscillator input end of the first chip; a local oscillator output end of the third chip is coupled with a local oscillator input end of the fourth chip; the local oscillator output end of the first chip is used for outputting a local oscillator signal, the local oscillator signal being used for realizing the phase synchronization of the plurality of chips.

Description

A phased array device, communication device and control method technical field

The present application relates to the technical field of communication, and in particular to a phased array device, communication equipment and a control method.

Background technique

The millimeter wave frequency band has rich spectrum resources and high bandwidth, so it is widely used in 5G communication, microwave backhaul and indoor short-distance communication and other fields. In the millimeter wave frequency band, due to the large space loss of the signal in the channel, the phased array technology is usually used to realize the millimeter wave communication to improve the effective isotropic radiated power (EIRP) when the signal is transmitted. , thereby increasing the transmission distance.

For some application scenarios with higher EIRP requirements, it is generally realized by splicing multiple chips (die) to form a phased array. However, how to realize the phase synchronization of multiple chips in the splicing process is a problem worth studying.

Contents of the invention

The present application provides a phased array device, a communication device and a control method, which are used to realize phase synchronization of multiple chips when splicing multiple chips to form a phased array.

In order to achieve the above object, the application adopts the following technical solutions:

In a first aspect, a phased array device is provided, the device includes: a power divider network and a plurality of chips, the power divider network includes a first power divider, and the plurality of chips include a first chip, a second chip, a first chip Three chips and a fourth chip, each chip in the plurality of chips has a local oscillator input terminal and a local oscillator output terminal; wherein, the local oscillator output terminal of the first chip is coupled with the input terminal of the first power divider, and the first The two output terminals of the power divider are respectively coupled with the local oscillator input terminal of the second chip and the local oscillator input terminal of the third chip, the local oscillator output terminal of the second chip is coupled with the local oscillator input terminal of the first chip, and the third chip is coupled with the local oscillator input terminal of the third chip. The local oscillator output terminal of the chip is coupled to the local oscillator input terminal of the fourth chip; the local oscillator output terminal of the first chip is used to output a local oscillator signal, and the local oscillator signal is used to realize phase synchronization of the multiple chips.

In the above technical solution, the local oscillator signal output by the local oscillator output terminal of the first chip is divided into two local oscillator signals by the first power divider; the first local oscillator signal is used to drive the second chip to work, and is passed through the first power divider. The second chip outputs to the local oscillator input of the first chip to drive the first chip to work; the second local oscillator signal can be used to drive the third chip to work, and is output to the local oscillator input of the fourth chip through the third chip to drive the first chip to work. Drive the fourth chip to work. That is to say, the local oscillator signal output by the local oscillator output terminal of the first chip can simultaneously drive the first chip, the second chip, the third chip and the fourth chip to work, thereby ensuring the The working local oscillator signals are of the same source, thereby realizing the phase synchronization of the four chips. In addition, compared with multiple chips coupled in series to form a phased array device, the number of stages of series coupling is greatly reduced, thereby reducing the accumulation of phase errors; the phased array device is coupled in parallel with multiple chips Compared with forming a phased array device, there is no need to add an additional chip for providing a local oscillator signal, thereby reducing costs, and at the same time, under a phased array device of the same scale, design difficulty and power consumption can be reduced.

In a possible implementation of the first aspect, the local oscillator signal output by the local oscillator output terminal of the first chip is divided into two parallel signals by the first power divider, and the two signals are divided by transmitted to the second chip and the third chip, and then transmitted to the third chip and the fourth chip after passing through the second chip and the third chip respectively. In the above possible implementation, the local oscillator signal output by the local oscillator output terminal of the first chip is divided into two parallel signals by power, and the two signals can drive the second chip and the third chip at the same time, and respectively pass through the second After the chip and the third chip, the first chip and the fourth chip can be driven, so that the accumulation of phase errors is reduced by first connecting in parallel and then in series, and at the same time reducing design difficulty and power consumption.

In a possible implementation manner of the first aspect, the device further includes: a metal wire, where the metal wire is used to couple the local oscillator output end of the first chip and the local oscillator input end of the first chip. In the above possible implementation manner, the local oscillator output terminal of the first chip is connected to the local oscillator input terminal of the first chip through the metal wire, so that the local oscillator signal output by the local oscillator output terminal of the first chip can be Directly drive the first chip to work, so as to realize the self-driving of the first chip, so that the phased array device can not only support the original working mode of the phased array, but also support the single-chip self-driving work, thereby improving the performance of the phased array Flexibility of device work.

In a possible implementation manner of the first aspect, the device further includes: a fifth chip, a sixth chip, a seventh chip, and an eighth chip; the power divider network further includes a second power divider and a third power divider device; wherein, the input end of the second power divider and the input end of the third power divider are respectively coupled with the two output ends of the first power divider, and the two output ends of the second power divider are respectively connected with the second chip The local oscillator input terminal of the fifth chip is coupled with the local oscillator input terminal of the fifth chip, and the two output terminals of the third power divider are respectively coupled with the local oscillator input terminal of the third chip and the local oscillator input terminal of the sixth chip; the fifth chip The local oscillator output terminal of the chip is coupled to the local oscillator output terminal of the seventh chip, and the local oscillator output terminal of the sixth chip is coupled to the local oscillator input terminal of the eighth chip. In the above possible implementation, when the device includes more chips, the phase synchronization of more chips can still be achieved by first coupling in parallel and then coupling in series, and it is the same as that of the same scale only through series coupling or only through parallel coupling. As far as the formed phased array device is concerned, it has the advantages of small phase error, low cost, low design difficulty and low power consumption.

In a possible implementation of the first aspect, the local oscillator signal output by the local oscillator output terminal of the first chip is divided by the first power divider and the second power divider and the third power divider. After the second power division, parallel four-way signals are obtained; among the four-way signals, the two-way signals output by the second power divider are transmitted to the second chip and the fifth chip respectively, and pass through the second chip and the fifth chip respectively and then transmitted to the first chip and the seventh chip; the two-way signals output by the third power divider among the four-way signals are respectively transmitted to the third chip and the sixth chip, and are respectively passed through the third chip and the sixth chip and then respectively Transfer to the fourth chip and the eighth chip. In the above possible implementation mode, the local oscillator signal output by the local oscillator output terminal of the first chip is divided into multiple times by the power divider network to obtain a parallel multi-channel signal, and the multi-channel signal can be used to drive the first parallel and then series Multiple chips, so as to achieve phase synchronization of multiple chips, and at the same time reduce the accumulation of phase errors, reduce design difficulty and power consumption.

In a possible implementation manner of the first aspect, each of the plurality of chips includes: a selection circuit and a phase-locked loop, the first selection end of the selection circuit is coupled to the local oscillator input end of the chip, and the The second selection end of the selection circuit is coupled to the output end of the phase-locked loop, and the output end of the selection circuit is coupled to the local oscillator output end of the chip; wherein, the selection circuit in the first chip is used to communicate with the phase-locked loop With the local oscillator input terminal of the chip, the selection circuit in other chips of the plurality of chips except the first chip is used to connect the local oscillator input terminal coupling and the local oscillator output terminal of the chip. In the above possible implementation, multiple chips of the same structure can be spliced in parallel first and then in series to form a phased array device, and the working modes of the multiple chips can be controlled through different control methods to realize the multiple chips. phase synchronization.

In a possible implementation manner of the first aspect, each of the multiple chips further includes: a first frequency multiplier and a second frequency multiplier; the selection circuit includes a first selector and a second selector ; Wherein, the local oscillator input terminal of the chip is coupled with the input terminal of the first frequency multiplier and the first selection terminal of the first selector, and the second selection terminal of the first selector is coupled with the first output terminal of the phase-locked loop Coupling, the local oscillator input terminal of the chip is also coupled with the input terminal of the second frequency multiplier and the first selection terminal of the second selector, and the second selection terminal of the second selector is coupled with the second output terminal of the phase-locked loop Coupling, the output terminal of the first selector and the output terminal of the second selector are coupled as the output terminal of the selection circuit. The above possible implementation can enable the phased array device to support communication in different frequency bands, and realize multi-band communication through a power divider network, thereby reducing the complexity and cost of the phased array device.

In a possible implementation of the first aspect, the frequency multiplier of the first frequency multiplier and the second frequency multiplier are different; the first output terminal and the second output terminal of the phase-locked loop are used to output different frequencies LO signal. The above possible implementation can enable the phased array device to support communication in different frequency bands, and realize multi-band communication through a power divider network, thereby reducing the complexity and cost of the phased array device.

In a possible implementation manner of the first aspect, each of the plurality of chips further includes: a first mixer and a second mixer, and the input terminal of the first mixer is connected to the first frequency multiplier The output terminal of the mixer is coupled, and the input terminal of the second mixer is coupled with the output terminal of the second frequency multiplier. Optionally, in a possible implementation manner of the first aspect, the first mixer is a low frequency mixer, and the second mixer is a high frequency mixer. The above possible implementation can enable the phased array device to support high-band and low-band communications, and can be realized through a power divider network, thereby reducing the complexity and cost of the phased array device.

In a second aspect, a phased array module is provided, and the phased array module includes the phased array device provided in the first aspect or any possible implementation manner of the first aspect.

In a third aspect, a communication device is provided, the communication device includes a circuit board, and a phased array device fixed on the circuit board, the phased array device is as the first aspect or any possible implementation of the first aspect way provided by the phased array device.

In a fourth aspect, a method for controlling a phased array device is provided, the device comprising: a power divider network and a plurality of chips, the power divider network comprising a first power divider, and the plurality of chips comprising a first chip and a second chip , the third chip and the fourth chip, each chip in the plurality of chips has a local oscillator input terminal and a local oscillator output terminal; wherein, the local oscillator output terminal of the first chip is coupled with the input terminal of the first power divider, and the first chip The two output terminals of a power divider are respectively coupled to the local oscillator input terminal of the second chip and the local oscillator input terminal of the third chip, the local oscillator output terminal of the second chip is coupled to the local oscillator input terminal of the first chip, and the local oscillator input terminal of the second chip is coupled to the local oscillator input terminal of the first chip. The local oscillator output terminals of the three chips are coupled with the local oscillator input terminals of the fourth chip, and the method includes: the first chip outputs a local oscillator signal; the first power divider performs power division on the local oscillator signal to output two parallel signals; The second chip receives one signal of the two signals and outputs it to the first chip; the third chip receives the other signal of the two signals and outputs it to the fourth chip, so that multiple chips realize phase synchronization.

In a possible implementation manner of the fourth aspect, the device further includes a metal wire for coupling the local oscillator output end of the first chip and the local oscillator input end of the first chip, and the method further includes The first chip receives the local oscillator signal output by the local oscillator output terminal of the first chip through the local oscillator input terminal of the first chip, and the local oscillator signal is transmitted to the local oscillator input terminal of the first chip through metal traces.

In a possible implementation manner of the fourth aspect, the device further includes: a fifth chip, a sixth chip, a seventh chip, and an eighth chip; the power divider network further includes a second power divider and a third power divider device; wherein, the input end of the second power divider and the input end of the third power divider are respectively coupled with the two output ends of the first power divider, and the two output ends of the second power divider are respectively connected with the second chip The local oscillator input terminal of the fifth chip is coupled with the local oscillator input terminal of the fifth chip, and the two output terminals of the third power divider are respectively coupled with the local oscillator input terminal of the third chip and the local oscillator input terminal of the sixth chip; the fifth chip The local oscillator output terminal of the seventh chip is coupled with the local oscillator output terminal of the seventh chip, and the local oscillator output terminal of the sixth chip is coupled with the local oscillator input terminal of the eighth chip; the method also includes: a second power divider and a third power divider The two-way signal is divided by the two-way signal to output parallel four-way signals; the second chip and the fifth chip respectively receive the two-way signals output by the second power divider in the four-way signals, and output them to the first chip and the second Seven chips; the third chip and the sixth chip respectively receive the two-way signals output by the third power divider among the four-way signals, and output them to the fourth chip and the eighth chip.

In a possible implementation of the fourth aspect, each of the multiple chips includes: a selection circuit and a phase-locked loop, the first selection end of the selection circuit is coupled to the local oscillator input end of the chip, and the first selection end of the selection circuit is coupled to the local oscillator input end of the chip. The second selection terminal is coupled to the output terminal of the phase-locked loop, and the output terminal of the selection circuit is coupled to the local oscillator output terminal of the chip; the method also includes: the selection circuit in the first chip is connected to the phase-locked loop and the local oscillator of the first chip The input end; the selection circuits in the other chips except the first chip among the plurality of chips are connected to the local oscillator input end coupling and the local oscillator output end of the chips.

In a possible implementation manner of the fourth aspect, each of the multiple chips further includes: a first frequency multiplier and a second frequency multiplier; the selection circuit includes a first selector and a second selector; Wherein, the local oscillator input terminal of the chip is coupled with the input terminal of the first frequency multiplier and the first selection terminal of the first selector, the second selection terminal of the first selector is coupled with the first output terminal of the phase-locked loop, and the chip The local oscillator input terminal of the second frequency multiplier is also coupled with the input terminal of the second frequency multiplier and the first selection terminal of the second selector, and the second selection terminal of the second selector is coupled with the second output terminal of the phase-locked loop. The output end of the device and the output end of the second selector are coupled as the output end of the selection circuit; the method also includes: when the device works in the first frequency band, the first selector of the first chip is connected to the phase-locked loop of the chip The first output end of the chip, the first selector of the chip other than the first chip in the plurality of chips is connected to the local oscillator input end of the chip, and the first frequency multiplier of each chip in the plurality of chips is used for the local oscillator input of the chip. The chip received by the local oscillator input terminal performs frequency multiplication processing; or, when the device is working in the second frequency band, the second selector of the first chip is connected to the second output terminal of the phase-locked loop of the chip where the chip is located. The second selector of the chips other than the first chip is connected to the local oscillator input of the chip, and the second frequency multiplier of each chip in the multiple chips is used to multiply the chip received by the local oscillator input of the chip. frequency processing.

In a possible implementation manner of the fourth aspect, the frequency multipliers of the first frequency multiplier and the second frequency multiplier are different.

In a possible implementation manner of the fourth aspect, the first output terminal and the second output terminal of the phase-locked loop are used to output local oscillator signals of different frequencies.

In a possible implementation manner of the fourth aspect, each of the plurality of chips further includes: a first mixer and a second mixer, and the input end of the first mixer is connected to the first frequency multiplier The output end of the mixer is coupled, and the input end of the second mixer is coupled with the output end of the second frequency multiplier; the method also includes: when the device works in the first frequency band, the first chip of each chip in the plurality of chips A mixer performs mixing processing on the signal output by the first frequency multiplier of the chip; or, when the device works in the second frequency band, the second mixer of each chip in the plurality of chips performs a frequency mixing process on the chip. The signal output by the second frequency multiplier is mixed.

In a possible implementation manner of the fourth aspect, the first mixer is a low frequency mixer, and the second mixer is a high frequency mixer.

It can be understood that any phased array module, communication device and control method provided above include all the content of the phased array device provided above, therefore, the beneficial effects it can achieve can refer to the above The beneficial effects of the provided phased array device will not be repeated here.

Description of drawings

Fig. 1 is a schematic diagram of a phased array device;

Fig. 2 is the schematic diagram of another kind of phased array device;

FIG. 3 is a schematic structural diagram of a phased array device provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a selection circuit provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of a self-driving chip provided by an embodiment of the present application;

Fig. 6 is a schematic structural diagram of another phased array device provided by the embodiment of the present application;

FIG. 7 is a schematic structural diagram of a chip provided by an embodiment of the present application;

Fig. 8 is a schematic structural diagram of another phased array device provided by the embodiment of the present application;

Fig. 9 is a schematic structural diagram of another phased array device provided by the embodiment of the present application;

FIG. 10 is a schematic structural diagram of a communication device provided by an embodiment of the present application.

Detailed ways

The making and using of various embodiments are discussed in detail below. It should be appreciated, however, that the application provides many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the description and technology, and do not limit the scope of the application.

Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

Each circuit or other component may be described or referred to as "operating" to perform one or more tasks. In this context, "for" is used to imply structure by indicating that a circuit/component includes structure (eg, circuitry) that performs one or more tasks during operation. Accordingly, even when the specified circuit/component is not currently operational (eg, not turned on), the circuit/component may be said to be used to perform the task. A circuit/component used with the phrase "for" includes hardware, such as a circuit to perform an operation, and the like.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In this application, "at least one" means one or more, and "multiple" means two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist at the same time, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (unit) of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be It can be single or multiple.

The embodiment of the present application uses words such as "first" and "second" to distinguish objects with similar names or functions or effects. and order of execution. The term "coupled" is used to indicate an electrical connection, including direct connection through wires or terminals or indirect connection through other devices. "Coupling" should therefore be viewed as an electronic communication connection in a broad sense.

It should be noted that, in this application, words such as "exemplary" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design described herein as "exemplary" or "for example" is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner.

The technical solutions provided in this application can be applied to millimeter wave communications. The millimeter wave frequency band has rich spectrum resources and high bandwidth, and is suitable for application scenarios with large bandwidth and high data rate. It is widely used in 5G communication, microwave backhaul, indoor short-distance communication and other fields. Optionally, the millimeter wave frequency band has multiple operating frequency bands such as 24.25GHz-29.5GHz, 37.0GHz-43.5GHz, and 57GHz-71GHz.

In the millimeter-wave frequency band, the signal has a large space loss in the channel, and the transmission characteristics are closer to direct radiation. Since the phased array technology can improve the effective isotropic radiated power (EIRP) during signal transmission, the The transmission distance, so phased array technology is often used when realizing millimeter wave communication. For some application scenarios with higher EIRP requirements, it is generally realized by splicing multiple chips (die) to form a phased array. However, how to realize the phase synchronization of multiple chips in the splicing process is a problem worth studying.

FIG. 1 shows a schematic structural diagram of a phased array device formed by coupling multiple chips in series. The phased array device includes: four chips and denoted as D1 to D4, the output end of chip D1 is coupled to the input end of chip D2, the output end of chip D2 is coupled to the input end of chip D3, the output end of chip D3 is coupled to the chip The input of D4 is coupled. Among them, the phase locked loop (phase locked loop, PLL) in the chip D1 is in the working state, which is used to output the local oscillator signal and drive the chip D1 to work. At the same time, the local oscillator signal output by the output terminal of the chip D1 drives the chip D2 to work. The local oscillator signal output by the output terminal of D2 drives the chip D3 to work, and the local oscillator signal output by the output terminal of the chip D3 drives the chip D4 to work, so that the local oscillator signals of the driving chips D1 to D4 work from the same source, thereby realizing the four chips. phase synchronization. In Figure 1, each chip includes a PLL, a selector MUX, two drivers DRV1 and DRV2, and a mixer MIX, the PLLs in chips D2 and D3 do not work, and the PLL and DRV2 in chip D4 do not work as an example Be explained.

FIG. 2 shows a schematic structural diagram of a phased array device formed by coupling multiple chips in parallel. The phased array device includes: five chips denoted as D1 to D5, and three power dividers PD1 to PD3. The output terminal of the chip D5 is coupled with the input terminal of the power divider PD1, and the two output terminals of the power divider PD1 are respectively coupled with the input terminals of the power divider PD2 and the input terminal of PD3, and the two output terminals of the power divider PD2 are respectively It is coupled with the input end of the chip D1 and the input end of the chip D2, and the two output ends of the power divider PD3 are respectively coupled with the input end of the chip D3 and the input end of the chip D4. Wherein, the phase-locked loop (phase locked loop, PLL) in the chip D5 is in the working state, and is used for outputting the local oscillator signal and driving the chip D1 to the chip D4 to work, so that the local oscillator signals of the driving chips D1 to D4 have the same source, thereby Realize the phase synchronization of these four chips. That is, the chip D5 is used to provide a local oscillator signal, and the chips D1 to D4 are connected in parallel and realize phase synchronization through the local oscillator signal provided by the chip D5. In Fig. 2, each chip includes a PLL, a selector MUX, two drivers DRV1 and DRV2 and a mixer (mixer) MIX, the PLL and DRV2 in the chip D1 to the chip D4 do not work, and the DRV1 in the chip D5 and MIX does not work as an example to explain.

However, although the above two methods can realize the synchronization of multiple chips, there are still some problems, so the use is limited. For the above-mentioned first method, when the scale of the phased array device is large, it needs to be implemented by connecting more stages in series, and each stage of series connection will bring a certain phase error, which will cause more phase errors when the number of stages is large. A large degree of phase error accumulation makes it difficult to achieve phase synchronization in large-scale phased array devices. For the above-mentioned second method, it is necessary to add an additional chip that provides local oscillator signals, which will lead to an increase in cost; in addition, when the scale of the phased array device is large, it is necessary to use more stages of power dividers, thus The output power of the chip providing the local oscillator signal is further increased, which increases design difficulty and power consumption. Based on this, an embodiment of the present application provides a phased array device and a communication device, which can be used to solve the above problems. The technical solution of the embodiment of the present application will be described in detail below.

FIG. 3 is a schematic structural diagram of a phased array device provided by an embodiment of the present application. The phased array device includes: a plurality of chips, each of which has a local oscillator input terminal and a local oscillator output terminal, and the multiple chips include a first chip D1, a second chip D2, and a third chip D3 and the fourth chip D4. Wherein, the local oscillator output terminal of the first chip D1 is respectively coupled with the local oscillator input terminal of the second chip D2 and the local oscillator input terminal of the third chip D3, and the local oscillator output terminal of the second chip D2 is coupled with the local oscillator input terminal of the first chip D1. The local oscillator output terminal of the third chip D3 is coupled to the local oscillator input terminal of the fourth chip D4. In addition, the local oscillator output terminal of the first chip D1 is used to output a local oscillator signal, and the local oscillator signal is used to realize phase synchronization of the multiple chips.

Optionally, the phased array device further includes a power divider network PD. In an example, the power divider network PD may include a first power divider PD1, the local oscillator output terminal of the first chip D1 is coupled to the input terminal of the first power divider PD1, and the two power divider PD1 The two output terminals are respectively coupled to the local oscillator input terminal of the second chip D2 and the local oscillator input terminal of the third chip D3. In practical applications, the power divider network PD in the embodiment of the present application may also be called a splitter network, and the power divider may also be called a splitter, which is not specifically limited in the embodiment of the present application.

Specifically, in the phased array device, the local oscillator signal output by the local oscillator output terminal of the first chip D1 can output two parallel local oscillator signals after being divided by the first power divider PD1; The first local oscillator signal in the local oscillator signal can be used to drive the second chip D2 to work, and output to the local oscillator input terminal of the first chip D1 through the second chip D2 to drive the first chip D1 to work; The second local oscillator signal in the oscillator signal can be used to drive the third chip D3 to work, and output to the local oscillator input terminal of the fourth chip D4 through the third chip D3 to drive the fourth chip D4 to work. That is to say, the local oscillator signal output by the local oscillator output terminal of the first chip D1 can simultaneously drive the first chip D1, the second chip D2, the third chip D3 and the fourth chip D4 to work, thereby ensuring that the The local oscillator signals of the chip D1 to the fourth chip D4 work on the same source, thereby realizing the phase synchronization of these four chips. In addition, compared with the above-mentioned phased-array device shown in Figure 1, the phased-array device has greatly reduced series coupling stages, thereby reducing the accumulation of phase errors; Compared with the current phased array device, there is no need to add an additional chip to provide the local oscillator signal, thereby reducing the cost. At the same time, under the same scale of the phased array device, the number of power dividers can be reduced, thereby reducing the design difficulty and power consumption.

In a possible embodiment, as shown in FIG. 3, each chip in the plurality of chips may include a selection circuit MUX and a phase-locked loop PLL, the phase-locked loop PLL may be used to generate a local oscillator signal, and the selection circuit MUX The first selection end of the selection circuit is coupled with the local oscillator input end of the chip, the second selection end of the selection circuit MUX is coupled with the output end of the phase-locked loop PLL, and the output end of the selection circuit is coupled with the local oscillation output end of the chip . Further, each chip may further include a driving circuit DRV and a mixer MIX, one end of the driving circuit DRV is coupled to the local oscillator input end of the chip, and the other end of the driving circuit DRV is coupled to the mixer MIX.

Exemplarily, as shown in FIG. 3, in the case where the local oscillator output terminal of the first chip D1 is used to output a local oscillator signal, the phase-locked loop PLL in the first chip D1 works, and the selection circuit MUX is used to communicate with the lock The phase loop PLL and the local oscillator input terminal of the first chip D1, that is, the selection circuit MUX in the first chip D1 is used to output the local oscillator signal generated by the phase locked loop PLL to the local oscillator output terminal of the first chip D1. At this time, the phase-locked loops PLLs in other chips except the first chip D1 in the plurality of chips do not work, and the selection circuit MUX is used to connect the local oscillator input terminal coupling and the local oscillator output terminal of the chips, that is, other The selection circuit MUX in the chip is used to output the local oscillator signal received by the local oscillator input terminal to the local oscillator output terminal. For example, as shown in Figure 3, the phase-locked loop PLL in the second chip D2 to the fourth chip D4 does not work, and the selection circuit MUX in the second chip D2 to the fourth chip D4 is used to receive the signal received by the local oscillator input terminal. The local oscillator signal is output to the local oscillator output terminal. Further, in the case that no chip is connected to the next stage of the fourth chip D4, the selection circuit MUX in the fourth chip D4 may also not work.

Optionally, as shown in FIG. 4 , the selection circuit MUX may include: six transistors T1 to T6 , two input matching networks 1 and 2 , and one output matching network 3 . Wherein, the two input terminals of the input matching network 1 are used as the first selection terminals of the selection circuit MUX, the two input terminals of the input matching network 2 are used as the second selection terminals of the selection circuit MUX, and the two outputs of the output matching network 3 are terminal as the output terminal of the selection circuit MUX. The gate of the transistor T1 and the gate of the transistor T2 are respectively coupled to the two output terminals of the input matching network 1 , and the gates of the transistor T3 and the transistor T4 are respectively coupled to the two output terminals of the input matching network 2 . One pole (for example, source) of transistor T1 and one pole (for example, source) of transistor T2 are both coupled to the ground terminal, and one pole (for example, source) of transistor T3 and one pole (for example, source) of transistor T4 are coupled to the ground terminal. poles) are coupled to ground. The other pole (such as the drain) of the transistor T1 and the other pole (such as the drain) of the transistor T2 are connected to one pole (such as the source) of the transistor T5 and one pole (such as the source) of the transistor T6 respectively. coupling. The other pole (such as the drain) of the transistor T3 and the other pole (such as the drain) of the transistor T4 are connected to one pole (such as the source) of the transistor T5 and one pole (such as the source) of the transistor T6 respectively. coupling. The other pole (for example, the drain) of the transistor T5 and the other pole (for example, the drain) of the transistor T6 are respectively coupled to two input terminals of the output matching network 3 . The gate of the transistor T5 is used for receiving the control signal VB1, and the gate of the transistor T6 is used for receiving the control signal VB2. In the selection circuit MUX, the transistors T1 and T2 may be called a pair of common source transistors, the transistors T3 and T4 may be called a pair of common source transistors, and the transistors T5 and T6 may be called a pair of cascode transistors.

Specifically, in the selection circuit MUX, when the transistors T1 and T2 are turned on, the transistors T5 and T6 are turned on, and the transistors T3 and T4 are turned off, the selection circuit MUX is used to input the two input terminals of the matching network 1 ( That is, the input signal 1 received by the first selection terminal) is output to the two output terminals of the output matching network 3 to use the input signal 1 as an output signal; when the transistors T1 and T2 are turned off, the transistors T3 and T4 are turned on, and the transistor T5 When T6 and T6 are turned on, the selection circuit MUX is used to output the input signal 2 received by the two input terminals (ie, the second selection terminal) of the input matching network 2 to the two output terminals of the output matching network 3, so as to input Signal 2 is used as output signal. Using the selection circuit MUX can quickly and effectively realize the selection of the input signal, and the selection circuit MUX has the advantages of small size and low power consumption, so applying the selection circuit MUX to a chip can reduce the area and power consumption of the chip.

It should be noted that the above-mentioned transistors T1 to T6 may be metal oxide semiconductor (MOS) transistors, specifically PMOS transistors, or NMOS transistors. The above-mentioned transistors shown in FIG. The embodiments of the present application are not limited.

Further, as shown in FIG. 5 , the phased array device may further include a metal wire ML for coupling the local oscillator output terminal of the first chip D1 and the local oscillator input terminal of the first chip D1 . For example, in practical applications, the metal wiring ML can be arranged on the redistribution layer (redistribution layer, RDL), packaging layer or printed circuit board of the first chip D1, so that the local oscillator output terminal of the first chip D1 Connect with the local oscillator input end of the first chip D1. In the above technical solution, the local oscillator output terminal of the first chip D1 is connected to the local oscillator input terminal of the first chip D1 through the metal wiring ML, so that the local oscillator output terminal of the first chip D1 can output The signal can directly drive the first chip D1 to work, thereby realizing the self-driving of the first chip D1, so that the phased array device can not only support the original working mode of the phased array, but also support the single-chip self-driving work, thereby improving The flexibility of the phased array device work.

Further, as shown in FIG. 6, the plurality of chips may also include a fifth chip D5, a sixth chip D6, a seventh chip D7, and an eighth chip D8, and the power divider network may also include a second power divider PD2 and the third power divider PD3. Wherein, the two output terminals of the first power divider PD1 are respectively coupled with the input terminals of the second power divider PD2 and the input terminal of the third power divider PD3; the two output terminals of the second power divider PD2 are respectively coupled with the first The local oscillator input end of the second chip D2 is coupled with the local oscillator input end of the fifth chip D5; the two output ends of the third power divider PD3 are respectively connected with the local oscillator input end of the third chip D3 and the local oscillator of the sixth chip D6 The input terminal is coupled; the local oscillator output terminal of the fifth chip D5 is coupled to the local oscillator input terminal of the seventh chip D7, and the local oscillator output terminal of the sixth chip D6 is coupled to the local oscillator input terminal of the eighth chip D8. Similarly, when the phased array device includes more chips, the coupling of more chips can be realized by adding more power dividers. The working process will be described below by taking 8 chips as an example.

Specifically, in the phased array device, the local oscillator signal output from the local oscillator output terminal of the first chip D1 passes through the first power divider PD1, the second power divider PD2 and the third power divider PD3. After splitting, four parallel local oscillator signals can be output; the first local oscillator signal can be used to drive the second chip D2 to work, and output to the local oscillator input terminal of the first chip D1 through the second chip D2 to drive the first chip D1 works; the second local oscillator signal can be used to drive the third chip D3 to work, and output to the local oscillator input of the fourth chip D4 through the third chip D3 to drive the fourth chip D4 to work; the third local oscillator signal It can be used to drive the fifth chip D5 to work, and output to the local oscillator input terminal of the seventh chip D7 through the fifth chip D5 to drive the seventh chip D7 to work; the fourth local oscillator signal can be used to drive the sixth chip D6 to work, And output to the local oscillator input end of the eighth chip D8 through the sixth chip D6 to drive the eighth chip D8 to work.

That is to say, the local oscillator signal output by the local oscillator output terminal of the first chip D1 can simultaneously drive the first chip D1 to the eighth chip D8 to work, thereby ensuring the local oscillator signal used to drive the first chip D1 to the eighth chip D8 to work. The vibration signals are from the same source, and then the phase synchronization of these multiple chips is realized. In addition, compared with the above-mentioned phased-array device shown in Figure 1, the phased-array device has greatly reduced series coupling stages, thereby reducing the accumulation of phase errors; Compared with the current phased array device, there is no need to add an additional chip to provide the local oscillator signal, thereby reducing the cost. At the same time, under the same scale of the phased array device, the number of power dividers can be greatly reduced, thereby reducing the difficulty of design and power consumption.

Further, when the phased array device works in an application scenario of multi-band (for example, working in millimeter wave multi-band) communication, it is also required that the phased array device can support communication in multiple different frequency bands. For multiple frequency bands with large differences in local oscillator frequencies, if multiple power divider networks PD are used to achieve phase synchronization in different frequency bands, the complexity and cost of the phased array device will increase. Based on this, the embodiment of the present application also provides a phased array device, each chip in the phased array device can support multi-band communication, and multiple chips can still be used when splicing to form a phased array device. The splicing method provided in this article can realize multi-band communication through a power divider network PD.

Taking each chip in the phased array device as an example supporting communication in two frequency bands, the structure of the chip will be described in detail below. As shown in Figure 7, the chip includes: a phase-locked loop PLL, a selection circuit MUX, a first frequency multiplier (multiplier, MUL) MUL1, a second frequency multiplier MUL2, a first mixer MIX1 and a second mixer MIX2, the selection circuit MUX includes a first selector SW1 and a second selector SW2. Among them, the local oscillator input terminal LO_IN of the chip is connected to the input terminal of the first frequency multiplier MUL1, the first selection terminal of the first selector SW1, the input terminal of the second frequency multiplier MUL12 and the first selection terminal of the second selector SW2. Select end coupling. The output terminal of the first frequency multiplier MUL1 is coupled to the input terminal of the first mixer MIX1, and the output terminal of the second frequency multiplier MUL2 is coupled to the input terminal of the second mixer MIX2. The second selection terminal of the first selector SW1 is coupled to the first output terminal a of the PLL, and the second selection terminal of the second selector SW2 is coupled to the second output terminal b of the PLL. Both the output end of the first selector SW1 and the output end of the second selector SW2 are coupled to the local oscillator output end LO_OUT of the chip.

Optionally, the chip may further include a first driver and a second driver circuit. The first driving circuit is coupled between the first frequency multiplier MUL1 and the first mixer MIX1, and the second driving circuit is coupled between the second frequency multiplier MUL2 and the second mixer MIX2. The first driver and the second driver circuit are not shown in FIG. 7 .

In a possible embodiment, the frequency multiplication factor of the first frequency multiplier MUL1 is M, the frequency multiplication factor of the second frequency multiplier MUL2 is N, and both M and N are greater than 0. Wherein, the frequency multiplication multiples of the first frequency multiplier MUL1 and the second frequency multiplier MUL2 may be the same or different. In an example, M is smaller than N, that is, the frequency multiplication factor of the first frequency multiplier MUL1 is smaller than the frequency multiplication factor of the second frequency multiplier MUL2.

In addition, the first mixer MIX1 may be a low frequency mixer, and the second mixer MIX2 may be a high frequency mixer. The frequency of the local oscillator signal output by the first output terminal a and the second output terminal b of the phase-locked loop PLL is different. For example, the first output terminal a is used to output the local oscillator signal LO_INT1, and the second output terminal b is used to output the local oscillator signal. The frequency of the signals LO_INT2, LO_INT1 is less than the frequency of LO_INT2.

In one example, take the two frequency bands that the chip supports communication including low frequency band (low band, LB) and high frequency band (high band, HB) as an example, when the chip is used for low frequency band LB communication, the first time The frequency multiplier MUL1, the first mixer MUX1 and the first selector SW1 work, and the second frequency multiplier MUL2, the second mixer MUX2 and the second selector SW2 do not work; when the chip is used for high-band HB communication , the first frequency multiplier MUL1, the first mixer MUX1 and the first selector SW1 do not work, and the second frequency multiplier MUL2, the second mixer MUX2 and the second selector SW2 work.

Further, the multiple chips shown in FIG. 7 above can be spliced to form a phased array device supporting communications in multiple different frequency bands. Specifically, the phased array device can be formed by splicing in the manner shown in FIG. 3 or FIG. 6 above. Exemplarily, with reference to FIG. 3 , as shown in FIG. 8 and FIG. 9 , it is a schematic structural diagram of a phased array device supporting communications in multiple different frequency bands provided by an embodiment of the present application. It should be noted that the coupling relationship between the plurality of chips and the power divider network in Figure 8 and Figure 9, and the transmission process of the local oscillator signal used to drive each chip to work is consistent with the description in Figure 3 above, For details, refer to the relevant description in FIG. 3 above, and the embodiment of the present application will not be repeated here. The following only illustrates how to select a corresponding local oscillator signal for each chip in the phased array device shown in FIG. 8 in the working scenarios of the low frequency band LB and the high frequency band HB.

In a possible example, as shown in FIG. 8, when the phased array device is used for low-frequency LB communication, the phase-locked loop PLL in the first chip D1 outputs the local oscillator signal LO_INT1 through the first output terminal a, The first selector SW1 in the first chip D1 selects the local oscillator signal LO_INT1 received by the second selection terminal and outputs it to the local oscillator output terminal of the first chip D1. The first selector SW1 of each chip in the second chip D2 to the fourth chip selects the local oscillator signal LO_IN received by the first selection terminal to output to the local oscillator output terminal of the corresponding chip, and the second chip D2 to the fourth chip Phase locked loop PLL does not work.

In another possible example, as shown in FIG. 9, when the phased array device is used for high-frequency band HB communication, the phase-locked loop PLL in the first chip D1 outputs the local oscillator signal LO_INT2 through the second output terminal b The second selector SW2 in the first chip D1 selects the local oscillator signal LO_INT2 received by the second selection terminal and outputs it to the local oscillator output terminal of the first chip D1. The second selector SW2 of each chip in the second chip D2 to the fourth chip selects the local oscillator signal LO_IN received by the first selection terminal to output to the local oscillator output terminal of the corresponding chip, and the second selector SW2 in the second chip D2 to the fourth chip Phase locked loop PLL does not work.

In the embodiment of the present application, the phased array device formed by splicing multiple chips can support communication in multiple different frequency bands, and the phased array device can realize communication in different frequency bands through a power divider network PD, thereby reducing the Complexity and cost of a phased array device supporting communications in multiple different frequency bands.

Based on this, an embodiment of the present application further provides a method for controlling a phased array device, and the method is used for controlling the phased array device provided above. For a specific description of the phased array device, reference may be made to the above description, and the embodiments of the present application are not repeated here.

In a possible embodiment, the device includes: a first power divider, a first chip, a second chip, a third chip, and a fourth chip; the method includes: the first chip outputs a local oscillator signal; the first power The splitter divides the power of the local oscillator signal to output two parallel signals; the second chip receives one of the two signals and outputs it to the first chip; the third chip receives the other signal of the two signals, and Output to the fourth chip for phase synchronization of multiple chips.

Optionally, the device further includes a metal wire for coupling the local oscillator output end of the first chip and the local oscillator input end of the first chip. The method may also include: the first chip receives the local oscillator signal output by the local oscillator output terminal of the first chip through the local oscillator input terminal of the first chip, and the local oscillator signal is transmitted to the local oscillator of the first chip through the metal wiring. input.

In another possible embodiment, the device further includes: a second power divider, a third power divider, a fifth chip, a sixth chip, a seventh chip, and an eighth chip; the method may also include the following steps : The second power divider and the third power divider respectively divide the two signals to output four parallel signals; the second chip and the fifth chip respectively receive two signals output by the second power divider in the four signals. The signals are output to the first chip and the seventh chip; the third chip and the sixth chip respectively receive the two signals output by the third power divider among the four signals, and output to the fourth chip and the eighth chip.

Further, each of the plurality of chips includes: a selection circuit and a phase-locked loop, the first selection end of the selection circuit is coupled to the local oscillator input end of the chip, and the second selection end of the selection circuit is coupled to the lock The output terminal of the phase loop is coupled, and the output terminal of the selection circuit is coupled with the local oscillator output terminal of the chip. The method also includes: the selection circuit in the first chip is connected to the phase-locked loop and the local oscillator input terminal of the first chip; the selection circuit in other chips in the plurality of chips except the first chip is connected to the chip The LO input is coupled to the LO output.

Optionally, each chip in the plurality of chips also includes: a first frequency multiplier and a second frequency multiplier; the selection circuit includes a first selector and a second selector; wherein, the local oscillator input of the chip The terminal is coupled with the input terminal of the first frequency multiplier and the first selection terminal of the first selector, the second selection terminal of the first selector is coupled with the first output terminal of the phase-locked loop, and the local oscillator input terminal of the chip Also coupled with the input end of the second frequency multiplier and the first selection end of the second selector, the second selection end of the second selector is coupled with the second output end of the phase-locked loop, and the output end of the first selector Coupled with the output terminal of the second selector as the output terminal of the selection circuit.

In an example, the method may further include: when the device works in the first frequency band, the first selector of the first chip is connected to the first output terminal of the phase-locked loop of the chip where the chip is located, and all but one of the multiple chips The first selector of the chip other than the first chip is connected to the local oscillator input end of the chip, and the first frequency multiplier of each chip in the plurality of chips is used to multiply the chip received by the local oscillator input end of the chip. frequency processing.

In another example, the method may further include: when the device works in the second frequency band, the second selector of the first chip is connected to the second output terminal of the phase-locked loop of the chip where the chip is located, and the plurality of chips The second selector of the chips other than the first chip is connected to the local oscillator input of the chip, and the second frequency multiplier of each chip in the plurality of chips is used to perform the chip received by the local oscillator input of the chip. multiplier processing.

Optionally, the frequency multiples of the first frequency multiplier and the second frequency multiplier are different. The first output terminal and the second output terminal of the phase-locked loop are used to output local oscillator signals of different frequencies.

Further, each chip in the plurality of chips also includes: a first mixer and a second mixer, the input terminal of the first mixer is coupled to the output terminal of the first frequency multiplier, and the second mixer The input terminal of the multiplier is coupled to the output terminal of the second frequency multiplier. The method also includes: when the device works in the first frequency band, the first mixer of each chip in the plurality of chips performs frequency mixing processing on the signal output by the first frequency multiplier of the chip; or, when the When the device works in the second frequency band, the second mixer of each chip in the plurality of chips performs frequency mixing processing on the signal output by the second frequency multiplier of the corresponding chip. Optionally, the first mixer is a low frequency mixer, and the second mixer is a high frequency mixer.

In another aspect of the present application, the embodiment of the present application further provides a phased array module and a communication device, and both the phased array module and the communication device include the phased array device provided above. Exemplarily, FIG. 10 is a schematic structural diagram of a communication device provided by an embodiment of the present application. The communication device includes a memory 101, a processor 102, and the phased array device 103 provided above.

Among them, the communication device can be deployed on land, including indoor or outdoor, handheld or vehicle-mounted; the communication device can also be deployed on water (such as ships, etc.), and can also be deployed in the air (such as aircraft, balloons and satellites, etc.) . For example, the communication device may be a terminal device or a base station. For example, the terminal device includes, but is not limited to: smart phones, tablet computers, notebook computers, handheld computers, mobile internet devices (mobile internet device, MID), wearable devices (such as smart watches, smart bracelets, pedometers, etc.) , vehicle equipment (for example, automobiles, bicycles, electric vehicles, airplanes, ships, trains, high-speed rail, etc.), virtual reality (virtual reality, VR) equipment, augmented reality (augmented reality, AR) equipment, industrial control (industrial control) terminals, smart home devices (such as refrigerators, TVs, air conditioners, electricity meters, etc.), intelligent robots, workshop equipment, terminals in self-driving (self-driving), terminals in remote medical surgery, smart grid Terminals in (smart grid), terminals in transportation safety, terminals in smart city, or terminals in smart home, flying devices (such as intelligent robots, hot air balloons, drones, airplanes, etc.

In one embodiment, when the communication device is a smart phone, the phased array device 103 may also be called a communication circuit, and the communication device may also include an input/output device 104 . The processor 102 is mainly used to process communication protocols and communication data, control the entire smart phone, execute software programs, and process data of the software programs. The memory 101 is mainly used to store software programs and data. The phased array device 103 is mainly used for converting baseband signals and radio frequency signals, processing radio frequency signals, and transmitting and receiving radio frequency signals in the form of electromagnetic waves. The input/output devices, such as touch screens, display screens, and keyboards, are mainly used to receive data input by users and output data to users.

When the smart phone is turned on, the processor 102 can read the software program in the memory 101, interpret and execute the instructions of the software program, and process the data of the software program. When it is necessary to transmit data wirelessly, the processor 102 performs baseband processing on the data to be transmitted, and then outputs the baseband signal to the phased array device 103, and the phased array device 103 performs radio frequency processing on the baseband signal and passes the radio frequency signal through the antenna to It is sent out in the form of electromagnetic waves. When data is sent to the smart phone, the phased array device 103 receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor 102, and the processor 102 converts the baseband signal into data and process the data.

Those skilled in the art can understand that, for ease of illustration, FIG. 9 only shows one memory and one processor. In an actual terminal device, there may be multiple processors and multiple memories. A memory may also be called a storage medium or a storage device. It should be noted that, the embodiment of the present application does not limit the type of the memory.

Finally, it should be noted that: the above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto, and any changes or replacements within the technical scope disclosed in the application shall be covered by this application. within the scope of the application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims (21)

A phased array device, characterized in that the device includes: a power divider network and a plurality of chips, the power divider network includes a first power divider, and the plurality of chips include a first chip, a second chip, a third chip and a fourth chip, each chip in the plurality of chips has a local oscillator input terminal and a local oscillator output terminal; Wherein, the local oscillator output terminal of the first chip is coupled to the input terminal of the first power divider, and the two output terminals of the first power divider are respectively connected to the local oscillator input terminal of the second chip and the input terminal of the first power divider. The local oscillator input terminal of the third chip is coupled, the local oscillator output terminal of the second chip is coupled to the local oscillator input terminal of the first chip, and the local oscillator output terminal of the third chip is coupled to the fourth chip The local oscillator input of the chip is coupled; The local oscillator output terminal of the first chip is used to output a local oscillator signal, and the local oscillator signal is used to realize phase synchronization of the multiple chips. The device according to claim 1, wherein the local oscillator signal output by the local oscillator output terminal of the first chip is divided into two parallel signals by the first power divider, and the two signals are transmitted to the second chip and the third chip respectively, and are transmitted to the third chip and the fourth chip after passing through the second chip and the third chip respectively. The device according to claim 1 or 2, characterized in that the device further comprises: a metal wire, the metal wire is used to couple the local oscillator output end of the first chip and the first chip local oscillator input. The device according to any one of claims 1-3, wherein the device further comprises: a fifth chip, a sixth chip, a seventh chip and an eighth chip; the power divider network further comprises a second A power splitter and a third power splitter; Wherein, the input end of the second power divider and the input end of the third power divider are respectively coupled with the two output ends of the first power divider, and the two outputs of the second power divider terminal is respectively coupled with the local oscillator input terminal of the second chip and the local oscillator input terminal of the fifth chip, and the two output terminals of the third power divider are respectively connected with the local oscillator input terminal of the third chip coupled with the local oscillator input terminal of the sixth chip; The local oscillator output terminal of the fifth chip is coupled to the local oscillator output terminal of the seventh chip, and the local oscillator output terminal of the sixth chip is coupled to the local oscillator input terminal of the eighth chip. The device according to claim 4, characterized in that the local oscillator signal output by the local oscillator output terminal of the first chip passes through the primary power division of the first power divider and the second power divider and After the second power division of the third power divider, parallel four-way signals are obtained; wherein, the two-way signals output by the second power divider in the four-way signals are respectively transmitted to the second chip and the The fifth chip is transmitted to the first chip and the seventh chip after passing through the second chip and the fifth chip respectively; the output of the third power splitter in the four-way signal The two signals are respectively transmitted to the third chip and the sixth chip, and are respectively transmitted to the fourth chip and the eighth chip after passing through the third chip and the sixth chip. The device according to any one of claims 1-5, wherein each chip in the plurality of chips comprises: a selection circuit and a phase-locked loop, the first selection terminal of the selection circuit is connected to the chip The local oscillator input terminal of the selection circuit is coupled, the second selection terminal of the selection circuit is coupled with the output terminal of the phase-locked loop, and the output terminal of the selection circuit is coupled with the local oscillator output terminal of the chip; Wherein, the selection circuit in the first chip is used to connect the phase-locked loop with the local oscillator input end of the first chip, and other chips in the plurality of chips except the first chip The selection circuit in is used to connect the local oscillator input terminal coupling and the local oscillator output terminal of the chip where it resides. The device according to claim 6, wherein each chip in the plurality of chips further comprises: a first frequency multiplier and a second frequency multiplier; the selection circuit comprises a first selector and a second frequency multiplier Selector; Wherein, the local oscillator input terminal of the chip is coupled with the input terminal of the first frequency multiplier and the first selection terminal of the first selector, and the second selection terminal of the first selector is coupled with the lock The first output terminal of the phase loop is coupled, and the local oscillator input terminal of the chip is also coupled with the input terminal of the second frequency multiplier and the first selection terminal of the second selector, and the first selection terminal of the second selector The second selection terminal is coupled to the second output terminal of the phase-locked loop, and the output terminal of the first selector and the output terminal of the second selector are coupled as the output terminal of the selection circuit. The device according to claim 7, characterized in that the frequency multiplication factors of the first frequency multiplier and the second frequency multiplier are different. The device according to claim 7 or 8, characterized in that, the first output terminal and the second output terminal of the phase-locked loop are used to output local oscillator signals of different frequencies. The device according to any one of claims 7-9, wherein each of the plurality of chips further comprises: a first mixer and a second mixer, the first mixer The input end of the first frequency multiplier is coupled to the output end of the first frequency multiplier, and the input end of the second frequency mixer is coupled to the output end of the second frequency multiplier. The device according to claim 10, wherein the first mixer is a low frequency mixer, and the second mixer is a high frequency mixer. A communication device, characterized in that the communication device includes a circuit board, and a phased array device fixed on the circuit board, and the phased array device is the phased array device according to any one of claims 1-11. Array control device. A control method for a phased array device, characterized in that the device includes: a power divider network and a plurality of chips, the power divider network includes a first power divider, and the plurality of chips includes a first chip , a second chip, a third chip and a fourth chip, each chip in the plurality of chips has a local oscillator input terminal and a local oscillator output terminal; wherein, the local oscillator output terminal of the first chip is connected to the first chip The input terminal of a power divider is coupled, the two output terminals of the first power divider are respectively coupled with the local oscillator input terminal of the second chip and the local oscillator input terminal of the third chip, and the second The local oscillator output terminal of the chip is coupled to the local oscillator input terminal of the first chip, the local oscillator output terminal of the third chip is coupled to the local oscillator input terminal of the fourth chip, and the method includes: The first chip outputs a local oscillator signal; The first power divider performs power division on the local oscillator signal to output two parallel signals; The second chip receives one of the two signals and outputs it to the first chip; The third chip receives the other signal of the two signals and outputs it to the fourth chip, so that the multiple chips realize phase synchronization. The method according to claim 13, wherein the device further comprises a metal wire for coupling the local oscillator output terminal of the first chip with the local oscillator input of the first chip end, the method also includes; The first chip receives the local oscillator signal output by the local oscillator output terminal of the first chip through the local oscillator input terminal of the first chip, and the local oscillator signal is transmitted to the first chip through the metal wiring. The local oscillator input of the chip. The method according to claim 13 or 14, wherein the device further comprises: a fifth chip, a sixth chip, a seventh chip and an eighth chip; the power divider network further comprises a second power divider and a third power divider; wherein, the input end of the second power divider and the input end of the third power divider are respectively coupled with the two output ends of the first power divider, and the second power divider The two output terminals of the power divider are respectively coupled to the local oscillator input terminals of the second chip and the local oscillator input terminal of the fifth chip, and the two output terminals of the third power divider are respectively coupled to the first The local oscillator input terminals of the three chips are coupled to the local oscillator input terminals of the sixth chip; the local oscillator output terminals of the fifth chip are coupled to the local oscillator output terminals of the seventh chip, and the local oscillator output terminals of the sixth chip are coupled. The oscillator output terminal is coupled with the local oscillator input terminal of the eighth chip; the method also includes: The second power divider and the third power divider respectively perform power division on the two-way signals to output parallel four-way signals; The second chip and the fifth chip respectively receive the two-way signals output by the second power splitter among the four-way signals, and output them to the first chip and the seventh chip; The third chip and the sixth chip respectively receive two signals output by the third power divider among the four signals, and output them to the fourth chip and the eighth chip. The method according to claim 15, wherein each chip in the plurality of chips comprises: a selection circuit and a phase-locked loop, the first selection terminal of the selection circuit is connected to the local oscillator input terminal of the chip Coupling, the second selection end of the selection circuit is coupled to the output end of the phase-locked loop, and the output end of the selection circuit is coupled to the local oscillator output end of the chip; the method also includes: The selection circuit in the first chip is connected to the phase-locked loop and the local oscillator input terminal of the first chip; The selection circuits in other chips of the plurality of chips except the first chip are connected to the local oscillator input coupling and the local oscillator output of the chip. The method according to claim 16, wherein each chip in the plurality of chips further comprises: a first frequency multiplier and a second frequency multiplier; the selection circuit comprises a first selector and a second frequency multiplier A selector; wherein, the local oscillator input terminal of the chip is coupled to the input terminal of the first frequency multiplier and the first selection terminal of the first selector, and the second selection terminal of the first selector is coupled to the The first output terminal of the phase-locked loop is coupled, the local oscillator input terminal of the chip is also coupled with the input terminal of the second frequency multiplier and the first selection terminal of the second selector, and the second The second selection end of the selector is coupled to the second output end of the phase-locked loop, and the output end of the first selector is coupled to the output end of the second selector as the output end of the selection circuit; The method also includes: When the device works in the first frequency band, the first selector of the first chip is connected to the first output end of the phase-locked loop of the chip, and the first chip is excluded from the plurality of chips. The first selector of the other chip is connected to the local oscillator input of the chip, and the first frequency multiplier of each chip in the plurality of chips is used to receive the chip received by the local oscillator input of the chip. Do frequency multiplication; or, When the device works in the second frequency band, the second selector of the first chip is connected to the second output terminal of the phase-locked loop of the chip, and the first chip is excluded from the plurality of chips. The second selector of the other chip is connected to the local oscillator input of the chip, and the second frequency multiplier of each chip in the plurality of chips is used to receive the chip received by the local oscillator input of the chip. Perform frequency multiplication. The method according to claim 17, characterized in that the frequency multiplication factors of the first frequency multiplier and the second frequency multiplier are different. The method according to claim 17 or 18, characterized in that the first output terminal and the second output terminal of the phase-locked loop are used to output local oscillator signals of different frequencies. The method according to any one of claims 17-19, wherein each of the plurality of chips further comprises: a first mixer and a second mixer, the first mixer The input end of the first frequency multiplier is coupled to the output end of the first frequency multiplier, and the input end of the second frequency mixer is coupled to the output end of the second frequency multiplier; the method also includes: When the device works in the first frequency band, the first mixer of each chip in the plurality of chips performs frequency mixing processing on the signal output by the first frequency multiplier of the chip; or, When the device works in the second frequency band, the second mixer of each chip in the plurality of chips performs frequency mixing processing on the signal output by the second frequency multiplier of the corresponding chip. The method of claim 20, wherein the first mixer is a low frequency mixer, and the second mixer is a high frequency mixer.

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