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WO2023092407A1 - 一种高电子迁移率晶体管、射频晶体管、功率放大器和高电子迁移率晶体管的制备方法 - Google Patents

一种高电子迁移率晶体管、射频晶体管、功率放大器和高电子迁移率晶体管的制备方法 Download PDF

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WO2023092407A1
WO2023092407A1 PCT/CN2021/133250 CN2021133250W WO2023092407A1 WO 2023092407 A1 WO2023092407 A1 WO 2023092407A1 CN 2021133250 W CN2021133250 W CN 2021133250W WO 2023092407 A1 WO2023092407 A1 WO 2023092407A1
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layer
electron mobility
high electron
mobility transistor
channel layer
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PCT/CN2021/133250
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English (en)
French (fr)
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胡彬
朱敏
段焕涛
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华为技术有限公司
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Priority to CN202180104452.2A priority Critical patent/CN118318308A/zh
Priority to PCT/CN2021/133250 priority patent/WO2023092407A1/zh
Priority to EP21965142.9A priority patent/EP4407688A4/en
Priority to JP2024531257A priority patent/JP2024543256A/ja
Publication of WO2023092407A1 publication Critical patent/WO2023092407A1/zh
Priority to US18/676,360 priority patent/US20240322029A1/en

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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/472—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6738—Schottky barrier electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
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    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates

Definitions

  • the present application relates to the technical field of microelectronics, and in particular to a high electron mobility transistor, a radio frequency transistor, a power amplifier and a method for preparing the high electron mobility transistor.
  • Wide bandgap semiconductor gallium nitride (GaN) material has the advantages of large bandgap, high breakdown field strength, high polarization coefficient, high electron mobility, high electron saturation drift speed, etc., and is gradually widely used in the fields of power electronics and radio frequency. application.
  • the present application provides a high electron mobility transistor with lower ohmic contact resistance, a radio frequency transistor, a power amplifier and a preparation method of the high electron mobility transistor.
  • the present application provides a high electron mobility transistor, which at least includes a channel layer, a barrier layer and a substrate layer arranged in sequence.
  • a two-dimensional electron gas layer is formed in the channel layer, and the two-dimensional electron gas layer is in contact with the potential barrier layer.
  • a source and a drain are also included, the source and the drain are located on the channel layer, and the source and the drain are in ohmic contact with the channel layer.
  • the two-dimensional electron gas layer is generated by the polarization effect at the junction interface between the channel layer and the barrier layer.
  • the two-dimensional electron gas layer is located in the channel layer, and the two-dimensional electron gas layer is in contact with the barrier layer, therefore, the surface of the channel layer facing away from the barrier layer can obtain a lower ohmic contact resistance, or, it can be understood that, There is lower ohmic contact resistance between the source and drain and the channel layer, so it can be better applied in high frequency and power scenarios.
  • the two-dimensional electron gas layer refers to a virtual layer of two-dimensional electron gas generated by the polarization effect at the heterojunction interface of the channel layer and the barrier layer.
  • the two-dimensional electron gas layer is located in the channel layer, and the two-dimensional electron gas layer is in contact with the potential barrier layer.
  • the material of the channel layer may be gallium nitride (GaN).
  • the material of the barrier layer may be aluminum gallium nitride (AlGaN).
  • High electron mobility transistors can achieve high electron mobility through the two-dimensional electron gas generated by the polarization effect at the interface of AlGaN and GaN heterojunctions.
  • the surface of the channel layer facing away from the barrier layer is a nitrogen (N) surface.
  • the surface of the high electron mobility transistor ie, the surface facing away from the substrate layer
  • the channel layer, the barrier layer, and the substrate layer can be grown and formed sequentially. Therefore, when the high electron mobility transistor provided by the embodiment of the present application is manufactured, it is easier to obtain a high electron mobility transistor on the nitrogen surface, and it can effectively Guarantee the crystal quality of the nitrogen surface.
  • the high electron mobility transistor on the nitrogen surface can obtain lower ohmic contact resistance, so the high electron mobility transistor on the nitrogen surface can be better applied in in high frequency and power scenarios.
  • the substrate layer its material may be silicon (Si), silicon carbide (SiC) or diamond in specific applications.
  • the substrate layer may use a diamond material. Since the diamond material has higher thermal conductivity, it can effectively improve the heat dissipation performance of the device.
  • the channel layer, the barrier layer and the substrate layer are grown and formed sequentially. Therefore, microwave plasma chemical vapor deposition (Microwave Plasma.
  • the diamond substrate layer is directly grown on the barrier layer, so that the preparation efficiency and quality of the substrate layer can be effectively improved.
  • the gate in one implementation manner, it may be disposed on the channel layer and be in Schottky contact with the channel layer.
  • the gate can also be arranged on other structures.
  • the high electron mobility transistor may further include a nucleation layer.
  • the nucleation layer is located on the side of the channel layer facing away from the barrier layer.
  • the gate is located in the nucleation layer, and the gate is in Schottky contact with the nucleation layer.
  • the material of the nucleation layer may be aluminum nitride (AlN), or other materials that are beneficial to the formation of the channel layer, which is not limited in the present application.
  • the barrier layer in one implementation, aluminum gallium nitride may be included.
  • the barrier layer may include a silicon-doped aluminum gallium nitride layer and an aluminum gallium nitride layer with an aluminum composition greater than 20% arranged in sequence along a direction away from the channel layer.
  • the silicon-doped aluminum gallium nitride layer can adjust the energy band and prevent holes from being trapped.
  • the aluminum gallium nitride layer with a large aluminum composition can effectively increase the electron gas concentration.
  • the performance of high electron mobility transistors can be effectively improved by using the silicon-doped aluminum gallium nitride layer and the aluminum gallium nitride layer with an aluminum composition greater than 20%.
  • the high electron mobility transistor may further include a high resistance layer.
  • the high resistance layer is located between the barrier layer and the substrate layer.
  • the nucleation layer, the channel layer, the barrier layer, the high resistance layer and the substrate layer may be arranged in sequence.
  • the material of the high resistance layer may be gallium nitride doped with iron (Fe) or carbon (C).
  • Fe iron
  • C carbon
  • the main function of the high-resistance layer is to increase the resistance value of the high-electron mobility transistor, so that it can be applied to application scenarios that require a higher resistance value.
  • the high electron mobility transistor may also be a P-type (or normally-off type).
  • a high electron mobility transistor includes a channel layer, a barrier layer, and a substrate layer arranged in sequence.
  • the gate is in Schottky contact with the P-type doped GaN layer.
  • the source and drain are in ohmic contact with the channel layer.
  • the final device structure may also have the high-resistance layer, nucleation layer, etc. mentioned in the above-mentioned embodiments, which will not be described in detail here.
  • the present application also provides a radio frequency transistor and a power amplifier, including any one of the above high electron mobility transistors.
  • the high electron mobility transistor provided in the present application can be widely applied to equipment such as base stations, radars, mobile phones, and notebook computers.
  • the present application does not limit the specific application scenarios of the high electron mobility transistor.
  • the present application also provides a method for preparing a high electron mobility transistor, which may include: at least growing a channel layer, a barrier layer and a substrate layer sequentially along a specific direction on a substrate, removing the substrate, A source electrode and a drain electrode are prepared on the channel layer, and the source electrode and the drain electrode are in ohmic contact with the channel layer.
  • the substrate can be a material such as silicon (Si) or silicon carbide (SiC). It can be understood that, in the embodiment of the present application, the main function of the substrate is to serve as a substrate for growing epitaxial structures such as a channel layer and a barrier layer, so as to facilitate the preparation of the epitaxial structure.
  • the material of the channel layer may be gallium nitride, and the material of the barrier layer may be aluminum gallium nitride.
  • the channel layer, the barrier layer and the substrate layer are sequentially grown and formed. Therefore, when the high electron mobility transistor is prepared through the preparation method provided in the embodiments of the present application, it can It is easier to obtain high electron mobility transistors on the nitrogen surface, and the crystal quality of the nitrogen surface can be effectively guaranteed.
  • the preparation method may further include preparing a gate.
  • the gate may be on the channel layer, and the gate may be in Schottky contact with the channel layer.
  • the channel layer on the substrate may further include: growing a nucleation layer on the substrate along a specific direction. Wherein, the channel layer is located on the nucleation layer.
  • the gate when preparing the gate, may be located on the nucleation layer and be in Schottky contact with the nucleation layer.
  • the nucleation layer can also be removed after removing the substrate.
  • the nucleation layer on the substrate along a specific direction may further include: growing a buffer layer on the nucleation layer along a specific direction.
  • the nucleation and buffer layers can be removed.
  • the arrangement of the buffer layer can facilitate the effective removal of the nucleation layer and itself without affecting the quality of the channel layer.
  • the barrier layer when growing the barrier layer, it may specifically include: sequentially growing a silicon-doped aluminum gallium nitride layer along a specific direction, and an aluminum gallium nitride layer with an aluminum composition greater than 20%.
  • before growing the substrate layer may further include: growing a high-resistance layer on the surface of the barrier layer along a specific direction.
  • the main function of the high-resistance layer is to increase the resistance value of the high-electron mobility transistor, so that it can be applied to application scenarios that require a higher resistance value.
  • P-type (or normally-off) high electron mobility transistors can also be prepared based on the preparation method provided in this application.
  • a P-type doped (or hole-doped) gallium nitride layer can be added on the channel layer, and the gate and P-type doped nitrogen GaN layer Schottky contacts.
  • the preparation method of the present application can be adapted to adjust the sequence of different processes according to actual needs, which is not limited in the present application.
  • FIG. 1 is a schematic structural diagram of a current high electron mobility transistor provided in an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a high electron mobility transistor provided in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another high electron mobility transistor provided in an embodiment of the present application.
  • Fig. 4 is a schematic structural diagram of another high electron mobility transistor provided in the embodiment of the present application during the preparation process
  • FIG. 5 is a schematic structural diagram of another high electron mobility transistor provided in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another high electron mobility transistor during the preparation process provided by the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another high electron mobility transistor during the preparation process provided by the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another high electron mobility transistor during the preparation process provided by the embodiment of the present application.
  • FIG. 9 is a schematic structural view of another high electron mobility transistor provided in the embodiment of the present application during the preparation process.
  • FIG. 10 is a schematic structural diagram of another high electron mobility transistor provided in an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another high electron mobility transistor provided in the embodiment of the present application.
  • FIG. 12 is a flow chart of a method for manufacturing a high electron mobility transistor provided in an embodiment of the present application.
  • FIG. 13 is a schematic structural view of another high electron mobility transistor during the preparation process provided by the embodiment of the present application.
  • FIG. 14 is a schematic structural view of another high electron mobility transistor during the preparation process provided by the embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of another high electron mobility transistor during the preparation process provided by the embodiment of the present application.
  • FIG. 16 is a schematic structural view of another high electron mobility transistor during the preparation process provided by the embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of another high electron mobility transistor during the preparation process provided by the embodiment of the present application.
  • FIG. 18 is a schematic structural view of another high electron mobility transistor during the preparation process provided by the embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of another high electron mobility transistor provided by an embodiment of the present application.
  • High electron mobility transistor mainly uses the two-dimensional electron gas (Two-dimensional electron gas) generated by the polarization effect at the interface of aluminum gallium nitride (AlGaN) / gallium nitride (GaN) heterojunction gas, 2DEG) to achieve high electron mobility.
  • Two-dimensional electron gas means that the movement of electrons in the direction perpendicular to the junction interface is bound by the potential well and quantized, while the movement of electrons in the direction parallel to the junction interface is still free.
  • Such a thin layer of electrons is called two-dimensional electronic gas.
  • High electron mobility transistors can be used in microelectronics fields such as microwave radio frequency or power electronics.
  • the high electron mobility transistor in the field of microwave radio frequency, can be used as a power amplifier, its main function is to amplify the radio frequency signal inside the active antenna processing unit (Active Antenna Unit, AAU), and then transmit it in the form of electromagnetic waves through the antenna go out.
  • AAU Active Antenna Unit
  • high electron mobility transistors can be used as power switches and drivers.
  • end devices such as mobile phones, laptops or tablets
  • high electron mobility transistors can be used as switches in charging circuits.
  • equipment such as lidar it can be used as the main component of the driver.
  • silicon (Si) or silicon carbide (SiC) is usually used as the substrate, and then aluminum nitride (AlN), gallium nitride (GaN) are sequentially grown on the substrate ), aluminum gallium nitride (AlGaN) and other materials are prepared. Then prepare a source 02 , a drain 03 and a gate 04 on the upper surface of the AlGaN layer. A two-dimensional electron gas layer 01 is formed in the GaN layer, and the two-dimensional electron gas layer 01 is in contact with the AlGaN layer.
  • the nitrogen (N) atoms in the compound will be formed first, and then along the specific direction in the N atoms.
  • Aluminum (Al) atoms and gallium (Ga) atoms are formed on the basis. Or it can be understood that, from a microscopic point of view, the N atoms, Al atoms, and Ga atoms in the AlGaN layer are arranged in sequence, so that the surface of the current high electron mobility transistor (the upper surface in the figure) is a Ga surface. However, compared with the high electron mobility transistors on the Ga surface, the high electron mobility transistors on the N surface can obtain lower ohmic contact resistance. Therefore, the high electron mobility transistors on the N surface can be better applied in high frequency and power scenario.
  • the embodiment of the present application provides a high electron mobility transistor capable of obtaining lower ohmic contact resistance.
  • the implementation of the present application provides a high electron mobility transistor. It includes a channel layer 30 , a barrier layer 20 and a substrate layer 10 . Wherein, the channel layer 30, the barrier layer 20 and the substrate layer 10 are sequentially arranged along a specific direction; a two-dimensional electron gas layer 01 (indicated by a dotted line in the figure) is formed in the channel layer 30, and the two-dimensional electron gas layer 01 In contact with the barrier layer 20.
  • the source 02 , the gate 04 and the drain 03 are located on the channel layer 30 , the source 02 and the drain 03 are in ohmic contact with the channel layer 30 , and the gate 04 is in Schottky contact with the channel layer 30 .
  • the two-dimensional electron gas layer is located in the channel layer and is in contact with the barrier layer, therefore, the surface of the channel layer away from the barrier layer can obtain lower ohmic contact resistance, Therefore, it can be better applied in high-frequency and power scenarios.
  • the two-dimensional electron gas layer 01 refers to a virtual layer of two-dimensional electron gas generated by the polarization effect at the heterojunction interface of the channel layer 30 and the barrier layer 20 .
  • the two-dimensional electron gas layer 01 is located in the channel layer 30 and is in contact with the barrier layer 20 .
  • Ohmic contact means that when a semiconductor is in contact with a metal, a potential barrier is often formed, but when the doping concentration of the semiconductor is high, electrons can pass through the potential barrier through the tunnel effect, thereby forming a low-resistance ohmic contact and good ohmic contact. Contact facilitates the input and output of electrical current.
  • Schottky contact means that when the gate 04 (such as a metal material) and the channel layer 30 (such as a semiconductor material) are in contact, the energy band of the semiconductor is bent at the interface to form a Schottky barrier.
  • the material of the channel layer 30 may be GaN.
  • the material of the barrier layer 20 may be AlGaN.
  • High electron mobility transistors can achieve high electron mobility through the two-dimensional electron gas generated by the polarization effect at the interface of AlGaN and GaN heterojunctions.
  • the surface of the high electron mobility transistor (ie, the surface facing away from the substrate layer 10) is a nitrogen (N) plane, therefore, the high electron mobility transistor can obtain lower ohmic contact resistance, or, It can be understood that there is lower ohmic contact resistance between the source 02 and the drain 03 and the channel layer 30 , so that it can be better applied in high frequency and power scenarios.
  • the channel layer 30, the barrier layer 20 and the substrate layer 10 are sequentially grown and formed, therefore, the high electron mobility transistor provided by the embodiment of the present application can be more easily manufactured The high electron mobility transistor of the N surface is obtained, and the crystal quality of the N surface can be effectively guaranteed.
  • high electron mobility transistors on the gallium (Ga) surface high electron mobility transistors on the N surface can obtain lower ohmic contact resistance, so the high electron mobility transistors on the N surface can be better applied in in high frequency and power scenarios.
  • the thickness of the channel layer 30 may be any value between 50-500 nm, and the thickness of the barrier layer 20 may be any value between 10-100 nm. In specific applications, the thicknesses of the channel layer 30 and the barrier layer 20 can be reasonably set according to actual needs, which is not specifically limited in this application.
  • the material of the channel layer 30 may be gallium arsenide (GaAs) or the like, and the material of the barrier layer 20 may be aluminum gallium arsenide (AlGaAs) or the like. In a specific application, the materials of the channel layer 30 and the barrier layer 20 can be reasonably selected and adjusted according to actual needs, which is not specifically limited in this application.
  • its material may be silicon (Si), silicon carbide (SiC) or diamond.
  • the thermal conductivity of Si is about 150W/mK
  • the thermal conductivity of SiC is about 370W/mK
  • the thermal conductivity of diamond is usually greater than 1000W/mK.
  • the thermal conductivity of Si or SiC Due to the poor thermal conductivity of Si or SiC, it will form a large thermal resistance, and the thermal conductivity will decrease with the increase of temperature. Therefore, in some high-power application scenarios, it will face the problem of insufficient heat dissipation, resulting in high Electron mobility transistors can only be operated at lower power densities for their long-term reliability. For example, the theoretical output power density of a GaN HMET device can reach more than 40W/mm.
  • the substrate material is Si or SiC
  • the high electron mobility transistor on the diamond substrate can achieve better heat dissipation, and at the same time, it also helps to increase the power density of the high electron mobility transistor.
  • the GaN layer is usually bonded to the diamond substrate during the preparation process.
  • the bonding process is relatively complicated and costly, which is not conducive to mass production.
  • the bonding process requires the diamond surface to be processed very flat (such as the surface roughness is less than 1nm).
  • the hardness of diamond is high, and it is very difficult to process a very flat surface.
  • the bonding process is also a single-chip process, and the processing and production of one piece will lead to the problem of low production efficiency.
  • bonding it is necessary to add bonding layer materials such as silicon nitride (SiN) between the GaN layer and the diamond substrate. Due to the high thermal resistance of the bonding layer material, it will reduce the heat dissipation performance of the device.
  • SiN silicon nitride
  • the diamond material has good thermal conductivity, it can significantly improve the heat dissipation performance of the device.
  • diamond material may be used as the substrate layer 10 to improve the heat dissipation performance of the device.
  • the channel layer 30, the barrier layer 20 and the substrate layer 10 are grown and formed sequentially, therefore, microwave plasma chemical vapor deposition (Microwave Plasma. Chemical Vapor Deposition, MPCVD) etc. can be used The process directly grows the diamond substrate layer 10 on the barrier layer 20 , so that the preparation efficiency and quality of the substrate layer 10 can be effectively improved.
  • microwave plasma chemical vapor deposition Microwave Plasma. Chemical Vapor Deposition, MPCVD
  • the substrate layer 10 when the substrate layer 10 is prepared, the use of a bonding process to bond the substrate layer 10 and the barrier layer 20 can be avoided, thereby reducing the Preparation difficulty and production cost.
  • a bonding material such as SiN
  • the structure of the HMET device can be varied.
  • the high electron mobility transistor further includes a nucleation layer 40 , and the nucleation layer 40 is located on the side of the channel layer 30 away from the barrier layer 20 .
  • the material of the nucleation layer 40 may be AlN.
  • the thickness of the nucleation layer 40 can be any value between 10-50 nm. In specific applications, the thickness of the nucleation layer 40 can be reasonably set according to actual needs, which is not specifically limited in this application.
  • the channel layer 30 is grown conveniently.
  • the nucleation layer 40 may be grown first, and then the channel layer 30 may be grown on the basis of the nucleation layer 40 .
  • a substrate 100 for growing the channel layer 30 or the nucleation layer 40 is usually provided.
  • the base material 100 is usually made of Si or SiC material.
  • the nucleation layer 40 may be grown on the substrate 100 first, so that the channel layer 30 may be grown on the nucleation layer 40 .
  • the materials of the GaN channel layer 30 and the Si or SiC substrate 100 are different, they generally have different lattice constants and thermal expansion coefficients. If the channel layer 30 of GaN is directly grown on the substrate 100 of Si or SiC, there may be a large number of hexagonal defects between the channel layer 30 and the substrate 100 due to problems such as lattice mismatch and thermal adaptation. Defects are macro-defects, and the crystal planes have large fluctuations, which will destroy the continuity of the crystal film, resulting in very difficult and low-quality device fabrication.
  • the channel layer 30 of GaN is directly grown on the substrate 100 of Si or SiC, the ionization of oxygen impurities will cause the channel layer 30 to have a higher background carrier concentration, thus significantly reducing the mobility of electrons. , affecting the performance of the device.
  • the nucleation layer 40 may be grown on the substrate 100 first, and then the channel layer 30 may be grown on the nucleation layer 40 .
  • a high electron mobility transistor may include a nucleation layer 40 in the final product structure.
  • the source electrode 02 and the drain electrode 03 can pass through the nucleation layer 40 and be in ohmic contact with the channel layer 30, and the gate 04 can be located on the nucleation layer 40 and be in contact with the nucleation layer 40. Teki contacts.
  • the gate 04 may also pass through the nucleation layer 40 and be in Schottky contact with the channel layer 30 . This application is not limited to this.
  • the barrier layer 20 may be made of AlGaN material or doped AlGaN material during specific implementation.
  • the barrier layer 20 may include a Si-doped AlGaN layer and an AlGaN layer with an Al composition greater than 20% arranged in sequence along a direction away from the channel layer 30 .
  • the Si-doped AlGaN layer can adjust the energy band and prevent holes from being trapped.
  • the AlGaN layer with a larger Al composition can effectively increase the electron gas concentration.
  • the performance of high electron mobility transistors can be effectively improved by the Si-doped AlGaN layer and the AlGaN layer with an Al composition greater than 20%.
  • the overall thickness of the barrier layer 20 may be between 10-100 nm.
  • the thickness of the Si-doped AlGaN layer may be between 10-50 nm.
  • the thickness of the AlGaN layer with an Al composition greater than 20% may be between 1-20 nm.
  • the Al composition may be 21%, 22%, 30%, etc., and the present application does not limit the specific proportion of the Al composition.
  • the overall thickness of the barrier layer 20 , the thickness of the Si-doped AlGaN layer, and the thickness of the AlGaN layer with an Al composition greater than 20% can be adaptively adjusted according to actual conditions, which is not limited in this application.
  • the high electron mobility transistor may further include a high resistance layer 50 .
  • the high resistance layer 50 is located between the barrier layer 20 and the substrate layer 10 .
  • the nucleation layer 40 , the channel layer 30 , the barrier layer 20 , the high resistance layer 50 and the substrate layer 10 may be grown sequentially along a specific direction.
  • the high resistance layer 50 may be GaN doped with iron (Fe) or carbon (C). Among them, the main function of the high-resistance layer 50 is to increase the resistance value of the high-electron mobility transistor, so that it can be applied to application scenarios requiring a higher resistance value.
  • the thickness of the high resistance layer 50 can be any value between 10-500 nm.
  • the specific concentration of doped Fe or C can be reasonably set according to actual requirements, which is not limited in this application.
  • the nucleation layer 40 , the channel layer 30 , the barrier layer 20 and the high resistance layer 50 can be grown sequentially on the substrate 100 along a specific direction.
  • the substrate layer 10 is grown on the high resistance layer 50 .
  • the substrate 100 is removed.
  • a gate 04 , a drain 03 and a source 02 are prepared on the surface of the nucleation layer 40 .
  • the gate 04 is in Schottky contact with the nucleation layer 40
  • the source 02 and the drain 03 are in ohmic contact with the channel layer 30 .
  • high electron mobility transistors are mainly divided into two categories: N-type (or normally-on) and P-type (or normally-off).
  • N-type high electron mobility transistors can be widely used in the field of microwave radio frequency. For example, it can be applied to equipment such as base stations and radars to amplify radio frequency signals.
  • P-type high electron mobility transistors can be widely used in the field of power electronics. For example, in terminal equipment such as mobile phones and notebook computers, it can be used as a driver or switch.
  • an N-type (or normally-on) high electron mobility transistor is taken as an example for specific description.
  • the P-type (or normally-off) high electron mobility transistor is adaptively designed according to the above structure.
  • a P-type doped (or hole-doped) GaN layer can be added on the basis of the HMET device in any of the above embodiments.
  • a high electron mobility transistor includes a channel layer 30, a barrier layer 20, and a substrate layer 10 that are sequentially grown along a specific direction.
  • a P-type doped GaN layer 60 on the side of the channel layer 30 away from the specific direction.
  • the gate 04 is in Schottky contact with the P-type doped GaN layer 60 .
  • the source 02 and the drain 03 are in ohmic contact with the channel layer 30 .
  • the final device structure may also have the high-resistance layer 50 , the nucleation layer 40 , etc. mentioned in the above embodiments, which will not be repeated here.
  • the embodiment of the present application also provides a method for preparing a high electron mobility transistor, the method may include the following steps:
  • the specific direction refers to any direction in space.
  • each layer of material is usually grown sequentially from bottom to top, therefore, the specific direction may be from bottom to top.
  • the specific direction may also be a direction from top to bottom, or may also be a direction from left to right, which is not specifically limited in the present application.
  • the substrate 100 may be made of materials such as silicon (Si) or silicon carbide (SiC). It can be understood that, in the embodiment of the present application, the main function of the substrate 100 is to serve as a substrate for growing epitaxial structures such as the channel layer 30 and the barrier layer 20 , so as to facilitate the preparation of the epitaxial structures.
  • the material of the channel layer 30 may be GaN, and the material of the barrier layer 20 may be AlGaN.
  • the channel layer 30, the barrier layer 20 and the substrate layer 10 are sequentially grown and formed. , it is easier to obtain high electron mobility transistors on the N-face, and the crystal quality of the N-face can be effectively guaranteed.
  • the channel layer 30 and the barrier layer 20 are grown, they can be prepared by metal-organic chemical vapor deposition (Metal-organic Chemical Vapor Deposition, MOCVD) and other techniques.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • the present application does not limit the preparation process of the channel layer 30 and the barrier layer 20 .
  • materials such as Si, SiC or diamond can be used for preparation during preparation.
  • a process such as Microwave Plasma Chemical Vapor Deposition (MPCVD) can be used to directly grow a diamond material on the barrier layer 20, thereby realizing the preparation of the substrate layer 10.
  • MPCVD Microwave Plasma Chemical Vapor Deposition
  • FIG. 1 As shown in FIG. 1 .
  • AlN, AlGaN and GaN materials are grown sequentially on the substrate layer 10 of Si or SiC material.
  • the source 02 , drain 03 and gate 04 are prepared on the surface of GaN (ie, the surface away from the substrate layer 10 ).
  • a substrate (not shown) of Si or SiC material can be used, and then a channel layer 30 (such as GaN), a barrier layer 20 (such as AlGaN) and a substrate are grown on the substrate.
  • Substrate layer 10 (such as Si, SiC or diamond). Then the substrate is removed, and the source 02 , the drain 03 and the gate 04 are prepared on the channel layer 30 .
  • the diamond can be directly grown and shaped, so as to facilitate the preparation of the substrate layer 10 .
  • the substrate 100 may be thinned first by using a mechanical grinding process, and then the remaining substrate 100 may be removed by an etching process. Therefore, the removal efficiency and quality of the substrate 100 can be improved.
  • the process of removing the base material 100 is not limited in this application.
  • the specific preparation in order to ensure the molding quality of the channel layer 30, before preparing the channel layer 30 on the substrate 100, it may also include: growing the nucleation layer 40 on the substrate 100 along a specific direction, and then Channel layer 30 is grown on layer 40 .
  • the material of the nucleation layer 40 may be AlN, or AlN doped with C or Fe. The present application does not limit the specific material composition of the nucleation layer 40 .
  • the nucleation layer 40 may be grown on the substrate 100 first, so that the channel layer 30 may be grown on the nucleation layer 40 .
  • the materials of the GaN channel layer 30 and the Si or SiC substrate 100 are different, they generally have different lattice constants and thermal expansion coefficients. If the channel layer 30 of GaN is directly grown on the substrate 100 of Si or SiC, there may be a large number of hexagonal defects between the channel layer 30 and the substrate 100 due to problems such as lattice mismatch and thermal adaptation. Defects are macro-defects, and the crystal planes have large fluctuations, which will destroy the continuity of the crystal film, resulting in very difficult and low-quality device fabrication.
  • the channel layer 30 of GaN is directly grown on the substrate 100 of Si or SiC, the ionization of oxygen impurities will cause the channel layer 30 to have a higher background carrier concentration, thus significantly reducing the mobility of electrons. , affecting the performance of the device.
  • the nucleation layer 40 may be grown on the substrate 100 first, and then the channel layer 30 may be grown on the nucleation layer 40 .
  • the nucleation layer 40 may not be removed, so that the manufacturing process can be simplified and the manufacturing efficiency can be improved.
  • the source 02 and the drain 03 need to be in ohmic contact with the channel layer 30 . Therefore, before preparing the source electrode 02 and the drain electrode 03 , a via hole penetrating to the surface of the channel layer 30 may also be prepared on the nucleation layer 40 by means of mechanical drilling or etching. Finally, the source 02 and the drain 03 may be prepared in different through holes, so that the source 02 and the drain 03 are in ohmic contact with the channel layer 30 .
  • the gate 04 can be directly prepared on the surface of the nucleation layer 40 and is in Schottky contact with the nucleation layer 40 .
  • a via hole can be formed on the nucleation layer 40 to inform the surface of the channel layer 30 , and the gate 04 is in Schottky contact with the channel layer 30 .
  • the nucleation layer 40 may also be removed.
  • an etching process may be used to remove the nucleation layer 40 .
  • other processes such as mechanical grinding may also be used, which is not limited in the present application.
  • the quality of the surface of the channel layer 30 may be affected when the nucleation layer 40 is removed separately.
  • the method may also include growing a buffer layer 70 on the surface of the nucleation layer 40 along a specific direction after the growth of the nucleation layer 40 is completed, and then growing a buffer layer 70 on the surface of the buffer layer 70 A channel layer 30 is grown.
  • the material of the buffer layer 70 may be AlGaN, and may be prepared by metalorganic chemical vapor deposition and other techniques.
  • thermal oxidation and wet etching When removing the buffer layer 70 and the nucleation layer 40, a combined process of thermal oxidation and wet etching may be used. Among them, the temperature required for the thermal oxidation process is generally between 550-650° C., and the time is about 30-60 minutes.
  • the main solution in the wet etching process is potassium hydroxide (KOH).
  • KOH potassium hydroxide
  • AlN, AlGaN and oxygen react to form aluminum oxide (Al 2 O 3 ), gallium oxide (Ga 2 O 3 ) and nitrogen (N 2 ), among which, the oxides Al 2 O 3 and Ga 2 O 3 can be The KOH solution at 70° C.
  • AlGaN is more easily oxidized than GaN under the temperature condition of high temperature oxidation.
  • the main reason why AlGaN is more easily oxidized than GaN is that the Gibbs free energy of Al 2 O 3 obtained by the reaction is greater than the Gibbs free energy of Ga 2 O 3 obtained by the reaction. In this way, the influence on the GaN channel layer 30 can be reduced as much as possible.
  • AlGaN may be directly grown on the surface of the channel layer 30 by metalorganic chemical vapor deposition.
  • a Si-doped AlGaN layer and an AlGaN layer with an Al composition greater than 20% may be sequentially grown along a specific direction on the surface of the channel layer 30 .
  • the Si-doped AlGaN layer can adjust the energy band and prevent holes from being trapped.
  • the AlGaN layer with a larger Al composition can effectively increase the electron gas concentration.
  • the performance of high electron mobility transistors can be effectively improved by the Si-doped AlGaN layer and the AlGaN layer with an Al composition greater than 20%.
  • the high resistance layer 50 may be GaN doped with iron (Fe) or carbon (C). It can be prepared by organometallic chemical vapor deposition and other techniques.
  • the main function of the high-resistance layer 50 is to increase the resistance value of the high electron mobility transistor, so that it can be applied to application scenarios requiring a higher resistance value.
  • the nucleation layer 40 , the buffer layer 70 , the channel layer 30 , the barrier layer 20 and the high resistance layer 50 can be grown sequentially along a specific direction on the substrate 100 .
  • the substrate layer 10 is grown on the high resistance layer 50 .
  • the substrate 100 is removed.
  • the nucleation layer 40 and the buffer layer 70 are removed.
  • a gate 04 , a drain 03 and a source 02 are prepared on the surface of the channel layer 30 .
  • the gate 04 is in Schottky contact with the channel layer 30
  • the source 02 and the drain 03 are in ohmic contact with the channel layer 30 .
  • high electron mobility transistors are mainly divided into two categories: N-type (or normally-on) and P-type (or normally-off).
  • N-type high electron mobility transistors can be widely used in the field of microwave radio frequency. For example, it can be applied to equipment such as base stations and radars to amplify radio frequency signals.
  • P-type high electron mobility transistors can be widely used in the field of power electronics. For example, in terminal equipment such as mobile phones and notebook computers, it can be used as a driver or switch.
  • the preparation method of an N-type (or normally-on) high electron mobility transistor is taken as an example for specific description.
  • the above-mentioned preparation method can also be applied to the preparation of P-type (or normally-off) high electron mobility transistors.
  • a P-type doped GaN layer 60 can be added on the channel layer 30, and the gate 04 and the P-type doped GaN layer 60 Schottky contacts.

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Abstract

本申请提供了一种高电子迁移率晶体管、射频晶体管、功率放大器和高电子迁移率晶体管的制备方法，涉及微电子技术领域，以解决氮面高电子迁移率晶体管性能不佳的技术问题。本申请提供的高电子迁移率晶体管，包括依次设置的沟道层、势垒层和衬底层；沟道层的与势垒层接触的表面具有二维电子气层，还包括源极和漏极，源极和漏极位于沟道层上，且源极和漏极与沟道层欧姆接触。本申请实施例提供的高电子迁移率晶体管，可以实现较低的欧姆接触电阻，能够较好的应用在高频和功率场景中。

Description

一种高电子迁移率晶体管、射频晶体管、功率放大器和高电子迁移率晶体管的制备方法 技术领域
本申请涉及微电子技术领域，尤其涉及一种高电子迁移率晶体管、射频晶体管、功率放大器和高电子迁移率晶体管的制备方法。
背景技术
宽禁带半导体氮化镓(GaN)材料具有禁带宽度大、击穿场强高、极化系数高、电子迁移率高、电子饱和漂移速度高等性能优势，在电力电子和射频领域逐渐被广泛应用。
目前氮化镓基的高电子迁移率晶体管结构存在缺陷，需要改进的需求。
发明内容
本申请提供了一种具有较低欧姆接触电阻的高电子迁移率晶体管、射频晶体管、功率放大器和高电子迁移率晶体管的制备方法。
一方面，本申请提供了一种高电子迁移率晶体管，至少包括依次设置的沟道层、势垒层和衬底层。沟道层中形成有二维电子气层，且二维电子气层与势垒层接触。还包括源极和漏极，源极和漏极位于沟道层上，且源极和漏极与沟道层欧姆接触。其中，二维电子气层是由沟道层和势垒层之间的结界面处极化效应产生的。二维电子气层位于沟道层中，且二维电子气层与势垒层接触，因此，沟道层背离势垒层的表面可以获得更低的欧姆接触电阻，或者，可以理解的是，源极和漏极与沟道层之间具有更低的欧姆接触电阻，从而能够较好的应用在高频和功率场景中。
其中，二维电子气层指的是，沟道层和势垒层的异质结界面处极化效应产生的二维电子气的虚拟层。该二维电子气层位于沟道层中，且二维电子气层与势垒层接触。
在一种实现方式中，沟道层的材料可以是氮化镓(GaN)。势垒层的材料可以是氮化铝镓(AlGaN)。高电子迁移率晶体管可以通过氮化铝镓和氮化镓异质结界面处极化效应产生的二维电子气实现高电子迁移率。
另外，在本申请提供的实施例中，沟道层背离势垒层的表面为氮(N)面。或者，可以理解的是，高电子迁移率晶体管的表面(即背离衬底层的表面)为氮面。沟道层、势垒层和衬底层可以是依次生长成型的，因此，本申请实施例提供的高电子迁移率晶体管在制备时，能够更容易获得氮面的高电子迁移率晶体管，并且能有效保证氮面的晶体质量。另外，相较于镓(Ga)面的高电子迁移率晶体管，氮面的高电子迁移率晶体管可以获得更低的欧姆接触电阻，因此，氮面的高电子迁移率晶体管能够较好的应用在高频和功率场景中。
对于衬底层，在具体应用时，其材料可以是硅(Si)、碳化硅(SiC)或金刚石等。在本申请提供的一种实现方式中，衬底层可以采用金刚石材料。由于金刚石材料具有更高的热导率，因此，可以有效提升器件的散热性能。另外，在本申请提供的实现方式中，沟道层、势垒层和衬底层是依次生长形成的，因此，可以采用微波等离子化学气相沉淀(Microwave Plasma.Chemical Vapour Deposition，MPCVD)等工艺在势垒层上直接生长金 刚石衬底层，从而可以有效提升衬底层的制备效率和品质。
对于栅极，在一种实现方式中，可以设置在沟道层上，并与沟道层肖特基接触。
另外，根据高电子迁移率晶体管结构的不同，栅极也可以设置在其他的结构上。
例如，在本申请提供的一种实现方式中，高电子迁移率晶体管还可以包括成核层。成核层位于沟道层的背离势垒层的一侧。栅极位于成核层，且栅极与成核层肖特基接触。其中，成核层的材料可以是氮化铝(AlN)，也可以是其他有利于沟道层成型的材料，本申请对此不作限制。
对于势垒层，在一种实现方式中，可以包括氮化镓铝。或者，势垒层可以包括沿背离沟道层的方向依次设置的掺杂硅的氮化铝镓层，以及铝组分大于20％的氮化铝镓层。其中，掺硅的氮化铝镓层能够调整能带，防止空穴被束缚。铝组分较大的氮化铝镓层能够有效提升电子气浓度。概括来说，通过掺硅的氮化铝镓层和铝组分大于20％的氮化铝镓层可以有效提升高电子迁移率晶体管的性能。
在一种实现方式中，高电子迁移率晶体管还可以包括高阻层。具体来说，高阻层位于势垒层和衬底层之间。其中，成核层、沟道层、势垒层、高阻层和衬底层可以是依次设置的。高阻层的材料可以是掺杂有铁(Fe)或碳(C)的氮化镓。其中，高阻层的主要作用是，能够提升高电子迁移率晶体管的阻值，从而可以应用到所需阻值较高的应用场景中。
另外，在一种实现方式中，高电子迁移率晶体管也可以是P型(或常关型)。例如，高电子迁移率晶体管包括依次设置的沟道层、势垒层、和衬底层。另外，在沟道层背离该势垒层的一侧具有P型掺杂(或空穴掺杂)的氮化镓层。并且，栅极与P型掺杂的氮化镓层肖特基接触。源极和漏极与沟道层欧姆接触。在最终的器件结构上，也可以具有上述实施例中提到的高阻层、成核层等，在此不作赘述。
另一方面，本申请还提供了一种射频晶体管和功率放大器，包括上述任一种高电子迁移率晶体管。或者，可以理解的是，本申请提供的高电子迁移率晶体管可以广泛的应用到基站、雷达、手机、笔记本电脑等设备中。本申请对高电子迁移率晶体管的具体应用场景不作限制。
另一方面，本申请还提供了一种高电子迁移率晶体管的制备方法，可以包括：至少在基材上沿特定方向依次生长沟道层、势垒层和衬底层，去除基材，在沟道层上制备源极和漏极，且源极和漏极与沟道层欧姆接触。基材可以是硅(Si)或碳化硅(SiC)等材料。可以理解的是，在本申请实施例中，基材的主要作用是作为用于生长沟道层和势垒层等外延结构的衬底，以便于对外延结构进行制备。沟道层的材料可以是氮化镓，势垒层的材料可以是氮化铝镓。另外，在本申请提供的实施例中，沟道层、势垒层和衬底层是依次生长成型的，因此，通过本申请实施例提供的制备方法在对高电子迁移率晶体管进行制备时，能够更容易获得氮面的高电子迁移率晶体管，并且能有效保证氮面的晶体质量。
在一种实现方式中，该制备方法还可以包括制备栅极。栅极可以位于沟道层上，且栅极可以与沟道层肖特基接触。
或者，在一些制备方法中，在基材上制备沟道层之前还可以包括：沿特定方向在基材上生长成核层。其中，沟道层位于成核层上。
另外，在对栅极进行制备时，栅极可以位于成核层上，并与成核层肖特基接触。
或者，在一些制备方法中，也可以在去除基材后，将成核层进行去除。
或者，在一些制备方法中，沿特定方向在基材上生长成核层后还可以包括：沿特定方 向在成核层上生长缓冲层。
当去除基材后，可以去除成核层和缓冲层。其中，缓冲层的设置能够便于将成核层以及自身进行有效去除，同时，也不会影响到沟道层的品质。
在一些制备方法中，在生长势垒层时，具体可以包括：沿特定方向依次生长掺杂硅的氮化铝镓层，以及铝组分大于20％的氮化铝镓层。
或者，在一些实现方式中，生长衬底层之前还可以包括：沿特定方向在势垒层的表面生长高阻层。其中，高阻层的主要作用是，能够提升高电子迁移率晶体管的阻值，从而可以应用到所需阻值较高的应用场景中。
另外，基于本申请提供的制备方法还可以对P型(或常关型)高电子迁移率晶体管进行制备。例如，在对P型高电子迁移率晶体管进行制备时，可以在沟道层上，增加P型掺杂(或空穴掺杂)的氮化镓层，且栅极与P型掺杂的氮化镓层肖特基接触。
可以理解的是，在具体应用时，本申请的制备方法可以根据实际需求对不同工艺的顺序进行适应性调整，本申请对此不作限定。
附图说明
图1为本申请实施例提供的一种目前的高电子迁移率晶体管的结构示意图；
图2为本申请实施例提供的一种高电子迁移率晶体管的结构示意图；
图3为本申请实施例提供的另一种高电子迁移率晶体管的结构示意图；
图4为本申请实施例提供的另一种高电子迁移率晶体管在制备过程中的结构示意图；
图5为本申请实施例提供的另一种高电子迁移率晶体管的结构示意图；
图6为本申请实施例提供的另一种高电子迁移率晶体管在制备过程中的结构示意图；
图7为本申请实施例提供的另一种高电子迁移率晶体管在制备过程中的结构示意图；
图8为本申请实施例提供的另一种高电子迁移率晶体管在制备过程中的结构示意图；
图9为本申请实施例提供的另一种高电子迁移率晶体管在制备过程中的结构示意图；
图10为本申请实施例提供的另一种高电子迁移率晶体管的结构示意图；
图11为本申请实施例提供的另一种高电子迁移率晶体管的结构示意图；
图12为本申请实施例提供的一种高电子迁移率晶体管的制备方法的流程图；
图13为本申请实施例提供的另一种高电子迁移率晶体管在制备过程中的结构示意图；
图14为本申请实施例提供的另一种高电子迁移率晶体管在制备过程中的结构示意图；
图15为本申请实施例提供的另一种高电子迁移率晶体管在制备过程中的结构示意图；
图16为本申请实施例提供的另一种高电子迁移率晶体管在制备过程中的结构示意图；
图17为本申请实施例提供的另一种高电子迁移率晶体管在制备过程中的结构示意图；
图18为本申请实施例提供的另一种高电子迁移率晶体管在制备过程中的结构示意图；
图19为本申请实施例提供的另一种高电子迁移率晶体管的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
为了方便理解本申请实施例提供的高电子迁移率晶体管，下面首先介绍一下其工作原 理。
高电子迁移率晶体管(Hight Electron Mobility Transistor，HEMT)，主要是利用氮化铝镓(AlGaN)/氮化镓(GaN)异质结界面处极化效应产生的二维电子气(Two-dimensional electron gas，2DEG)实现高电子迁移率。二维电子气指的是，电子在垂直于结界面方向的运动被势阱束缚而被量子化，电子在平行于结界面方向的运动仍然是自由的，这样的电子薄层被称为二维电子气。
高电子迁移率晶体管可以应用在微波射频或电力电子等微电子领域中。例如，在微波射频领域中，高电子迁移率晶体管可以作为功率放大器，其主要作用是将有源天线处理单元(Active Antenna Unit，AAU)内部的射频信号进行放大，然后通过天线以电磁波的形式发射出去。在电力电子领域中，高电子迁移率晶体管可以作为功率开关和驱动。例如，在手机、笔记电脑或平板电脑等终端设备中，高电子迁移率晶体管可以作为充电电路中的开关。在激光雷达等设备中，可以作为驱动器的主要组成部件。
如图1所示，在一些高电子迁移率晶体管中，通常采用硅(Si)或碳化硅(SiC)作为衬底，然后在衬底上依次生长氮化铝(AlN)、氮化镓(GaN)、氮化铝镓(AlGaN)等材料进行制备。然后在AlGaN层的上表面制备源极02、漏极03和栅极04。GaN层中形成有二维电子气层01，且二维电子气层01与AlGaN层接触在对AlGaN进行制备时，化合物中的氮(N)原子会首先形成，随后沿特定方向在N原子的基础上形成铝(Al)原子和镓(Ga)原子。或者可以理解为，在微观角度上来看，AlGaN层中的N原子、Al原子和Ga原子是依次排列的，使得目前的高电子迁移率晶体管的表面(如图中的上表面)为Ga面。但是，相较于Ga面的高电子迁移率晶体管，N面的高电子迁移率晶体管可以获得更低的欧姆接触电阻，因此，N面的高电子迁移率晶体管能够较好的应用在高频和功率场景中。
为此，本申请实施例提供了一种可以获得更低欧姆接触电阻的高电子迁移率晶体管。
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图和具体实施例对本申请作进一步地详细描述。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”和“该”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。还应当理解，在本申请以下各实施例中，“至少一个”是指一个、两个或两个以上。
在本说明书中描述的参考“一个实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施方式中”、“在另外的实施方式中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
如图2所示，本申请实施提供了一种高电子迁移率晶体管。包括沟道层30、势垒层20和衬底层10。其中，沟道层30、势垒层20和衬底层10沿特定方向依次设置；沟道层30中形成有二维电子气层01(在图中用虚线表示)，且二维电子气层01与势垒层20接触。源极02、栅极04和漏极03位于沟道层30上，源极02和漏极03与沟道层30欧姆接触，栅极04与沟道层30肖特基接触。
在本申请提供的高电子迁移率晶体管中，二维电子气层位于沟道层中，并与势垒层接触，因此，沟道层背离势垒层的表面可以获得更低的欧姆接触电阻，从而能够较好的应用在高频和功率场景中。
其中，二维电子气层01指的是，沟道层30和势垒层20的异质结界面处极化效应产生的二维电子气的虚拟层。该二维电子气层01位于沟道层30中，并与势垒层20接触。
欧姆接触指的是，半导体与金属接触时，多会形成势垒，但当半导体掺杂浓度较高时，电子可以借隧道效应穿过势垒，从而形成低阻值的欧姆接触，良好的欧姆接触有利于电流的输入和输出。肖特基接触指的是栅极04(如金属材料)和沟道层30(如半导体材料)相接触时，在交界面处半导体的能带弯曲，形成肖特基势垒。
在具体实施时，沟道层30的材料可以是GaN。势垒层20的材料可以是AlGaN。高电子迁移率晶体管可以通过AlGaN和GaN异质结界面处极化效应产生的二维电子气实现高电子迁移率。
在本申请提供的实施例中，高电子迁移率晶体管的表面(即背离衬底层10的表面)为氮(N)面，因此，高电子迁移率晶体管可以获得更低的欧姆接触电阻，或者，可以理解的是，源极02和漏极03与沟道层30之间具有更低的欧姆接触电阻，从而能够较好的应用在高频和功率场景中。另外，在本申请提供的实施例中，沟道层30、势垒层20和衬底层10是依次生长成型的，因此，本申请实施例提供的高电子迁移率晶体管在制备时，能够更容易获得N面的高电子迁移率晶体管，并且能有效保证N面的晶体质量。另外，相较于镓(Ga)面的高电子迁移率晶体管，N面的高电子迁移率晶体管可以获得更低的欧姆接触电阻，因此，N面的高电子迁移率晶体管能够较好的应用在高频和功率场景中。
其中，沟道层30的厚度可以是50-500nm之间的任意值，势垒层20的厚度可以是10-100nm之间的任意值。在具体应用时，沟道层30和势垒层20的厚度可以根据实际需求进行合理设置，本申请对此不作具体限定。另外，在其他的实施方式中，沟道层30的材料也可以是砷化镓(GaAs)等，势垒层20的材料可以是砷化铝镓(AlGaAs)等。在具体应用时，沟道层30和势垒层20的材料可以根据实际需求进行合理选择和调整，本申请对此不作具体限定。
对于衬底层10，在具体应用时，其材料可以是硅(Si)、碳化硅(SiC)或金刚石等。
其中，在室温(如25℃)下，Si的热导率在150W/mK左右，SiC的热导率在370W/mK左右，金刚石的热导率通常会大于1000W/mK。
由于Si或SiC的热导率较差，会形成较大热阻，且热导率会随温度上升而下降，因此，在某些大功率的应用场景下会面临散热能力不足的问题，导致高电子迁移率晶体管只能在较低的功率密度下运行，以保证其长期可靠性。例如，GaN的HMET器件的理论输出功率密度可达40W/mm以上，然而由于衬底材料采用Si或SiC时，为保证高电子迁移率晶体管的长期可靠性，需要使高电子迁移率晶体管处在比较低的功率密度下运行(如小于10W/mm)，因此，不利于发挥高电子迁移率晶体管的工作性能。
因此，金刚石衬底的高电子迁移率晶体管能够实现更好的散热，同时，也有助于提升高电子迁移率晶体管的功率密度。
当衬底采用金刚石材料时，在进行制备的过程中，通常是将GaN层键合到金刚石衬底上，但是，键合工艺比较复杂且成本高，不利于大规模生产。键合的工艺需要金刚石表面加工的非常平整(如表面粗糙度小于1nm)，但是，金刚石的硬度较高，若加工到非常平 整的表面非常困难。并且，键合的工艺也是单片式的工艺，一片一片的加工生产会导致生产效率较低的问题。另外，在进行键合时，需要在GaN层和金刚石衬底之间加入氮化硅(SiN)等键合层材料。由于键合层材料具有较高的热阻，因此，会降低器件的散热性能。
并且，由于金刚石材料具有较好的热导率，因此，能够明显提升器件的散热性能。
在本申请提供的实施例中，可以采用金刚石材料作为衬底层10，以提升器件的散热性能。
另外，在本申请提供的实施例中，沟道层30、势垒层20和衬底层10是依次生长形成的，因此，可以采用微波等离子化学气相沉淀(Microwave Plasma.Chemical Vapour Deposition，MPCVD)等工艺在势垒层20上直接生长金刚石衬底层10，从而可以有效提升衬底层10的制备效率和品质。
或者，可以理解的是，在本申请提供的高电子迁移率晶体管中，在对衬底层10进行制备时，能够避免采用键合工艺将衬底层10与势垒层20进行键合，从而能够降低制备难度和制作成本。另外，由于避免采用的键合工艺，因此，也就避免了在衬底层10和势垒层20之间添加较大热阻的键合材料(如SiN)，因此，能够保证器件的散热性能。
在具体实施时，HMET器件的结构可以是多样的。
例如，如图3所示，在本申请提供的另一个实施例中，高电子迁移率晶体管还包括成核层40，成核层40位于沟道层30背离势垒层20的一侧。其中，成核层40的材料可以是AlN。另外，成核层40的厚度可以是10-50nm之间的任意值。在具体应用时，成核层40的厚度可以根据实际需求进行合理设置，本申请对此不作具体限定。
具体来说，在进行制备时，为了便于生长沟道层30。可以首先生长成核层40，然后在成核层40的基础上生长沟道层30。
如图4所示，可以理解的是，在对高电子迁移率晶体管进行制备时，通常会提供一个用于生长上述沟道层30或成核层40的基材100。其中，基材100通常采用Si或SiC材料。
在目前的制备工艺中，沟道层30很难在基材100上直接生长。因此，可以首先在基材100上生长成核层40，从而可以在成核层40上生长沟道层30。
或者，可以理解的是，由于GaN的沟道层30和Si或SiC的基材100的材料不同，通常具有不同的晶格常数和热膨胀系数。如果直接在Si或SiC的基材100上生长GaN的沟道层30，沟道层30与基材100之间可能会由于晶格不匹配和热适配等问题而大量的六方缺陷，这种缺陷属于宏观缺陷，且晶面起伏较大，会破坏晶体薄膜的连续性，导致器件制备非常困难且质量较低。另外，当直接在Si或SiC的基材100上生长GaN的沟道层30时，氧杂质电离会导致沟道层30具有较高的背景载流子浓度，因此，会明显降低电子的迁移率，影响器件的工作性能。
因此，为了生长出高质量的N面沟道层30，可以首先在基材100上生长成核层40，然后在成核层40上生长出沟道层30。
如图3所示，在本申请提供的实施例中，因制备工艺流程而产生的成核层40可以不进行去除，以降低制备成本、简化制备流程。因此，在最终的产品结构上高电子迁移率晶体管可以包括成核层40。
另外，在对电极进行制备时，源极02和漏极03可以穿过成核层40并与沟道层30欧姆接触，栅极04可以位于成核层40上，并与成核层40肖特基接触。
可以理解的是，在其他的实施方式中，栅极04也可以穿过成核层40与沟道层30肖 特基接触。本申请对此不作限定。
对于势垒层20，在具体实施时，可以是AlGaN材料，或者，也可以掺杂的AlGaN材料。
例如，在本申请提供的一个实施例中，势垒层20可以包括沿背离沟道层30的方向依次设置的掺Si的AlGaN层以及Al组分大于20％的AlGaN层。其中，掺Si的AlGaN层能够调整能带，防止空穴被束缚。Al组分较大的AlGaN层能够有效提升电子气浓度。概括来说，通过掺Si的AlGaN层和Al组分大于20％的AlGaN层可以有效提升高电子迁移率晶体管的性能。
可以理解的是，在具体应用时，势垒层20的整体厚度可以是10-100nm之间。其中，掺Si的AlGaN层的厚度可以是10-50nm之间。Al组分大于20％的AlGaN层的厚度可以是1-20nm之间。另外，在Al组分大于20％的AlGaN层中，Al的组分可以是21％、22％、30％等，本申请对Al组分的具体占比不作限制。另外，势垒层20的整体厚度、掺Si的AlGaN层的厚度以及Al组分大于20％的AlGaN层的厚度可以根据实际情况进行适应性调整，本申请对此不作限制。
另外，如图5所示，在其他的实施方式中，高电子迁移率晶体管还可以包括高阻层50。
具体来说，高阻层50位于势垒层20和衬底层10之间。其中，成核层40、沟道层30、势垒层20、高阻层50和衬底层10可以是沿特定方向依次生长形成的。
高阻层50可以是掺杂有铁(Fe)或碳(C)的GaN。其中，高阻层50的主要作用是，能够提升高电子迁移率晶体管的阻值，从而可以应用到所需阻值较高的应用场景中。
在具体应用时，高阻层50的厚度可以是10-500nm之间的任意值。另外，在高阻层50中，所掺杂的Fe或C的具体浓度可以根据实际需求进行合理设置，本申请对此不作限制。
为了便于清楚理解本申请技术方案，下面对高电子迁移率晶体管的成型过程进行详细说明。
如图6所示，可以在基材100上沿特定方向依次生长成核层40、沟道层30、势垒层20和高阻层50。
如图7所示，在高阻层50上生长衬底层10。
如图8所示，将器件进行翻转。
如图9所示，对基材100进行去除。
如图10所示，在成核层40的表面制备栅极04、漏极03和源极02。其中，栅极04与成核层40肖特基接触，源极02和漏极03与沟道层30欧姆接触。
可以理解的是，高电子迁移率晶体管主要分为N型(或常开型)和P型(或常关型)两大类。N型高电子迁移率晶体管可以广泛的应用到微波射频领域中。例如，可以应用到基站、雷达等设备中，用于对射频信号进行放大等作用。P型高电子迁移率晶体管可以广泛的应用到电力电子领域中。例如，在手机、笔记本电脑等终端设备中，可以作为驱动器或开关等。
在上述的实施例中，以N型(或常开型)高电子迁移率晶体管为例进行的具体说明。
当然，在其他的实施方式中，P型(或常关型)高电子迁移率晶体管依照上述的结构进行适应性设计。或者，可以理解的是，在P型高电子迁移率晶体管中，可以在上述任一实施例中的HMET器件的基础上，增加P型掺杂(或空穴掺杂)的GaN层。
例如，如图11所示，在本申请提供的一个实施例中，高电子迁移率晶体管包括沿特定 方向依次生长形成的沟道层30、势垒层20、和衬底层10。另外，在沟道层30背离该特定方向的一侧具有P型掺杂的GaN层60。并且，栅极04与P型掺杂的GaN层60肖特基接触。源极02和漏极03与沟道层30欧姆接触。
可以理解的是，在最终的器件结构上，也可以具有上述实施例中提到的高阻层50、成核层40等，在此不作赘述。
另外，如图12所示。本申请实施例还提供了一种高电子迁移率晶体管的制备方法，该方法可以包括以下步骤：
S100、至少在基材上沿特定方向依次生长沟道层、势垒层和衬底层。
S200、去除基材。
S300、在沟道层上制备源极和漏极。其中，源极和漏极与沟道层欧姆接触。
在具体制备时，该特定方向指的是空间内的任意的一个方向。例如，由于常规的制备方式中，为了便于获得较好的成型质量，各层材料通常是由下到上依次生长形成的，因此，该特定方向可以是由下到上的方向。可以理解的是，在其他的实施方式中，该特定方向也可以是由上到下的方向，或者，也可以是由左到右的方向，本申请对此不作具体限定。
请结合参阅图6。在具体实施时，基材100可以是硅(Si)或碳化硅(SiC)等材料。可以理解的是，在本申请实施例中，基材100的主要作用是作为用于生长沟道层30和势垒层20等外延结构的衬底，以便于对外延结构进行制备。
在实际应用中，沟道层30的材料可以是GaN，势垒层20的材料可以是AlGaN。另外，在本申请提供的实施例中，沟道层30、势垒层20和衬底层10是依次生长成型的，因此，通过本申请实施例提供的制备方法在对高电子迁移率晶体管进行制备时，能够更容易获得N面的高电子迁移率晶体管，并且能有效保证N面的晶体质量。
在对沟道层30和势垒层20进行生长时，可以采用有机金属化学气相沉积法(Metal-organic Chemical Vapor Deposition，MOCVD)等工艺进行制备。当然，本申请对沟道层30和势垒层20的制备工艺不作限制。
对于衬底层10，在进行制备时，可以采用Si、SiC或金刚石等材料进行制备。例如，当衬底层10采用金刚石材料时，可以采用微波等离子化学气相沉淀(Microwave Plasma.Chemical Vapour Deposition，MPCVD)等工艺在势垒层20上直接生长金刚石材料，从而实现对衬底层10的制备。
或者，可以理解的是，如图1所示。在常规的制备方法中，通常是在Si或SiC材料的衬底层10上依次生长AlN、AlGaN和GaN材料。最后在GaN的表面(即背离衬底层10的表面)制备源极02漏极03和栅极04。
请结合参阅图2。在本申请提供的制备方法中，可以采用Si或SiC材料的基材(图中未示出)，然后在基材上生长沟道层30(如GaN)、势垒层20(如AlGaN)和衬底层10(如Si、SiC或金刚石)。然后去除基材，并在沟道层30上制备源极02、漏极03和栅极04。
通过本申请实施提供的制备方法，可以获得较高质量的N面高电子迁移率晶体管。另外，金刚石可以直接生长成型，从而便于对衬底层10进行制备。
请结合参阅图8和图9。在对基材100进行去除时，可以采用蚀刻工艺、机械磨削工艺或者两者的结合。
例如，可以首先采用机械磨削工艺对基材100进行减薄处理，然后采用蚀刻工艺对残留的基材100进行去除。从而能够提升基材100的去除效率和品质。
可以理解的是，在具体实施时，对基材100进行去除的工艺本申请不作限制。
另外，在具体制备时，为了保证沟道层30的成型质量，在基材100上制备沟道层30之前还可以包括：沿特定方向在基材100上生长成核层40，然后在成核层40上生长沟道层30。其中，成核层40的材料可以是AlN，或者掺杂C或Fe的AlN。本申请对成核层40的具体材料成分不作限制。
在目前的制备工艺中，沟道层30很难在基材100上直接生长。因此，可以首先在基材100上生长成核层40，从而可以在成核层40上生长沟道层30。
或者，可以理解的是，由于GaN的沟道层30和Si或SiC的基材100的材料不同，通常具有不同的晶格常数和热膨胀系数。如果直接在Si或SiC的基材100上生长GaN的沟道层30，沟道层30与基材100之间可能会由于晶格不匹配和热适配等问题而大量的六方缺陷，这种缺陷属于宏观缺陷，且晶面起伏较大，会破坏晶体薄膜的连续性，导致器件制备非常困难且质量较低。另外，当直接在Si或SiC的基材100上生长GaN的沟道层30时，氧杂质电离会导致沟道层30具有较高的背景载流子浓度，因此，会明显降低电子的迁移率，影响器件的工作性能。
因此，为了生长出高质量的N面沟道层30，可以首先在基材100上生长成核层40，然后在成核层40上生长出沟道层30。
在具体实施时，当对基材100进行去除后，可以不对成核层40进行去除，从而能够简化制备工艺流程，有利于提升制备效率。
另外，请结合参阅图10。在对电极进行制备时，由于源极02和漏极03需要与沟道层30保持欧姆接触。因此，在对源极02和漏极03进行制备之前，还可以采用机械打孔或蚀刻的方式在成核层40上制备贯通至沟道层30表面的通孔。最后可以在不同通孔内制备源极02和漏极03，以使源极02和漏极03与沟道层30保持欧姆接触。
栅极04可以直接制备在成核层40表面，并与成核层40肖特基接触。或者，也可以在成核层40上制备馆通知沟道层30表面的通孔，栅极04与沟道层30保持肖特基接触。
另外，在对基材100去除后，还可以去除成核层40。例如，可以采用刻蚀工艺将成核层40进行去除。当然，在对成核层40进行去除时，也可以采用机械磨削等其他的工艺，本申请对此不作限制。
基于目前的去除工艺，在对成核层40进行单独去除时，可能会影响到沟道层30表面的品质。
为此，如图13所示，在具体制备时，该方法还可以包括在成核层40生长完成后，沿特定方向在成核层40的表面生长缓冲层70，然后在缓冲层70的表面生长沟道层30。其中，缓冲层70的材料可以是AlGaN，且可以采用有机金属化学气相沉积法等工艺进行制备。
在对缓冲层70和成核层40进行去除时，可以采用热氧化和湿法刻蚀相结合的工艺。其中，热氧化工艺所需的温度一般为550-650℃之间，时间大约为30-60分钟，湿法刻蚀工艺中的主要溶液为氢氧化钾(KOH)。在热氧化的处理过程中，首先通入足够的氧气，使AlN和AlGaN充分氧化。其中，AlN、AlGaN和氧气反应生成三氧化二铝(Al 2O 3)、氧化镓(Ga 2O 3)和氮气(N 2)，其中，氧化物Al 2O 3和Ga 2O 3可以被70℃的KOH溶液蚀刻掉，且这种方法对GaN的沟道层30的影响比较小。或者，可以理解的是，在高温氧化的温度条件下，AlGaN比GaN更容易被氧化。其中，AlGaN比GaN更容易被氧化的主要原因是， 反应得到的Al 2O 3的吉布斯自由能(Gibbs free energy)比反应得到的Ga 2O 3的吉布斯自由能大。这样能够尽可能的降低对GaN沟道层30的影响。
另外，对于势垒层20在进行制备时，可以采用有机金属化学气相沉积法将AlGaN直接生长在沟道层30的表面。
或者，也可以在沟道层30的表面沿特定方向依次生长掺Si的AlGaN层以及Al组分大于20％的AlGaN层。其中，掺Si的AlGaN层能够调整能带，防止空穴被束缚。Al组分较大的AlGaN层能够有效提升电子气浓度。概括来说，通过掺Si的AlGaN层和Al组分大于20％的AlGaN层可以有效提升高电子迁移率晶体管的性能。
另外，在一些制备方法中，在生长衬底层10之间还可以包括，沿特定方向在势垒层20的表面生长高阻层50。其中，高阻层50可以是掺杂有铁(Fe)或碳(C)的GaN。可以采用有机金属化学气相沉积法等工艺进行制备。其中，高阻层50的主要作用是，能够提升高电子迁移率晶体管的阻值，从而可以应用到所需阻值较高的应用场景中。
当然，在具体实施时，本申请对高阻层50的具体制备方法不作限制。
为了便于清楚理解本申请技术方案，下面对高电子迁移率晶体管的另一种成型过程进行详细说明。
如图14所示，可以在基材100上沿特定方向依次生长成核层40、缓冲层70、沟道层30、势垒层20和高阻层50。
如图15所示，在高阻层50上生长衬底层10。
如图16所示，将器件进行翻转。
如图17所示，对基材100进行去除。
如图18所示，对成核层40和缓冲层70进行去除。
如图19所示，在沟道层30的表面制备栅极04、漏极03和源极02。其中，栅极04与沟道层30肖特基接触，源极02和漏极03与沟道层30欧姆接触。
可以理解的是，高电子迁移率晶体管主要分为N型(或常开型)和P型(或常关型)两大类。N型高电子迁移率晶体管可以广泛的应用到微波射频领域中。例如，可以应用到基站、雷达等设备中，用于对射频信号进行放大等作用。P型高电子迁移率晶体管可以广泛的应用到电力电子领域中。例如，在手机、笔记本电脑等终端设备中，可以作为驱动器或开关等。
在上述的制备方法中，以N型(或常开型)高电子迁移率晶体管的制备方法为例进行的具体说明。
当然，在其他的实施方式中，上述的制备方法也可以应用到用于制备P型(或常关型)高电子迁移率晶体管中。
例如，如图11，在对P型高电子迁移率晶体管进行制备时，可以在沟道层30上，增加P型掺杂的GaN层60，且栅极04与P型掺杂的GaN层60肖特基接触。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (24)

  1. 一种高电子迁移率晶体管，其特征在于，至少包括依次设置的沟道层、势垒层和衬底层；
    所述沟道层中形成有二维电子气层，且所述二维电子气层与所述势垒层接触；
    还包括源极和漏极，所述源极和所述漏极位于所述沟道层上，且所述源极和所述漏极与所述沟道层欧姆接触。
  2. 根据权利要求1所述的高电子迁移率晶体管，其特征在于，所述二维电子气层为所述沟道层和所述势垒层的异质结界面处极化效应产生的二维电子气的虚拟层。
  3. 根据权利要求1或2所述的高电子迁移率晶体管，其特征在于，所述沟道层的材料包括氮化镓，所述势垒层的材料包括氮化铝镓。
  4. 根据权利要求3所述的高电子迁移率晶体管，其特征在于，所述沟道层背离所述势垒层的表面为氮面。
  5. 根据权利要求1至3中任一项所述的高电子迁移率晶体管，其特征在于，所述衬底层的材料包括金刚石。
  6. 根据权利要求1至5中任一项所述的高电子迁移率晶体管，其特征在于，还包括栅极，所述栅极位于所述沟道层上，且所述栅极与所述沟道层肖特基接触。
  7. 根据权利要求1至5中任一项所述的高电子迁移率晶体管，其特征在于，还包括成核层和栅极；
    所述成核层位于所述沟道层的背离所述势垒层的一侧；
    所述栅极位于所述成核层，且所述栅极与所述成核层肖特基接触。
  8. 根据权利要求7所述的高电子迁移率晶体管，其特征在于，所述成核层的材料包括氮化铝。
  9. 根据权利要求1至8中任一项所述的高电子迁移率晶体管，其特征在于，所述势垒层包括背离所述沟道层的方向依次设置的掺杂硅的氮化铝镓层，以及铝组分大于20％的氮化铝镓层。
  10. 根据权利要求1至9中任一项所述的高电子迁移率晶体管，其特征在于，还包括高阻层，所述高阻层位于所述势垒层和所述衬底层之间。
  11. 根据权利要求10所述的高电子迁移率晶体管，其特征在于，所述高阻层的材料包括掺杂有铁或碳的氮化镓。
  12. 根据权利要求1至5中任一项所述的高电子迁移率晶体管，其特征在于，所述沟道层背离所述势垒层的一侧的材料包括空穴掺杂的氮化镓；
    还包括栅极，且所述栅极与所述空穴掺杂的氮化镓肖特基接触。
  13. 一种射频晶体管，其特征在于，包括如权利要求1至12中任一项所述的高电子迁移率晶体管。
  14. 一种功率放大器，其特征在于，包括如权利要求1至12中任一项所述的高电子迁移率晶体管。
  15. 一种高电子迁移率晶体管的制备方法，其特征在于，包括：
    至少在基材上沿特定方向依次生长沟道层、势垒层和衬底层；
    去除所述基材；
    在所述沟道层上制备源极和漏极，且所述源极和所述漏极与所述沟道层欧姆接触。
  16. 根据权利要求15所述的制备方法，其特征在于，在所述基材上制备沟道层之前还包括：
    沿所述特定方向在所述基材上生长成核层；
    其中，所述沟道层位于所述成核层上。
  17. 根据权利要求16所述的制备方法，其特征在于，还包括制备栅极；
    所述栅极位于所述成核层上，且所述栅极与所述成核层肖特基接触。
  18. 根据权利要求16所述的制备方法，其特征在于，所述去除所述基材之后还包括，去除所述成核层。
  19. 根据权利要求16所述的制备方法，其特征在于，所述沿所述特定方向在所述基材上生长成核层后还包括：
    沿所述特定方向在所述成核层上生长缓冲层。
  20. 根据权利要求19所述的制备方法，其特征在于，所述去除所述基材后还包括：
    去除所述成核层和所述缓冲层。
  21. 根据权利要求15、18或20所述的制备方法，其特征在于，还包括制备栅极；
    所述栅极位于所述沟道层上，且所述栅极与所述沟道层肖特基接触。
  22. 根据权利要求15至21中任一项所述的制备方法，其特征在于，生长所述势垒层包括：
    沿所述特定方向依次生长掺杂硅的氮化铝镓层，以及铝组分大于20％的氮化铝镓层。
  23. 根据权利要求15至22中任一项所述的制备方法，其特征在于，生长所述衬底层之前还包括：
    沿所述特定方向在所述势垒层的表面生长高阻层。
  24. 根据权利要求15所述的制备方法，其特征在于，所述去除所述基材后还包括：
    在所述沟道层背离所述特定方向的表面制备空穴掺杂的氮化镓；
    在所述空穴掺杂的氮化镓制备栅极，且所述栅极与所述空穴掺杂的氮化镓肖特基接触。
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