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WO2023004717A1 - 一种解码方法及装置 - Google Patents

一种解码方法及装置 Download PDF

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Publication number
WO2023004717A1
WO2023004717A1 PCT/CN2021/109382 CN2021109382W WO2023004717A1 WO 2023004717 A1 WO2023004717 A1 WO 2023004717A1 CN 2021109382 W CN2021109382 W CN 2021109382W WO 2023004717 A1 WO2023004717 A1 WO 2023004717A1
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Prior art keywords
decoding
decoded
code block
code
block
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Application number
PCT/CN2021/109382
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English (en)
French (fr)
Inventor
章成旻
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180100685.5A priority Critical patent/CN117693909A/zh
Priority to EP21951320.7A priority patent/EP4369638A4/en
Priority to PCT/CN2021/109382 priority patent/WO2023004717A1/zh
Publication of WO2023004717A1 publication Critical patent/WO2023004717A1/zh
Priority to US18/424,339 priority patent/US20240171304A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0015—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes

Definitions

  • the present application relates to the field of communication technologies, and in particular to a decoding method and device.
  • the Ethernet physical layer includes a physical coding sublayer (PCS), a physical medium attachment (PMA) sublayer, and a physical media dependent (PMD) sublayer.
  • PCS is located between the coordination sublayer (reconciliation sublayer, RS) and the PMA sublayer of the media access control (media access control, MAC) layer.
  • RS coordination sublayer
  • MAC media access control
  • PCS is used to map an Ethernet MAC flow to the encoding and physical layer signaling system.
  • the current 10G-400G standard defined by the IEEE802.3 protocol and the 800G private standard all stipulate that the PCS code adopts 64b/66b code.
  • MII media independence interface
  • 64b/66b encoding is used to encode and map 8 8-bit (8-bit) data and 1 8-bit control signal transmitted by MII to generate block payload (block Payload), sync header (sync header) and block type field (block type field), and generate a 66-bit block (block) for parallel output according to the specified format.
  • the IEEE protocol stipulates that the state jump when 64b/66b decodes a 66-bit block (block) needs to refer to the attributes of the next 66-bit block (block), so all decoding operations need to be completed within one clock cycle (that is, a single shot). Under low bus width and advanced technology, it is usually possible to complete the state transition of all 66-bit blocks within one clock cycle, but under large bus width or low technology, if it is completed within one clock cycle All state transitions of 66-bit blocks (blocks) have a large implementation timing risk.
  • Embodiments of the present application provide a decoding method and device, which are used to be compatible with requirements of different bus bit widths or different processes on the timing of physical coding sublayer decoding, thereby improving system compatibility and flexibility.
  • a decoder in a first aspect, includes:
  • a type detection module configured to detect the types of N code blocks to be decoded, the N code blocks to be decoded are arranged in order, and N is an integer greater than or equal to 1;
  • a decoding and prediction module configured to decode the N code blocks to be decoded according to the types of the N code blocks to be decoded, to obtain decoding results of the N code blocks to be decoded; and, to obtain the N code blocks to be decoded A predictive decoding method for at least one code block in the code blocks to be decoded;
  • a state judgment module configured to select a decoding method from the predictive decoding methods of each code block in the at least one code block
  • An output processing module configured to update the decoding result according to the decoding method, obtain and output the media-independent interface information corresponding to the N code blocks to be decoded;
  • the decoder also includes a delay device for delaying the received data for at least one clock cycle before outputting, wherein:
  • the type detection module sends the types of the N code blocks to be decoded to the decoding and prediction module through the delay device; or, the decoding and prediction module sends the predictive decoding method through the delay device to the state judgment module, and send the decoding results of the N code blocks to be decoded to the output processing module; or, the state judgment module sends the decoding method to the output through the delay device processing module.
  • the above-mentioned decoder can be applied to physical layer decoding, for example, it can be used for PCS 64b/66b decoding.
  • the delay device is set in the decoder so that the data is delayed by at least one clock cycle to output, and the splitting of the clock cycle is realized, so that the operation that needs to be performed in one clock cycle is split into two or two It can be executed in more than one clock cycle, which can be compatible with the timing requirements of different bus bit widths or different processes for the decoding of the physical coding sublayer, thereby improving system flexibility.
  • the state judgment module is specifically configured to: according to the type of the first code block to be decoded and the type of the next code block of the first code block to be decoded, from the first Select one of the predictive decoding modes of the code block to be decoded, wherein the first code block to be decoded is any code block in the at least one code block.
  • a decoding method corresponds to a state in the FSM, and in a given FSM state, there may be multiple FSM state jumps according to different jump conditions, and the jump conditions are based on the state to be decoded
  • the type of the code block (including the type of the input code block to be decoded in the FSM state, further including the type of the next code block of the code block to be decoded).
  • the first code block to be decoded in a given FSM state (that is, the decoding mode of the previous code block to be decoded of the first code block to be decoded), according to the type and The type of the next code block of the first code block to be decoded can determine the jump condition under the FSM state, so it can be determined that the only FSM state to jump to (that is to say from the first code block to be decoded) Select one of the multiple predictive decoding modes of the block), so as to jump to the FSM state to decode the first decoding code block.
  • the output processing module is specifically configured to: if the decoding method used by the decoding and prediction module for the first code block to be decoded is the same as that used by the state judgment module from the first code block to be decoded The decoding mode selected in the predictive decoding mode of the decoded code block is different, then the decoding of the first code block to be decoded is performed according to the decoding mode selected by the state judgment module from the predictive decoding mode of the first code block to be decoded The results are updated; wherein, the first code block to be decoded is any code block in the at least one code block.
  • the output processing module is specifically configured to: if the decoding method selected from the predictive decoding methods of the first code block to be decoded is the decoding method used in an error state, the A decoding result of a code block to be decoded is updated to an error code; wherein, the first code block to be decoded is any code block in the at least one code block.
  • the output processing module is specifically configured to: if the decoding mode selected from the predicted code block mode of the first code block to be decoded is the decoding mode used in the low power consumption state, the The decoding result of the first code block to be decoded is updated as a low power consumption control code; wherein, the first code block to be decoded is any code block in the at least one code block.
  • the output processing module corrects the decoding result obtained by the early decoding according to the state judgment result output by the state judgment module, so as to ensure the correctness of the output decoding result.
  • the type detection module includes N type detection submodules, and the N type detection submodules correspond to the N code blocks to be decoded one by one;
  • the decoding and prediction module includes N decoding sub-modules and N prediction sub-modules, the N decoding sub-modules correspond to the N code blocks to be decoded one-to-one, and the N prediction sub-modules correspond to the N code blocks to be decoded one-to-one Correspondence;
  • the output processing module includes N output processing sub-modules, and the N output processing sub-modules are in one-to-one correspondence with the N code blocks to be decoded.
  • the N type detection sub-modules run in parallel
  • the N decoding sub-modules run in parallel
  • the N prediction sub-modules run in parallel
  • the N output processing modules run in parallel.
  • N type detection sub-modules run in parallel
  • N decoding sub-modules run in parallel
  • N prediction sub-modules run in parallel
  • N output processing modules run in parallel
  • the code block to be decoded is a 66-bit block descrambled by the physical coding sublayer PCS, the 66-bit block includes a 2-bit synchronization header and a 64-bit payload, and the 64-bit effective
  • the payload includes 8-bit block type information and 56-bit data;
  • the media-independent interface information includes 64-bit XGMII/XXVGMII interface data and 8-bit XGMII/XXVGMII interface control information.
  • a decoding method comprising:
  • N is an integer greater than or equal to 1
  • decoding the N code blocks to be decoded according to the types of the N code blocks to be decoded, to obtain the N code blocks to be decoded The decoding result of the block, and obtain the predictive decoding mode of at least one code block in the N code blocks to be decoded; select a decoding mode from the predictive decoding mode of each code block in the at least one code block; according to The decoding method selected in the decoding method updates the decoding result, obtains and outputs the media-independent interface information corresponding to the N code blocks to be decoded; wherein, the method further includes at least one of the following operations: The types of the N decoded code blocks are delayed for at least one clock cycle and output; the predictive decoding method and the decoding results of the N code blocks to be decoded are delayed for at least one clock cycle and output; the at least one code block is output The decoding mode selected in the predictive decoding mode of each code block in is
  • the obtaining the predictive decoding method of at least one of the N code blocks to be decoded includes: according to the type of the first code block to be decoded and the first code block to be decoded The type of the next code block, select a decoding method from the predictive decoding method of the first code block to be decoded, wherein the first code block to be decoded is any code in the at least one code block piece.
  • the updating the decoding result according to the decoding method selected from the prediction decoding method of each code block in the at least one code block includes: if the decoding and prediction module is The decoding method used by the first code block to be decoded is different from the decoding method selected by the state judgment module from the predictive decoding methods of the first code block to be decoded, then according to the state judgment module from the first code block to be decoded
  • the decoding method selected in the predictive decoding method of decoding the code block updates the decoding result of the first code block to be decoded; wherein, the first code block to be decoded is any code block in the at least one code block .
  • the updating of the decoding result by selecting a decoding method from the predictive decoding methods of each code block in the partial code blocks includes: if the first code block to be decoded If the decoding method selected in the predictive decoding method is the decoding method used in the error state, the decoding result of the first code block to be decoded is updated to an error code; wherein, the first code block to be decoded is the at least Any code block in a code block.
  • the updating of the decoding result by selecting a decoding method from the predictive decoding methods of each code block in the partial code blocks includes: if the first code block to be decoded The decoding mode selected in the predicted code block mode is the decoding mode used in the low power consumption state, then update the decoding result of the first code block to be decoded to a low power consumption control code; wherein, the first code block to be decoded The code block is any code block in the at least one code block.
  • the code block to be decoded is a 66-bit block descrambled by the physical coding sublayer PCS, the 66-bit block includes a 2-bit synchronization header and a 64-bit payload, and the 64-bit effective
  • the payload includes 8-bit block type information and 56-bit data;
  • the media-independent interface information includes 64-bit XGMII/XXVGMII interface data and 8-bit XGMII/XXVGMII interface control information.
  • an electronic device in a third aspect, includes: one or more processors; one or more memories; wherein, one or more computer programs are stored in the one or more memories, and the one or more The or multiple computer programs include instructions, which, when executed by the one or more processors, cause the electronic device to perform the method as described in any one of the above second aspects.
  • a computer-readable storage medium includes a computer program, and when the computer program runs on an electronic device, the computer executes the computer program described in any one of the above-mentioned second aspects. Methods.
  • a chip in a fifth aspect, includes: one or more processors; one or more memories; wherein, one or more computer programs are stored in the one or more memories, and the one or more A plurality of computer programs comprising instructions which, when executed by the one or more processors, cause the chip to perform the method as described in any one of the above second aspects.
  • a computer program product is provided.
  • the computer program product When the computer program product is invoked by a computer, the computer executes the method described in any one of the above-mentioned second aspects.
  • FIG. 1 is a schematic diagram of a communication system according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of an open system interconnection model according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a network device according to an embodiment of the present application.
  • Fig. 4 is the schematic diagram of the PCS 64b/66b encoding and decoding in the embodiment of the present application;
  • FIG. 5 is a schematic diagram of the 66b coding block in the embodiment of the present application.
  • Figure 6 is the 64b/66b encoding table used by XGMII/XXVGMII of 10G/25GBASE-R in the embodiment of the present application;
  • FIG. 7 is a 64b/66b encoding state diagram in the embodiment of the present application.
  • FIG. 8 is a schematic diagram of a decoding process of a traditional 64b/66b block
  • FIG. 9 is a schematic diagram of a decoding principle applied to a physical coding sublayer in an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a 64b/66b decoder provided in an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a decoder suitable for 64b/66b encoding provided by the embodiment of the present application.
  • FIG. 12 is a schematic diagram of a decoding process provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the communication system 100 includes a network device (e.g., a switch or router) 110(a) coupled to a plurality of network devices 110(b) and 110(c) via respective data links (or physical channels) 120 ).
  • Network devices 110(b) and 110(c) may exchange data with switch/router 110(a) over respective data links 120.
  • Network devices 110(b) and 110(c) may be any suitable network-capable devices including, for example, computers, switches, routers, hubs, gateways, access points, and the like.
  • the network devices 110(b) and 110(c) may include any electronic device capable of connecting to a wired or wireless network, including, for example, a mobile phone, a personal digital assistant (PDA), a set-top box, or a game console.
  • PDA personal digital assistant
  • router/switch 110(a), network devices 110(b) and 110(c), and data link 120 are merely exemplary components of a network, as the network may further include any number of suitable devices to form a relatively Larger networks including, for example, local area networks (LANs), wide area networks (WANs), wireless LANs (WLANs), and/or can be connected to the Internet.
  • LANs local area networks
  • WANs wide area networks
  • WLANs wireless LANs
  • Data link 120 may be any suitable physical medium channel including, for example, coaxial cable, fiber optics, and/or unshielded/shielded twisted-pair wire.
  • Network devices 110(a)-110(c) may communicate with each other using Ethernet technology as described in the IEEE 802.3 family of standards.
  • FIG. 2 there is a block diagram of an open system interconnection (OSI) model 200 ( a , b ) of network devices 110 ( a ) and 110 ( b ) or 110 ( c ) in FIG. 1 .
  • the OSI model 200 (a, b) is divided into 7 logical layers, including from top to bottom: application layer 211 (a, b), presentation layer 212 (a, b), session layer 213 (a, b), transmission Layer 214(a,b), Network Layer 215(a,b), Data Link Layer 216(a,b), Physical Layer 217(a,b).
  • OSI model 200(a,b) may be used to represent network devices 110(a) and 110(b)/110(c), but it should be noted that other suitable models may be used to represent Ethernet network equipment.
  • the physical layer 217(a,b) provides electrical and physical specifications for interactions between the network device 110 and the data link 120, including things like pin layout and signal voltages.
  • Data link layer 216(a,b) provides functional and/or procedural provisions for data transfer between network devices 110(a) and 110(b)/110(c), such as addressing and Channel access control mechanism.
  • the data link layer 216(a, b) has two sublayers, which include a logical link control (logical link control, LLC) layer and a MAC layer from top to bottom.
  • logical link control, LLC logical link control
  • MAC layer MAC layer from top to bottom.
  • the data link layer 216(a,b) is also referred to as the MAC layer in the subsequent description herein.
  • MII Media Independent Interface
  • XGMII is defined as a 10Gbit interface from the MAC to the physical layer
  • XXVGMII is defined as a 25Gbit interface from the MAC to the physical layer
  • the network device 300 may be one of the network devices 110 ( a ), 110 ( b ), and 110 ( c ) in FIGS. 1 and 2 .
  • Network device 300 includes processor 310 , memory 320 and Ethernet transceiver 330 coupled to one or more physical channels 120 .
  • Ethernet transceiver 330 is shown in FIG. 3 as being included in PHY 350, for other embodiments, transceiver 330 may be a separate device or an integrated circuit.
  • Memory 320 may be any suitable memory element or device including, for example, EEPROM or flash memory.
  • Processor 310 may be any suitable processor capable of executing the scripts or instructions of one or more software programs stored, for example, in memory 320 .
  • the network device 300 may also include what is known as a cache memory that stores frequently used instructions and/or data.
  • the network device 300 includes a physical layer device (PHY) 350 and a MAC layer device (or MAC device) 340 .
  • PHY 350 and MAC device 340 include MII 360-1 and 360-2, respectively, for sending signals between the two devices via signal path 370.
  • the MAC device 340 may be any device or integrated circuit that implements MAC layer functions, and may be an independent device or integrated into the network device 300 .
  • the PHY 350 may be any device or integrated circuit that implements the functions of the physical layer, and may be an independent device or may be integrated into the network device 300 .
  • both PHY 350 and MAC device 340 may be implemented in an integrated circuit mounted on a circuit board, and signal path 370 may be implemented as a trace on the circuit board.
  • processor 310 processes the data according to the top layers of the OSI model and then sends PHY 350 sends data.
  • the PHY 350 encodes the data from the MII (such as using 64b/66b encoding), scrambles and other operations, and then sends the data to the physical channel 120 via the transceiver 330 .
  • the transceiver 330 of the network device 300 receives the data from the physical channel 120 through the network, the PHY 350 descrambles and decodes the data and sends it to the MAC device 340 via the MII.
  • FIG. 4 it is a schematic diagram of a 64b/66b codec adopted in the embodiment of the present application.
  • the MAC layer sends data (TXD ⁇ 31:0>) and control signals (TDC ⁇ 3:0>) to PCS via XGMII/XXVGMII, further A clock signal (TX_CLK) can also be sent, wherein the clock signal is not required to be sent, and it is not necessary to send a clock signal to the PCS when the MAC layer and the PCS use the same clock signal.
  • TX_CLK clock signal
  • PCS forms two data (TXD ⁇ 31:0>) into eight 8-bit width data (TXD ⁇ 63:0>), and two control signals (TDC ⁇ 3:0>) into one 8-bit width Control signal (TXC ⁇ 7:0>), and 64b/66b encoding of 64-bit data (TXD ⁇ 63:0>) and 8-bit control signal (TXC ⁇ 7:0>) to obtain a 66-bit block (block ), and then perform operations such as scrambling (scramble) and bit width conversion (gear box) on the 66-bit block, and then send it to the downstream module of PCS transmission (PCS trasmit) for encapsulation and other operations.
  • PCS trasmit PCS transmission
  • PCS trasmit can be PMA, Reed-Solomon forward error correction (Reed-Solomon forward error correction, RS-FEC) module or WIS (wan interface sunlayer) sublayer, depending on the application Scenes.
  • RS-FEC Reed-Solomon forward error correction
  • WIS wan interface sunlayer
  • PCS receives data from PMA or RS-FEC module or WIS sublayer, and performs error checking and synchronization header detection on the received data, if the received data conforms to the basic coding rules ( basic encoding rule, BER), the PCS descrambles the received data, decodes 64b/66b, and finally generates 64-bit received data (RXD ⁇ 63:0>) and 8-bit received control signal (RXC ⁇ 7:0>), and split into two data (RXD ⁇ 31:0>) and two control signals (RXD ⁇ 3:0>), sent to the MAC layer via MII.
  • basic coding rules basic encoding rule, BER
  • FIG. 5 it is a schematic diagram of an encoded 66-bit block (block) in the embodiment of the present application.
  • Block is the basic processing unit of PCS and consists of 66 bits.
  • the PCS maps MII (including, for example, XGMII/XXVGMII) structure data (TXD ⁇ 63:0> and TXC ⁇ 7:0>) into a 66-bit block (tx_coded ⁇ 65:0>) based on the 64b/66b coding scheme.
  • MII including, for example, XGMII/XXVGMII
  • the synchronization header (2 bits) of the 66-bit block (tx_coded ⁇ 65:0>) is used to detect the boundary of the block during the PCS synchronization process on the receiving side, so that the receiving side can achieve block alignment on the PHY bit stream.
  • Each rectangle in Fig. 5 represents one bit of data.
  • the bit data with a smaller index value is first transmitted on the physical link.
  • 64b/66b encoding ensures that there is enough randomness in the physical layer (PHY) bitstream to allow proper clock recovery in the receive direction. 64b/66b encoding also preserves the possibility of detecting any single or multiple bit errors that may occur during transmission and reception of information.
  • PHY physical layer
  • 10G/25G PCS supports the control words defined in XGMII/XXVGMII (the control words defined in XGMII and XXVGMII are the same).
  • the representation of the control word is the control code.
  • PCS uses TXC on XGMII/XXVGMII to distinguish whether the corresponding byte is a control code or a data byte. If TXC is set, the corresponding 8-bit data is the control code. For example, if TXC ⁇ 0> is set, the first byte ⁇ 7:0> in TXD ⁇ 63:0> is the control code.
  • the PCS defines a symbol for each value of the control code, as shown in Table 1 for example.
  • the /LI/ character is transmitted when the PCS receives a Low Power (LPI) control character (0x06) from the MII.
  • LPI Low Power
  • the LPI control character /LI/ is sent continuously instead of the control character /I/.
  • the start control character /S/ indicates the start of a packet. /S/ is only valid for the first or fifth byte in MII TXD ⁇ 63:0>. Receipt of /S/ on any other byte of MII TXD ⁇ 63:0> indicates an error.
  • /T/ The termination control character /T/ indicates the end of the packet. Due to the different packet lengths, /T/ can appear on any byte in MII TXD ⁇ 63:0>.
  • Ordered sets are used to extend the ability to send control and status information over the link, such as remote fault and local fault status.
  • a sequence ordered_set consists of a special control character /Q/ and three data bytes.
  • Ordered sets (ordered_set) always start from the first or fifth byte of the MII (including, for example, XGMII/XXVGMII).
  • a signal ordered_set consists of a special control character /Fsig/ followed by three data bytes.
  • the control symbol /Q/ is equal to the control symbol /O/. Receipt of /Q/ on any other byte of TXD other than specified above indicates an error.
  • the error control character /E/ is generated whenever /E/ is detected from the MII. /E/ is also generated when the PCS detects an error from the MII. /E/ Allows PCS to send detected errors.
  • the 64b/66b encoder receives data TXD ⁇ 63:0> and control signal TXC ⁇ 7:0> from XGMII/XXVGMII, and generates a 66-bit block (block) by looking up the coding table.
  • FIG. 6 shows a 64b/66b encoding table used by XGMII/XXVGMII of 10GBASE-R/25GBASE-R.
  • the first column represents the transmission data from XGMII/XXVGMII.
  • the second column (tx_coded) is a 66-bit block, and its encoded result consists of a synchronization header (SYNC) column and a block payload (block payload) column.
  • the first two bits of the 66-bit block are the synchronization header (SYNC).
  • the value of the sync header is displayed as a binary value.
  • the value of the sync header is "01" and "10".
  • "01” means that the following 64 bits are all data
  • "10” means that the following 64 bits are control information or a mixture of data and control information.
  • the 8 bits next to the sync header are the block type field, and the next 56 bits are control information or data or a mixture of the two.
  • a block payload in a 66-bit block, data codes are marked as D 0 to D 7 , and one data code is 8 bits.
  • the control characters /I/, /LI/ and /E/ are labeled C 0 to C 7 .
  • the control characters /Q/ or /Fsig/ are marked O 0 or O 4 because they are valid only on the first or fifth octet of an XGMII/XXVGMII transmission.
  • control character /S/ is marked as S 0 or S 4 , since two transmit TXD ⁇ 31:0>s are used to create one TXD ⁇ 63:0>, the value of the block type field implicitly encodes /S / as the first or fifth character of a block.
  • the control characters /T/ are marked as T 0 to T 7 , and the position of /T/ in the block is implicitly encoded in the block type field, when a block containing /T/ is followed by a control block that does not contain /T/ and /E/ , the packet effectively ends.
  • the subscript in the label in the above encoding table indicates the position of the character in the 8 bytes in the XGMII/XXVGMII transmission.
  • the leftmost bit (bit) is transmitted first.
  • the contents of the block type field, data octets, and control codes are shown as hexadecimal values.
  • PCS 64b/66b decoding is the inverse of encoding.
  • the definitions of data and control characters (or control codes) are the same as the encoding, and you can refer to the encoding scheme shown in the PCS transmission section.
  • PCS can perform 64b/66b decoding according to 64b/66b decoding finite state machine (finite state machine, FSM) and encoding tables (such as Table 1 and Figure 6) to recover the original data bytes from the descrambled input block stream .
  • FSM finite state machine
  • encoding tables such as Table 1 and Figure 6
  • the 64b/66b decoding state machine or decoding state diagram is used to define the rules followed by the 64b/66b encoding and decoding, and according to the rules, Ethernet data packets that meet the format requirements can be output.
  • FIG. 7 shows a 64b/66b decoding state diagram in the embodiment of the present application.
  • the descrambled vector rx_coded ⁇ 65:0> is demarcated successfully, or the vector rx_coded ⁇ 65:0> is not a high bit error, or is currently in reset or test mode, then enter the RX_INIT state (also known as the initial state). After entering the RX_INIT state, initialize the 72-bit vector rx_raw ⁇ 71:0> to be transmitted to XGMII/XXVGMII, so that the vector contains two local fault ordered sets ordered_set.
  • the input vector rx_coded ⁇ 65:0> belongs to the S type, it indicates that the vector contains the start control character /S/, then transfer to the RX_D state (also called the data state);
  • the input vector rx_coded ⁇ 65:0> belongs to the C type, it indicates that the vector is a control code block that does not contain the start control character /S/, then transfer to the RX_C (also called the control state) state;
  • the input vector rx_coded ⁇ 65:0> belongs to one of the E, D, T, LI types, it will enter the RX_E state (also called the error state).
  • the vector rx_coded ⁇ 65:0> may belong to one of the following types:
  • Type C The value of the synchronization header is binary 10, and one of the following conditions is met:
  • the value of the block type field is 0x1E, including 8 valid control characters except /E/; if the EEE or LPI encoding function is supported, 0 or 4 of them are /LI/;
  • the value of the block type field is 0x2D or 0x4B, including valid O codes and 4 valid control characters;
  • the value of the block type field is 0x55, which contains 2 valid O codes.
  • Type LI For the EEE or LPI encoding function, support the LI type, where the value of the synchronization header in the vector is binary 10, the value of the block type field is 0x1E, and contains 8 control characters 0x06(/LI/) .
  • Type S the value of the synchronization header is binary 10, and one of the following conditions is met:
  • the value of the block type field is 0x33, and contains 4 valid control characters
  • the block type field has a value of 0x66 and contains valid O codes
  • Type T The value of the synchronization header is binary 10, and one of the following conditions is met:
  • the value of the block type field is 0x87, 0x99, 0xAA, 0xB4, 0xCC, 0xD2, 0xE1 or 0xFF, and all control characters are valid.
  • Type D the value of the synchronization header included in the vector is 01 in binary.
  • a valid control character was specified in the transport section. If the block type is E, the block is an invalid block. An apparently invalid block satisfies at least one of the following properties:
  • the value of the sync header is binary 00 or 11;
  • the value of the block type field is an invalid value (a value not included in the coding table);
  • the value of the block type field is 0x1E, and the 8 control characters are /E/.
  • the input vector rx_coded ⁇ 65:0> belongs to the D type, indicating that the vector is a data code block, then maintain the current state, decode the vector rx_coded ⁇ 65:0>, and update the vector rx_raw ⁇ 71:0> with the decoding result;
  • the input vector rx_coded ⁇ 65:0> is of T type and the next vector is of S, C or LI type, indicating that the current input vector contains the termination control character /T/, and the block type of the subsequent vector is correct, then transfer to the RX_T state ( can also be called the end state);
  • the input vector rx_coded ⁇ 65:0> is of T type and the next vector is of E, D or T type, indicating that the current input vector contains the termination control character /T/, and the block type of the subsequent vector is incorrect, then transfer to the RX_E state ;or, if the input vector rx_coded ⁇ 65:0> is of type E, C, S, or LI, go to RX_E state.
  • the input vector rx_coded ⁇ 65:0> belongs to the LI type, it is transferred to the RX_LI state (also called a low power consumption state);
  • the input vector rx_coded ⁇ 65:0> belongs to the C type, keep the current state, decode the current vector rx_coded ⁇ 65:0>, and update the vector rx_raw ⁇ 71:0> with the decoding result;
  • the decoding process may be stopped immediately, and two local fault ordered sets are continuously transmitted on the XGMII/XXVGMII of the Ethernet PHY.
  • the decoding process of the N 66-bit blocks has a serial structure, and the decoding process of one 66-bit block may include block type prediction, decoding according to the block type, and output processing of the decoding result.
  • the FSM state jump judgment for N 66-bit blocks (block) in one clock cycle and the timing risk of decoding the N 66-bit blocks are relatively low, but in large If the bus bit width is low or in a low process, there will be a greater risk of implementation timing.
  • the embodiment of the present application provides a decoding method and a device capable of implementing the method.
  • the decoding operation of N blocks in one clock cycle is divided into two or more clock cycles Further, the decoding operations of the N blocks are processed in parallel within at least one clock cycle, so that timing can be guaranteed, compatibility with different processes or different bus bit widths, and system compatibility and flexibility are improved.
  • the embodiment of the present application can be applied to the implementation of 64b/66b decoding, and can also be applied to the implementation of other types of decoding.
  • the embodiment of the present application may be implemented in a physical layer (PHY), for example, may be implemented in a PCS sublayer.
  • PHY physical layer
  • FIG. 9 it is a schematic diagram of the principle of decoding implementation provided by the embodiment of the present application.
  • the principle of decoding implementation can be applied to the physical layer, for example, it can be applied to the PCS 64b/66b decoding process.
  • a code block to be decoded (for example, including a 66-bit block), its decoding process may include operations such as type detection, decoding, state prediction, state judgment, and output processing.
  • the type detection operation includes detecting the type of the code block to be decoded
  • the decoding operation includes decoding the code block to be decoded according to the type of the code block to be decoded
  • the state prediction operation includes the next code block to be decoded for the current code block to be decoded Block, predict all possible decoding methods (referred to as predictive decoding methods in the embodiment of this application)
  • the state judgment operation includes selecting a decoding method from the predictive decoding methods for the code block to be decoded
  • the output processing operation includes selecting a decoding method for the code block to be decoded
  • the decoding mode selected in the predictive decoding mode of the code block updates the decoding result of the code block, and outputs the media-independent interface information (for example, including media-independent interface data and media-independent interface control information) corresponding to the code block to be decoded.
  • media-independent interface information for example, including media-independent interface data and media-independent interface control information
  • a delay device may be set in the decoder, which is used to delay the received data for at least one clock cycle before outputting it.
  • the result of the type detection can be output by delaying one or more clock cycles through a delay device.
  • the decoding result may be delayed by one or more clock cycles through the delay device, and the output predicted by the decoding method may be delayed by one or more clock cycles through the delay device.
  • the predictive decoding mode may delay output by one or more clock cycles through a delay device.
  • the delay device may be a register.
  • the register may be, for example, a D flip-flop, and when the D flip-flop is triggered by a trigger signal (such as a clock signal), it outputs the stored data.
  • the "register” mentioned in the embodiment of this application can be a register or a register group composed of at least two registers, which mainly depends on the data bandwidth and register bit width. For example, if the output data is 8 bits, Then one 8-bit register or two 4-bit registers can be set.
  • a delay device can be set at at least one of the above-mentioned first position, second position, and third position, so that at the position where the delay device is set, the output of the previous stage operation is delayed by at least Sent to the next stage operation after one clock cycle.
  • the time delay can be realized by setting a delay device at at least one of the first position, the second position, and the third position.
  • a register is inserted at the first position (the box containing a triangle in FIG. 9 represents the register), so that the output data of the type detection operation is delayed by at least one clock cycle through the register, and then output to the decoding operation and the state prediction operation, As input data for decoding operations and state prediction operations.
  • the embodiment of the present application inserts a delay between adjacent operations, so that the data is delayed by at least one clock cycle, and the splitting of the clock cycle is realized, thereby splitting the operations that need to be executed within one clock cycle It can be executed within two or more clock cycles, and thus can be compatible with the requirements of different bus bit widths or different processes for the decoding and implementation timing of the physical coding sublayer, thereby improving system flexibility.
  • the decoding method provided in the embodiment of the present application can be applied to the PCS 64b/66b decoding process, and can also be applied to a similar decoding process implemented on the physical sub-layer.
  • FIG. 10 shows the structure of a decoder provided by the embodiment of the present application.
  • FIG. 10 it is a schematic structural diagram of a decoder provided by an embodiment of the present application.
  • the decoder can be realized by hardware, such as by a field programmable gate array (field programmable gate array, FPGA) or other integrated circuits.
  • the decoder can also be realized by software, and can also be realized by a combination of software and hardware. The application embodiment does not limit this.
  • a decoder 1000 provided by the embodiment of the present application may include a type detection module 1010 , a decoding and prediction module 1020 , a state judgment module 1030 and an output processing module 1040 .
  • the decoding and prediction module 1020 is configured to decode the N code blocks to be decoded according to the types of the N code blocks to be decoded, to obtain decoding results of the N code blocks to be decoded; and, to obtain the N code blocks to be decoded
  • the predictive decoding mode of at least one code block in is configured to select a decoding method from the predictive decoding methods of each code block in the at least one code block.
  • the output processing module 1040 is configured to update the decoding result according to the decoding method, obtain and output the media-independent interface information corresponding to the N code blocks to be decoded.
  • the decoding and prediction module 1020 uses the decoding mode and state judgment module 1030 for the first code block to be decoded from the first The decoding method selected in the predictive decoding method of the code block to be decoded is different, then the output processing module 1040 decodes the first code block to be decoded according to the decoding method selected from the predictive decoding method of the first code block to be decoded by the state judgment module 1030 The results are updated.
  • the decoding result of the first code block to be decoded is updated to is the error code.
  • the decoding mode selected by the output processing module 1040 from the predicted code block modes of the first code block to be decoded is the decoding mode used in the low power consumption state, then the decoding mode of the first code block to be decoded The result is updated as a low power control code.
  • the decoder 1000 also includes a delay device (a block containing a triangle in FIG. 10 represents a delay device), which is used to delay the received data for at least one clock cycle before outputting it.
  • the type detection module 1010 may send the types of the N code blocks to be decoded (ie, type detection results) to the decoding and prediction module 1020 through the delay device.
  • the decoding and prediction module 1020 may send the prediction decoding method (ie prediction result) to the state decision module 1030 through a delay device, and send the decoding results of the N code blocks to be decoded to the output processing module 1040 .
  • the state judgment module 1030 may send a decoding method (ie, the judgment result) selected from the predictive decoding methods to the output processing module 1040 through a delay device.
  • the type detection module 1010 can output the type detection result to the decoding and prediction module 1020 through the first-level register, and the decoding and prediction module 1020 can output the prediction result to the state judgment module 1030 through the first-level register, and through the two-level register
  • the decoding result is output to the output processing module 1040, and the state judgment module 1030 outputs the judgment result to the processing module 1040 through the first-level register.
  • the predictive decoding method of a code block to be decoded can be understood as: based on a decoding finite state machine (FSM), in an FSM state, the input code block to be decoded may jump to an FSM state. There may be one or more FSM states that may be jumped to, and each FSM state corresponds to a decoding method. In this way, these possible jumping FSM states correspond to the predictive decoding mode of the code block to be decoded.
  • FSM decoding finite state machine
  • the decoding FSM of 64b/66b in the decoding FSM of 64b/66b, in the RX_D state, for the currently input code block to be decoded, according to the three jump conditions in the RX_D state, it may jump to one of the three FSM states state, the code block to be decoded is decoded, and the three decoding modes corresponding to the three FSM states are the predictive decoding modes of the code block to be decoded.
  • the current code block to be decoded is code block i
  • the decoding FSM is currently in state 1. If it can only jump from state 1 to state 2, then for code block i+1 (that is, code block i For the next code block of i+1), the decoding method that can be used is unique (that is, the decoding method corresponding to state 2), so it is not necessary to predict the decoding method of the code block i+1 to be decoded, of course, it is also possible to use
  • the decoding mode corresponding to state 2 is determined as the predictive decoding mode of the decoded code block i+1.
  • the state judgment module 1030 may be specifically configured to: according to the type of the first code block to be decoded (the first code block to be decoded is any code block in the above at least one code block) and the first code block to be decoded The type of the next code block of the block, and select a decoding method from the predictive decoding methods of the first code block to be decoded.
  • a decoding method corresponds to a state in the FSM, and in a given FSM state, there may be multiple FSM state jump situations according to different jump conditions, and the jump conditions depend on the type of the code block to be decoded ( Including the type of the code block to be decoded input in the FSM state, further including the type of the next code block of the code block to be decoded).
  • the first code block to be decoded in a given FSM state (that is, the decoding mode of the previous code block to be decoded of the first code block to be decoded), according to the type and The type of the next code block of the first code block to be decoded can determine the jump condition under the FSM state, so it can be determined that the only FSM state to jump to (that is, from the first code block to be decoded) Select one of the multiple predictive decoding modes), so as to jump to the FSM state to decode the first decoding code block.
  • the decoding and prediction module 1020 can decode N code blocks in advance, and when decoding a code block, it depends on the type of the code block, which may lead to decoding errors (because in some cases, When decoding a code block, not only the type of the code block, but also the type of the next code block is required to determine which decoding method to use), so the decoding result may be inaccurate (that is, the decoding method used may be Inaccurate).
  • the decoding method of the code block to be decoded is predicted by the decoding and prediction module 1020, and then a certain decoding method is selected through the state decision module 1030, so that when the decoding method used in the decoding and prediction module 1020 of the code block to be decoded is the same as
  • the output processing module 1040 updates the decoding result of the code block to be decoded according to the decoding method determined in the state decision module 1030, so as to ensure the accuracy of decoding.
  • the decoder provided by the above-mentioned embodiments can delay the output data of at least one module in the type detection module 1010, the decoding and prediction module 1020, and the state judgment module 1030 to the next-level module through a delay device (such as a register), so that The data is delayed by at least one clock cycle to realize the splitting of the clock cycle, so that the decoding operation that needs to be executed in one clock cycle is split into two or more clock cycles, which is compatible with different bus bit widths or Different technologies have requirements on the timing of physical coding sub-layer decoding to improve system flexibility.
  • a delay device such as a register
  • the type detection module 1010 includes N type detection sub-modules, and the N type detection sub-modules correspond to the N code blocks to be decoded one-to-one, that is, one type detection sub-module
  • the sub-module is used to decode a code block to be decoded
  • the decoding and prediction module 1020 includes N decoding and prediction sub-modules, and the N decoding and prediction sub-modules are in one-to-one correspondence with the N code blocks to be decoded, that is, a decoding and prediction module
  • the prediction sub-module is used to decode a code block to be decoded, and perform type prediction on the next code block to be decoded of the code block to be decoded
  • the output processing module 1040 includes N output processing sub-modules, and the N output processing sub-modules
  • the modules are in one-to-one correspondence with the N code blocks to be decoded, that is, one output processing sub-module is
  • the decoder 1000 includes N decodings, and each decoding is used to process a code block to be decoded.
  • Each decoding includes a type detection submodule, a decoding and prediction submodule, and an output processing submodule.
  • the N decodings can be Share a status judgment module 1030 .
  • the N type detection sub-modules run in parallel
  • the N decoding sub-modules run in parallel
  • the N prediction sub-modules run in parallel
  • the N output processing modules run in parallel
  • the decoding and prediction sub-module may include a decoding sub-module and a prediction sub-module to respectively implement a decoding operation and a type prediction operation.
  • FIG. 11 shows a decoder structure and input and output diagrams suitable for 64b/66b encoding.
  • the 2-bit sync header block0[1:0] and the 8-bit block type field block0[9:2] in the 66-bit block block0 after PCS descrambling are input to the type detection sub-module 0 in the type detection module 1010 . If the value of the synchronization header is "01", the type detection sub-module 0 determines that block0 is a data code block, and if the value of the synchronization header is "10", the type detection sub-module 0 determines that block0 is a control code block, otherwise, it determines that block0 is encoded mistake.
  • block0 is a control code block
  • the block type of block0 can be determined by looking up the 64b/66b encoding table (for example, as shown in Figure 6), and the block type of block0 can indicate the format of block0.
  • the block type of block0 may be one of types C, LI, S, T, D, and E.
  • the type information of block0 detected by type detection sub-module 0 is sent to decoding sub-module 0 and prediction sub-module 0 after being delayed by one clock cycle by the register.
  • the type detection methods of other code blocks to be decoded are similar.
  • Decoding sub-module 0 obtains the type detection result of block0 output by type detection sub-module 0 and the 56-bit data block[65:10] in block0, by checking the 64b/66b encoding table (for example, as shown in Figure 6), the 56-bit data block [65:10] Decoded into 64-bit data rx_coded0 of the corresponding format.
  • the decoding result (that is, the 64-bit data rx_coded0) is sent to the output processing sub-module 0 after being delayed by two clock cycles through two-stage registers.
  • the decoding methods of other code blocks to be decoded are similar.
  • the decoding submodule 0 may also generate 8-bit control information according to the block type of block0, and the value of each bit in the control information is used to indicate whether the corresponding 8-bit byte in rx_coded0 is data or a control code.
  • the decoding sub-module 0 can output the 64-bit data rx_coded0 and the generated 8-bit control information to the output processing sub-module 0 as a decoding result. Further, the decoding sub-module 0 may also send the indication information of the decoding mode adopted by block0 to the output processing sub-module 0.
  • the prediction sub-module 0 obtains the type detection result of block0 output by the type detection sub-module 0, according to the 64b/66b encoding and decoding rules (such as the 64b/66b decoding state diagram, as shown in Figure 7), according to the block type of block0 and the corresponding The FSM state (that is, the state the FSM state machine is in when decoding block0) predicts which FSM state or states it is possible to jump to to decode the next 66-bit block block1.
  • the 64b/66b encoding and decoding rules such as the 64b/66b decoding state diagram, as shown in Figure 7
  • the prediction result of the prediction sub-module 0 may include a block index (such as the index of block0 and/or block1) and indication information of all possible decoding modes (ie, FSM states) that may be used for decoding block1 obtained through prediction.
  • a block index such as the index of block0 and/or block1
  • indication information of all possible decoding modes ie, FSM states
  • the decoding mode prediction method of other code blocks to be decoded is similar.
  • the type of each code block in block0 ⁇ blockN-1 can be sent to the state judgment module 1030 by the type detection module 1010, or can be sent to the state judgment module 1030 by the corresponding prediction sub-module, for example, the prediction sub-module 0 can send The type of block0 is sent to the state judgment module 1030, and the prediction sub-module 1 can send the type of block1 to the state judgment module 1030, and so on.
  • the state decision module 1030 is used to select a decoding method from the predictive decoding methods of each code block based on the 64b/66b decoding state diagram (as shown in FIG. 7 ) according to the type of the code block, and obtain a judgment result.
  • the decision result is delayed by the register for one clock cycle and sent to the corresponding output processing sub-module.
  • the predictive decoding method of block1 received by the state decision module 1030 from the prediction sub-module 0 includes: the decoding method corresponding to RX_D, the decoding method corresponding to RX_T and the decoding method corresponding to RX_E, and the type of block1 received from the prediction sub-module 1 If it is type D, then according to the decoding state diagram shown in FIG.
  • the decision information output by the state decision module 1030 may include: indication information of the selected decoding mode, and may further include an index of a code block.
  • the output processing module 1040 After the output processing module 1040 receives the judgment result from the state judgment module 1030, if it judges that for a certain code block, the decoding method adopted by the corresponding decoding sub-module is different from the decoding method selected by the state judgment module 1030, then the The decoding method selected by the decision module 1030 updates the decoding result of the code block.
  • the output processing sub-module 1 does not need to The decoding result of block1 is updated; for another example, for block1, if the decoding mode selected by the state judgment module 1030 is the decoding mode corresponding to RX_E (that is, the decoding mode used in the error state), then due to the decoding mode and the decoding submodule 1
  • the output processing sub-module 1 updates the decoding result of block1 according to the decoding method corresponding to RX_E, that is, the 8 characters of XGMII/XXVGMII RXD ⁇ 63:0> corresponding to block1 Sections are all updated to the error control character /E/; for another example, for block5, if the decoding mode selected by the state judgment module 1030 is the
  • the output processing module 1040 generates corresponding 64-bit XGMII/XXVGMII interface data and 8-bit XGMII/XXVGMII interface control information according to the decoding results of N code blocks, and outputs them to the XGMII/XXVGMII interface.
  • the decoder 1000 provided in the embodiment of the present application can be applied to a time-division architecture, and can also be applied to a space-division architecture.
  • N code blocks to be decoded are input to the type detection module 1010 at the same clock cycle.
  • the type detection module 1010 detects the types of the N code blocks to be decoded at the same clock cycle, and the type detection results of the N code blocks to be decoded are input to the decoding and prediction module 1020 at the same clock cycle.
  • the decoding and prediction module 1020 decodes the N code blocks to be decoded and performs decoding mode prediction operations in the same clock cycle.
  • the predictive decoding modes and type detection results of the N code blocks to be decoded are input to the state decision module 1030 at the same clock cycle. Since the state judgment module 1030 can obtain the predictive decoding modes and type detection results of the N code blocks to be decoded in one clock cycle, it can select one decoding mode from the predictive decoding modes of the corresponding code blocks in one clock cycle.
  • FIG. 11 shows a decoder structure and input and output diagrams suitable for 64b/66b encoding.
  • the state decision module 1030 receives the types of N 66-bit blocks (block0-blockN-1) output by the N type detection sub-modules within one clock cycle, and receives the predictive decoding mode of block0-blockN-1.
  • the state judgment module 1030 selects one decoding type from the predictive decoding types of block0 to blockN-1 according to the output of N type detection sub-modules and the output of N prediction sub-modules within one clock cycle.
  • N code blocks to be decoded are sequentially input to the type detection module 1010 according to clock cycles.
  • the type detection module 1010 performs type detection on the received code blocks to be decoded, and the type detection results of the N code blocks to be decoded are sequentially input to the decoding and prediction module 1020 according to clock cycles.
  • the decoding and prediction module 1020 sequentially performs decoding operation and decoding mode prediction operation on the code block to be decoded.
  • the predictive decoding modes and type detection results of the N code blocks to be decoded are sequentially input to the state decision module 1030 according to clock cycles.
  • the state decision module 1030 can first buffer the received type prediction results and predictive decoding methods of the code blocks to be decoded , after obtaining the type detection results and predictive decoding modes of the N code blocks to be decoded, select a decoding mode from the predictive decoding modes of the corresponding code blocks.
  • Fig. 11 shows the decoder structure and input and output diagrams suitable for 64b/66b encoding.
  • the state judgment module 1030 sequentially receives the types of N 66-bit blocks (block0-blockN-1) output by N type detection sub-modules within clock cycle 0 to clock cycle N-1, and receives the output of N prediction sub-modules The predictive decoding method of each code block.
  • the state decision module 1030 caches the received type detection results and predictive decoding methods, and after obtaining the type prediction results and predictive decoding methods of N code blocks, selects one of the predictive decoding methods from block0 to blockN-1 respectively.
  • the delay device when the delay device is only provided at any two of the above-mentioned first position, second position and third position, or only at any one of the above-mentioned first position, second position and third position
  • the structure of the corresponding decoder can be derived by referring to the decoding principle shown in FIG. 9 and the decoder structure shown in FIG. 10 above, and will not be described separately in the embodiments of the present application.
  • any two positions of the above-mentioned first position, second position, and third position can be Set the delay device on the top or any position, and it will not affect the functions of the above modules.
  • FIG. 12 it is a schematic flowchart of a decoding method provided by an embodiment of the present application. This process can be realized by the above-mentioned decoder. Optionally, the above process is applicable to decoding 64b/66b encoded code blocks. As shown, the process may include the following steps:
  • S1200 Detect types of N code blocks to be decoded, where N is an integer greater than or equal to 1.
  • the operation of detecting the types of the N code blocks to be decoded is performed in parallel.
  • S1202 Decode the N code blocks to be decoded according to the types of the N code blocks to be decoded, to obtain the decoding results of the N code blocks to be decoded; and obtain at least one code block of the N code blocks to be decoded Predictive decoding method.
  • the operation of decoding the N code blocks to be decoded according to the types of the N code blocks to be decoded is performed in parallel; the operation of obtaining the predictive decoding mode of at least one code block among the N code blocks to be decoded is performed by Execute in parallel.
  • S1204 Select a decoding mode from the predictive decoding modes of each code block in the at least one code block.
  • the operation of S1200 can be completed within the same clock cycle, and the operation of S1202 can be completed within the same clock cycle, so that in S1204, the type of each code block and the predictive decoding can be obtained within the same clock cycle mode, so that the operation of S1204 can be completed within this clock cycle.
  • This approach can be applied to space-separated architectures.
  • the N code blocks to be decoded are sequentially detected according to the clock cycle, for example, the type detection is performed on block0 in the first clock cycle, and the type detection is performed on block1 in the second clock cycle, so that By analogy, correspondingly, the type detection results of each code block are sequentially output according to the clock cycle.
  • each code block is sequentially subjected to decoding operation and decoding mode prediction operation, and the decoding results and prediction results are sequentially output.
  • the received predictive decoding mode of each code block and the types of the N code blocks to be decoded can be cached first, and then after the types and predictive decoding modes of the N code blocks are obtained from the cache, according to the cached information from A decoding method is selected from the predictive decoding methods corresponding to the code block to be decoded.
  • This approach can be applied to time-division architectures.
  • S1206 Update the decoding result according to the decoding mode, and obtain and output the media-independent interface information corresponding to the N code blocks to be decoded.
  • any one of the N code blocks to be decoded is referred to as a first code block to be decoded.
  • the decoding method selected from the predictive decoding methods of the first code block to be decoded is the decoding method used in the error state, update the decoding result of the first code block to be decoded as an error or, if one of the decoding methods selected from the predicted code block methods of the first code block to be decoded is the decoding method used in the low power consumption state, update the decoding result of the first code block to be decoded to low power
  • the decoding method selected from the predictive decoding method of the first code block to be decoded is the same as the decoding method adopted for the first code block to be decoded in S1202, there is no need to update the code block of the first code block to be decoded Decode the result.
  • S1201 Delaying the types of the N decoded code blocks (that is, the processing results of S1200) for at least one clock cycle, and outputting after delaying for at least one clock cycle;
  • S1203 Delay the predictive decoding mode and the decoding results of the N code blocks to be decoded (that is, the processing results of S1202) after at least one clock cycle;
  • S1205 Select a decoding method (that is, the processing result of S1204) from the predictive decoding methods of each code block in at least one code block, and output it after delaying at least one clock cycle.
  • the above-mentioned decoding principle provided by the embodiment of the present application can also be applied to the encoding process, that is, the encoding operation of the physical encoding sublayer is divided into two or more clock cycles to be compatible with different bus bit widths or different processes for physical
  • the coding sublayer codes to realize timing requirements, thereby improving system compatibility and flexibility.
  • the embodiment of the present application also provides an electronic device, which may have a structure as shown in FIG. 13 , the electronic device has computing capabilities, and can implement the method flow provided in the embodiment of the present application.
  • the electronic device 1300 shown in FIG. 13 may include at least one processor 1302, and the at least one processor 1302 is used to be coupled with a memory, read and execute instructions in the memory to implement the method provided in the embodiment of the present application.
  • the electronic device may further include a communication interface 1301, configured to support the electronic device in receiving or sending signaling or data.
  • the communication interface 1301 in the electronic device can be used to realize interaction with other electronic devices.
  • the processor 1302 may be configured to enable the electronic device to execute the steps in the method shown in FIG. 12 .
  • the electronic device may also include a memory 1304, in which computer programs and instructions are stored, and the memory 1304 may be coupled with the processor 1302 and/or the communication interface 1301, for supporting the processor 1302 to call the computer program in the memory 1304 , instructions to implement the steps involved in the method provided by the embodiment of the present application; in addition, the memory 1304 can also be used to store the data involved in the method embodiment of the present application, for example, to store the data necessary to support the communication interface 1301 to realize interaction, The instruction, and/or, is used to store configuration information necessary for the electronic device to execute the method described in the embodiment of the present application.
  • the embodiment of the present application also provides a computer-readable storage medium on which some instructions are stored. When these instructions are called and executed by the computer, the computer can complete the above-mentioned method embodiment and method implementation. methods involved in any one possible design of the example.
  • the computer-readable storage medium is not limited, for example, it may be RAM (random-access memory, random access memory), ROM (read-only memory, read-only memory), etc.
  • the present application also provides a computer program product, which can complete the method involved in the method embodiment and any possible design of the above method embodiment when the computer program product is invoked and executed by a computer.
  • the present application also provides a chip, which may include a processor and an interface circuit, for completing the above method embodiment and any possible implementation of the method embodiment.
  • a chip which may include a processor and an interface circuit, for completing the above method embodiment and any possible implementation of the method embodiment.
  • “coupled” means that two parts are joined to each other directly or indirectly, this joint may be fixed or movable, and this joint may allow flowing fluids, electricity, electrical signals or other types of signals between the two communication between components.
  • the processor in the embodiments of the present application may be a central processing unit (Central Processing Unit, CPU), and may also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), Field Programmable Gate Array (Field Programmable Gate Array, FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.
  • a general-purpose processor can be a microprocessor, or any conventional processor.
  • the method steps in the embodiments of the present application may be implemented by means of hardware, or may be implemented by means of a processor executing software instructions.
  • Software instructions can be composed of corresponding software modules, and software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only Memory, registers, hard disk, removable hard disk, CD-ROM or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
  • the storage medium may also be a component of the processor.
  • the processor and storage medium can be located in the ASIC.
  • the ASIC can be located in the base station or the terminal.
  • the processor and the storage medium may also exist in the base station or the terminal as discrete components.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product comprises one or more computer programs or instructions. When the computer program or instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present application are executed in whole or in part.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, a base station, user equipment or other programmable devices.
  • the computer program or instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instructions may be downloaded from a website, computer, A server or data center transmits to another website site, computer, server or data center by wired or wireless means.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrating one or more available media.
  • the available medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it may also be an optical medium, such as a digital video disk; and it may also be a semiconductor medium, such as a solid state disk.
  • the computer readable storage medium may be a volatile or a nonvolatile storage medium, or may include both volatile and nonvolatile types of storage media.
  • “at least one” means one or more, and “multiple” means two or more.
  • “And/or” describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the contextual objects are an “or” relationship; in the formulas of this application, the character “/” indicates that the contextual objects are a "division” Relationship.

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Abstract

一种解码方法及装置。解码器包括类型检测模块、解码及预测模块、状态判决模块、输出处理模块。类型检测模块用于对待解码码块进行类型检测，解码及预测模块用于对待解码码块进行解码以及获得待解码码块的预测解码方式，状态判决模块用于从待解码码块的预测解码方式中选取一种解码方式，输出处理模块用于根据状态判决模块选取的解码方式对解码结果进行更新。其中，解码器还包括延迟设备，用于将接收的数据延迟至少一个时钟周期后输出。采用本申请可兼容不同总线位宽或不同工艺对物理编码子层解码实现时序的要求，进而提高系统灵活性。

Description

一种解码方法及装置 技术领域
本申请涉及通信技术领域，尤其涉及一种解码方法及装置。
背景技术
以太网物理层从上至下包括物理编码子层(physical coding sublayer，PCS)、物理介质连接(physical medium attachment，PMA)子层和物理介质相关(physical media dependent，PMD)子层。其中，PCS位于介质接入控制(media access control，MAC)层的协调子层(reconciliation sublayer，RS)和PMA子层之间。PCS用于将一条以太网MAC流映射到编码和物理层信号系统上。目前IEEE802.3协议定义的10G～400G标准以及800G私有标准中均规定PCS编码采用64b/66b编码。其中，PCS和上层RS/MAC子层的接口由介质无关接口(media independence interface，MII)提供。
64b/66b编码用于将MII传输的8个8比特(8-bit)数据和1个8比特控制信号进行编码映射，产生块净荷(block Payload)、同步头(sync header)和块类型域(block type field)，并将三者按照规定格式生成66比特块(block)并行输出。
IEEE协议规定64b/66b解码一个66比特块(block)时的状态跳转需要参考下一个66比特块(block)的属性，因此需要在一个时钟周期(即单拍)内完成解码所有操作。在低总线位宽及先进工艺下，通常可以满足在一个时钟周期内完成所有66比特块(block)的状态跳转，但在大总线位宽或在低工艺下，如果在一个时钟周期内完成所有66比特块(block)的状态跳转就会存在较大的实现时序风险。
发明内容
本申请实施例提供一种解码方法及装置，用以兼容不同总线位宽或不同工艺对物理编码子层解码实现时序的要求，进而提高系统兼容性和灵活性。
第一方面，提供一种解码器，所述解码器包括：
类型检测模块，用于检测N个待解码码块的类型，所述N个待解码码块顺序排列，N为大于或等于1的整数；
解码及预测模块，用于根据所述N个待解码码块的类型对所述N个待解码码块进行解码，得到所述N个待解码码块的解码结果；以及，获得所述N个待解码码块中至少一个码块的预测解码方式；
状态判决模块，用于从所述至少一个码块中每个码块的预测解码方式中选取一种解码方式；
输出处理模块，用于根据所述解码方式更新所述解码结果，得到并输出所述N个待解码码块对应的介质无关接口信息；
所述解码器还包括延迟设备，用于将接收的数据延迟至少一个时钟周期后输出，其中：
所述类型检测模块通过所述延迟设备将所述N个待解码码块的类型发送至所述解码及预测模块；或者，所述解码及预测模块通过所述延迟设备将所述预测解码方式发送至所述状态判决模块，以及将所述N个待解码码块的解码结果发送给所述输出处理模块；或者， 所述状态判决模块通过所述延迟设备将所述解码方式发送至所述输出处理模块。
可选的，上述解码器可应用于物理层解码，比如可用于PCS 64b/66b解码。
上述实现方式中，通过在解码器中设置延迟设备，以使得数据延时至少一个时钟周期输出，实现时钟周期的拆分，从而将需要在一个时钟周期内执行的操作拆分到两个或两个以上的时钟周期内执行，进而可以兼容不同总线位宽或不同工艺对物理编码子层解码实现时序的要求，提高系统灵活性。
在一种可能的实现方式中，所述状态判决模块，具体用于：根据第一待解码码块的类型以及所述第一待解码码块的下一个码块的类型，从所述第一待解码码块的预测解码方式中选择一种解码方式，其中，所述第一待解码码块为所述至少一个码块中的任一码块。
上述实现方式中，由于一个解码方式对应于FSM中的一种状态，而在一个给定的FSM状态下，根据不同的跳转条件可能存在多种FSM状态跳转情况，跳转条件依据待解码码块的类型(包括在该FSM状态下输入的待解码码块的类型，进一步包括该待解码码块的下一个码块的类型)。因此，以第一待解码码块为例，在一个给定的FSM状态下(即第一待解码码块的上一个待解码码块的解码方式)，根据第一待解码码块的类型和第一待解码码块的下一个码块的类型，即可确定出该FSM状态下的跳转条件，因而可以确定出唯一的一个跳转到的FSM状态(也就是说从第一待解码码块的多种预测解码方式中选择出一种解码方式)，以便跳转到该FSM状态下对第一解码码块进行解码。
在一种可能的实现方式中，所述输出处理模块，具体用于：若所述解码及预测模块对第一待解码码块所使用的解码方式与所述状态判决模块从所述第一待解码码块的预测解码方式中选择的解码方式不同，则根据所述状态判决模块从所述第一待解码码块的预测解码方式中选择的解码方式对所述第一待解码码块的解码结果进行更新；其中，所述第一待解码码块为所述至少一个码块中的任一码块。
在一种可能的实现方式中，所述输出处理模块，具体用于：若从第一待解码码块的预测解码方式中选取的解码方式为错误状态下使用的解码方式，则将所述第一待解码码块的解码结果更新为错误码；其中，所述第一待解码码块为所述至少一个码块中的任一码块。
在一种可能的实现方式中，所述输出处理模块，具体用于：若从第一待解码码块的预测码块方式中选取的解码方式为低功耗状态下使用的解码方式，则将所述第一待解码码块的解码结果更新为低功耗控制码；其中，所述第一待解码码块为所述至少一个码块中的任一码块。
上述实现方式中，输出处理模块根据状态判决模块输出的状态判决结果，对提前解码所获得到的解码结果进行修正，从而可以保证输出的解码结果的正确性。
在一种可能的实现方式中，所述类型检测模块包括N个类型检测子模块，所述N个类型检测子模块与所述N个待解码码块一一对应；所述解码及预测模块包括N个解码子模块和N个预测子模块，所述N个解码子模块与所述N个待解码码块一一对应，所述N个预测子模块与所述N个待解码码块一一对应；所述输出处理模块包括N个输出处理子模块，所述N个输出处理子模块与所述N个待解码码块一一对应。
进一步的，所述N个类型检测子模块并行地运行，所述N个解码子模块并行地运行，所述N个预测子模块并行地运行，所述N个输出处理模块并行地运行。
上述实现方式中，N个类型检测子模块并行地运行，N个解码子模块并行地运行，N个预测子模块并行地运行，N个输出处理模块并行地运行，从而可以保证解码性能。
在一种可能的实现方式中，所述待解码码块为物理编码子层PCS解扰后的66比特块，所述66比特块包括2比特同步头以及64比特有效负载，所述64比特有效负载包括8比特块类型信息以及56比特数据；所述介质无关接口信息包括64比特XGMII/XXVGMII接口数据以及8比特XGMII/XXVGMII接口控制信息。
第二方面，提供一种解码方法，所述方法包括：
检测N个待解码码块的类型，N为大于或等于1的整数；根据所述N个待解码码块的类型对所述N个待解码码块进行解码，得到所述N个待解码码块的解码结果，以及，获得所述N个待解码码块中至少一个码块的预测解码方式；从所述至少一个码块中每个码块的预测解码方式中选取一种解码方式；根据所述解码方式中选取的解码方式更新所述解码结果，得到并输出所述N个待解码码块对应的介质无关接口信息；其中，所述方法还包括以下操作中的至少一项：将所述N个解码码块的类型延迟至少一个时钟周期后输出；将所述预测解码方式以及所述N个待解码码块的解码结果延迟至少一个时钟周期后输出；将从所述至少一个码块中每个码块的预测解码方式中选取的解码方式延迟至少一个时钟周期后输出。
在一种可能的实现方式中，所述获得所述N个待解码码块中至少一个码块的预测解码方式，包括：根据第一待解码码块的类型以及所述第一待解码码块的下一个码块的类型，从所述第一待解码码块的预测解码方式中选择一种解码方式，其中，所述第一待解码码块为所述至少一个码块中的任一码块。
在一种可能的实现方式中，所述根据从所述至少一个码块中每个码块的预测解码方式中选取的解码方式，更新所述解码结果，包括：若所述解码及预测模块对第一待解码码块所使用的解码方式与所述状态判决模块从所述第一待解码码块的预测解码方式中选择的解码方式不同，则根据所述状态判决模块从所述第一待解码码块的预测解码方式中选择的解码方式对所述第一待解码码块的解码结果进行更新；其中，所述第一待解码码块为所述至少一个码块中的任一码块。
在一种可能的实现方式中，所述根据从所述部分码块中每个码块的预测解码方式中选取一种解码方式，更新所述解码结果，包括：若从第一待解码码块的预测解码方式中选取的解码方式为错误状态下使用的解码方式，则将所述第一待解码码块的解码结果更新为错误码；其中，所述第一待解码码块为所述至少一个码块中的任一码块。
在一种可能的实现方式中，所述根据从所述部分码块中每个码块的预测解码方式中选取一种解码方式，更新所述解码结果，包括：若从第一待解码码块的预测码块方式中选取的解码方式为低功耗状态下使用的解码方式，则将所述第一待解码码块的解码结果更新为低功耗控制码；其中，所述第一待解码码块为所述至少一个码块中的任一码块。
在一种可能的实现方式中，所述待解码码块为物理编码子层PCS解扰后的66比特块，所述66比特块包括2比特同步头以及64比特有效负载，所述64比特有效负载包括8比特块类型信息以及56比特数据；所述介质无关接口信息包括64比特XGMII/XXVGMII接口数据以及8比特XGMII/XXVGMII接口控制信息。
第三方面，提供一种电子设备，所述电子设备包括：一个或多个处理器；一个或多个存储器；其中，所述一个或多个存储器存储有一个或多个计算机程序，所述一个或多个计算机程序包括指令，当所述指令被所述一个或多个处理器执行时，使得所述电子设备执行如上述第二方面中任一项所述的方法。
第四方面，提供一种计算机可读存储介质，所述计算机可读存储介质包括计算机程序，当计算机程序在电子设备上运行时，使得所述计算机执行如上述第二方面中任一项所述的方法。
第五方面，提供一种芯片，所述电子设备包括：一个或多个处理器；一个或多个存储器；其中，所述一个或多个存储器存储有一个或多个计算机程序，所述一个或多个计算机程序包括指令，当所述指令被所述一个或多个处理器执行时，使得所述芯片执行如上述第二方面中任一项所述的方法。
第六方面，提供一种计算机程序产品，所述计算机程序产品在被计算机调用时，使得所述计算机执行如上述第二方面中任一项所述的方法。
附图说明
图1为本申请实施例的一种通信系统示意图；
图2为本申请实施例的一种开放系统互连模型示意图；
图3为本申请实施例的一种网络设备的结构示意图；
图4为本申请实施例的中的PCS 64b/66b编解码示意图；
图5为本申请实施例中的66b编码块的示意图；
图6为本申请实施例中10G/25GBASE-R的XGMII/XXVGMII使用的64b/66b编码表；
图7为本申请实施例中的64b/66b编码状态图；
图8为传统的64b/66b块的解码过程示意图；
图9为本申请实施例中的应用于物理编码子层的解码原理示意图；
图10为本申请实施例提供的64b/66b解码器结构示意图；
图11为本申请实施例提供的适用于64b/66b编码的解码器结构示意图；
图12为本申请实施例提供的解码流程示意图；
图13为本申请实施例提供的电子设备的结构示意图。
具体实施方式
下面结合附图对本申请实施例进行详细描述。
参见图1，为可以实现本申请实施例的示例性通信系统100的框图。通信系统100包括网络设备(例如，交换机或路由器)110(a)，网络设备110(a)经由分别的数据链路(或物理信道)120耦合到多个网络设备110(b)和110(c)。网络设备110(b)和110(c)可以通过各自的数据链路120与交换机/路由器110(a)交换数据。网络设备110(b)和110(c)可以是任何适当的、能够联网的设备，包括例如计算机、交换机、路由器、集线器、网关、接入点等。此外，根据本实施例，网络设备110(b)和110(c)可以包括能够连接到有线或无线网络的任何电子设备，包括例如移动电话、个人数字助理(PDA)、机顶盒或游戏机。当然，路由器/交换机110(a)、网络设备110(b)和110(c)以及数据链路120仅仅是网络的示例性组件，这是由于网络可以进一步包括任意数量的适当的设备以形成较大的网络(包括例如，局域网(LAN)、广域网(WAN)、无线LAN(WLAN))，和/或可以连接到互联网。数据链路120可以是任意适当的物理介质信道，包括例如同轴电缆、光导纤维和/或无屏蔽的/屏蔽的双绞线。网络设备110(a)-110(c)可以使用如在IEEE802.3标准族中所描述的以太网技术来 彼此通信。
参见图2，为图1中的网络设备110(a)和110(b)或110(c)的开放系统互连(OSI)模型200(a,b)的框图。OSI模型200(a,b)被划分成7个逻辑层，自上而下包括：应用层211(a,b)，表示层212(a,b)，会话层213(a,b)，传输层214(a,b)，网络层215(a,b)，数据链路层216(a,b)，物理层217(a,b)。OSI模型200(a,b)可以用于表示网络设备110(a)和110(b)/110(c)，但是应当指出的是，其它适当的模型可以用于表示根据本实施例配置的以太网设备。
物理层217(a,b)提供了针对在网络设备110和数据链路120之间交互的电气的和物理的规范，包括像引脚布局和信号电压等。数据链路层216(a,b)提供了针对在网络设备110(a)和110(b)/110(c)之间的数据传输的功能性和/或程序性的规定，诸如寻址和信道接入控制机制。数据链路层216(a,b)具有两个子层，这两个子层自上而下包括逻辑链路控制(logical link control，LLC)层和MAC层。为了简单起见，在本文后续描述中，数据链路层216(a,b)也被称为MAC层。在MAC层216(a,b)和物理层217(a,b)之间存在MII(即介质无关接口)(未在图中示出)。MII的例子包括XGMII(XGMII被定义为从MAC到物理层的10G比特接口)、XXVGMII(XXVGMII被定义为从MAC到物理层的25G比特接口)等。
参见图3，为网络设备300的结构示意图，网络设备300可以是图1和图2中的网络设备110(a)、110(b)、110(c)中的一个。网络设备300包括处理器310、存储器320和以太网收发机330，以太网收发机330耦合到一个或多个物理信道120。虽然以太网收发机330在图3中示为包括在PHY 350中，但是对于其它实施例，收发机330可以是独立的设备或集成的电路。存储器320可以是任意适当的存储器元件或设备，包括例如EEPROM或闪存。处理器310可以是能够执行存储在例如存储器320中的一个或多个软件程序的脚本或指令的任意适当的处理器。网络设备300还可以包括公知的高速缓冲存储器，该高速缓冲存储器存储频繁地使用的指令和/或数据。
网络设备300包括物理层设备(PHY)350和MAC层设备(或MAC设备)340。PHY350和MAC设备340分别包括MII 360-1和360-2，用于经由信号路径370在两个设备之间发送信号。
MAC设备340可以是实现MAC层功能的任意设备和集成电路，并且可以是独立的设备或可以被集成到网络设备300中。类似地，PHY350可以是实现物理层的功能的任意设备或集成电路，并且可以是独立的设备或可以被集成到网络设备300中。在一些实施例中，PHY350和MAC设备340均可以在安装在电路板上的集成电路中实现，并且信号路径370可以在电路板上实现为走线(trace)。
在正常的数据传输操作期间，当网络设备300上的终端用户软件应用通过网络来发送数据时(例如，向互联网)，处理器310根据OSI模型的顶层来处理数据，并且随后通过MAC设备340向PHY 350发送数据。PHY 350对来自MII的数据进行编码(比如采用64b/66b方式编码)、加扰等操作，然后经由收发机330将数据发送到物理信道120上。当网络设备300的收发机330通过网络接收到来自于物理信道120的数据后，PHY 350对该数据进行解扰、解码等操作后经由MII发送给MAC设备340。
参见图4，为本申请实施例采用的一种64b/66b编解码示意图。以MII具体为XGMII/XXVGMII为例，在IEEE802.3PCS接收模式下，MAC层经由XGMII/XXVGMII向PCS发送数据(TXD<31:0>)和控制信号(TDC<3:0>)，进一步的还可发送时钟信号(TX_CLK)，其中，时钟信号并不是必须发送的，在MAC层和PCS采用相同时钟信号时 可无需向PCS发送时钟信号。PCS将两个数据(TXD<31:0>)形成8个8比特宽度的数据(TXD<63:0>)，将两个控制信号(TDC<3:0>)形成1个8比特宽度的控制信号(TXC<7:0>)，并将64比特数据(TXD<63:0>)和8比特控制信号(TXC<7:0>)进行64b/66b编码，得到一个66比特块(block)，然后对该66比特块进行加扰(scramble)、位宽转换(gear box)等操作之后发送给PCS发送(PCS trasmit)的下游模块进行封装等操作。PCS发送(PCS trasmit)的下游模块可以是PMA，也可以是里得所罗门前向纠错(Reed-Solomon forward error correction，RS-FEC)模块或WIS(wan interface sunlayer)子层，具体取决于应用场景。
在IEEE802.3 PCS接收模式下，PCS接收来自PMA或RS-FEC模块或WIS子层的数据，并对接收到的数据进行误码检查和同步头检测，如果接收到的数据符合基本编码规则(basic encoding rule，BER)要求的信号质量，则PCS对接收到的数据进行解扰、64b/66b解码，最后生成64比特接收数据(RXD<63:0>)和8比特接收控制信号(RXC<7:0>)，并拆分成两个数据(RXD<31:0>)和两个控制信号(RXD<3:0>)，经由MII发送给MAC层。
参见图5，为本申请实施例中编码后的66比特块(block)的示意图。block是PCS的基本处理单元，由66比特组成。PCS基于64b/66b编码方案将MII(包括例如XGMII/XXVGMII)结构数据(TXD<63:0>和TXC<7:0>)映射到66比特block(tx_coded<65:0>)中。66比特block(tx_coded<65:0>)的同步头(2比特)用于接收侧PCS同步过程检测block的边界，使接收侧能够在PHY比特流上实现block对齐。图5中的每个矩形表示一个比特数据。对于66比特block，索引值较小的比特数据首先在物理链路上传输。
通过64b/66b编码，可以改善链路上传输的信息的传输特性，并支持控制和数据字符的传输。64b/66b编码可以确保物理层(PHY)比特流中存在足够的随机度，以使接收方向上能正常时钟恢复。64b/66b编码还保留了检测信息传输和接收期间可能发生的任何单个或多个比特错误的可能性。
10G/25G PCS支持XGMII/XXVGMII中定义的控制字(XGMII和XXVGMII中定义的控制字相同)。控制字的表示是控制码。PCS通过XGMII/XXVGMII上的TXC来区分对应的字节是控制码还是数据字节。如果TXC被置位，则相应的8比特数据是控制码，比如TXC<0>被置位，则TXD<63:0>中的第一个字节<7:0>为控制码。PCS为控制码的每种取值定义了一个符号，示例性的，如表1所示。
表1：控制字符集和符号
Figure PCTCN2021109382-appb-000001
Figure PCTCN2021109382-appb-000002
下面对表1中的各控制符号进行说明。
/I/：当PCS从MII接收到空闲控制字符(0x07)时，PCS传输控制字符/I/。/I/不能由PCS添加和删除，否则会更改预定义带宽。
/LI/：当PCS从MII接收到低功耗(LPI)控制字符(0x06)时，传输/LI/字符。LPI控制字符/LI/代替控制字符/I/连续发送。
/S/：开始控制字符/S/表示数据包的开始。/S/仅对MII TXD<63:0>中的第一个或第五个字节有效。在MII TXD<63:0>的任何其他字节上收到/S/表示错误。
/T/：终止控制字符/T/表示数据包的结束。由于包长不同，所以/T/可以出现在MII TXD<63:0>中的任意一个字节上。
/O/：有序集(ordered sets)用于扩展通过链路发送控制和状态信息的能力，如远程故障和本地故障状态。有两种有序集：序列有序集(sequence ordered_set)和信号有序集(signal ordered_set)。在MII上，序列有序集(sequence ordered_set)由一个特殊的控制字符/Q/和三个数据字节组成。有序集(ordered_set)始终从MII(包括比如XGMII/XXVGMII)的第一个或第五个字节开始。信号有序集(signal ordered_set)由特殊控制字符/Fsig/后跟三个数据字节组成。在本文中，控制符号/Q/等于控制符号/O/。除上述指定外，在TXD的任何其他字节上收到/Q/表示错误。
/E/：在64b/66b编码器中，每当从MII检测到/E/时，就会生成错误控制字符/E/。当PCS从MII检测到错误时也会生成/E/。/E/允许PCS发送检测到的错误。
64b/66b编码器从XGMII/XXVGMII接收数据TXD<63:0>和控制信号TXC<7:0>，通过查编码表生成66比特块(block)。示例性的，图6示出了10GBASE-R/25GBASE-R的XGMII/XXVGMII使用的64b/66b编码表。
图6所示的编码表中，第一列(input data)表示来自XGMII/XXVGMII的传输数据。有16种编码格式。只有一种被编码为数据块(如表中的D 0D 1D 2D 3D 4D 5D 6D 7)，其他被编码为控制块。第二列(tx_coded)是66比特块，它的编码结果由同步头(SYNC)列和块有效负载(block payload)列组成。
66比特块的前两位是同步头(SYNC)。同步头的值显示为二进制值。同步头的取值有“01”和“10”两种，“01“表示随后的64比特都是数据，“10”表示随后的64比特是控制信息或者是数据和控制信息的混合，其中紧挨着同步头的8比特是块类型域(block type field)，后面的56比特是控制信息或者数据或者两者的混合。
66比特块中的块有效负载(block payload)中，数据码标记为D 0至D 7，1个数据码为8比特。控制字符/I/、/LI/和/E/标记为C 0至C 7。对于有序集，控制字符/Q/或/Fsig/被标记为O 0或O 4，因为它们仅在XGMII/XXVGMII传输的第一个或第五个8比特字节上有效。由于相同的原因，控制字符/S/被标记为S 0或S 4，由于使用两个传输TXD<31:0>创建一个TXD<63:0>，因此块类型域的值隐式编码/S/作为块的第一个或第五个字符。控制字符/T/标记为T 0到T 7，/T/在块中的位置隐式编码在块类型域中，当包含/T/的块后跟不包含/T/和 /E/的控制块时，数据包有效结束。
上述编码表中的标签中的下标(比如“D 1”的下标“1”)表示字符在XGMII/XXVGMII传输中的8个字节中的位置。图6中，对于显示为二进制的值，最左边的比特(位)被首先传输。块类型域(block type field)、数据8比特字节和控制码的内容显示为十六进制值。
PCS 64b/66b解码是编码的逆操作。数据和控制字符(或控制码)的定义与编码相同，可以参考PCS传输部分中所示的编码方案。
PCS可以根据64b/66b解码有限状态机(finite state machine，FSM)以及编码表(例如表1和图6)进行64b/66b解码，以从解扰后的输入块流中恢复出原始数据字节。对于每个输入块(待解码的66比特块)，基于解码状态图，通过上下文块分析其验证(validation)，并预测可能的后续块类型，最后确定当前正确的解码状态。一旦确定解码状态，可以解码当前块，重新映射得到原始流rx_raw<71:0>。
64b/66b解码状态机或解码状态图，用于定义64b/66b编解码所遵循的规则，根据该规则可以输出符合格式要求的以太网数据包。示例性的，图7示出了本申请实施例中的一种64b/66b的解码状态图。
如图7所示，如果对解扰后的向量rx_coded<65:0>定界成功，或向量rx_coded<65:0>非高误码，或当前为重置或测试模式，则进入RX_INIT状态(也可称为初始状态)。进入RX_INIT状态后，初始化待传输给XGMII/XXVGMII的72比特向量rx_raw<71:0>，使得该向量包含两个本地故障有序集ordered_set。
在RX_INIT状态下：
如果输入向量rx_coded<65:0>属于S类型，表明该向量中包含开始控制字符/S/，则转入RX_D状态(也可称为数据状态)；
如果输入向量rx_coded<65:0>属于C类型，表明该向量为不包含开始控制字符/S/的控制码块，则转入RX_C(也可称为控制状态)状态；
如果输入向量rx_coded<65:0>属于E、D、T、LI类型中的一种，则转入RX_E状态(也可称为错误状态)。
其中，向量rx_coded<65:0>可能属于以下类型中的一种：
(1)类型C：同步头的值为二进制的10，且满足以下条件之一：
a)块类型域的值为0x1E，包含除/E/以外的8个有效控制字符；如果支持EEE或LPI编码功能，则其中0或4个字符为/LI/；
b)块类型域的值为0x2D或0x4B，包含有效的O代码和4个有效的控制字符；
c)块类型域的值为0x55，包含2个有效的O代码。
(2)类型LI：对于EEE或LPI编码功能，支持LI类型，其中向量中的同步头的值为二进制的10、块类型域的值为0x1E，且包含8个控制字符0x06(/LI/)。
(3)类型S；同步头的值为二进制的10，且满足以下条件之一：
a)块类型域的值为0x33，并包含4个有效控制字符；
b)块类型域的值为0x66，并包含有效的O代码；
c)块类型域的值为0x78。
(4)类型T：同步头的值为二进制的10，以及满足以下条件之一：
a)块类型域的值为0x87、0x99、0xAA、0xB4、0xCC、0xD2、0xE1或0xFF，且所有控制字符都有效。
(5)类型D：向量中包含的同步头的值为二进制的01。
(6)类型E；向量不符合任何其他值的标准；
在传输部分中指定了有效的控制字符。如果块类型为E，则该块为无效块。显然无效的块至少满足以下属性之一：
a)同步头的值为二进制的00或11；
b)块类型域的值为无效值(编码表中不包括的值)；
c)当*_PCS_DEC_CBLK_IDEN中的相应字段设置为0时，任何控制字符都包含定义的控制代码表中不包含的值；
d)根据上下文被视为无效块；
e)块类型域的值为0x1E，且8个控制字符为/E/。
进入RX_D状态后，解码当前向量rx_coded<65:0>，并用解码结果更新向量rx_raw<71:0>。
在RX_D状态下：
如果输入向量rx_coded<65:0>属于D类型，表明该向量为数据码块，则保持当前状态，解码该向量rx_coded<65:0>，并用解码结果更新向量rx_raw<71:0>；
如果输入向量rx_coded<65:0>属于T类型且下一个向量属于S、C或LI类型，表明当前输入向量包含终止控制字符/T/，且后续向量的块类型正确，则转入RX_T状态(也可称为结束状态)；
如果输入向量rx_coded<65:0>属于T类型且下一个向量属于E、D或T类型，表明当前输入向量包含终止控制字符/T/，且后续向量的块类型不正确，则转入RX_E状态；或者，如果输入向量rx_coded<65:0>属于E、C、S或LI类型，则转入RX_E状态。
进入RX_T状态后，解码当前向量rx_coded<65:0>，并用解码结果更新向量rx_raw<71:0>。
在RX_T状态下：
如果输入向量rx_coded<65:0>属于C类型，则转入RX_C状态；
如果输入向量rx_coded<65:0>属于LI类型，则转入RX_LI状态(也可称为低功耗状态)；
如果输入向量rx_coded<65:0>属于S类型，则转入RX_D状态。
进入RX_C状态后，解码当前向量rx_coded<65:0>，并用解码结果更新向量rx_raw<71:0>。
在RX_C状态下：
如果输入向量rx_coded<65:0>属于C类型，则保持当前状态，解码当前向量rx_coded<65:0>，并用解码结果更新向量rx_raw<71:0>；
如果输入向量rx_coded<65:0>属于S类型，则转入RX_D状态；
如果输入向量rx_coded<65:0>属于LI类型，则转入RX_LI状态；
如果输入向量rx_coded<65:0>属于E、D或T类型，则转入RX_E状态。
进入RX_LI状态后，将向量rx_raw<71:0>中的8个控制字符更新为“LI”字符(即0x06)。
在RX_LI状态下：
如果rx_lpi_active的值为“false”且新的输入向量rx_coded<65:0>属于C类型，则转 入RX_C状态；其中，rx_lpi_active的值为“false”时，表明PCS接收处于活动状态并能够接收数据；
如果rx_lpi_active的值为“false”且新的输入向量rx_coded<65:0>属于E、D、S或T类型，则转入RX_E状态。
进入RX_E状态后，将向量rx_raw<71:0>中的8个8字节数据均设置为/E/。
在RX_E状态下：
如果输入向量rx_coded<65:0>属于T类型，且下一个向量属于S、C或LI类型，则转入RX_T状态；
如果输入的向量rx_coded<65:0>属于D类型，则转入RX_D状态；
如果输入的向量rx_coded<65:0>属于C类型，则转入RX_C状态；
如果输入的向量rx_coded<65:0>属于LI类型，则转入RX_LI状态；
如果输入的向量rx_coded<65:0>属于T类型且下一个向量属于E、D或T类型，或者如果输入的向量rx_coded<65:0>属于E或S类型，则保持在RX_E状态。
根据上述图7所示的64b/66b解码状态图，当满足任何停止解码的条件时均可能立即停止解码过程，并在以太网PHY的XGMII/XXVGMII上连续传输两个本地故障有序集。
由于IEEE协议规定64b/66b解码当前的66比特块(block)时的状态跳转，需要参考下一个66比特块(block)的属性，因此传统64b/66b编解码实现是一个时钟周期(即单拍)内完成所有操作。示例性的，图8示出了在一个时钟周期内完成对N个(N为大于或等于1的整数，比如N＝8)66比特块(block)进行解码的示意图。根据图7所示的解码状态图，在当前FSM状态下输入一个66比特块时，应跳转到哪个FSM状态对该输入的66比特块进行解码，则需要依赖下一个66比特块的类型，因此需要在一个时钟周期完成对该N个66比特块的解码操作。该N个66比特块的解码过程为串行结构，其中一个66比特块的解码过程可包括块类型预测、根据块类型进行解码、对解码结果进行输出处理等。在低总线位宽及先进工艺下，在一个时钟周期内针对N个66比特块(block)进行FSM状态跳转判断从而对该N个66比特块进行解码的实现时序风险较低，但在大总线位宽或在低工艺下，就会存在较大的实现时序风险。
为解决上述问题，本申请实施例提供了解码方法以及能够实现该方法的装置，本申请实施例通过将一个时钟周期内对N个块的解码操作拆分到两个或两个以上时钟周期内进行，进一步的，在至少一个时钟周期内对该N个块的解码操作进行并行处理，从而可以保证实现时序，兼容不同工艺或不同总线位宽，提高系统兼容性以及灵活性。本申请实施例可应用于64b/66b的解码实现中，也可应用于其他类型的解码实现中。本申请实施例可在物理层(PHY)实现，比如可在PCS子层中实现。
下面结合附图对本申请实施例进行详细描述。
参见图9，为本申请实施例提供的解码实现原理示意图，可选的，该解码实现原理可应用于物理层，比如可应用于PCS 64b/66b解码过程。
对于一个待解码码块块(例如包括66比特block)，其解码过程可包括类型检测、解码、状态预测、状态判决、输出处理等操作。其中，类型检测操作包括对待解码码块的类型进行检测，解码操作包括根据待解码码块的类型对该待解码码块进行解码，状态预测操作包括针对当前待解码码块的下一个待解码码块，预测其可能的所有解码方式(本申请实施例中称为预测解码方式)，状态判决操作包括针对待解码码块，从其预测解码方式中选择一 个解码方式，输出处理操作包括针对待解码码块，根据对其解码操作时所使用的解码方式以及从该待解码码块的预测解码方式中选择的解码方式，确定是否需要更新该码块的解码结果，如果需要更新，则根据从该码块的预测解码方式中选择的解码方式更新该码块的解码结果，并输出待解码码块对应的介质无关接口信息(比如可包括介质无关接口数据和介质无关接口控制信息)。上述类型检测、解码、状态预测、状态判决、输出处理等操作的具体实现方式，请参见后面图10、图11中的相关内容。
本申请实施例中，可在解码器中设置延迟设备，用于将接收的数据延迟至少一个时钟周期后输出。可选的，类型检测的结果可通过延迟设备延迟一个或多个时钟周期输出。可选的，解码结果可通过延迟设备延迟一个或多个时钟周期输出，解码方式预测的结果可通过延迟设备延迟一个或多个时钟周期输出。可选的，预测解码方式可通过延迟设备延迟一个或多个时钟周期输出。
可选的，所述延迟设备可以是寄存器。所述寄存器，举例来说可以是D触发器，当D触发器在受到触发信号(如时钟信号)的触发后，将存储的数据进行输出。
需要说明的是，本申请实施例中所说的“寄存器”可以是一个寄存器或者至少两个寄存器组成的寄存器组，主要取决于数据带宽以及寄存器位宽，比如，如果输出的数据为8比特，则可设置一个8比特寄存器或者两个4比特寄存器。
为便于理解，下面示例性的，将类型检测操作与解码及状态预测操作之间的位置称为第一位置，将解码及状态预测操作与状态判决操作间的位置称为第二位置，将状态判决操作与输出处理操作之间的位置称为第三位置，解码操作与输出处理操作之间包含有上述第二位置和第三位置。本申请实施例中，可在上述第一位置、第二位置、第三位置中的至少一个位置上设置延迟设备，以使得在设置延迟设备的位置上，其前一级操作的输出被延迟至少一个时钟周期后发送到后一级操作。
可选的，可通过在第一位置、第二位置、第三位置中的至少一个位置上设置延迟设备的方式实现延时。比如，在第一位置上插入寄存器(图9中包含有三角形的方框表示寄存器)，使得类型检测操作的输出数据经过该寄存器被延迟至少一个时钟周期后，输出到解码操作和状态预测操作，作为解码操作和状态预测操作的输入数据。
根据上述解码实现原理，本申请实施例通过在相邻操作间插入延时，以使得数据延时至少一个时钟周期，实现时钟周期的拆分，从而将需要在一个时钟周期内执行的操作拆分到两个或两个以上的时钟周期内执行，进而可以兼容不同总线位宽或不同工艺对物理编码子层解码实现时序的要求，提高系统灵活性。
本申请实施例提供的解码方法可适用于PCS 64b/66b解码过程，还可适用于类似的物理子层上实现的解码过程。
根据以上解码原理，图10示出了本申请实施例提供的一种解码器的结构。
参见图10，为本申请实施例提供的一种解码器的结构示意图。该解码器可通过硬件方式实现，比如通过现场可编程门阵列(field programmable gate array，FPGA)或其他集成电路实现，该解码器也可通过软件方式实现，还可以通过软硬件结合方式实现，本申请实施例对此不作限制。
如图10所示，本申请实施例提供的一种解码器1000可包括类型检测模块1010、解码及预测模块1020、状态判决模块1030和输出处理模块1040。
类型检测模块1010用于检测N个待解码码块的类型，该N个待解码码块顺序排列， N为大于或等于1的整数，比如N＝8。解码及预测模块1020用于根据该N个待解码码块的类型对该N个待解码码块进行解码，得到该N个待解码码块的解码结果；以及，获得该N个待解码码块中至少一个码块的预测解码方式。状态判决模块1030用于从该至少一个码块中每个码块的预测解码方式中选取一种解码方式。输出处理模块1040用于根据所述解码方式更新上述解码结果，得到并输出该N个待解码码块对应的介质无关接口信息。
示例性的，以第一待解码码块为上述至少一个码块中的任意一个为例，若解码及预测模块1020对第一待解码码块所使用的解码方式与状态判决模块1030从第一待解码码块的预测解码方式中选择的解码方式不同，则输出处理模块1040根据状态判决模块1030从第一待解码码块的预测解码方式中选择的解码方式对第一待解码码块的解码结果进行更新。比如，在一些实施例中，若输出处理模块1040从第一待解码码块的预测解码方式中选取的解码方式为错误状态下使用的解码方式，则将第一待解码码块的解码结果更新为错误码。在另一些实施例中，若输出处理模块1040从第一待解码码块的预测码块方式中选取的解码方式为低功耗状态下使用的解码方式，则将第一待解码码块的解码结果更新为低功耗控制码。
该解码器1000还包括延迟设备(图10中包含有三角形的方框表示延迟设备)，用于将接收的数据延迟至少一个时钟周期后输出。可选的，类型检测模块1010可通过该延迟设备将N个待解码码块的类型(即类型检测结果)发送至解码及预测模块1020。可选的，解码及预测模块1020可通过延迟设备将预测解码方式(即预测结果)发送至状态判决模块1030，以及将N个待解码码块的解码结果发送给输出处理模块1040。可选的，状态判决模块1030可通过延迟设备将从预测解码方式中选取的一种解码方式(即判决结果)发送至输出处理模块1040。
示例性的，类型检测模块1010可通过一级寄存器将类型检测结果输出给解码及预测模块1020，解码及预测模块1020通过可一级寄存器将预测结果输出给状态判决模块1030，并通过两级寄存器将解码结果输出给输出处理模块1040，状态判决模块1030通过一级寄存器将判决结果输出给处理模块1040。
可理解的，一个待解码码块的预测解码方式可理解为：基于解码有限状态机(FSM)，在一个FSM状态下，对于输入的待解码码块，可能跳转到的FSM状态。其中可能跳转到的FSM状态可能有一个或多个，每个FSM状态对应一种解码方式。这样，这些可能跳转的FSM状态对应于该待解码码块的预测解码方式。比如，在64b/66b的解码FSM中，在RX_D状态下时，对当前输入的待解码码块，根据RX_D状态下的三种跳转条件，则可能跳转到三种FSM状态中的一种状态下对该待解码码块进行解码，则这三种FSM状态对应的三种解码方式即为该待解码码块的预测解码方式。
可理解的，在一些情形下，当前待解码码块为码块i，解码FSM当前处于状态1，如果从状态1仅能跳转到状态2，则对于码块i+1(即码块i的下一个码块)来说，其可采用的解码方式是唯一的(即状态2所对应的解码方式)，因此可以不用对该待解码码块i+1进行解码方式预测，当然也可将状态2对应的解码方式确定为该解码码块i+1的预测解码方式。
可选的，状态判决模块1030可具体用于：根据第一待解码码块(该第一待解码码块为上述至少一个码块中的任一码块)的类型以及该第一待解码码块的下一个码块的类型，从该第一待解码码块的预测解码方式中选择一种解码方式。
由于一个解码方式对应于FSM中的一种状态，而在一个给定的FSM状态下，根据不同的跳转条件可能存在多种FSM状态跳转情况，跳转条件依据待解码码块的类型(包括在该FSM状态下输入的待解码码块的类型，进一步包括该待解码码块的下一个码块的类型)。因此，以第一待解码码块为例，在一个给定的FSM状态下(即第一待解码码块的上一个待解码码块的解码方式)，根据第一待解码码块的类型和第一待解码码块的下一个码块的类型，即可确定出该FSM状态下的跳转条件，因而可以确定出唯一的一个跳转到的FSM状态(也即从第一待解码码块的多种预测解码方式中选择出一种解码方式)，以便跳转到该FSM状态下对第一解码码块进行解码。
上述实施例提供的解码器中，解码及预测模块1020可提前对N个码块进行解码，对一个码块解码时依据该码块的类型，这样有可能导致解码错误(因为在有些情况下，对一个码块进行解码时不仅需要依据该码块的类型，还需要依据下一个码块的类型，才能确定采用哪种解码方式)，因此解码结果可能不准确(也即所采用的解码方式可能不准确)。通过解码及预测模块1020对待解码码块进行解码方式预测，再通过状态判决模块1030从中选择一种确定的解码方式，这样，当有待解码码块在解码及预测模块1020中所使用的解码方式与在状态判决模块1030中确定出的解码方式不同时，输出处理模块1040根据状态判决模块1030中确定出的解码方式对该待解码码块的解码结果进行更新，从而可以保证解码的准确性。
上述实施例提供的解码器，可通过延迟设备(如寄存器)，将类型检测模块1010、解码及预测模块1020、状态判决模块1030中至少一个模块的输出数据延迟输入到下一级模块，以使得数据延时至少一个时钟周期，实现时钟周期的拆分，从而将需要在一个时钟周期内执行的解码操作拆分到两个或两个以上的时钟周期内执行，进而可以兼容不同总线位宽或不同工艺对物理编码子层解码实现时序的要求，提高系统灵活性。
可选的，本申请实施例提供的解码器1000中，类型检测模块1010包括N个类型检测子模块，该N个类型检测子模块与N个待解码码块一一对应，即，一个类型检测子模块用于对一个待解码码块进行解码；解码及预测模块1020包括N个解码及预测子模块，该N个解码及预测子模块与N个待解码码块一一对应，即一个解码及预测子模块用于对一个待解码码块进行解码，并对该待解码码块的下一个待解码码块进行类型预测；输出处理模块1040包括N个输出处理子模块，该N个输出处理子模块与N个待解码码块一一对应，即，一个输出处理子模块用于对一个待解码码块的解码结果进行输出处理。可以理解，解码器1000中包括N路解码，每一路解码用于处理一个待解码码块，每一路解码包括一个类型检测子模块、解码及预测子模块、输出处理子模块，该N路解码可共享一个状态判决模块1030。
可选的，上述N个类型检测子模块并行地运行，上述N个解码子模块并行地运行，上述N个预测子模块并行地运行，上述N个输出处理模块并行地运行。
可选的，解码及预测子模块可包括解码子模块和预测子模块，以分别实现解码操作和类型预测操作。
下面以64b/66b编码为例，对上述解码器中的各模块所实现的功能或所执行的操作进行详细说明。
以64b/66b编码为例，图11示出了适用于64b/66b编码的解码器结构以及输入和输出示意图。PCS解扰后的66比特块block0中的2比特同步头block0[1:0]和8比特块类型域block0[9:2]被输入到类型检测模块1010中的类型检测子模块0。如果同步头的值为“01” 则类型检测子模块0确定block0是数据码块，如果同步头的值是“10”则类型检测子模块0确定block0是控制码块，否则，确定block0发生编码错误。进一步的，如果block0是控制码块，则根据block0的块类型域的值，通过查64b/66b编码表(例如如图6)确定block0的块类型，block0的块类型可以指示block0的格式。block0的块类型可能是类型C、LI、S、T、D、E中的一种。类型检测子模块0检测到的block0的类型信息被寄存器延迟一个时钟周期后发送给解码子模块0和预测子模块0。其他待解码码块的类型检测方法类似。
解码子模块0获得类型检测子模块0输出的block0的类型检测结果以及block0中的56比特数据block[65:10]，通过查64b/66b编码表(例如如图6)，将56比特数据block[65:10]解码为相应格式的64比特数据rx_coded0。该解码结果(即64比特数据rx_coded0)经过两级寄存器，被延迟两个时钟周期后发送给输出处理子模块0。其他待解码码块的解码方法类似。
可选的，解码子模块0还可以根据block0的块类型生成8比特的控制信息，该控制信息中的各比特的值用于指示rx_coded0中对应8比特字节是数据还是控制码。解码子模块0可将64比特数据rx_coded0以及生成的8比特控制信息作为解码结果输出给输出处理子模块0。进一步的，解码子模块0还可以将block0所采用的解码方式的指示信息发送给输出处理子模块0。
预测子模块0获得类型检测子模块0输出的block0的类型检测结果后，依据64b/66b编解码规则(比如64b/66b解码状态图，如图7所示)，根据block0的块类型以及对应的FSM状态(即解码block0时FSM状态机所处的状态)，预测有可能跳转到哪个或哪些FSM状态对下一个66比特块block1进行解码。举例来说，根据图7所示的FSM，如果block0的类型为S，则跳转到RX_D状态下对block0进行解码，那么针对下一个块block1，则根据相应的条件，可能会有3种状态跳转可能：(1)保持当前RX_D状态，即在RX_D状态下对block1进行解码；(2)跳转到RX_T状态，即跳转到RX_T状态下对block1进行解码；(3)跳转到RX_E状态，即跳转到RX_E状态下对block1进行解码。预测子模块0的预测结果被寄存器延迟一个时钟周期后发送给状态判决模块1030。可选的，预测子模块0的预测结果可包括块索引(比如block0和/或block1的索引)以及预测得到的解码block1可能采用的所有解码方式(即FSM状态)的指示信息。其他待解码码块的解码方式预测方法类似。
可选的，block0～blockN-1中各码块的类型可由类型检测模块1010发送给状态判决模块1030，也可以由相应的预测子模块发送给状态判决模块1030，比如，预测子模块0可将block0的类型发送给状态判决模块1030，预测子模块1可将block1的类型发送给状态判决模块1030，以此类推。
状态判决模块1030，用于根据码块的类型，基于64b/66b的解码状态图(如图7所示)，分别从各码块的预测解码方式中选择一种解码方式，得到判决结果，该判决结果被寄存器延迟一个时钟周期后发送给相应的输出处理子模块。比如，状态判决模块1030从预测子模块0接收到的block1的预测解码方式包括：RX_D对应的解码方式、RX_T对应的解码方式和RX_E对应的解码方式，从预测子模块1接收到的block1的类型为类型D，则根据图7所示的解码状态图，从上述三种解码方式中选择RX_D对应的解码方式，并将该解码方式的指示信息发送给输出处理子模块1。可选的，状态判决模块1030输出的判决信息可包括：选择出的解码方式的指示信息，进一步的还可包括码块的索引。
输出处理模块1040接收来自于状态判决模块1030的判决结果后，若判断对于某个码块，对应的解码子模块所采用的解码方式与状态判决模块1030所选择出的解码方式不同，则以状态判决模块1030选择的解码方式对该码块的解码结果进行更新。比如，对于block,1，如果状态判决模块1030选择出的解码方式为RX_D对应的解码方式，则由于该解码方式与解码子模块1对block1所采用的解码方式相同，则输出处理子模块1无需对block1的解码结果进行更新；再例如，对于block1，如果状态判决模块1030选择出的解码方式为RX_E对应的解码方式(即错误状态下使用的解码方式)，则由于该解码方式与解码子模块1对block1所采用的解码方式不相同，则输出处理子模块1按照RX_E对应的解码方式对block1的解码结果进行更新，即，将block1对应的XGMII/XXVGMII RXD<63:0>的8个字节均更新为错误控制字符/E/；再例如，对于block5，如果状态判决模块1030选择出的解码方式为RX_LI对应的解码方式(即低功耗状态下使用的解码方式)，则由于该解码方式与解码子模块1对block1所采用的解码方式不相同，则输出处理子模块5按照RX_LI对应的解码方式对block1的解码结果进行更新，即，将block1对应的XGMII/XXVGMII RXD<63:0>的8个字节均更新为低功耗控制字符/LI/。输出处理模块1040根据N个码块的解码结果，生成相应的64比特XGMII/XXVGMII接口数据以及8比特XGMII/XXVGMII接口控制信息，并输出给XGMII/XXVGMII接口。
本申请实施例提供的解码器1000可应用于时分架构，也可应用于空分架构。
在一种示例性的空分架构中，N个待解码码块在同一时钟周期输入到类型检测模块1010。类型检测模块1010在同一时钟周期对该N个待解码码块的类型进行检测，该N个待解码码块的类型检测结果被在同一时钟周期输入到解码及预测模块1020。解码及预测模块1020在同一时钟周期内对该N个待解码码块进行解码以及进行解码方式预测操作。该N个待解码码块的预测解码方式以及类型检测结果被在同一时钟周期输入到状态判决模块1030。由于状态判决模块1030能够在一个时钟周期获得N个待解码码块的预测解码方式以及类型检测结果，因此可以在一个时钟周期内从相应码块的预测解码方式中选择一种解码方式。
以64b/66b编码为例，图11示出了适用于64b/66b编码的解码器结构以及输入和输出示意图。状态判决模块1030在一个时钟周期内接收到N个类型检测子模块输出的N个66比特块(block0～blockN-1)的类型，并接收到block0～blockN-1的预测解码方式。状态判决模块1030在一个时钟周期内，根据N个类型检测子模块的输出以及N个预测子模块的输出，分别从block0～blockN-1的预测解码类型中选择一个解码类型。
在一种示例性的时分架构中，N个待解码码块按照时钟周期先后依次输入到类型检测模块1010。类型检测模块1010对接收到的待解码码块进行类型检测，该N个待解码码块的类型检测结果按照时钟周期先后依次输入到解码及预测模块1020。解码及预测模块1020依次对待解码码块进行解码操作以及进行解码方式预测操作。该N个待解码码块的预测解码方式以及类型检测结果按照时钟周期被先后依次输入到状态判决模块1030。由于状态判决模块1030无法在一个时钟周期获得所有N个待解码码块的类型检测结果和预测解码方式，因此状态判决模块1030可首先缓存接收到的待解码码块的类型预测结果和预测解码方式，待获得N个待解码码块的类型检测结果和预测解码方式后，从相应码块的预测解码方式中选择一种解码方式。
以64b/66b编码为例，图11示出了适用于64b/66b编码的解码器结构以及输入和输出 示意图。状态判决模块1030在时钟周期0～时钟周期N-1内依次接收到N个类型检测子模块输出的N个66比特块(block0～blockN-1)的类型，并接收到N个预测子模块输出的各码块的预测解码方式。状态判决模块1030缓存接收到的类型检测结果以及预测解码方式，并在获得N个码块的类型预测结果和预测解码方式后，分别从block0～blockN-1的预测解码方式中选择一种。
可理解，对于仅在上述第一位置、第二位置和第三位置中的任意两个位置上设置延迟设备时，或者仅在上述第一位置、第二位置和第三位置中的任意一个位置上设置延迟设备时，对应的解码器的结构可参照图9所示的解码原理以及上述图10所示的解码器结构推导得出，本申请实施例不再分别单独描述。
这里虽然在上述三个位置上均设置有延迟设备，但可理解的，在其他一些实施例提供的解码器中，可在上述第一位置、第二位置、第三位置中的任意两个位置上或者任意一个位置上设置延迟设备，且均不会影响上述各模块的功能。
参见图12，为本申请实施例提供的解码方法的流程示意图。该流程可由上述解码器实现。可选的，上述流程可适用于对64b/66b编码的码块进行解码。如图所示，该流程可包括以下步骤：
S1200：检测N个待解码码块的类型，N为大于或等于1的整数。
可选的，检测N个待解码码块的类型的操作被并行执行。
S1202：根据N个待解码码块的类型对该N个待解码码块进行解码，得到该N个待解码码块的解码结果；以及，获得该N个待解码码块中至少一个码块的预测解码方式。
可选的，分根据N个待解码码块的类型对该N个待解码码块进行解码的操作被并行执行；获得该N个待解码码块中至少一个码块的预测解码方式的操作被并行执行。
S1204：从上述至少一个码块中每个码块的预测解码方式中选取一种解码方式。
在一些实施例中，S1200的操作可在同一时钟周期内完成，S1202的操作可在同一时钟周期内完成，这样，在S1204中，可在同一个时钟周期内获得各码块的类型以及预测解码方式，从而可以在该时钟周期内完成S1204的操作。该方法可应用于空分架构。
在另一些实施例中，S1200中，N个待解码码块按照时钟周期被依次进行类型检测，比如，第一个时钟周期对block0进行类型检测，第二个时钟周期对block1进行类型检测，以此类推，相应的，各码块的类型检测结果按照时钟周期被依次输出，在S1202中，各码块被依次进行解码操作和解码方式预测操作，解码结果以及预测结果被依次输出。在S1204中，可先缓存接收到的各码块的预测解码方式以及该N个待解码码块的类型，然后待缓存得到该N个码块的类型和预测解码方式后，根据缓存的信息从相应待解码码块的预测解码方式中选择一种解码方式。该方法可应用于时分架构。
S1206：根据所述解码方式更新解码结果，得到并输出该N个待解码码块对应的介质无关接口信息。
为描述方便，将该N个待解码码块中的任意一个称为第一待解码码块。可选的，在S1206中，若从第一待解码码块的预测解码方式中选取的一种解码方式为错误状态下使用的解码方式，则将第一待解码码块的解码结果更新为错误码；或者，若从第一待解码码块的预测码块方式中选取的一种解码方式为低功耗状态下使用的解码方式，则将第一待解码码块的解码结果更新为低功耗控制码；若从第一待解码码块的预测解码方式中选取的一种解码方式与S1202中对第一待解码码块采用的解码方式相同，则无需更新该第一待解码码 块的解码结果。
上述流程中，还包括以下操作中的至少一项：
S1201：将N个解码码块的类型(即S1200的处理结果)延迟至少一个时钟周期后输出，延迟至少一个时钟周期后输出；
S1203：将预测解码方式以及N个待解码码块的解码结果(即S1202的处理结果)，延迟至少一个时钟周期后输出；
S1205：将从至少一个码块中每个码块的预测解码方式中选取一种解码方式(即S1204的处理结果)，延迟至少一个时钟周期后输出。
需要说明的是，上述解码流程的具体实现方式可参照前述解码器实施例中的相关描述。
本申请实施例提供的上述解码原理也可应用于编码过程，即，将物理编码子层的编码操作拆分到两个或两个以上时钟周期进行，以兼容不同总线位宽或不同工艺对物理编码子层编码实现时序的要求，进而提高系统兼容性和灵活性。
基于相同的技术构思，本申请实施例还提供一种电子设备，该电子设备可以具有如图13所示的结构，该电子设备具有计算能力，能够实现本申请实施例提供的方法流程。
如图13所示的电子设备1300可以包括至少一个处理器1302，所述至少一个处理器1302用于与存储器耦合，读取并执行所述存储器中的指令以实现本申请实施例提供的方法中服务器涉及的步骤。可选的，该电子设备还可以包括通信接口1301，用于支持该电子设备进行信令或者数据的接收或发送。电子设备中的通信接口1301，可用于实现与其他电子设备的进行交互。处理器1302可用于实现电子设备执行如图12所示的方法中的步骤。可选的，该电子设备通还可以包括存储器1304，其中存储有计算机程序、指令，存储器1304可以与处理器1302和/或通信接口1301耦合，用于支持处理器1302调用存储器1304中的计算机程序、指令以实现本申请实施例提供的方法涉及的步骤；另外，存储器1304还可以用于存储本申请方法实施例所涉及的数据，例如，用于存储支持通信接口1301实现交互所必须的数据、指令，和/或，用于存储电子设备执行本申请实施例所述方法所必须的配置信息。
基于与上述方法实施例相同构思，本申请实施例还提供了一种计算机可读存储介质，其上存储有一些指令，这些指令被计算机调用执行时，可以使得计算机完成上述方法实施例、方法实施例的任意一种可能的设计中所涉及的方法。本申请实施例中，对计算机可读存储介质不做限定，例如，可以是RAM(random-access memory，随机存取存储器)、ROM(read-only memory，只读存储器)等。
基于与上述方法实施例相同构思，本申请还提供一种计算机程序产品，该计算机程序产品在被计算机调用执行时可以完成方法实施例以及上述方法实施例任意可能的设计中所涉及的方法。
基于与上述方法实施例相同构思，本申请还提供一种芯片，该芯片可以包括处理器以及接口电路，用于完成上述方法实施例、方法实施例的任意一种可能的实现方式中所涉及的方法，其中，“耦合”是指两个部件彼此直接或间接地结合，这种结合可以是固定的或可移动性的，这种结合可以允许流动液、电、电信号或其它类型信号在两个部件之间进行通信。
可以理解的是，本申请的实施例中的处理器可以是中央处理单元(Central Processing Unit，CPU)，还可以是其它通用处理器、数字信号处理器(Digital Signal Processor，DSP)、 专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其它可编程逻辑器件、晶体管逻辑器件，硬件部件或者其任意组合。通用处理器可以是微处理器，也可以是任何常规的处理器。
本申请的实施例中的方法步骤可以通过硬件的方式来实现，也可以由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器、闪存、只读存储器、可编程只读存储器、可擦除可编程只读存储器、电可擦除可编程只读存储器、寄存器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于基站或终端中。当然，处理器和存储介质也可以作为分立组件存在于基站或终端中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机程序或指令。在计算机上加载和执行所述计算机程序或指令时，全部或部分地执行本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、基站、用户设备或者其它可编程装置。所述计算机程序或指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机程序或指令可以从一个网站站点、计算机、服务器或数据中心通过有线或无线方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是集成一个或多个可用介质的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，例如，软盘、硬盘、磁带；也可以是光介质，例如，数字视频光盘；还可以是半导体介质，例如，固态硬盘。该计算机可读存储介质可以是易失性或非易失性存储介质，或可包括易失性和非易失性两种类型的存储介质。
在本申请的各个实施例中，如果没有特殊说明以及逻辑冲突，不同的实施例之间的术语和/或描述具有一致性、且可以相互引用，不同的实施例中的技术特征根据其内在的逻辑关系可以组合形成新的实施例。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。在本申请的文字描述中，字符“/”，一般表示前后关联对象是一种“或”的关系；在本申请的公式中，字符“/”，表示前后关联对象是一种“相除”的关系。
可以理解的是，在本申请的实施例中涉及的各种数字编号仅为描述方便进行的区分，并不用来限制本申请的实施例的范围。上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定。

Claims (18)

  1. 一种解码器，其特征在于，所述解码器包括：
    类型检测模块，用于检测N个待解码码块的类型，所述N个待解码码块顺序排列，N为大于或等于1的整数；
    解码及预测模块，用于根据所述N个待解码码块的类型对所述N个待解码码块进行解码，得到所述N个待解码码块的解码结果；以及，获得所述N个待解码码块中至少一个码块的预测解码方式；
    状态判决模块，用于从所述至少一个码块中每个码块的预测解码方式中选取一种解码方式；
    输出处理模块，用于根据所述解码方式更新所述解码结果，得到并输出所述N个待解码码块对应的介质无关接口信息；
    所述解码器还包括延迟设备，用于将接收的数据延迟至少一个时钟周期后输出，其中：
    所述类型检测模块通过所述延迟设备将所述N个待解码码块的类型发送至所述解码及预测模块；或者，
    所述解码及预测模块通过所述延迟设备将所述预测解码方式发送至所述状态判决模块，以及将所述N个待解码码块的解码结果发送给所述输出处理模块；或者，
    所述状态判决模块通过所述延迟设备将所述解码方式发送至所述输出处理模块。
  2. 如权利要求1所述的解码器，其特征在于，所述状态判决模块，具体用于：
    根据第一待解码码块的类型以及所述第一待解码码块的下一个码块的类型，从所述第一待解码码块的预测解码方式中选择一种解码方式，其中，所述第一待解码码块为所述至少一个码块中的任一码块。
  3. 如权利要求1或2所述的解码器，其特征在于，所述输出处理模块，具体用于：
    若所述解码及预测模块对第一待解码码块所使用的解码方式与所述状态判决模块从所述第一待解码码块的预测解码方式中选择的解码方式不同，则根据所述状态判决模块从所述第一待解码码块的预测解码方式中选择的解码方式对所述第一待解码码块的解码结果进行更新；其中，所述第一待解码码块为所述至少一个码块中的任一码块。
  4. 如权利要求1-3任一项所述的解码器，其特征在于，所述输出处理模块，具体用于：
    若从第一待解码码块的预测解码方式中选取的解码方式为错误状态下使用的解码方式，则将所述第一待解码码块的解码结果更新为错误码；其中，所述第一待解码码块为所述至少一个码块中的任一码块。
  5. 如权利要求1-3任一项所述的解码器，其特征在于，所述输出处理模块，具体用于：
    若从第一待解码码块的预测码块方式中选取的解码方式为低功耗状态下使用的解码方式，则将所述第一待解码码块的解码结果更新为低功耗控制码；其中，所述第一待解码码块为所述至少一个码块中的任一码块。
  6. 如权利要求1-5任一项所述的解码器，其特征在于，所述类型检测模块包括N个类型检测子模块，所述N个类型检测子模块与所述N个待解码码块一一对应；
    所述解码及预测模块包括N个解码子模块和N个预测子模块，所述N个解码子模块与所述N个待解码码块一一对应，所述N个预测子模块与所述N个待解码码块一一对应；
    所述输出处理模块包括N个输出处理子模块，所述N个输出处理子模块与所述N个待解码码块一一对应。
  7. 如权利要求6所述的解码器，其特征在于，所述N个类型检测子模块并行地运行，所述N个解码子模块并行地运行，所述N个预测子模块并行地运行，所述N个输出处理模块并行地运行。
  8. 如权利要求1-7任一项所述的解码器，其特征在于，所述待解码码块为物理编码子层PCS解扰后的66比特块，所述66比特块包括2比特同步头以及64比特有效负载，所述64比特有效负载包括8比特块类型信息以及56比特数据；所述介质无关接口信息包括64比特XGMII/XXVGMII接口数据以及8比特XGMII/XXVGMII接口控制信息。
  9. 一种解码方法，其特征在于，所述方法包括：
    检测N个待解码码块的类型，N为大于或等于1的整数；
    根据所述N个待解码码块的类型对所述N个待解码码块进行解码，得到所述N个待解码码块的解码结果；以及，获得所述N个待解码码块中至少一个码块的预测解码方式；
    从所述至少一个码块中每个码块的预测解码方式中选取一种解码方式；
    根据所述解码方式更新所述解码结果，得到并输出所述N个待解码码块对应的介质无关接口信息；
    其中，所述方法还包括以下操作中的至少一项：
    将所述N个解码码块的类型延迟至少一个时钟周期后输出；
    将所述预测解码方式以及所述N个待解码码块的解码结果延迟至少一个时钟周期后输出；
    将从所述至少一个码块中每个码块的预测解码方式中选取的解码方式延迟至少一个时钟周期后输出。
  10. 如权利要求9所述的方法，其特征在于，所述获得所述N个待解码码块中至少一个码块的预测解码方式，包括：
    根据第一待解码码块的类型以及所述第一待解码码块的下一个码块的类型，从所述第一待解码码块的预测解码方式中选择一种解码方式，其中，所述第一待解码码块为所述至少一个码块中的任一码块。
  11. 如权利要求9或10所述的方法，其特征在于，所述根据从所述至少一个码块中每个码块的预测解码方式中选取的解码方式，更新所述解码结果，包括：
    若所述解码及预测模块对第一待解码码块所使用的解码方式与所述状态判决模块从所述第一待解码码块的预测解码方式中选择的解码方式不同，则根据所述状态判决模块从所述第一待解码码块的预测解码方式中选择的解码方式对所述第一待解码码块的解码结果进行更新；其中，所述第一待解码码块为所述至少一个码块中的任一码块。
  12. 如权利要求9-11任一项所述的方法，其特征在于，所述根据从所述部分码块中每个码块的预测解码方式中选取一种解码方式，更新所述解码结果，包括：
    若从第一待解码码块的预测解码方式中选取的解码方式为错误状态下使用的解码方式，则将所述第一待解码码块的解码结果更新为错误码；其中，所述第一待解码码块为所述至少一个码块中的任一码块。
  13. 如权利要求9-11任一项所述的方法，其特征在于，所述根据从所述部分码块中每个码块的预测解码方式中选取一种解码方式，更新所述解码结果，包括：
    若从第一待解码码块的预测码块方式中选取的解码方式为低功耗状态下使用的解码方式，则将所述第一待解码码块的解码结果更新为低功耗控制码；其中，所述第一待解码 码块为所述至少一个码块中的任一码块。
  14. 如权利要求9-13任一项所述的方法，其特征在于，所述待解码码块为物理编码子层PCS解扰后的66比特块，所述66比特块包括2比特同步头以及64比特有效负载，所述64比特有效负载包括8比特块类型信息以及56比特数据；所述介质无关接口信息包括64比特XGMII/XXVGMII接口数据以及8比特XGMII/XXVGMII接口控制信息。
  15. 一种电子设备，其特征在于，所述电子设备包括：一个或多个处理器；一个或多个存储器；其中，所述一个或多个存储器存储有一个或多个计算机程序，所述一个或多个计算机程序包括指令，当所述指令被所述一个或多个处理器执行时，使得所述电子设备执行如权利要求9-14任一项所述的方法。
  16. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质包括计算机程序，当计算机程序在电子设备上运行时，使得所述计算机执行如权利要求9-14任一项所述的方法。
  17. 一种芯片，其特征在于，所述电子设备包括：一个或多个处理器；一个或多个存储器；其中，所述一个或多个存储器存储有一个或多个计算机程序，所述一个或多个计算机程序包括指令，当所述指令被所述一个或多个处理器执行时，使得所述芯片执行如权利要求9-14任一项所述的方法。
  18. 一种计算机程序产品，其特征在于，所述计算机程序产品在被计算机调用时，使得所述计算机执行如权利要求9-14任一项所述的方法。
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