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WO2023000481A1 - 半导体结构、半导体结构的形成方法及存储器 - Google Patents

半导体结构、半导体结构的形成方法及存储器 Download PDF

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Publication number
WO2023000481A1
WO2023000481A1 PCT/CN2021/118803 CN2021118803W WO2023000481A1 WO 2023000481 A1 WO2023000481 A1 WO 2023000481A1 CN 2021118803 W CN2021118803 W CN 2021118803W WO 2023000481 A1 WO2023000481 A1 WO 2023000481A1
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Prior art keywords
layer
barrier layer
conductive layer
semiconductor structure
conductive
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PCT/CN2021/118803
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English (en)
French (fr)
Inventor
吴双双
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长鑫存储技术有限公司
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Priority to US17/648,675 priority Critical patent/US20230024544A1/en
Publication of WO2023000481A1 publication Critical patent/WO2023000481A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

Definitions

  • Embodiments of the present application relate to but are not limited to a semiconductor structure, a method for forming the semiconductor structure, and a memory.
  • the density of devices in integrated circuits is getting higher and higher, the feature size of semiconductor devices is continuously reduced, and the electrode area of semiconductor structures is also continuously reduced.
  • a metal interconnection structure will be fabricated on the electrodes.
  • the introduction of the metal interconnection structure can not only increase the integration level of the device and improve the working speed of the device, but also can reduce the cost of the chip and simplify the device manufacturing process.
  • the barrier layer plays a key role in the metal interconnection structure and directly affects the performance of the device.
  • the contact surfaces of different conductive layers become uneven.
  • the existing In the technology the contact area between the barrier layer and different conductive layers is small, and the adhesion effect between the barrier layer and the conductive layer is not good, which may cause separation between different conductive layers in the subsequent manufacturing process and affect the performance of the semiconductor structure.
  • an embodiment of the present application provides a semiconductor structure on the one hand, including: a substrate; a first conductive layer, a part of the first conductive layer is located in the substrate, and the rest of the first conductive layer Partially protruding above the base; a barrier layer, the barrier layer is located on the base, and at least located on the sidewall of the first conductive layer protruding from the base; a dielectric layer, the dielectric layer is located On the barrier layer; a second conductive layer, the second conductive layer runs through the dielectric layer and the barrier layer, the second conductive layer is in contact with the sidewall of the barrier layer, and the second conductive layer A layer is in contact with at least part of the upper surface of the first conductive layer.
  • another embodiment of the present application further provides a method for forming a semiconductor structure, including: providing a substrate; forming a first conductive layer, a part of the first conductive layer is located in the substrate, and the The rest of the first conductive layer protrudes above the base; forming a barrier layer on the base and at least on sidewalls of the first conductive layer protruding from the base; forming a dielectric layer, the dielectric layer covers the surface of the barrier layer; forming a second conductive layer, the second conductive layer runs through the dielectric layer and the barrier layer, the second conductive layer and the barrier layer The sidewalls are in contact, and the second conductive layer is in contact with at least part of the upper surface of the first conductive layer.
  • another embodiment of the present application further provides a memory, including the semiconductor structure described in any one of the foregoing.
  • Fig. 1 is a structural schematic diagram of a semiconductor structure
  • FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present application.
  • 4 to 11 are structural schematic diagrams corresponding to each step of a method for forming a semiconductor structure provided by another embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure.
  • a semiconductor structure includes: a substrate 100, an electrode 101 is provided in the substrate 100; a first conductive layer 102, the first conductive layer 102 is located in the substrate 100, and the first The conductive layer 102 is in contact with the electrode 101; the barrier layer 104, the barrier layer 104 is located on the substrate 100, and the top surface of the first conductive layer 102 exposed by the substrate 100; the dielectric layer 105, the dielectric layer 105 is located on the barrier layer 104; The second conductive layer 106, the second conductive layer 106 penetrates the dielectric layer 105 and the barrier layer 104, the second conductive layer 106 is in contact with the sidewall of the barrier layer 104, and the second conductive layer 106 is in contact with part of the upper surface of the first conductive layer 102 touch.
  • the barrier layer 104 is only located on part of the upper surface of the first conductive layer 102, and the contact area between the barrier layer 104 and the first conductive layer 102 is small, resulting in poor adhesion and fixation effect between the first conductive layer 102 and the barrier layer 104;
  • the bottom surfaces of the barrier layer 104 and the second conductive layer 106 are on the same horizontal plane, in the subsequent process technology, when the process stress causes the position of the second conductive layer 106 to change, the position change direction of the barrier layer 104 under the process stress is the same as that of the second conductive layer 106.
  • the position of the second conductive layer 106 changes in the same direction, which cannot fix the second conductive layer 106 .
  • the barrier layer is not only in contact with the sidewall of the first conductive layer protruding from the substrate, but also contacts the sidewall of the second conductive layer, so that the same barrier layer and different conductive layers There are contacts between them, which is beneficial to use the barrier layer to fix the position between different conductive layers.
  • the barrier layer is in contact with the side wall of the conductive layer, which is beneficial to increase the contact area, and the larger the contact area, the better the adhesion and fixation effect of the barrier layer to the conductive layer.
  • FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application.
  • the semiconductor structure includes: a substrate 200; a first conductive layer 202, a part of the first conductive layer 202 is located in the substrate 200, and the rest of the first conductive layer 202 protrudes above the substrate 200; a barrier layer 204, a barrier layer 204 is located on the substrate 200, and at least located on the sidewall of the first conductive layer 202 protruding from the substrate 200; the dielectric layer 205, the dielectric layer 205 is located on the barrier layer 204; the second conductive layer 206, the second conductive layer 206 penetrates the dielectric layer 205 and the barrier layer 204 , the second conductive layer 206 is in contact with the sidewall of the barrier layer 204 , and the second conductive layer 206 is in contact with at least part of the upper surface of the first conductive layer 202 .
  • the barrier layer 204 is not only in contact with the sidewall of the first conductive layer 202 protruding from the substrate 200, but also in contact with the sidewall of the second conductive layer 206, so that between the same barrier layer 204 and different conductive layers All have contacts, which is beneficial to use the barrier layer 204 to fix the positions between different conductive layers.
  • it is not easy to be affected by the process stress so that the positional relationship between different conductive layers changes, thereby generating gaps. It affects the performance of the semiconductor structure; at the same time, the barrier layer 204 is in contact with the sidewall of the conductive layer, which is beneficial to increase the contact area. The larger the contact area, the better the adhesion and fixation effect of the barrier layer 204 to the conductive layer.
  • the material of the base 200 is an isolation material for isolating the conductive layer from other conductive structures.
  • the material of the base 200 is silicon dioxide.
  • the substrate 200 may also be silicon nitride or silicon carbide.
  • Some embodiments are to form a metal interconnection structure on the semiconductor substrate to be processed on which the source electrode, drain electrode and gate electrode have been formed, so the substrate 200 may also have an electrode 201, which is an electrical connection structure drawn from the semiconductor substrate.
  • the specific material Metal materials such as metal tungsten and metal silver can be used.
  • the width of the upper surface of the electrode 201 is larger than the width of the lower surface.
  • the surface of the electrode 201 in contact with the first conductive layer 202 is the upper surface. The larger the width of the upper surface, the larger the contact area, and the larger the contact area, the lower the contact resistance, which can effectively improve the conductivity of the semiconductor structure.
  • the surface of the electrode 201 may have a protective layer (not shown in the figure), and the material of the protective layer may be titanium nitride, which can effectively prevent the ions in the electrode 201 from diffusing outward and causing adverse effects.
  • the material of the first conductive layer 202 is metal copper, and the resistivity of metal copper is low, which is beneficial to reduce the production cost of the semiconductor structure while improving the conduction effect of the semiconductor structure.
  • the material of the first conductive layer may also be metal aluminum or metal cobalt.
  • the first conductive layer 202 may be directly formed by using a copper sputtering process. In other embodiments, the first conductive layer may also be formed by chemical vapor deposition.
  • part of the first conductive layer 202 is located in the substrate 200, and the rest of the first conductive layer 202 protrudes above the substrate 200, because the barrier layer 204 formed subsequently needs to be in contact with the part of the first conductive layer 202.
  • the sidewalls are in contact, so the substrate 200 needs to expose part of the first conductive layer 202 .
  • the thickness ratio of the first conductive layer 202 protruding from the substrate 200 to the first conductive layer 202 inside the substrate 200 is 1:1 ⁇ 1:2.
  • the base 200 Since part of the first conductive layer 202 is located in the base 200, the base 200 also has a fixing effect on the first conductive layer 202, and the ratio of the thickness of the first conductive layer 202 protruding from the base 200 to the first conductive layer 202 located in the base 200 Keeping within the above range, while ensuring the fixing effect of the substrate 200 on the first conductive layer 202 , a sufficient contact area is reserved for the barrier layer 204 .
  • the first conductive layer 202 is not only in contact with the upper surface of the electrode 201, but also part of the sidewall of the electrode 201, the contact area is relatively large, so the contact resistance between the first conductive layer 202 and the electrode 201 is low, further improving the conductivity of the semiconductor structure. Effect.
  • the surface of the first conductive layer 202 can also have a protective layer (not shown in the figure), which can prevent the outward diffusion of ions in the first conductive layer 202, and the material of the protective layer on the surface of the first conductive layer 202 can be tantalum metal or Tantalum nitride.
  • it further includes: a stop layer 203 located on the upper surface of the substrate 200 , and the stop layer 203 is located between the substrate 200 and the barrier layer 204 .
  • the material of the stop layer 203 can be silicon nitride or silicon carbonitride, because when forming the first conductive layer 202, in order to make part of the first conductive layer 202 be located on the substrate 200, after the formation of the first conductive layer 202, Part of the substrate 200 is removed, and the stop layer 203 can be used as an etching stop layer in the process of removing part of the substrate 200, effectively preventing over-etching.
  • the barrier layer 204 is not only located on the sidewall of the first conductive layer 202 protruding above the substrate 200 , but also contacts part of the upper surface of the first conductive layer 202 .
  • the contact area between the barrier layer 204 and the first conductive layer 202 is larger, which is conducive to improving the adhesion and fixation effect of the barrier layer 204 to the first conductive layer 202;
  • the first conductive layer 202 is subjected to process stress in a certain direction, even if the barrier layer 204 in contact with one side of the first conductive layer 202 cannot exert the adhesion effect, the barrier layer 204 in contact with the other surfaces of the first conductive layer 202 will also exert adhesion.
  • the adhesion effect ensures that the barrier layer 204 and the first conductive layer 202 have better adhesion effect in most cases.
  • the barrier layer 204 may be a double-layer structure, including a first barrier layer 214 and a second barrier layer 224 stacked in sequence, and the materials of the first barrier layer 214 and the second barrier layer 224 are different;
  • the barrier layer 224 , the first barrier layer 214 and the first conductive layer 202 enclose a hole; the second conductive layer 206 also fills the hole.
  • the barrier layer can also be a single-layer structure.
  • the upper surface of the first conductive layer 202 exposes a larger area for contacting with the second conductive layer 206, which is conducive to improving the first
  • the contact area between the conductive layer 202 and the second conductive layer 206 reduces the contact resistance and further improves the conductive effect of the entire semiconductor structure; because of the holes, the first barrier layer 214 and the second barrier layer 224 will form a snap-like structure, the second conductive layer 206 that fills the hole is stuck in it, and in the subsequent process, no matter the second conductive layer 206 is subjected to process stress in any direction, the first barrier layer 214 and the second barrier layer 224 will hold the second conductive layer 206
  • the second conductive layer 206 is fixed to ensure that the second conductive layer 206 will not detach from the surface of the first conductive layer 202 .
  • the thickness of the first barrier layer 214 is smaller than the thickness of the second barrier layer 224 .
  • the thickness of the second barrier layer 224 is larger, which is conducive to ensuring Even if the first barrier layer 214 is over-etched, the upper surface of the first conductive layer 202 still has a larger barrier layer 204; the thickness of the first barrier layer 214 is smaller, which is beneficial to control the etching effect when forming holes.
  • the thickness ratio of the first barrier layer 214 and the second barrier layer 224 is 1:3 ⁇ 1:4.
  • the thickness of the first barrier layer 214 is 5 nanometers to 10 nanometers, specifically 6 nanometers, 7 nanometers or 8 nanometers; the thickness of the second barrier layer 224 15 nanometers to 40 nanometers, specifically 20 nanometers, 25 nanometers or 30 nanometers.
  • the first barrier layer 214 ensures the adhesion effect, it will not be difficult to control the etching effect when forming holes due to being too thick; the second barrier layer 224 will not cause the first barrier layer 214 to be over-etched due to being too thin.
  • the adhesion effect of the entire barrier layer 204 is not good when it is etched.
  • the material of the first barrier layer 214 includes silicon oxynitride or silicon fluoride nitride; the material of the second barrier layer 224 includes silicon nitride or silicon carbonitride.
  • the etching selectivity ratio of the first barrier layer 214 is greater than the etching selectivity ratio of the second barrier layer 224, which is beneficial to avoid damaging the first barrier layer 214 when etching the first barrier layer 214 to form holes.
  • the second barrier layer 224 has an excessive effect.
  • the material of the dielectric layer 205 can be the same as that of the substrate 200 to prevent electrical contact between different second conductive layers 206 , and the material of the dielectric layer 205 can specifically be silicon dioxide, silicon nitride or silicon carbide.
  • the width of the second conductive layer 206 located in the vicinity of the second barrier layer 224 is smaller than the width of the top surface of the second conductive layer 206; such arrangement ensures that the upper surface of the first conductive layer 202 has a larger area.
  • the area of the exposed top surface of the second conductive layer 206 used for subsequent detection or wiring is increased.
  • the material of the second conductive layer 206 may be metal tungsten. In some other embodiments, the material of the second conductive layer may also be a metal material with high conductivity such as metal silver or metal cobalt.
  • the surface of the second conductive layer 206 can have a protective layer (not shown in the figure), and the material of the protective layer can be titanium nitride, which can effectively prevent the ions in the second conductive layer 206 from diffusing outward and causing adverse effects.
  • FIG. 3 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present application.
  • the second conductive layer 206 is in contact with the entire upper surface of the first conductive layer 202 .
  • the conductive layer 202 and the second conductive layer 206 have the largest contact area to reduce contact resistance.
  • the barrier layer 204 is not only in contact with the sidewall of the first conductive layer 202 protruding from the substrate 200, but also in contact with the sidewall of the second conductive layer 206, so that the same barrier layer 204 and different conductive There are contacts between the layers, which is beneficial to use the barrier layer 204 to fix the positions between the different conductive layers.
  • another embodiment of the present application further provides a method for forming a semiconductor structure.
  • the semiconductor structure formed by the method for forming a semiconductor structure provided in another embodiment of the present application is the same as the semiconductor structure provided in the foregoing embodiments.
  • a method for forming a semiconductor structure provided by another embodiment of the present application will be described in detail below with reference to the accompanying drawings.
  • 4 to 11 are structural schematic diagrams corresponding to each step of a method for forming a semiconductor structure provided by another embodiment of the present application.
  • a substrate 300 is provided.
  • the material of the base 300 is an isolation material for isolating the conductive layer from other conductive structures.
  • the material of the base 300 is silicon dioxide.
  • the substrate 300 may also be silicon nitride or silicon carbide.
  • Some embodiments are to form a metal interconnection structure on the semiconductor substrate to be processed on which the source electrode, drain electrode and gate electrode have been formed, so the substrate 300 may also have an electrode 301, which is an electrical connection structure drawn from the semiconductor substrate, and the specific material Metal materials such as metal tungsten and metal silver can be used.
  • the width of the upper surface of the electrode 301 is larger than the width of the lower surface.
  • the surface of the electrode 301 in contact with the subsequently formed first conductive layer is the upper surface.
  • the larger the width of the upper surface the larger the contact area.
  • a first conductive layer 302 is formed, a part of the first conductive layer 302 is located in the base 300 , and the rest of the first conductive layer 302 protrudes above the base 300 .
  • a stop layer 303 is formed on the upper surface of the substrate 300 .
  • the stop layer 303 is formed by an atomic layer deposition process, and the material of the stop layer 303 can be silicon nitride or silicon carbonitride, because when the first conductive layer is subsequently formed, in order to make part of the first conductive layer Above the substrate 300 , the sacrificial layer needs to be removed after the first conductive layer is formed, and the stop layer 303 can be used as an etching stop layer in the process of removing the sacrificial layer to effectively prevent over-etching.
  • a sacrificial layer 307 is formed on the substrate 300 , specifically the sacrificial layer 307 is located on the upper surface of the stop layer 303 .
  • a chemical vapor deposition process is used to form the sacrificial layer 307, the material of the sacrificial layer 307 is the same as that of the substrate 300, the materials of the substrate 300 and the sacrificial layer 307 are the same, and the rate of etching the sacrificial layer 307 and the substrate 300 can be Consistent, more conducive to the implementation of the process.
  • the sacrificial layer 307 and the substrate 300 are patterned to form a first trench 308 in the sacrificial layer 307 and the substrate 300 .
  • a wet etching process is used to remove part of the sacrificial layer 307 , part of the stop layer 303 and part of the substrate 300 to form the first trench 308 for subsequent formation of the first conductive layer.
  • the first conductive layer 302 filling the first trench 308 (see FIG. 6 ) is formed; the sacrificial layer 307 (see FIG. 6 ) is removed until the stop layer 303 is exposed.
  • the first conductive layer 302 is formed by a chemical vapor deposition process; the sacrificial layer 307 is removed by a wet etching process, and the stop layer 303 is used as an etching stop layer.
  • the material of the first conductive layer 302 is metal copper, which has a low resistivity, which is beneficial to reduce the production cost of the semiconductor structure while improving the conduction effect of the semiconductor structure.
  • the material of the first conductive layer may also be metal aluminum or metal cobalt.
  • part of the first conductive layer 302 is located in the substrate 300, and the remaining part of the first conductive layer 302 protrudes above the substrate 300, because the barrier layer 304 formed subsequently needs to be in contact with the part of the first conductive layer 302. The sidewalls are in contact, so the substrate 300 needs to expose part of the first conductive layer 302 .
  • the first conductive layer 302 is not only in contact with the upper surface of the electrode 301, but also part of the sidewall of the electrode 301, the contact area is relatively large, so the contact resistance between the first conductive layer 302 and the electrode 301 is low, further improving the conductivity of the semiconductor structure. Effect.
  • a barrier layer 304 is formed, and the barrier layer 304 is located on the substrate 300, and at least on the sidewall of the first conductive layer 302 protruding from the substrate 300; a dielectric layer 305 is formed, and the dielectric layer 305 covers the barrier layer 304 surface; form a second conductive layer 306, the second conductive layer 306 runs through the dielectric layer 305 and the barrier layer 304, the second conductive layer 306 is in contact with the sidewall of the barrier layer 304, and the second conductive layer 306 is in contact with the first conductive layer 303 At least part of the upper surface is in contact.
  • the barrier layer 304 is not only in contact with the sidewall of the first conductive layer 302 protruding from the substrate 300, but also in contact with the sidewall of the second conductive layer 306, there is no difference between the same barrier layer 304 and different conductive layers. There is contact, which is beneficial to use the barrier layer 304 to fix the position between different conductive layers. In the subsequent process, it is not easy to be affected by the process stress so that the positional relationship between different conductive layers will change, thereby generating gaps, affecting The performance of the semiconductor structure; at the same time, the barrier layer 304 is in contact with the sidewall of the conductive layer, which is beneficial to increase the contact area. The larger the contact area, the better the adhesion and fixation effect of the barrier layer 304 to the conductive layer.
  • an initial barrier layer 334 is formed, and the initial barrier layer 334 covers the exposed surface of the first conductive layer 302, and the initial barrier layer 334 is located on the substrate 300; an initial dielectric layer 315 is formed, and the initial dielectric layer 315 covers the initial the upper surface of the barrier layer 334 .
  • the initial barrier layer 304 includes an initial first barrier layer 344 and an initial second barrier layer 354, and the initial first barrier layer 304 is first formed on the substrate 300 and the surface of the first conductive layer 302 protruding from the substrate 300 by using an atomic deposition process.
  • a barrier layer 344, and then an initial second barrier layer 354 is formed on the surface of the initial first barrier layer 344 by atomic deposition; and an initial dielectric layer 315 is formed by chemical vapor deposition.
  • the material of the initial first barrier layer 344 is different from the material of the initial second barrier layer 354, the material of the initial first barrier layer 344 includes silicon oxynitride or silicon fluoride nitride; the material of the initial second barrier layer 354 Includes silicon nitride or silicon carbonitride.
  • the etching selectivity ratio of the initial first barrier layer 344 is greater than the etching selectivity ratio of the initial second barrier layer 354, which is beneficial to prevent holes from being formed by subsequent etching of the first barrier layer. Excessive impact on the second barrier layer.
  • the material of the initial dielectric layer 315 can be the same as that of the substrate 300, which can prevent electrical contact between different second conductive layers formed later.
  • the material of the initial dielectric layer 315 can specifically be silicon dioxide, silicon nitride or silicon carbide.
  • the initial dielectric layer 315 and the initial barrier layer 334 are patterned until at least part of the surface of the first conductive layer 302 is exposed to form the second groove 309, and the remaining initial dielectric layer 315 is used as the dielectric layer 305, and the remaining initial dielectric layer 315 is used as the dielectric layer 305.
  • Barrier layer 334 acts as barrier layer 304 .
  • the barrier layer 304 includes a first barrier layer 314 and a second barrier layer 324 stacked in sequence, and the materials of the first barrier layer 314 and the second barrier layer 324 are different.
  • the thickness of the first barrier layer 314 is smaller than the thickness of the second barrier layer 324 .
  • the thickness of the second barrier layer 324 is larger, which is beneficial It is ensured that even if the first barrier layer 314 is over-etched, the upper surface of the first conductive layer 302 still has a larger area of the barrier layer 304; the thickness of the first barrier layer 314 is small, which is beneficial to control the etching effect when forming holes.
  • the thickness ratio of the first barrier layer 314 and the second barrier layer 324 is 1:3 ⁇ 1:4.
  • the thickness of the first barrier layer 314 is 5 nanometers to 10 nanometers, specifically 6 nanometers, 7 nanometers or 8 nanometers; the thickness of the second barrier layer 324 15 nanometers to 40 nanometers, specifically 20 nanometers, 25 nanometers or 30 nanometers.
  • the first barrier layer 314 ensures the adhesion effect, it will not be difficult to control the etching effect when forming holes due to being too thick; the second barrier layer 324 will not cause the first barrier layer 314 to be over-etched due to being too thin.
  • the adhesion effect of the entire barrier layer 304 is not good when it is etched.
  • the second trench 309 after forming the second trench 309, it also includes: performing wet etching on the first barrier layer 314 exposed by the second trench 309, so that the second barrier layer 324, the first conductive layer 302 and the remaining The first barrier layer 314 surrounds the hole 310 .
  • the upper surface of the first conductive layer 302 exposes a larger area for contact with the second conductive layer 306, which is conducive to increasing the
  • the contact area of the first conductive layer 302 and the second conductive layer 306 reduces the contact resistance and further improves the conductive effect of the entire semiconductor structure; because of the hole 310, the first barrier layer 314 and the second barrier layer 324 will form a structure similar to The buckle-like structure clamps the second conductive layer 306 filling the hole 310.
  • the first barrier layer 314 and the second barrier layer 324 will fix the second conductive layer 306 to ensure that the second conductive layer 306 will not detach from the surface of the first conductive layer 302 .
  • the etching selectivity of the wet etching process to the first barrier layer 314 is greater than that of the second barrier layer 324 . Therefore, the second barrier layer 324 will not be affected during the wet etching process.
  • the etching solution selected for the wet etching process includes hydrofluoric acid aqueous solution.
  • the mass ratio of hydrofluoric acid to water is 1:50-1:100, specifically 1:60, 1:70 or 1:80.
  • the second conductive layer 306 is formed to fill the second trench 309 (see FIG. 10 ), and the second conductive layer 306 is also filled with the hole 310 (see FIG. 10 ).
  • the width of the second conductive layer 306 located in the vicinity of the second barrier layer 324 is smaller than the width of the top surface of the second conductive layer 306; in this way, the upper surface of the first conductive layer 302 is guaranteed to have a larger area.
  • the area of the exposed top surface of the second conductive layer 306 used for subsequent detection or wiring is increased.
  • the second conductive layer 306 is formed by a chemical vapor deposition process, and the material of the second conductive layer 306 may be metal tungsten. In some other embodiments, the material of the second conductive layer may also be a metal material with high conductivity such as metal silver or metal cobalt.
  • the formed barrier layer 304 is not only in contact with the sidewall of the first conductive layer 302 protruding from the substrate 300, but also in contact with the sidewall of the second conductive layer 306, the same barrier layer 304 and There are contacts between different conductive layers, which is beneficial to use the barrier layer 304 to fix the positions between different conductive layers.
  • Another embodiment of the present application further provides a memory, including: the semiconductor structure provided in the above embodiment.
  • the memory includes a barrier layer in the semiconductor structure that not only contacts the sidewall of the first conductive layer protruding from the substrate, but also contacts the sidewall of the second conductive layer, so that the same barrier layer and different There are contacts between the conductive layers, which is beneficial to use the barrier layer to fix the position between different conductive layers. In the subsequent process, it is not easy to be affected by the process stress to change the positional relationship between different conductive layers. Furthermore, a gap is generated, which affects the performance of the semiconductor structure; at the same time, the barrier layer is in contact with the side wall of the conductive layer, which is beneficial to increase the contact area. The larger the contact area, the better the adhesion and fixation effect of the barrier layer to the conductive layer.
  • the barrier layer not only contacts the sidewall of the first conductive layer protruding from the base, but also contacts the sidewall of the second conductive layer, so that the same barrier layer and different conductive layers There are contacts between them, which is beneficial to use the barrier layer to fix the position between different conductive layers.
  • it is not easy to be affected by stress, so that the positional relationship between different conductive layers changes, thereby generating gaps;
  • the barrier layer is in contact with the side wall of the conductive layer, which is beneficial to increase the contact area, and the larger the contact area, the better the adhesion and fixation effect of the barrier layer to the conductive layer.

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Abstract

本申请实施例涉及半导体领域，提供一种半导体结构、半导体结构的形成方法及存储器，半导体结构包括：基底；第一导电层，所述第一导电层的部分位于所述基底内，所述第一导电层的其余部分凸出于所述基底上方；阻挡层，所述阻挡层位于所述基底上，以及至少位于凸出于所述基底的所述第一导电层的侧壁；介质层，所述介质层位于所述阻挡层上；第二导电层，所述第二导电层贯穿所述介质层和所述阻挡层，所述第二导电层与所述阻挡层侧壁相接触，且所述第二导电层与所述第一导电层的至少部分上表面相接触，至少可以提高半导体结构的性能。

Description

半导体结构、半导体结构的形成方法及存储器
相关申请的交叉引用
本申请要求在2021年07月20日提交中国专利局、申请号为202110819890.9、申请名称为“半导体结构、半导体结构的形成方法及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及但不限于一种半导体结构、半导体结构的形成方法及存储器。
背景技术
随着集成电路技术的快速发展，集成电路中器件的密集度越来越高，半导体器件的特征尺寸不断减小，半导体结构的电极面积也不断减小，在制作过程中，为了引线或测试需要，会在电极上制作金属互联结构。金属互联结构的引入不仅可以增加器件集成度以及提升器件工作速度，同时，还可以降低芯片成本和简化器件制备工艺。
而阻挡层在金属互联结构中起到关键作用，直接影响器件性能的好坏，在金属互联结构加工的过程中，经过多步加工工艺之后，不同的导电层接触表面变得高低不平，现有技术中阻挡层与不同导电层的接触面积较小，阻挡层与导电层的粘附效果不佳，在后续的制程工艺中可能导致不同导电层之间脱离，影响半导体结构的性能。
如何改进金属互联结构中不同导电层之间的接触效果，成为本领域技术人员亟须解决的问题。
发明内容
根据本申请一些实施例，本申请实施例一方面提供一种半导体结构，包括：基底；第一导电层，所述第一导电层的部分位于所述基底内，所述第一导电层的其余部分凸出于所述基底上方；阻挡层，所述阻挡层位于所述基底上，以及至少位于凸出于所述基底的所述第一导电层的侧壁；介质层，所述介质层位于所述阻挡层上；第二导电层，所述第二导电层贯穿所述介质层和所述阻挡层，所述第二导电层与所述阻挡层侧壁相接触，且所述第二导电层与所述第一导电层的至少部分上表面相接触。
根据本申请一些实施例，本申请实施例另一方面还提供一种半导体结构的形成方法，包括：提供基底；形成第一导电层，所述第一导电层的部分位于所述基底内，所述第一导电层的其余部分凸出于所述基底上方；形成阻挡层，所述阻挡层位于所述基底上，以及至少位于凸出于所述基底的所述第一导电层的侧壁；形成介质层，所述介质层覆盖所述阻挡层的表面；形成第二导电层，所述第二导电层贯穿所述介质层和所述阻挡层，所述第二导电层与所述阻挡层侧壁相接触，且所述第二导电层与所述第一导电层的至少部分上表面相接触。
根据本申请一些实施例，本申请实施例再一方面还提供一种存储器，包括上述任一项所述的半导体结构。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种半导体结构的结构示意图；
图2为本申请一实施例提供的半导体结构的结构示意图；
图3为本申请一实施例提供的另一半导体结构的结构示意图；
图4～图11为本申请另一实施例提供的半导体结构的形成方法各步骤对应的结构示意图。
附图标记说明：
100、200、300-基底；101、201、301-电极；102、202、302-第一导电层；203、303-停止层；104、204、304-阻挡层；105、205、305-介质层；106、206、306-第二导电层；214、314-第一阻挡层；224、324-第二阻挡层；307-牺牲层；308-第一沟槽；315-初始介质层；344-初始第一阻挡层；354-初始第二阻挡层；309-第二沟槽；310-孔洞。
具体实施方式
由背景技术可知，半导体结构不同导电层之间的接触效果不佳。
图1为一种半导体结构的结构示意图。
现结合一种半导体结构进行具体说明，参考图1，一种半导体结构，包括：基底100， 基底100内具有电极101；第一导电层102，第一导电层102位于基底100内，且第一导电层102与电极101相接触；阻挡层104，阻挡层104位于基底100上，以及位于基底100暴露出的第一导电层102的顶面；介质层105，介质层105位于阻挡层104上；第二导电层106，第二导电层106贯穿介质层105和阻挡层104，第二导电层106与阻挡层104侧壁相接触，且第二导电层106与第一导电层102的部分上表面相接触。
可以得到，阻挡层104只位于第一导电层102的部分上表面，阻挡层104和第一导电层102的接触面积较小，导致第一导电层102和阻挡层104的黏附固定效果不佳；同时由于阻挡层104和第二导电层106的底面在同一水平面上，在后续的制程工艺中，制程应力使得第二导电层106位置变化时，阻挡层104在该制程应力下的位置变化方向与第二导电层106的位置变化方向相同，不能起到固定第二导电层106的作用。
本申请实施提供一种半导体结构，阻挡层不仅与位于凸出于基底的第一导电层的侧壁相接触，还与第二导电层的侧壁相接触，这样同一阻挡层和不同的导电层之间都有接触，有利于利用阻挡层将不同的导电层之间的位置固定，在后续的工艺中，不容易受应力的影响使得不同导电层之间的位置关系产生变化，进而产生间隙；同时阻挡层和导电层的侧壁相接触，有利于增加接触面积，接触面积越大，阻挡层对导电层的粘附固定效果越好。
下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图2为本申请一实施例提供的半导体结构的结构示意图。
参考图2，半导体结构包括：基底200；第一导电层202，第一导电层202的部分位于基底200内，第一导电层202的其余部分凸出于基底200上方；阻挡层204，阻挡层204位于基底200上，以及至少位于凸出于基底200的第一导电层202的侧壁；介质层205，介质层205位于阻挡层204上；第二导电层206，第二导电层206贯穿介质层205和阻挡层204，第二导电层206与阻挡层204侧壁相接触，且第二导电层206与第一导电层202的至少部分上表面相接触。
其中，阻挡层204不仅与位于凸出于基底200的第一导电层202的侧壁相接触，还与第二导电层206的侧壁相接触，这样同一阻挡层204和不同的导电层之间都有接触，有利于利用阻挡层204将不同的导电层之间的位置固定，在后续的工艺中，不容易受制程应力的影响使得不同导电层之间的位置关系产生变化，进而产生间隙，影响半导体结 构的性能；同时阻挡层204和导电层的侧壁相接触，有利于增加接触面积，接触面积越大，阻挡层204对导电层的粘附固定效果越好。
以下将结合附图对本申请实施例进行更为详细的说明。
基底200的材料为隔离材料，用于将导电层与其他导电结构隔离，一些实施例中，基底200的材料为二氧化硅。在另一些实施例中，基底200也可以氮化硅或碳化硅。
一些实施例为在已经形成源电极、漏电极和栅电极的待加工半导体基片上形成金属互联结构，所以基底200内还可以具有电极201，电极201为半导体基片上引出的电连接结构，具体材料可以为金属钨、金属银等金属材料。
电极201的上表面的宽度大于下表面的宽度。电极201与第一导电层202接触的表面为上表面，上表面的宽度越大，接触面积就越大，接触面积越大，接触电阻越低，可以有效提高半导体结构的导电效率。
电极201表面可以具有保护层(图中未示出)，保护层的材料可以为氮化钛，可以有效防止电极201内的离子向外扩散，造成不良影响。
一些实施例中，第一导电层202的材料为金属铜，金属铜的电阻率较低，在提高半导体结构导电效果的同时，有利于降低半导体结构的生产成本。在另一些实施例中，第一导电层的材料也可以为金属铝或者金属钴。
一些实施例中，可以采用铜溅射工艺直接形成第一导电层202。在另一些实施例中，也可以采用化学气相沉积工艺形成第一导电层。
一些实施例中，第一导电层202的部分位于基底200内，第一导电层202的其余部分凸出于基底200上方，这是由于后续形成的阻挡层204要与第一导电层202的部分侧壁相接触，所以基底200需要暴露出部分第一导电层202。
具体地，在垂直于基底200上表面的方向上，凸出基底200的第一导电层202与位于基底200内的第一导电层202的厚度比为1：1～1：2。
由于部分第一导电层202位于基底200内，所以基底200对第一导电层202也具有固定效果，凸出基底200的第一导电层202与位于基底200内的第一导电层202的厚度比保持在上述范围内，在保证了基底200对第一导电层202的固定效果的同时，给阻挡层204预留了足够的接触面积。
第一导电层202不仅与电极201的上表面接触，还与电极201的部分侧壁接触，接触面积较大，所以第一导电层202与电极201的接触电阻较低，进一步提高半导体结构的导电效果。
第一导电层202的表面也可以具有保护层(图中未示出)，可以防止第一导电层202内的离子向外扩散，第一导电层202表面的保护层的材料可以为钽金属或氮化钽。
一些实施例中，还包括：停止层203，停止层203位于基底200上表面，且停止层203位于基底200和阻挡层204之间。
停止层203的材料可以为氮化硅或碳氮化硅，由于在形成第一导电层202的时候，为了使得部分第一导电层202位于基底200上方，需要在形成第一导电层202之后，去除部分基底200，停止层203可以作为去除部分基底200工艺的刻蚀停止层，有效防止过刻蚀。
一些实施例中，阻挡层204不仅位于凸出于基底200上方的第一导电层202的侧壁，还与第一导电层202的部分上表面接触。阻挡层204与第一导电层202的接触面积较大，有利于提高阻挡层204对于第一导电层202的黏附固定效果；同时由于阻挡层204与第一导电层202的接触面不止一个，所以当第一导电层202受到某一方向的制程应力时，即使与第一导电层202其中一面接触的阻挡层204不能发挥黏附效果，与第一导电层202其他面接触的阻挡层204也会发挥黏附效果，保证了阻挡层204和第一导电层202在多数情况下具有较好的黏附效果。
一些实施例中，阻挡层204可以为双层结构，包括依次堆叠的第一阻挡层214和第二阻挡层224，且第一阻挡层214的材料和第二阻挡层224的材料不同；第二阻挡层224、第一阻挡层214和第一导电层202围成孔洞；第二导电层206还填充满孔洞。在另一些实施例中，阻挡层也可以为单层结构。
由于第二阻挡层224、第一阻挡层214和第一导电层202围成孔洞，所以第一导电层202上表面暴露出可供与第二导电层206接触的面积较大，有利于提高第一导电层202和第二导电层206的接触面积，减小接触电阻，进一步提高整个半导体结构的导电效果；因为具有孔洞，第一阻挡层214和第二阻挡层224会组成一个类似于卡扣状的结构，将填充孔洞的第二导电层206卡在其中，在后续的制程过程中，无论第二导电层206受到任何方向的制程应力，第一阻挡层214和第二阻挡层224都会将第二导电层206固定，保证第二导电层206不会脱离第一导电层202的表面。
一些实施例中，在垂直于第一导电层202上表面的方向上，第一阻挡层214的厚度小于第二阻挡层224的厚度。
在刻蚀第一阻挡层214形成孔洞时，容易出现过刻蚀的现象，导致位于第一导电层202上表面的阻挡层204较少，所以第二阻挡层224的厚度较大，有利于保证即使第一阻挡层214过刻蚀，第一导电层202上表面仍具有较大面积的阻挡层204；第一阻挡层 214的厚度较小，在形成孔洞时，有利于控制刻蚀效果。
一些实施例中，在垂直于第一导电层202上表面的方向上，第一阻挡层214和第二阻挡层224的厚度比为1：3～1：4。
具体地，在垂直于第一导电层202上表面的方向上，第一阻挡层214的厚度为5纳米～10纳米，具体可以为6纳米、7纳米或8纳米；第二阻挡层224的厚度为15纳米～40纳米，具体可以为20纳米、25纳米或30纳米。
在此范围内，第一阻挡层214在保证了黏附效果的同时不会由于过厚造成形成孔洞时难以控制刻蚀效果；第二阻挡层224不会由于过薄造成第一阻挡层214过刻蚀时整个阻挡层204的黏附效果不佳。
一些实施例中，第一阻挡层214的材料包括氮氧化硅或氮氟化硅；第二阻挡层224的材料包括氮化硅或碳氮化硅。在同样的湿法刻蚀工艺下，第一阻挡层214的刻蚀选择比大于第二阻挡层224的刻蚀选择比，这样有利于在刻蚀第一阻挡层214形成孔洞时不会对第二阻挡层224造成过大的影响。
一些实施例中，介质层205的材料与基底200的材料可以相同，防止不同的第二导电层206电接触，介质层205的材料具体可以为二氧化硅、氮化硅或碳化硅。
一些实施例中，位于第二阻挡层224附近区域的第二导电层206的宽度小于第二导电层206顶面的宽度；如此设置，在保证位于第一导电层202上表面具有面积较大的阻挡层204的同时，提高后续用于检测或者引线的第二导电层206暴露出的顶面的面积。
一些实施例中，第二导电层206的材料可以为金属钨。在另一些实施例中，第二导电层的材料还可以为金属银或金属钴等导电率较高的金属材料。
第二导电层206表面可以具有保护层(图中未示出)，保护层的材料可以为氮化钛，可以有效防止第二导电层206内的离子向外扩散，造成不良影响。
图3为本申请一实施例提供的另一半导体结构的结构示意图。
参考图3，在另一些实施例中，第二导电层206与第一导电层202的整个上表面相接触。
在去除第一导电层202顶面的第一阻挡层214时，去除位于第一导电层202上表面的所有第一阻挡层214，暴露出第一导电层202的整个上表面，有利于第一导电层202和第二导电层206具有最大的接触面积，减少接触电阻。
一些实施例中，阻挡层204不仅与位于凸出于基底200的第一导电层202的侧壁相 接触，还与第二导电层206的侧壁相接触，这样同一阻挡层204和不同的导电层之间都有接触，有利于利用阻挡层204将不同的导电层之间的位置固定，在后续的工艺中，不容易受制程应力的影响使得不同导电层之间的位置关系产生变化，进而产生间隙，影响半导体结构的性能；同时阻挡层204和导电层的侧壁相接触，有利于提高接触面积，接触面积越大，阻挡层204对导电层的粘附固定效果越好。
相应的，本申请另一实施例还提供一种半导体结构的形成方法，本申请另一实施例提供的半导体结构的形成方法形成的半导体结构与前述实施例提供的半导体结构相同。以下将结合附图对本申请另一实施例提供的半导体结构的形成方法进行详细说明。
图4～图11为本申请另一实施例提供的半导体结构的形成方法各步骤对应的结构示意图。
参考图4，提供基底300。
基底300的材料为隔离材料，用于将导电层与其他导电结构隔离，一些实施例中，基底300的材料为二氧化硅。在另一些实施例中，基底300也可以氮化硅或碳化硅。
一些实施例为在已经形成源电极、漏电极和栅电极的待加工半导体基片上形成金属互联结构，所以基底300内还可以具有电极301，电极301为半导体基片上引出的电连接结构，具体材料可以为金属钨、金属银等金属材料。
电极301的上表面的宽度大于下表面的宽度。电极301与后续形成的第一导电层接触的表面为上表面，上表面的宽度越大，接触面积就越大，接触面积越大接触电阻越低，可以有效提高半导体结构的导电效率。
参考图5～图7，形成第一导电层302，第一导电层302的部分位于基底300内，第一导电层302的其余部分凸出于基底300上方。
具体地，参考图5，在基底300上表面形成停止层303。
一些实施例中，采用原子层沉积工艺形成停止层303，停止层303的材料可以为氮化硅或碳氮化硅，由于在后续形成第一导电层的时候，为了使得部分第一导电层位于基底300上方，需要在形成第一导电层之后，去除牺牲层，停止层303可以作为去除牺牲层工艺的刻蚀停止层，有效防止过刻蚀。
在基底300上形成牺牲层307，具体的牺牲层307位于停止层303上表面。
一些实施例中，采用化学气相沉积工艺形成牺牲层307，牺牲层307的材料与基底300的材料相同，基底300和牺牲层307的材料相同，在刻蚀牺牲层307和基底300时的速率可以保持一致，更利于工艺的实施。
参考图6，图形化牺牲层307以及基底300，在牺牲层307以及基底300内形成第一沟槽308。
一些实施例中，采用湿法刻蚀工艺去除部分牺牲层307、部分停止层303以及部分基底300，形成的第一沟槽308用于后续形成第一导电层。
参考图7，形成填充第一沟槽308(参考图6)的第一导电层302；去除牺牲层307(参考图6)直至暴露出停止层303。
一些实施例中，采用化学气相沉积工艺形成第一导电层302；采用湿法刻蚀工艺去除牺牲层307，停止层303作为刻蚀停止层。
一些实施例中，第一导电层302的材料为金属铜，金属铜的电阻率较低，在提高半导体结构导电效果的同时，有利于降低半导体结构的生产成本。在另一些实施例中，第一导电层的材料也可以为金属铝或者金属钴。
一些实施例中，第一导电层302的部分位于基底300内，第一导电层302的其余部分凸出于基底300上方，这是由于后续形成的阻挡层304要与第一导电层302的部分侧壁相接触，所以基底300需要暴露出部分第一导电层302。
第一导电层302不仅与电极301的上表面接触，还与电极301的部分侧壁接触，接触面积较大，所以第一导电层302与电极301的接触电阻较低，进一步提高半导体结构的导电效果。
参考图8～图11，形成阻挡层304，阻挡层304位于基底300上，以及至少位于凸出于基底300的第一导电层302的侧壁；形成介质层305，介质层305覆盖阻挡层304的表面；形成第二导电层306，第二导电层306贯穿介质层305和阻挡层304，第二导电层306与阻挡层304侧壁相接触，且第二导电层306与第一导电层303的至少部分上表面相接触。
由于阻挡层304不仅与位于凸出于基底300的第一导电层302的侧壁相接触，还与第二导电层306的侧壁相接触，这样同一阻挡层304和不同的导电层之间都有接触，有利于利用阻挡层304将不同的导电层之间的位置固定，在后续的工艺中，不容易受制程应力的影响使得不同导电层之间的位置关系产生变化，进而产生间隙，影响半导体结构的性能；同时阻挡层304和导电层的侧壁相接触，有利于提高接触面积，接触面积越大，阻挡层304对导电层的粘附固定效果越好。
具体地，参考图8，形成初始阻挡层334，初始阻挡层334覆盖第一导电层302暴露出的表面，且初始阻挡层334位于基底300上；形成初始介质层315，初始介质层315 覆盖初始阻挡层334的上表面。
一些实施例中，初始阻挡层304包括初始第一阻挡层344和初始第二阻挡层354，采用原子沉积工艺先在基底300上以及凸出于基底300的第一导电层302的表面形成初始第一阻挡层344，然后采用原子沉积工艺在初始第一阻挡层344表面形成初始第二阻挡层354；再采用化学气相沉积工艺形成初始介质层315。
一些实施例中，初始第一阻挡层344的材料和初始第二阻挡层354的材料不同，初始第一阻挡层344的材料包括氮氧化硅或氮氟化硅；初始第二阻挡层354的材料包括氮化硅或碳氮化硅。在同样的湿法刻蚀工艺下，初始第一阻挡层344的刻蚀选择比大于初始第二阻挡层354的刻蚀选择比，这样有利于在后续刻蚀第一阻挡层形成孔洞时不会对第二阻挡层造成过大的影响。
一些实施例中，初始介质层315的材料与基底300的材料可以相同，可以防止后续形成的不同的第二导电层电接触，初始介质层315的材料具体可以为二氧化硅、氮化硅或碳化硅。
参考图9，图形化初始介质层315以及初始阻挡层334，直至露出第一导电层302的至少部分表面，形成第二沟槽309，且剩余的初始介质层315作为介质层305，剩余的初始阻挡层334作为阻挡层304。
阻挡层304包括依次堆叠的第一阻挡层314和第二阻挡层324，且第一阻挡层314和第二阻挡层324的材料不同。
一些实施例中，在垂直于第一导电层302上表面的方向上，第一阻挡层314的厚度小于第二阻挡层324的厚度。
在后续刻蚀第一阻挡层314形成孔洞时，容易出现过刻蚀的现象，导致位于第一导电层302上表面的阻挡层304较少，所以第二阻挡层324的厚度较大，有利于保证即使第一阻挡层314过刻蚀，第一导电层302上表面仍具有较大面积的阻挡层304；第一阻挡层314的厚度较小，在形成孔洞时，有利于控制刻蚀效果。
一些实施例中，在垂直于第一导电层302上表面的方向上，第一阻挡层314和第二阻挡层324的厚度比为1：3～1：4。
具体地，在垂直于第一导电层302上表面的方向上，第一阻挡层314的厚度为5纳米～10纳米，具体可以为6纳米、7纳米或8纳米；第二阻挡层324的厚度为15纳米～40纳米，具体可以为20纳米、25纳米或30纳米。
在此范围内，第一阻挡层314在保证了黏附效果的同时不会由于过厚造成形成孔洞 时难以控制刻蚀效果；第二阻挡层324不会由于过薄造成第一阻挡层314过刻蚀时整个阻挡层304的黏附效果不佳。
参考图10，在形成第二沟槽309之后，还包括：对第二沟槽309露出的第一阻挡层314进行湿法刻蚀，以使第二阻挡层324、第一导电层302以及剩余第一阻挡层314围成孔洞310。
由于第二阻挡层324、第一阻挡层314和第一导电层302围成孔洞310，所以第一导电层302上表面暴露出可供与第二导电层306接触的面积较大，有利于增大第一导电层302和第二导电层306的接触面积，减小接触电阻，进一步提高整个半导体结构的导电效果；因为具有孔洞310，第一阻挡层314和第二阻挡层324会组成一个类似于卡扣状的结构，将填充孔洞310的第二导电层306卡在其中，在后续的制程过程中，无论第二导电层306受到任何方向的制程应力，第一阻挡层314和第二阻挡层324都会将第二导电层306固定，保证第二导电层306不会脱离第一导电层302的表面。
一些实施例中，湿法刻蚀工艺对第一阻挡层314的刻蚀选择比大于对第二阻挡层324的刻蚀选择比。所以在进行该湿法刻蚀工艺时，不会对第二阻挡层324产生影响。
一些实施例中，湿法刻蚀工艺选用的刻蚀溶液包括氢氟酸水溶液。其中，氢氟酸与水的质量比为1：50～1：100，具体可以为1：60、1：70或1：80。
参考图11，形成填充第二沟槽309(参考图10)的第二导电层306，第二导电层306还填充满孔洞310(参考图10)。
一些实施例中，位于第二阻挡层324附近区域的第二导电层306的宽度小于第二导电层306顶面的宽度；如此设置，在保证位于第一导电层302上表面具有面积较大的阻挡层304的同时，提高后续用于检测或者引线的第二导电层306暴露出的顶面的面积。
一些实施例中，采用化学气相沉积工艺形成第二导电层306，第二导电层306的材料可以为金属钨。在另一些实施例中，第二导电层的材料还可以为金属银或金属钴等导电率较高的金属材料。
一些实施例中，由于形成的阻挡层304不仅与位于凸出于基底300的第一导电层302的侧壁相接触，还与第二导电层306的侧壁相接触，这样同一阻挡层304和不同的导电层之间都有接触，有利于利用阻挡层304将不同的导电层之间的位置固定，在后续的工艺中，不容易受制程应力的影响使得不同导电层之间的位置关系产生变化，进而产生间隙，影响半导体结构的性能；同时阻挡层304和导电层的侧壁相接触，有利于提高接触面积，接触面积越大，阻挡层304对导电层的粘附固定效果越好。
本申请另一实施例还提供一种存储器，包括：如上述实施例提供的半导体结构。
一些实施例提供的存储器包括的半导体结构中的阻挡层不仅与位于凸出于基底的第一导电层的侧壁相接触，还与第二导电层的侧壁相接触，这样同一阻挡层和不同的导电层之间都有接触，有利于利用阻挡层将不同的导电层之间的位置固定，在后续的工艺中，不容易受制程应力的影响使得不同导电层之间的位置关系产生变化，进而产生间隙，影响半导体结构的性能；同时阻挡层和导电层的侧壁相接触，有利于提高接触面积，接触面积越大，阻挡层对导电层的粘附固定效果越好。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。
工业实用性
本申请实施例中的半导体结构，阻挡层不仅与位于凸出于基底的第一导电层的侧壁相接触，还与第二导电层的侧壁相接触，这样同一阻挡层和不同的导电层之间都有接触，有利于利用阻挡层将不同的导电层之间的位置固定，在后续的工艺中，不容易受应力的影响使得不同导电层之间的位置关系产生变化，进而产生间隙；同时阻挡层和导电层的侧壁相接触，有利于增加接触面积，接触面积越大，阻挡层对导电层的粘附固定效果越好。

Claims (17)

  1. 一种半导体结构，包括：
    基底；
    第一导电层，所述第一导电层的部分位于所述基底内，所述第一导电层的其余部分凸出于所述基底上方；
    阻挡层，所述阻挡层位于所述基底上，以及至少位于凸出于所述基底的所述第一导电层的侧壁；
    介质层，所述介质层位于所述阻挡层上；
    第二导电层，所述第二导电层贯穿所述介质层和所述阻挡层，所述第二导电层与所述阻挡层侧壁相接触，且所述第二导电层与所述第一导电层的至少部分上表面相接触。
  2. 根据权利要求1所述的半导体结构，其中，所述阻挡层包括依次堆叠的第一阻挡层和第二阻挡层，且所述第一阻挡层的材料和所述第二阻挡层的材料不同；
    所述第二阻挡层、所述第一阻挡层和所述第一导电层围成孔洞；
    所述第二导电层还填充满所述孔洞。
  3. 根据权利要求2所述的半导体结构，其中，在垂直于所述第一导电层上表面的方向上，所述第一阻挡层的厚度小于所述第二阻挡层的厚度。
  4. 根据权利要求3所述的半导体结构，其中，在垂直于所述第一导电层上表面的方向上，所述第一阻挡层和所述第二阻挡层的厚度比为1：3～1：4。
  5. 根据权利要求3所述的半导体结构，其中，在垂直于所述第一导电层上表面的方向上，所述第一阻挡层的厚度为5纳米～10纳米，所述第二阻挡层的厚度为15纳米～40纳米。
  6. 根据权利要求2所述的半导体结构，其中，所述第一阻挡层的材料包括氮氧化硅或氮氟化硅；所述第二阻挡层的材料包括氮化硅或碳氮化硅。
  7. 根据权利要求2所述的半导体结构，其中，所述第二导电层与所述第一导电层的整个上表面相接触。
  8. 根据权利要求1所述的半导体结构，其中，在垂直于所述基底上表面的方向上，凸出所述基底的所述第一导电层与位于所述基底内的所述第一导电层的厚度比为1： 1～1：2。
  9. 根据权利要求1所述的半导体结构，还包括：停止层，所述停止层位于所述基底上表面，且所述停止层位于所述基底和所述阻挡层之间。
  10. 一种半导体结构的形成方法，包括：
    提供基底；
    形成第一导电层，所述第一导电层的部分位于所述基底内，所述第一导电层的其余部分凸出于所述基底上方；
    形成阻挡层，所述阻挡层位于所述基底上，以及至少位于凸出于所述基底的所述第一导电层的侧壁；
    形成介质层，所述介质层覆盖所述阻挡层的表面；
    形成第二导电层，所述第二导电层贯穿所述介质层和所述阻挡层，所述第二导电层与所述阻挡层侧壁相接触，且所述第二导电层与所述第一导电层的至少部分上表面相接触。
  11. 根据权利要求10所述的半导体结构的形成方法，其中，形成所述第一导电层的步骤包括：在所述基底上形成牺牲层；
    图形化所述牺牲层以及所述基底，在所述牺牲层以及所述基底内形成第一沟槽；
    形成填充所述第一沟槽的所述第一导电层；
    去除所述牺牲层。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，在形成所述牺牲层之前，还包括：在所述基底上表面形成停止层；
    在去除所述牺牲层的工艺步骤中，去除所述牺牲层直至暴露出所述停止层。
  13. 根据权利要求10所述的半导体结构的形成方法，其中，形成所述阻挡层、所述介质层和所述第二导电层的步骤包括：形成初始阻挡层，所述初始阻挡层覆盖所述第一导电层暴露出的表面，且所述初始阻挡层位于所述基底上；
    形成初始介质层，所述初始介质层覆盖所述初始阻挡层的上表面；
    图形化所述初始介质层以及所述初始阻挡层，直至露出所述第一导电层的至少部分表面，形成第二沟槽，且剩余的所述初始介质层作为所述介质层，剩余的所述初始阻挡层作为所述阻挡层；
    形成填充所述第二沟槽的所述第二导电层。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，所述阻挡层包括依次堆叠的第一阻挡层和第二阻挡层，且所述第一阻挡层的材料和所述第二阻挡层的材料不同；
    在形成所述第二沟槽之后，还包括：
    对所述第二沟槽露出的所述第一阻挡层进行湿法刻蚀，以使所述第二阻挡层、所述第一导电层以及剩余所述第一阻挡层围成孔洞；
    在形成所述第二导电层的工艺步骤中，所述第二导电层还填充满所述孔洞。
  15. 根据权利要求14所述的半导体结构的形成方法，其中，所述湿法刻蚀工艺对所述第一阻挡层的刻蚀选择比大于对所述第二阻挡层的刻蚀选择比。
  16. 根据权利要求15所述的半导体结构的形成方法，其中，所述湿法刻蚀工艺选用的刻蚀溶液包括氢氟酸水溶液。
  17. 一种存储器，包括：如权利要求1-9任一项所述的半导体结构。
PCT/CN2021/118803 2021-07-20 2021-09-16 半导体结构、半导体结构的形成方法及存储器 WO2023000481A1 (zh)

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