WO2023000245A1 - Pll circuit and electronic device - Google Patents

Abstract

Provided by the present invention are a PLL circuit and an electronic device. The PLL circuit comprises a charge pump and a current input module; the charge pump is used to receive a control signal, and the control signal is used to control the charging current and the discharge current of the charge pump; one end of the current input module is connected to a voltage input end, and the other end of the current input module is connected to an output end of the charge pump; and the current input module is used for outputting a target current. In other words, the described PLL circuit changes the on/off timing sequence of the charge pump of the PLL circuit by externally connecting a current input module to the output end of the charge pump, thereby changing the fractional modulation mode, and achieving the purpose of optimizing fractional spur.

Description

A kind of PLL circuit and electronic equipment technical field

The present invention relates to the technical field of communication, and more specifically, relates to a PLL circuit and electronic equipment.

Background technique

In digital logic circuit design, a frequency divider is a basic circuit; it is usually used to divide a given frequency to obtain the desired target frequency.

Based on the integer frequency divider, its implementation method is relatively simple, and can be realized by using a standard counter or a programmable logic device.

However, in some occasions, when the clock source and the required target frequency are not integer multiples, a fractional frequency divider is required for frequency division. For example, the frequency division coefficients are half-integer frequency dividers such as 2.5, 3.5, and 7.5.

Furthermore, in the PLL (Phase Locked Loop, phase locked loop) frequency synthesis technology, in order to reduce the frequency step while ensuring low in-band phase noise, it is also necessary to use a PLL circuit including a fractional frequency divider. However, the use of fractional frequency division will inevitably produce fractional spurs, and severe cases will deteriorate the indicators of reception and transmission.

Then, how to suppress the fractional spurs of the PLL circuit is a technical problem to be solved urgently by those skilled in the art.

Contents of the invention

In view of this, in order to solve the above problems, the present invention provides a PLL circuit and electronic equipment, the technical solution is as follows:

A PLL circuit, the PLL circuit comprising: a charge pump and a current input module;

The charge pump is used to receive a control signal, and the control signal is used to control the charging current and the discharging current of the charge pump;

One end of the current input module is connected to the voltage input end, and the other end is connected to the output end of the charge pump;

The current input module is used to output target current.

Preferably, in the above PLL circuit, the difference between the discharge current and the charge current is equal to the target current.

Preferably, in the above PLL circuit, the current input module is a constant current source.

Preferably, in the above PLL circuit, the current input module is a load resistor;

Wherein, the first end of the load resistor is connected to the voltage input end;

The second end of the load resistor is connected to the output end of the charge pump.

Preferably, in the above PLL circuit, the current input module includes: a triode, a first resistor, a second resistor, and first to third capacitors;

Wherein, the first end of the first resistor is connected to the first end of the first capacitor, and the connection node is connected to the base of the triode;

The second end of the first resistor and the second end of the first capacitor are respectively grounded;

The first end of the second capacitor and the first end of the third capacitor are respectively connected to the first end of the second resistor, and the connection node is connected to the emitter of the triode;

The second end of the second capacitor and the second end of the third capacitor are respectively grounded;

The second end of the second resistor is connected to the voltage input end;

The collector of the triode is connected with the output terminal of the charge pump.

Preferably, in the above PLL circuit, the PLL circuit further includes: a loop filter;

Wherein, the input end of the loop filter is connected to the output end of the charge pump;

The loop filter is used to generate a loop control voltage based on a sum of the charging current, the discharging current and the target current.

Preferably, in the above PLL circuit, the PLL circuit further includes: a voltage controlled oscillator;

Wherein, the input end of the voltage controlled oscillator is connected to the output end of the loop filter;

The output terminal of the voltage-controlled oscillator is used as the output terminal of the PLL circuit;

The loop control voltage is used to control the frequency of the output signal of the voltage controlled oscillator.

Preferably, in the above PLL circuit, the PLL circuit further includes: a fractional frequency divider;

The input end of the fractional frequency divider is connected to the output end of the voltage controlled oscillator;

The fractional frequency divider is used to receive the output signal of the voltage-controlled oscillator and generate a feedback signal.

Preferably, in the above PLL circuit, the PLL circuit further includes: a frequency and phase detector;

The first input terminal of the frequency and phase detector is used to receive the phase frequency signal;

The second input terminal of the frequency and phase detector is connected to the output terminal of the fractional frequency divider for receiving the feedback signal;

The output end of the frequency and phase detector is connected to the control end of the charge pump;

The frequency and phase detector is used to generate the control signal according to the phase frequency signal and the feedback signal.

An electronic device, comprising the PLL circuit described in any one of the above items.

Compared with the prior art, the beneficial effects of the present application are:

A PLL circuit provided by the present invention includes: a charge pump and a current input module; the charge pump is used to receive a control signal, and the control signal is used to control the charge current and discharge current of the charge pump; the current input module One end is connected to the voltage input end, and the other end is connected to the output end of the charge pump; the current input module is used to output the target current. That is to say, the PLL circuit changes the timing of the PLL circuit charge pump by connecting a current input module externally to the output end of the charge pump, and then changes the fractional modulation mode, thereby achieving the purpose of optimizing fractional spurs. Moreover, the charge pump and frequency divider in the PLL circuit are integrated on the phase-locked loop chip, and the loop filter and voltage-controlled oscillator are set externally on the phase-locked loop chip; usually, the optimization of fractional spurs needs to rely on In the phase-locked loop chip, the PLL circuit provided by the present invention adds a current input module, which can change the timing of the charge pump of the PLL circuit, and then change the decimal modulation mode, so that the PLL circuit does not need to modify the fractional frequency division in the phase-locked loop chip In the modulation method, the fractional spurs can be improved through the current input module connected to the output terminal of the charge pump of the phase-locked loop chip, so that the optimization of the fractional spurs of the PLL circuit does not depend on the phase-locked loop chip.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic diagram of the principle of a PLL circuit provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of the principle of another PLL circuit provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of the principle of another PLL circuit provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of the principle of another PLL circuit provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of the principle of another PLL circuit provided by an embodiment of the present invention;

FIG. 6 is a schematic diagram of the principle of another PLL circuit provided by an embodiment of the present invention;

FIG. 7 is a schematic diagram of the principle of another PLL circuit provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of the principle of another PLL circuit provided by an embodiment of the present invention;

FIG. 9 is a schematic diagram of the principle of another PLL circuit provided by an embodiment of the present invention;

FIG. 10 is a schematic diagram of waveforms when a traditional PLL circuit is locked;

Fig. 11 is a schematic diagram of spurious analysis when a traditional PLL circuit is locked;

12 is a schematic diagram of waveforms when the PLL circuit is locked according to an embodiment of the present invention;

13 is a schematic diagram of spur analysis when the PLL circuit is locked according to an embodiment of the present invention;

FIG. 14 is another equivalent schematic diagram of the spurious analysis schematic diagram shown in FIG. 13 .

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The invention provides a novel PLL circuit structure, which effectively suppresses the fractional spurs of the PLL circuit, and further improves the performance of the PLL circuit.

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Referring to FIG. 1 , FIG. 1 is a schematic diagram of a PLL circuit provided by an embodiment of the present invention.

The PLL circuit includes: a charge pump CP and a current input module 11 .

The charge pump CP is used for receiving a control signal, and the control signal is used for controlling the charging current and the discharging current of the charge pump CP.

One terminal of the current input module 11 is connected to the voltage input terminal VCC, and the other terminal is connected to the output terminal of the charge pump CP.

The current input module 11 is used to output target current.

In this embodiment, the control signal is used to control the working state of the charge pump CP, and the working state of the charge pump CP at least includes a charging state and a discharging state; the charge pump CP is in a charging state for delivering Charging current; the charge pump CP is in a discharging state and is used to deliver the discharging current.

Furthermore, based on the current PLL circuit structure of the charge pump CP, a current input module 11 is connected to the output of the charge pump CP to change the timing of the charge pump in the PLL circuit, and then change the fractional modulation mode, so as to optimize the fractional spurious the goal of.

And, the described charge pump of PLL circuit is integrated on the phase-locked loop chip, under normal circumstances, needs to depend on the phase-locked loop chip to the optimization of fractional stray, and the PLL circuit that the present invention provides is in the current pump of phase-locked loop chip A current input module is added to the output end, which can change the timing of the PLL circuit charge pump, and then change the fractional modulation mode, so that the PLL circuit does not need to change the fractional frequency division modulation method of the frequency divider integrated in the phase-locked loop chip. The current control module connected to the output terminal of the charge pump of the phase-locked loop chip is used to improve the fractional spurs. The optimization of the fractional spurs in this scheme does not depend on the phase-locked loop chip.

Further, based on the above embodiments of the present invention, the difference between the discharge current and the charge current is equal to the target current. It should be noted that there is at least one current value of the discharge current that is not 0 in a working cycle, and the ratio of the product of the absolute value of the current value and the maintenance time of the current value to the working cycle is the first ratio, in a The charging current has at least one current value that is not 0 in the working cycle, the ratio of the product of the absolute value of the current value and the maintenance time of the current value to the working cycle is the second ratio, and the discharging current and the charging current The difference between is the difference between the first ratio and the second ratio, that is, the difference between the first ratio and the second ratio is equal to the target current. It should also be noted that the discharge current may also have multiple current values that are not 0 in one working cycle, and when the discharging current has multiple current values that are not 0 in one working cycle, the first A ratio includes: obtaining the product of the absolute value of each non-zero current value and its respective maintenance time, and then obtaining the sum of each product, and the first ratio is the ratio of the sum to the duty cycle; similarly, when When there are multiple non-zero currents in the charging current in one working cycle, the second ratio can be obtained according to the above calculation method.

Specifically, as shown in Figure 12, _ISOURCE in Figure 10 represents the charging current, and in one working cycle, the charging current has 6 current values that are not 0, and obtaining the first ratio includes: obtaining the above 6 values that are not The product of the absolute value of the electric current of 0 and its respective maintenance time, obtain the sum value of each product again, described first ratio is the ratio of this sum value and duty cycle; Among Fig. 10, I _SINX represents charging current, in a duty cycle , the discharge current has 6 current values that are not 0, and obtaining the second ratio includes: obtaining the product of the absolute value of the above 6 current values that are not 0 and their respective maintenance times, and then obtaining the sum of each product, so The second ratio is the ratio of the sum to the duty cycle.

In this embodiment, the final output current of the charge pump and the current input module is a current obtained by superimposing the discharging current, the charging current and the target current.

Further, based on the above-mentioned embodiments of the present invention, refer to FIG. 2 , which is a schematic schematic diagram of another PLL circuit provided by an embodiment of the present invention.

The PLL circuit also includes: a loop filter LPF.

Wherein, the input end of the loop filter LPF is connected with the output end of the charge pump CP.

The loop filter LPF is used for generating a loop control voltage based on the superimposed current of the charging current, the discharging current and the target current.

In this embodiment, the loop filter LPF performs filtering processing on the final output current of the charge pump CP and the current input module 11, and generates a loop control voltage CV.

Optionally, refer to FIG. 3 , which is a schematic schematic diagram of another PLL circuit provided by an embodiment of the present invention.

The loop filter LPF is an RC filter or a linear filter.

As shown in FIG. 3 , the loop filter LPF is an RC filter, which is composed of multiple capacitors C and multiple resistors R.

Further, based on the foregoing embodiments of the present invention, refer to FIG. 4 , which is a schematic schematic diagram of another PLL circuit provided by an embodiment of the present invention.

The PLL circuit also includes: a voltage-controlled oscillator VCO.

Wherein, the input end of the voltage controlled oscillator VCO is connected with the output end of the loop filter LPF.

The loop control voltage CV is used to control the frequency of the output signal of the voltage controlled oscillator VCO.

In this embodiment, the loop control voltage CV is used to control the frequency of the output signal of the voltage-controlled oscillator VCO. Generally, when the loop control voltage CV is at a high level, the voltage-controlled oscillator VCO The frequency of the output signal of the voltage-controlled oscillator VCO increases; when the loop control voltage CV is at a low level, the frequency of the output signal of the voltage-controlled oscillator VCO decreases.

Further, based on the above-mentioned embodiments of the present invention, refer to FIG. 5 , which is a schematic schematic diagram of another PLL circuit provided by an embodiment of the present invention.

The PLL circuit further includes: a fractional frequency divider DIV, and the fractional frequency divider and the current pump CP are integrated in a phase-locked loop chip.

The input terminal of the fractional frequency divider DIV is connected with the output terminal of the voltage-controlled oscillator VCO.

The fractional frequency divider DIV is used for receiving the output signal of the voltage-controlled oscillator VCO and generating a feedback signal.

In this embodiment, the frequency division coefficient of the fractional frequency divider DIV is determined according to actual requirements, and then the output signal of the voltage-controlled oscillator VCO is frequency-divided according to the frequency division coefficient to generate a feedback signal.

Further, based on the above-mentioned embodiments of the present invention, refer to FIG. 6 , which is a schematic schematic diagram of another PLL circuit provided by an embodiment of the present invention.

The PLL circuit further includes: a phase frequency detector PFD, and the phase frequency detector PFD, the fractional frequency divider and the current pump are all integrated in a phase locked loop chip.

The first input terminal of the phase frequency detector PFD is used for receiving the phase frequency frequency signal V _REF .

The second input terminal of the phase frequency detector PFD is connected to the output terminal of the fractional frequency divider DIV for receiving the feedback signal V _FB .

The output terminal of the phase frequency detector PFD is connected to the control terminal of the charge pump CP.

The phase frequency detector PFD is used for generating the control signal according to the phase frequency signal V _REF and the feedback signal V _FB .

In this embodiment, the control signal is used to control the working state of the charge pump CP, and the working state of the charge pump CP includes at least a charging state and a discharging state; in the charging state, it is used to deliver a charging current; in the discharging state state for delivering the discharge current. Then the control loop controls the magnitude of the voltage CV.

Further, based on the above-mentioned embodiments of the present invention, refer to FIG. 7 , which is a schematic schematic diagram of another PLL circuit provided by an embodiment of the present invention.

The current input module 11 is a constant current source 12 .

In this embodiment, the constant current source 12 is a constant current source for outputting a preset target current.

Further, based on the foregoing embodiments of the present invention, refer to FIG. 8 , which is a schematic schematic diagram of another PLL circuit provided by an embodiment of the present invention.

The current input module 11 is a load resistor Rs.

Wherein, the first end of the load resistor Rs is connected to the voltage input end VCC.

The second end of the load resistor Rs is connected to the output end of the charge pump CP.

In this embodiment, the resistance value of the load resistor Rs is determined according to the magnitude of the target current and the voltage at the voltage input terminal.

Further, based on the above-mentioned embodiments of the present invention, refer to FIG. 9 , which is a schematic schematic diagram of another PLL circuit provided by an embodiment of the present invention.

The current input module 11 includes: a transistor Q, a first resistor R1, a second resistor R2, and first to third capacitors C1-C3.

Wherein, the first end of the first resistor R1 is connected to the first end of the first capacitor C1, and the connection node is connected to the base of the transistor Q.

The second end of the first resistor R1 and the second end of the first capacitor C1 are respectively grounded.

The first end of the second capacitor C2 and the first end of the third capacitor C3 are respectively connected to the first end of the second resistor R2, and the connection node is connected to the emitter of the transistor Q.

The second terminal of the second capacitor C2 and the second terminal of the third capacitor C3 are respectively grounded.

A second terminal of the second resistor R2 is connected to the voltage input terminal VCC.

The collector of the transistor Q is connected to the output terminal of the charge pump CP.

Further, based on all the above-mentioned embodiments of the present invention, the principle of the PLL circuit provided by the present invention will be described again below:

First, analyze the fractional spurs based on the traditional PLL circuit.

For example, to achieve N+1/6 frequency division, in 6 frequency divisions, 5 times of N frequency division, 1 time of N+1 frequency division, then the cumulative frequency division number is (5·N+(N+1 ))/6=N+1/6.

Referring to FIG. 10 , FIG. 10 is a schematic waveform diagram of a locked state of a traditional PLL circuit.

Among them, V _REF represents the reference frequency waveform of phase detection; V _FB represents the output signal waveform of the fractional frequency divider; I _SOURCE represents the waveform of the charging state of the charge pump; I _SINX represents the waveform of the discharging state of the charge pump; I _CP represents the final voltage of the charge pump output current waveform.

Referring to FIG. 11 , FIG. 11 is a schematic diagram of spurious analysis when a conventional PLL circuit is locked.

Assuming that the period of the phase detection reference frequency of the frequency and phase detector is T, in order to facilitate the analysis, a time constant t ₀ is set, and the time constant t ₀ is the basic unit of the abscissa of the above-mentioned spurious distribution schematic diagram, namely t ₁ , t ₂ , t ₃ , t ₄ , t ₅ , and t ₆ are integer multiples of t _0. For 1/6 frequency division, the distribution period of fractional spurs is 6*T, and the spurs brought by fractional frequency division are low. The entire PLL circuit has the greatest impact and is the most difficult to filter out.

As shown in Figure 11, for each spurious point phase, the following relationship exists:

θ ₁ = θ(t ₁ ) = θ(t ₄ )-π;

θ ₂ = θ(t ₂ ) = θ(t ₅ )-π;

θ ₃ =θ(t ₃ )=θ(t ₆ )−π.

Then, perform Fourier transform on the spurious signal whose period is 6*T, let its frequency be ω ₀ , and only take the fundamental wave item:

f(t)＝I _cp ·K·6t ₀ ·[sin(ω ₀ ·t+θ ₁ )+sin(ω ₀ ·t+θ ₂ )+sin(ω ₀ ·t+θ ₃ )]

Among them, K represents the Fourier transform coefficient of the square wave, I _cp is a fixed value set according to the frequency output by the phase-locked loop circuit, and t ₀ is also a set fixed value.

It can be obtained from this, the fractional spurious situation of the traditional PLL circuit.

Secondly, analysis is performed based on the fractional spurs of the PLL circuit provided by the embodiment of the present invention.

Referring to FIG. 12 , FIG. 12 is a schematic waveform diagram of a locked state of a PLL circuit provided by an embodiment of the present invention.

For example, add a constant current source to the output of the charge pump, and set the output target current as: 4·t ₀ ·I _CP /T; the locking waveform is shown in Figure 12.

Among them, V _REF represents the reference frequency waveform of phase detection; V _FB represents the output signal waveform of the fractional frequency divider; I _SOURCE represents the waveform of the charging state of the charge pump; I _SINX represents the waveform of the discharging state of the charge pump; I _CP represents the final voltage of the charge pump output current waveform.

At this time, I _SINX is 4·t ₀ ·I _CP /T larger than I _SOURCE . It should be noted that the stable condition of the traditional PLL circuit is: within a cycle T, the current of the current pump CP needs to meet the difference between the charging current and the discharging current to be 0, and the embodiment of the present application is at the output end of the current pump A constant current source is added, and its target current size is: 4·t ₀ ·I _CP /T, so in order to ensure the stability of the PLL circuit, I _SINX is greater than I _SOURCE by 4·t ₀ ·I _CP /T.

Referring to FIG. 13 , FIG. 13 is a schematic diagram of spurious analysis when the PLL circuit is locked according to the embodiment of the present invention. I ₁₁ represents the waveform of a constant current source, and the actual I _CP becomes I _CP1 , and I _CP -I _CP1 =4 · t ₀ · _ICP /T.

Referring to FIG. 14 , FIG. 14 is another equivalent schematic diagram of the spurious analysis schematic diagram shown in FIG. 13 .

Using the same method as above to perform Fourier transform on I _CP1 :

f ₁ (t)＝I _CP ·K·6·t ₀ ·[(1-8·t ₀ /(3·T))Sin(ω ₀ ·t+θ ₁ )+(1-4·t ₀ / T)Sin(ω ₀ ·t+θ ₂ )+(1-4·t ₀ /T)Sin(ω ₀ ·t+θ ₃ )]

Then by comparing f(t) and f ₁ (t), we can know that for the signal amplitude of the same phase, f ₁ (t) is lower than f(t), that is:

For the fundamental wave of the stray signal, the amplitude of the PLL circuit provided by the invention is lower than that of the traditional PLL circuit.

It is found in some specific practice that it can be optimized by about 15dB.

It can be seen from the above description that a PLL circuit provided by the present invention connects a current input module externally to the output terminal of the charge pump to change the on/off timing of the charge pump in the PLL circuit, and then change the decimal modulation mode, so as to optimize the decimal complex. scattered purpose.

Moreover, the improved method has no dependence on the PLL circuit, does not require the PLL circuit to open any authority, and the cost of the improvement is very low.

Based on all the above-mentioned embodiments of the present invention, an electronic device is provided in another embodiment of the present invention, and the electronic device includes the PLL circuit described in the above-mentioned embodiments.

Above, a kind of PLL circuit and electronic equipment provided by the present invention have been introduced in detail. In this paper, specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only used to help understand the method of the present invention. and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and scope of application. limits.

It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. For the same and similar parts in each embodiment, refer to each other, that is, Can. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for the related information, please refer to the description of the method part.

It should also be noted that in this article, relational terms such as first and second etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations Any such actual relationship or order exists between. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that elements inherent in a process, method, article, or apparatus comprising a set of elements are included, or are also included as such , method, article or device inherent in the elements. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

A PLL circuit, characterized in that the PLL circuit includes: a charge pump and a current input module; The charge pump is used to receive a control signal, and the control signal is used to control the charging current and the discharging current of the charge pump; One end of the current input module is connected to the voltage input end, and the other end is connected to the output end of the charge pump; The current input module is used to output target current. The PLL circuit according to claim 1, wherein the difference between the discharge current and the charge current is equal to the target current. The PLL circuit according to claim 1, wherein the current input module is a constant current source. The PLL circuit according to claim 1, wherein the current input module is a load resistor; Wherein, the first end of the load resistor is connected to the voltage input end; The second end of the load resistor is connected to the output end of the charge pump. The PLL circuit according to claim 1, wherein the current input module comprises: a triode, a first resistor, a second resistor, and first to third capacitors; Wherein, the first end of the first resistor is connected to the first end of the first capacitor, and the connection node is connected to the base of the triode; The second end of the first resistor and the second end of the first capacitor are respectively grounded; The first end of the second capacitor and the first end of the third capacitor are respectively connected to the first end of the second resistor, and the connection node is connected to the emitter of the triode; The second end of the second capacitor and the second end of the third capacitor are respectively grounded; The second end of the second resistor is connected to the voltage input end; The collector of the triode is connected with the output terminal of the charge pump. The PLL circuit according to claim 1, wherein the PLL circuit further comprises: a loop filter; Wherein, the input end of the loop filter is connected to the output end of the charge pump; The loop filter is used to generate a loop control voltage based on a sum of the charging current, the discharging current and the target current. The PLL circuit according to claim 6, wherein the PLL circuit further comprises: a voltage-controlled oscillator; Wherein, the input end of the voltage controlled oscillator is connected to the output end of the loop filter; The output terminal of the voltage-controlled oscillator is used as the output terminal of the PLL circuit; The loop control voltage is used to control the frequency of the output signal of the voltage controlled oscillator. The PLL circuit according to claim 7, wherein the PLL circuit further comprises: a fractional frequency divider; The input end of the fractional frequency divider is connected to the output end of the voltage controlled oscillator; The fractional frequency divider is used to receive the output signal of the voltage-controlled oscillator and generate a feedback signal. The PLL circuit according to claim 8, wherein the PLL circuit further comprises: a frequency and phase detector; The first input terminal of the frequency and phase detector is used to receive the phase frequency signal; The second input terminal of the frequency and phase detector is connected to the output terminal of the fractional frequency divider for receiving the feedback signal; The output end of the frequency and phase detector is connected to the control end of the charge pump; The frequency and phase detector is used to generate the control signal according to the phase frequency signal and the feedback signal. An electronic device, characterized in that the electronic device comprises the PLL circuit according to any one of claims 1-9.

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