WO2022227451A1 - Packaging structure and packaging method - Google Patents

Abstract

Disclosed are a packaging structure and a packaging method. The packaging structure comprises: a chip unit, a first surface of the chip unit comprising a sensing region; an upper cover plate covering the first surface of the chip unit; and a supporting structure located between the upper cover plate and the chip unit, the sensing region being located in a cavity defined by the supporting structure and the first surface of the chip unit, wherein the inner wall surface of the cavity is covered with a light absorbing layer. According to the present invention, the inner wall surface of the cavity is covered with the light absorbing layer, which can absorb the reflected light passing through the side wall of the cavity and prevent the light from interfering with the front sensing region.

Description

Packaging structure and packaging method technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a packaging structure and a packaging method.

Background technique

Wafer Level Chip size Packaging (WLCSP) technology is a technology of packaging and testing the entire wafer and then cutting to obtain a single finished chip. The size of the packaged chip is the same as that of the bare chip. Wafer-level chip packaging technology subverts traditional packaging such as Ceramic Leadless Chip Carrier and Organic Leadless Chip Carrier , thinning and low-cost requirements. Chips packaged by wafer-level chip packaging technology have reached a high degree of miniaturization, and the cost of the chip is significantly reduced with the reduction of the chip and the increase of the wafer size. Wafer-level chip packaging technology is a technology that integrates IC design, wafer manufacturing, packaging and testing, and is the current hot spot and development trend in the packaging field.

In the existing wafer-level packaging technology, especially for the packaging of image sensor chips, a cover substrate is usually covered on the side of the semiconductor wafer on which the device is formed to protect the device from damage and contamination during the packaging process. , to protect the device.

With the miniaturization trend of wafer-level chip packaging, the more finished chip packages are integrated on the wafer-level chip, the smaller the size of a single finished chip package, and the corresponding gap between the sensing area and the cavity sidewall. The smaller the distance, the more obvious the interference of light reflections on the sensing area.

Chinese patent CN205789975U discloses an image sensor package structure, which uses a rack-shaped inner sidewall and a cofferdam with a height of 100 microns to replace the low photoresist polymer cofferdam, increases the height of the cofferdam, and has a light-transmitting cover. The distance between the contamination particles on the surface of the board and the photosensitive area increases, and the influence area of the light reaching the photosensitive area becomes smaller after being blocked by the particles. The mirror surface can effectively suppress the reflection of the oblique light or the reflected light from the photosensitive area on the inner wall of the cofferdam, reduce the interference light incident on the photosensitive area, and improve the imaging quality. However, the heightened wall, especially the wall above 100um, greatly increases the thickness of the final package, which is contrary to the existing trend of miniaturization and thinning (generally the height of the wall is 30-40um).

How to provide a packaging structure and method that is light and thin in structure and can reduce the interference light incident on the photosensitive area is an urgent problem to be solved.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a package structure for solving the problem that lightness and thinness and anti-interference cannot be satisfied at the same time in the prior art, including:

A package structure including:

a chip unit, the first surface of the chip unit includes a sensing area;

an upper cover plate, the upper cover plate covers the first surface of the chip unit;

A support structure is located between the upper cover plate and the chip unit, and the sensing area is located in the cavity enclosed by the support structure and the first surface of the chip unit, wherein,

The inner wall surface of the cavity is covered with a light absorbing layer.

In one embodiment, the light absorbing layer extends between the support structure and the chip unit.

In one embodiment, the light absorbing layer is glued to the first surface of the chip unit.

In one embodiment, the light absorbing layer is a black bonding glue.

In one embodiment, the chip unit further includes:

pads located outside the sensing area;

A through hole penetrating the chip unit from a second surface of the chip unit opposite to the first surface, the through hole exposing the bonding pad;

an insulating layer covering the second surface of the chip unit and the surface of the sidewall of the through hole;

a metal layer located on the surface of the insulating layer and electrically connected to the pad;

a solder resist layer located on the surface of the metal layer and the insulating layer, the solder resist layer having openings exposing part of the metal layer;

The openings are filled and circumscribed bumps outside the surface of the solder mask are exposed.

In one embodiment, the upper cover plate is set to a preset thickness and/or shape, and/or its surface is covered with a light shielding layer, so that the light reflected from the sidewall of the upper cover plate cannot be directly irradiated Or reduce the irradiation to the sensing area.

The present application also discloses a packaging method for the packaging structure, including:

A wafer is provided, the wafer includes a plurality of chip units arranged in an array;

An upper cover is provided, and a support structure with a cavity is fabricated on the surface of the upper cover;

bonding the support structure to the first surface of the chip unit;

The wafer, the upper cover plate and the support structure are divided by a cutting process to form a package structure of a plurality of chip units.

In one embodiment, it also includes:

forming a layer of black bonding glue on the surface of the support structure opposite to the first surface;

The support structure is bonded to the first surface of the chip unit, and the pressure and temperature are controlled to make the black bonding glue flow to the sidewall of the cavity.

In one embodiment, after completing the fabrication of the support structure, the method further includes:

Deposit a light absorbing layer on the side of the upper cover facing the wafer;

Etch the light absorbing layer located in the cavity and opposite to the sensing area;

The light absorbing layer is bonded to the first surface of the chip unit.

In one embodiment, the light absorbing layer is directly formed on the inner wall of the cavity by using graphic screen printing.

Compared with the prior art, in the present invention, by covering the inner wall surface of the cavity with a light absorbing layer, the reflected light passing through the side wall of the cavity can be absorbed to prevent the light from interfering with the front sensing area.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in this application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

1 is a cross-sectional view of a package structure in Embodiment 1 of the present application;

Fig. 2 is the light path diagram of the interference of light to the sensing area in the prior art;

3 to 12 are schematic diagrams of intermediate structures formed by the packaging structure in Embodiment 1 of the present application;

13 is a cross-sectional view of the package structure in Embodiment 2 of the present application;

14 to 18 are schematic diagrams of intermediate structures formed by the packaging structure in Embodiment 2 of the present application;

FIG. 19 is a schematic diagram of the structure of the light absorbing layer produced in Embodiment 3 of the present application.

Detailed ways

The present invention will be more fully understood from the following detailed description, which should be read in conjunction with the accompanying drawings. Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. Therefore, specific functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and for teaching one skilled in the art to vary in virtually any suitable detailed embodiment. The manner adopts the representative basis of the present invention.

Example 1

This embodiment provides a package structure. Referring to FIG. 1 , the package structure includes a chip unit 10 and an upper cover plate 20 .

In one embodiment, the chip unit is preferably an image sensor chip unit.

The chip unit 10 has a first surface 10 a and a second surface 10 b opposite to the first surface 10 a, the first surface 10 a including the sensing area 11 .

The chip unit 10 further includes bonding pads 12 , through holes (not marked), an insulating layer 13 , a metal layer 14 , a solder resist layer 15 and external bumps 16 .

The bonding pad 12 is located outside the sensing area 11; the through hole penetrates from the second surface of the chip unit opposite to the first surface, and the through hole exposes the bonding pad 12; the insulating layer 13 covers the second surface of the chip unit and the sidewall of the through hole surface; the metal layer 14 is located on the surface of the insulating layer 13 and is electrically connected to the pad 12; the solder resist layer 15 is located on the surface of the metal layer 14 and the insulating layer 13, and the solder resist layer 15 has openings exposing part of the metal layer 14; external protrusions 16 fills the opening and is exposed beyond the surface of the solder mask 15.

The upper cover 20 includes a first surface 20a and a second surface 20b opposite to the first surface 20a. The first surface 20a is provided with a support structure 30, and the upper cover 20 covers the first surface 10a of the chip unit 10. The support structure 30 It is supported between the upper cover 20 and the chip unit 10 , and the sensing area 11 is located in the cavity 31 surrounded by the support structure 30 and the first surface 10 a of the chip unit 10 .

As shown in Figure 2, four kinds of light are emitted from the same light source and pass through the upper cover plate (high light transmission glass) to reach the photosensitive area. The light s2 passes through the upper cover plate and is reflected by the side wall of the cavity, which interferes with the photosensitive area. With the development of fab technology and the need for miniaturization of the package size, the size of the non-sensing area of the chip will become smaller and smaller, that is, the distance between the reflective surface of the cavity sidewall and the sensing area will continue to shrink, and the sensor will be reflected through the surface. There will be more light in the area, and the interference will also become more and stronger, which will affect the final image quality. The edge area of the image has the greatest impact, which will cause glare.

In order to overcome the interference of the light s2 in FIG. 2 , in this embodiment, a light absorbing layer 40 is covered on the side wall of the cavity 31 .

In one embodiment, the light absorbing layer 40 is made of black bonding glue, and the black bonding glue extends between the support structure 30 and the contact surface of the chip unit 10 .

In this technical solution, on the one hand, the black bonding glue can realize the bonding between the support structure and the chip unit, and on the other hand, it covers the inner wall of the cavity and can absorb the reflected light passing through the side wall of the cavity.

2, in order to overcome the interference of the light s1 and s3, the upper cover plate 20 is set to a preset thickness, and/or shape, and/or its surface is covered with a light-shielding layer, so that the upper cover plate 20 is The light reflected from the sidewalls cannot be directly illuminated or reduced to the sensing area.

The light s1 is the light reflected by the side of the upper cover, which is the interference light; the light s3 is reflected by the side of the upper cover, and passes through the cavity side wall/side wall bonding glue (non-light-absorbing bonding glue) light, is interfering light.

In one embodiment, the area of the second surface 20a of the upper cover plate 20 is smaller than the area of the first surface 20b (not shown), and the package structure can reduce the interference light incident on the sensing area. For example, the side wall of the upper cover plate includes a vertical wall and an inclined wall, the first end of the inclined wall is connected with the edge of the second surface of the upper cover plate, and the opposite second end is connected with the top end of the vertical wall . The side wall structure with inclined walls can prevent the light originally reflected on the side walls from entering the upper cover structure, reducing the interference light reflected from the side walls of the upper cover and entering the sensing area, thereby improving the performance of the image sensor. The imaging quality of the chip package structure. This technology is the prior art (CN205050824U), which will not be repeated here.

In one embodiment, a light-shielding layer (not shown) is disposed on the surface of the upper cover plate 20, and the light-shielding layer covers the second surface of the upper cover plate opposite to the first surface, or is disposed on the side of the upper cover plate 20, and An intermediate region opposite the sensing region is exposed. The package structure can reduce the interference light incident on the sensing area. This technology is the prior art (CN204991711U, CN105244360A, CN106449546A), and will not be repeated here.

In one embodiment, the upper cover plate has a preset thickness, and the preset thickness is 50 μm˜200 μm, so that the light reflected from the sidewall of the upper cover plate cannot directly illuminate the sensing area. This technology is the prior art (105118843A), which will not be repeated here.

Correspondingly, an embodiment of the present invention provides a packaging method for forming a packaging structure as shown in FIG. 1 . Please refer to FIG. 3 to FIG. 12 , which are schematic diagrams of intermediate structures formed during the packaging process of the packaging method according to the embodiment of the present invention.

First, referring to FIGS. 3 and 4 , a wafer to be packaged 200 is provided, wherein FIG. 3 is a schematic top view of the wafer to be packaged 200 , and FIG. 4 is a cross-sectional view of FIG. 3 along A-A1 .

The chip unit 10 has a first surface 10 a and a second surface 10 b opposite to the first surface 10 a, the first surface 10 a including the sensing area 11 .

The wafer 200 to be packaged has a plurality of chip units 10 and a scribe line area 210 between the chip units 10 .

In this embodiment, the plurality of chip units 10 on the wafer to be packaged 200 are arranged in an array, the dicing lane area 210 is located between adjacent chip units 10, and the wafer to be packaged 200 is subsequently cut along the dicing lane area 210, A plurality of chip package structures including the chip unit 10 may be formed.

In this embodiment, the chip unit 10 is an image sensor chip unit, and the chip unit 10 has a sensing area 11 and a pad 12 located outside the sensing area 11 . The sensing area 11 is an optical sensing area, for example, it can be formed by arranging a plurality of photodiodes in an array, and the photodiodes can convert the optical signals irradiated to the sensing area 11 into electrical signals. The pads 12 serve as input and output terminals for connecting the devices in the sensing area 11 with external circuits.

In some embodiments, the chip unit 10 is formed on a silicon substrate, and the chip unit 10 may also include other functional devices formed in the silicon substrate.

It should be noted that, in the subsequent steps of the packaging method of the embodiment of the present invention, for the sake of simplicity and clarity, only the cross-sectional view along the A-A1 direction of the wafer 200 to be packaged shown in FIG. 3 is used as an example for description , and perform similar process steps in other areas.

Next, referring to FIGS. 5-7 , an upper cover plate 20 is provided. The upper cover plate 20 includes a first surface 20 a and a second surface 20 b opposite to the first surface 20 a. A support structure 30 is provided, and the groove structure surrounded by the support structure 30 and the first surface 20 a of the upper cover plate 20 corresponds to the sensing area 11 on the wafer 200 to be packaged.

In this embodiment, the upper cover plate 20 covers the first surface 10 a of the wafer to be packaged 200 in the subsequent process, so as to protect the sensing area 11 on the wafer to be packaged 200 . Since light needs to pass through the upper cover plate 20 to reach the sensing area 11 , the upper cover plate 20 has high light transmittance and is a light-transmitting material. Both surfaces of the upper cover plate 20 are flat and smooth, and will not cause scattering or diffuse reflection of incident light.

Specifically, the material of the upper cover plate 20 may be inorganic glass, organic glass or other light-transmitting materials with specific strength. In this embodiment, the thickness of the upper cover plate 20 is 300 μm˜500 μm, for example, it can be 400 μm. If the thickness of the upper cover plate 20 is too large, the thickness of the finally formed chip package structure will be too large, which cannot meet the requirements of thin and light electronic products; if the thickness of the upper cover plate 20 is too small, it will cause the upper cover plate 20 The strength of the sensor is small, it is easy to be damaged, and it cannot provide sufficient protection to the subsequent covered induction area.

In some embodiments, the support structure 30 is formed by depositing a layer of support structure material on the first surface 20 a of the upper cover plate 20 and then etching. Specifically, a support structure material layer covering the first surface 20a of the upper cover plate 20 is formed first, then the support structure material layer is patterned, and a part of the support structure material layer is removed to form the support structure 30 . The position of the groove structure surrounded by the support structure 30 and the first surface 20a of the upper cover plate 20 on the upper cover plate 20 corresponds to the position of the sensing area 11 on the wafer 200 to be packaged, so that after the subsequent bonding process , the sensing area 11 may be located in the groove enclosed by the support structure 30 and the first surface 20 a of the upper cover plate 20 .

In some embodiments, the material of the support structure material layer is wet film or dry film photoresist, which is formed by spraying, spin coating, or pasting processes, and the support structure material layer is exposed and developed to form the support structure after patterning. 30.

In some embodiments, the support structure material layer may also be an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride, which is formed by a deposition process, and then patterned by a photolithography and etching process to form the support structure 30 .

In some other embodiments, the support structure 30 may also be formed by etching the upper cover plate 20 . Specifically, a patterned photoresist layer can be formed on the upper cover plate 20, and then the upper cover plate 20 is etched by using the patterned photoresist layer as a mask, and the support structure 30 is formed in the upper cover plate 20, The support structure 30 is a protruding portion on the first surface 20 a of the upper cover plate 20 .

Next, referring to FIG. 8 , a layer of black bonding glue 40 is formed on the surface of the support structure 30 opposite to the first surface 10 a of the chip unit 10 . The gluing method can be roller brushing or screen printing.

Then, referring to FIGS. 9a, 9b and 9c, the first surface 20a of the upper cover plate 20 is opposed to and combined with the first surface 10a of the wafer 200 to be packaged, so that the support structure 30 and the first surface 10a of the wafer 200 to be packaged They are bonded together, and the bonding process is controlled by pressure, temperature, time, etc., so that part of the black bonding glue flows to the side of the cavity wall and covers it completely under the action of temperature and pressure, but does not flow. to the sensing area.

In this embodiment, after the first surface 20a of the upper cover plate 20 and the first surface 10a of the wafer 200 to be packaged are relatively combined, the support structure 30 and the first surface 10a of the wafer 200 to be packaged form a cavity. The position of the cavity corresponds to the position of the sensing area 11 , and the area of the cavity is slightly larger than that of the sensing area 11 , so that the sensing area 11 can be located in the cavity. In this embodiment, after the upper cover plate 20 and the to-be-packaged wafer 200 are combined, the pads 12 on the to-be-packaged wafer 200 are covered by the support structure 30 on the upper cover plate 20 . The upper cover plate 20 can play a role of protecting the wafer 200 to be packaged in the subsequent process.

Next, referring to FIG. 10 , a packaging process is performed on the wafer 200 to be packaged.

Specifically, first, the wafer to be packaged 200 is thinned from the second surface 10b of the wafer to be packaged 200 to facilitate subsequent etching of the through holes. The thinning of the wafer to be packaged 200 may use mechanical grinding or chemical mechanical grinding process, etc.; then, the to-be-packaged wafer 200 is etched from the second surface 10b of the to-be-packaged wafer 200 to form through holes (not marked), which expose the solder on the first surface 10a of the to-be-packaged wafer 200 pad 12; then, an insulating layer 13 is formed on the second surface 10b of the wafer 200 to be packaged and on the sidewalls of the through hole, the insulating layer 13 exposes the pad 12 at the bottom of the through hole, and the insulating layer 13 may be the wafer to be packaged The second surface 10b of the circle 200 provides electrical insulation, and can also provide electrical insulation for the substrate of the wafer to be packaged 200 exposed by the through holes. The material of the insulating layer 13 can be silicon oxide, silicon nitride, silicon oxynitride or insulating resin; then, a metal layer 14 connecting the pads 12 is formed on the surface of the insulating layer 13, and the metal layer 14 can be used as a re-wiring layer to lead the pads 12 to the second surface 10b of the wafer 200 to be packaged, and then communicate with the external circuit For connection, the metal layer 14 is formed by depositing a metal film and etching the metal film; then, a solder resist layer 15 with openings (not marked) is formed on the surface of the metal layer 14 and the surface of the insulating layer 13, and the openings expose parts On the surface of the metal layer 14, the material of the solder resist layer 15 is an insulating dielectric material such as silicon oxide and silicon nitride, which is used to protect the metal layer 14; The protrusions 16 fill the openings, and the external protrusions 16 may be connection structures such as solder balls and metal posts, and the materials may be metal materials such as copper, aluminum, gold, tin, or lead.

After the wafer to be packaged 200 is packaged, the chip package structure obtained by subsequent cutting can be connected to an external circuit through the external protrusions 16 . After the sensing area 11 of the chip unit converts the optical signal into an electrical signal, the electrical signal can be sequentially transmitted to an external circuit for processing through the bonding pad 12 , the metal layer 14 and the external bump 16 .

Next, referring to FIGS. 11 and 12 , the to-be-packaged wafer 200 and the upper cover plate 20 are cut along the scribe line area 210 of the to-be-packaged wafer 200 to form a plurality of package structures as shown in FIG. 1 .

Cutting can be done with a slicing knife or laser cutting, and a slicing knife can be cut with a metal knife or a resin knife.

Example 2

This embodiment provides another packaging structure. Referring to FIG. 13 , compared with Embodiment 1, the light absorbing layer 40 in this embodiment does not use bonding glue, and preferably uses black chrome material.

In order to realize the bonding between the upper cover plate 20 and the wafer to be packaged 200 , the light absorbing layer 40 and the first surface 10 a of the wafer to be packaged 200 are bonded by an adhesive layer 301 .

In this embodiment, the upper cover plate 20 and the wafer to be packaged 200 are combined by an adhesive layer (not shown). For example, an adhesive layer may be formed on the top surface of the formed light absorbing layer 40 and/or on the first surface 10a of the wafer 200 to be packaged by spraying, spin coating or sticking, and then the upper cover plate 20 The first surface 20a of the wafer 200 is relatively pressed against the first surface 10a of the wafer 200 to be packaged, and is bonded by an adhesive layer. The adhesive layer can not only realize the function of bonding, but also play the role of insulation and sealing. The adhesive layer can be a polymer adhesive material, such as silica gel, epoxy resin, benzocyclobutene and other polymer materials.

Except for the above differences, the structure of the second embodiment is similar to that of the first embodiment, and details are not repeated here.

Correspondingly, an embodiment of the present invention provides a method for fabricating a light absorbing layer (the packaging method is the same as that in Embodiment 1, and details are not repeated). Please refer to FIG. 14 to FIG. 17 , which are schematic diagrams of the intermediate structure formed by the light absorbing layer according to the embodiment of the present invention.

First, as shown in FIG. 14 , a layer of light-absorbing film 302 (eg, black chrome deposition) is deposited on the sidewall of the cavity and the upper cover plate 20;

Next, as shown in FIG. 15, a photoresist 303 is sprayed on the light-absorbing film 302, and a pattern is formed by photolithography (exposure, development);

Then, as shown in FIG. 16 , the light-absorbing film is etched (eg, chemically) and the photoresist 303 is removed to form the light-absorbing layer 40 .

Finally, as shown in FIGS. 17 and 18 , the adhesive layer 304 is spin-coated on the surface of the light absorbing layer 40 , the upper cover 20 and the wafer to be packaged 200 are combined, and subsequent packaging is completed to form the package structure shown in FIG. 13 .

Example 3

Because of the light absorption characteristics of the material, if the photolithographic black material is used in conjunction with the photolithography method, it is easy to cause the light to be absorbed by a layer of material on the surface and cannot penetrate to the bottom for exposure, resulting in residues, as in Example 2.

In order to overcome this technical problem, as shown in FIG. 19 , a black light-absorbing material can also be printed with a graphic screen 401 to directly form a patterned wall on the inner wall of the cavity.

The aspects, embodiments, features, and examples of the present invention are to be considered in all respects illustrative and not intended to limit the invention, the scope of which is defined only by the claims. Other embodiments, modifications, and uses will be apparent to those skilled in the art without departing from the spirit and scope of the claimed invention.

The use of headings and sections in this application is not meant to limit the invention; each section is applicable to any aspect, embodiment or feature of the invention.

Throughout this application, where a composition is described as having, comprising or including particular components, or where a process is described as having, comprising or including particular process steps, it is contemplated that the compositions of the present teachings will also be substantially The above consists of or consists of the recited components, and the processes taught herein also consist essentially of, or consist of, the recited process steps.

In this application, where an element or component is referred to as being included in and/or selected from a list of recited elements or components, it is to be understood that the element or component can be any of the recited elements or components and The group may be selected from two or more of the recited elements or components. Furthermore, it should be understood that the elements and/or features of the compositions, devices or methods described herein may be combined in various ways, whether expressly or implicitly herein, without departing from the spirit and scope of the present teachings. Instructions included.

The use of the terms "include, includes, including," "have, has, or having" should generally be understood to be open-ended and not limiting unless specifically stated otherwise.

The use of the singular herein includes the plural (and vice versa) unless specifically stated otherwise. Also, the singular forms "a (a, an)" and "the (the)" include the plural forms unless the context clearly dictates otherwise. Additionally, where the use of the term "about" precedes a magnitude, the teachings of the present invention also include the particular magnitude itself, unless specifically stated otherwise.

It should be understood that the order of the steps or the order in which the particular actions are performed is not critical so long as the present teachings remain operable. Furthermore, two or more steps or actions may be performed simultaneously.

It should be understood that the figures and descriptions of the present invention have been simplified to illustrate elements relevant to a clear understanding of the present invention, while other elements have been eliminated for clarity. However, one skilled in the art will recognize that these and other elements may be desirable. However, since such elements are well known in the art, and since they do not facilitate a better understanding of the present invention, no discussion of such elements is provided herein. It should be understood that the figures are presented for illustrative purposes and not as construction drawings. Omitted details and modifications or alternative embodiments are within the scope of those skilled in the art.

It will be appreciated that, in certain aspects of the invention, a single component may be replaced by a plurality of components and a plurality of components may be replaced by a single component to provide an element or structure or to perform a given function or functions. Except where such substitutions would not operate to practice specific embodiments of the invention, such substitutions are considered to be within the scope of the invention.

Although the present invention has been described with reference to illustrative embodiments, those skilled in the art will understand that various other changes, omissions and/or additions and the like may be made without departing from the spirit and scope of the invention Effects replace elements of the described embodiments. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is not intended herein to limit the invention to the particular embodiments disclosed for carrying out the invention, but it is intended that this invention include all embodiments falling within the scope of the appended claims. Furthermore, unless specifically stated, any use of the terms first, second, etc. does not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.

Claims (10)

A package structure, characterized in that, comprising: a chip unit, the first surface of the chip unit includes a sensing area; an upper cover plate, the upper cover plate covers the first surface of the chip unit; A support structure is located between the upper cover plate and the chip unit, and the sensing area is located in the cavity enclosed by the support structure and the first surface of the chip unit, wherein, The inner wall surface of the cavity is covered with a light absorbing layer. The package structure according to claim 1, wherein the light absorption layer extends between the support structure and the chip unit. The package structure according to claim 2, wherein the light absorbing layer is glued with the first surface of the chip unit. The package structure according to claim 1, wherein the light absorbing layer is a black bonding glue. The package structure according to claim 1, wherein the chip unit further comprises: pads located outside the sensing area; A through hole penetrating the chip unit from a second surface of the chip unit opposite to the first surface, the through hole exposing the bonding pad; an insulating layer covering the second surface of the chip unit and the surface of the sidewall of the through hole; a metal layer located on the surface of the insulating layer and electrically connected to the pad; a solder resist layer located on the surface of the metal layer and the insulating layer, the solder resist layer having openings exposing part of the metal layer; The openings are filled and circumscribed bumps outside the surface of the solder mask are exposed. The package structure according to claim 1, wherein the upper cover plate is set to a predetermined thickness and/or shape, and/or its surface is covered with a light shielding layer, so that the upper cover plate can be seen from the upper cover plate. The light reflected from the sidewalls cannot be directly illuminated or reduced to the sensing area. A packaging method for a packaging structure according to any one of claims 1 to 6, characterized in that, comprising: A wafer is provided, the wafer includes a plurality of chip units arranged in an array; An upper cover is provided, and a support structure with a cavity is fabricated on the surface of the upper cover; bonding the support structure to the first surface of the chip unit; The wafer, the upper cover plate and the support structure are divided by a cutting process to form a package structure of a plurality of chip units. The packaging method of the packaging structure according to claim 7, further comprising: forming a layer of black bonding glue on the surface of the support structure opposite to the first surface; The support structure is bonded to the first surface of the chip unit, and the pressure and temperature are controlled to make the black bonding glue flow to the sidewall of the cavity. The packaging method of the packaging structure according to claim 7, characterized in that, after completing the fabrication of the support structure, further comprising: Deposit a light absorbing layer on the side of the upper cover facing the wafer; Etch the light absorbing layer located in the cavity and opposite to the sensing area; The light absorbing layer is bonded to the first surface of the chip unit. The encapsulation method of the encapsulation structure according to claim 7, characterized in that a light absorbing layer is directly formed on the inner wall of the cavity by using graphic screen printing.

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