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WO2022161244A1 - 多主机仲裁方法、装置和可读存储介质 - Google Patents

多主机仲裁方法、装置和可读存储介质 Download PDF

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Publication number
WO2022161244A1
WO2022161244A1 PCT/CN2022/072956 CN2022072956W WO2022161244A1 WO 2022161244 A1 WO2022161244 A1 WO 2022161244A1 CN 2022072956 W CN2022072956 W CN 2022072956W WO 2022161244 A1 WO2022161244 A1 WO 2022161244A1
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WIPO (PCT)
Prior art keywords
host
level signal
bit
data
duration
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PCT/CN2022/072956
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English (en)
French (fr)
Inventor
鲁汉洋
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维沃移动通信有限公司
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Publication of WO2022161244A1 publication Critical patent/WO2022161244A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06M—COUNTING MECHANISMS; COUNTING OF OBJECTS NOT OTHERWISE PROVIDED FOR
    • G06M1/00—Design features of general application
    • G06M1/27—Design features of general application for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum
    • G06M1/272—Design features of general application for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum using photoelectric means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

Definitions

  • the present application belongs to the field of communication technologies, and in particular relates to a multi-host arbitration method, device and readable storage medium.
  • the integrated circuit (Inter-Integrated Circuit, I2C) bus is a two-wire serial bus that allows multi-host access. It is a special form of synchronous communication to transmit information between devices connected to the bus. It has the advantages of less interface lines, simple control methods, small device packaging, and high communication rate. It has become a widely used in the field of microelectronic communication control. bus standard. Since the I2C bus does not have any customized priorities, and there is no central host to formulate priorities, the I2C bus needs to achieve priority arbitration through competition between different hosts.
  • the purpose of the embodiments of the present application is to provide a multi-host arbitration method, device, and readable storage medium, which can solve the possibility of level transition of the serial data line and the level transition of the serial clock line of the existing I2C bus. At the same time, there is a problem that causes the I2C bus to go wrong.
  • an embodiment of the present application provides a multi-host arbitration method, which includes:
  • a first clock signal of the first host is generated, and the duration of the first high-level signal in the first clock signal is longer than that of the second
  • the duration of the high-level signal, the first high-level signal corresponds to the first bit of the byte in the data transmitted by the first host, and the second high-level signal corresponds to the word Corresponds to one bit except the first bit in the section;
  • the first host is controlled to stop transmitting data
  • the second host is controlled to retransmit data or stop transmitting data.
  • an embodiment of the present application provides a multi-master arbitration device, the device comprising:
  • the generating module is configured to generate a first clock signal of the first host when the first host uses the serial data line of the bus for data transmission, and the first high-level signal in the first clock signal is The duration is greater than the duration of the second high-level signal, the first high-level signal corresponds to the first bit of the byte in the data transmitted by the first host, and the second high-level signal The signal corresponds to one bit in the byte except for the first bit;
  • a first control module configured to detect that the data sent by the second host to the serial data line is data of repeated start bits or stop bits within the duration of the first high-level signal, And if the level signal of the serial data line matches the data sent by the second host, the first host is controlled to stop transmitting data, and the second host is controlled to retransmit data or stop transmission. data.
  • embodiments of the present application provide an electronic device, the electronic device includes a processor, a memory, and a program or instruction stored on the memory and executable on the processor, the program or instruction being The processor implements the steps of the method according to the first aspect when executed.
  • an embodiment of the present application provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the steps of the method according to the first aspect are implemented .
  • an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run a program or an instruction to implement the first aspect the method described.
  • an embodiment of the present application provides a computer program product, the computer program product is stored in a non-volatile storage medium, and the computer program product is executed by at least one processor to implement the first aspect. steps of the method described.
  • an embodiment of the present application provides a communication device, including: a processor, a memory, and a program stored in the memory and executable on the processor, when the program is executed by the processor The steps of implementing the method as described in the first aspect.
  • a first clock signal of the first host is generated, and the first high level in the first clock signal is The duration of the signal is greater than the duration of the second high-level signal, the first high-level signal corresponds to the first bit of the byte in the data transmitted by the first host, and the second high-level signal corresponds to the first bit of the byte in the data transmitted by the first host.
  • the level signal corresponds to one bit in the byte except the first bit; within the duration of the first high level signal, if it is detected that the second host sends the
  • the data sent by the serial data line is data with repeated start bits or stop bits, and the level signal of the serial data line matches the data sent by the second host, control the first The host stops transmitting data, and controls the second host to retransmit data or stop transmitting data.
  • the second host sends the repeated start bit or stop bit to the serial data line, it will occur within the duration of the first high level signal, thereby avoiding the level transition of the serial data line of the bus and the serial data line.
  • the error rate of the bus is reduced.
  • FIG. 1 is one of the flowcharts of a multi-host arbitration method provided by an embodiment of the present application
  • FIG. 2(a) is one of the schematic diagrams of arbitration between the first host and the second host provided by the embodiment of the present application;
  • FIG. 2(b) is the second schematic diagram of arbitration between the first host and the second host provided by the embodiment of the present application
  • FIG. 2(c) is the third schematic diagram of arbitration between the first host and the second host provided by the embodiment of the present application.
  • FIG. 3 is the second flow chart of the multi-host arbitration method provided by the embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a first host provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a multi-host arbitration apparatus provided by an embodiment of the present application.
  • FIG. 6 is one of the structural diagrams of an electronic device provided by an embodiment of the present invention.
  • FIG. 7 is a second structural diagram of an electronic device provided by an embodiment of the present invention.
  • first, second and the like in the description and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in sequences other than those illustrated or described herein, and distinguish between “first”, “second”, etc.
  • the objects are usually of one type, and the number of objects is not limited.
  • the first object may be one or more than one.
  • “and/or” in the description and claims indicates at least one of the connected objects, and the character “/" generally indicates that the associated objects are in an "or” relationship.
  • FIG. 1 is one of the flowcharts of the multi-host arbitration method provided by the embodiment of the present application. As shown in Figure 1, the multi-host arbitration method specifically includes the following steps:
  • Step 101 In the case where the first host uses the serial data line of the bus for data transmission, generate a first clock signal of the first host, and the duration of the first high-level signal in the first clock signal is longer than the second high-level signal.
  • the duration of the level signal, the first high-level signal corresponds to the first bit of the byte in the data transmitted by the first host, and the second high-level signal corresponds to the byte except the first bit in the byte.
  • the outer one bit corresponds to.
  • the above-mentioned bus includes but is not limited to I2C bus, and may also be other serial data transmission bus, which is not specifically limited in this application.
  • the above-mentioned first host refers to one or more hosts that use the bus for data transmission. It should be noted that the bus includes a serial data line and a serial clock line. When the first host uses the serial data line of the bus for data transmission, the first host also needs to generate a first clock signal and send it to the serial data line of the bus.
  • the row clock line sends the first clock signal, and controls the high and low level signals on the serial clock line of the bus through the first clock signal of the first host, and when the serial clock line of the bus is a high level signal , each byte in the data to be sent by the first host is sequentially transmitted according to the bits, so that the rate at which the first host sends data to the serial data line of the bus can be controlled by the first clock signal.
  • the duration of the first high-level signal in the first clock signal of the first host is greater than the duration of the second high-level signal, wherein the first high-level signal is related to the first host.
  • the first bit of the byte in the transmitted data corresponds to the second high level signal corresponding to one bit in the byte except the first bit, such as the second bit in the byte.
  • To each of the eighth bits corresponds.
  • the second high-level signal may correspond to the second bit in the byte, and may also correspond to the third bit, the fourth bit, the fifth bit, and the sixth bit in the byte. bit, the seventh bit or the eighth bit corresponds.
  • the durations of the high-level signals of the clock signal corresponding to the second bit to the eighth bit here may be the same or different. That is to say, the duration of the first high-level signal corresponding to the first bit of the byte in the data transmitted by the first host needs to be greater than the duration of the second high-level signal corresponding to other bits in the byte. .
  • the level signal on the serial clock line of the bus is determined by the first clock signal of the first host, that is, the level signal on the serial clock line of the bus is based on the first clock signal sent by the first host. And” logic to achieve.
  • the multiple first hosts can respectively send the first clock signal to the serial clock line of the bus, and the serial clock line of the bus can execute " Wire-AND logic, which determines the level signal on the serial clock line of the bus.
  • the "wire-and” logic here means that if any one of the multiple first clock signals is at a low level in a certain period of time, the serial clock line of the bus will show a low level in this period of time.
  • the serial clock line of the bus shows a high level in this period. Therefore, when the duration of the first high-level signal of the first clock signal is prolonged, the duration of the high-level signal at the corresponding position of the clock signal line of the bus is also prolonged, so that the first host is During data transmission, the repeated start bit or stop bit sent by other hosts will occur within the duration of the first high-level signal, rather than at the transition position of the first high-level signal, which is beneficial to Avoid the situation where the level transition of the serial data line of the bus occurs at the same time as the level transition of the serial clock line.
  • Step 102 During the duration of the first high-level signal, if it is detected that the data sent by the second host to the serial data line is data of repeated start bits or stop bits, and the level signal of the serial data line is the same as that of the serial data line. If the data sent by the second host matches, the first host is controlled to stop transmitting data, and the second host is controlled to retransmit data or stop transmitting data.
  • the above-mentioned second host is at least one other host connected to the bus except the above-mentioned first host.
  • the above-mentioned repeated start bit sent by the second host refers to the transition from a high-level signal to a low-level signal sent by the second host to the serial data line of the bus when the clock signal of the second host is a high-level signal.
  • the transition signal is used for the second host to request the bus to transmit new data.
  • the stop bit sent by the second host refers to the transition from a low-level signal to a high-level signal sent by the second host to the serial data line of the bus when the clock signal of the second host is a high-level signal.
  • the signal is used by the second host to request the bus to stop transmitting data.
  • the first host can be controlled to stop transmitting data
  • the second host can be controlled to retransmit data according to the repeated start bit sent by it, or stop data transmission according to the stop bit sent by it.
  • FIGS. 2 ( a ) to 2 ( b ) are schematic diagrams of arbitration between a first host and a second host according to an embodiment of the present application.
  • the first host includes a first clock signal and a first data signal
  • the second host includes a second clock signal and a second data signal
  • the level signal on the serial clock line of the bus is the first
  • the level signal after a clock signal and the second clock signal perform "wire AND” logic
  • the level signal on the serial data line of the bus is the electrical level signal after the first data signal and the second data signal perform "wire AND” logic. flat signal.
  • the second data signal sent by the second host is A stop bit, so after the serial data line of the bus performs the "wire AND" logic, the level signal at the position corresponding to the first high level signal is consistent with the second host, which is a stop bit. Therefore, the second host If the arbitration succeeds and the first host fails the arbitration, it is necessary to control the first host to stop transmitting data, and control the second host to also stop transmitting data. After that, the bus enters an idle state, and both the serial data line of the bus and the serial clock line of the bus are in a high-level state.
  • the first data signal sent by the first host is still a high-level signal
  • the second data signal sent by the second host is a repeated start bit
  • both are a repeated start bit. Therefore, if the second host succeeds in the arbitration, the first host fails in the arbitration, it is necessary to control the first host to stop transmitting data, and control the second host to transmit new data. After that, the level state of the serial data line of the bus is consistent with the level state of the second data signal of the second host.
  • the duration of the first high-level signal corresponding to the first bit of the byte is longer than that corresponding to other bits in the byte.
  • the duration of the second high-level signal so that when the second host sends a repeated start bit or stop bit to the serial data line, it will occur within the duration of the first high-level signal, thereby avoiding serial
  • the error rate of the bus is reduced.
  • FIG. 3 is the second flowchart of the multi-master arbitration method provided by the embodiment of the present application.
  • the method further includes:
  • Step 103 During the duration of the first high-level signal, if it is detected that the data sent by the second host to the serial data line is a repeating start bit or a stop bit, and the level signal of the serial data line is the same as that of the first high-level signal. When the level signals of the data sent by the host match, the first host is controlled to continue to transmit data.
  • the level signal of the data sent by the first host may be a high-level signal or a low-level signal, and is determined according to the data that the first host actually needs to send. For example, if the first host needs to send data 0 during the duration of the first high level signal, it sends a low level signal to the serial data line of the bus, if the first host needs to send data 0 for the duration of the first high level signal If data 1 needs to be sent, a high level signal is sent to the serial data line of the bus.
  • the first high-level signal if it is detected that the data sent by the second host to the serial data line of the bus is a repeated start bit or stop bit, and the level signal of the serial data line is detected In the case of matching the level signal of the data sent by the first host, it means that the signal transmitted on the serial data line of the bus at this time is consistent with the signal transmitted by the first host, then it can be determined that the first bus arbitration is successful, and the first bus arbitration is successful. The arbitration of the two buses fails, and at this time, the first host can be controlled to continue to transmit data.
  • FIG. 2( c ) is a schematic diagram of arbitration between another first host and a second host according to an embodiment of the present application.
  • the first data signal sent by the first host is a low-level signal
  • the second data signal sent by the second host is a If the start bit or a stop bit is repeated, after the serial data line of the bus performs the "wire AND" logic, the level signals at the position corresponding to the first high-level signal are all low-level signals, which are consistent with the first host. , therefore, the arbitration of the first host succeeds and the arbitration of the second host fails at this time. After that, the level state of the serial data line of the bus is consistent with the level state of the first data signal of the first host.
  • the level signal of the serial data line of the bus can be judged by Whether it matches with the data bits sent by the first host determines whether the first host succeeds in arbitration. Therefore, when the second host sends repeated start bits or stop bits, correct arbitration can be achieved and the error rate of the bus can be reduced.
  • the duration of the first high-level signal is twice the duration of the second high-level signal.
  • the above-mentioned first high-level signal corresponds to the first bit of the byte in the data transmitted by the first host
  • the above-mentioned second high-level signal corresponds to a byte other than the first bit in the byte.
  • the bits correspond, for example, to each of the second to eighth bits in the byte.
  • the second high-level signal may correspond to the second bit in the byte, and may also correspond to the third bit, the fourth bit, the fifth bit, and the sixth bit in the byte. bit, the seventh bit or the eighth bit corresponds.
  • the duration of the first high-level signal is twice the duration of the second high-level signal. For example, if the duration of the high level signal of the clock signal corresponding to the second bit to the eighth bit in the byte is 5 milliseconds, the duration of the first bit in the byte is 10 millisecond. In this way, the duration of the high-level signal corresponding to the first bit of the byte in the data can be longer than that of the high-level signal corresponding to other bits, thereby better avoiding the serial data line of the bus. The level transition of the serial clock line occurs at the same time, so as to achieve the effect of reducing the error rate of the bus.
  • the high-level signal corresponding to the first bit in the byte is twice the duration of the high-level signal corresponding to the other bit except the first bit in the byte, it is actually The transmission efficiency of the bus has little effect. Therefore, this can not only avoid the conflict between the repeated start bit or the stop bit and the normal data bit when different hosts send data at the same time, especially for the cumulative read and write transmission, the effect is relatively obvious.
  • the first host includes a byte counter, a bit counter and a clock signal generator
  • step 101 generating the first clock signal of the first host, includes:
  • the clock signal generator is controlled to generate a first high level signal at the position.
  • FIG. 4 is a schematic structural diagram of a first host provided by an embodiment of the present application.
  • the first host includes a byte counter, a bit counter and a clock signal generator, wherein the byte counter is used to count the bytes of data transmitted by the first host to the serial data line of the bus , the bit counter is used to count the bits in the bytes of the data transmitted by the first host to the serial data line of the bus, and the clock signal generator is used to generate the first clock signal.
  • the first host may also include a control unit, a master state machine, a read register, a write register, a serial-to-parallel module, a parallel-to-serial module, etc., wherein the master state machine is used for the bus and the slave connected to the bus
  • the control unit is used to read or write the data in the read register and write register according to the monitoring result of the main state machine, and the serial-to-parallel module is used to receive the serial data line from the bus. After the received data is converted from serial to parallel, it is transmitted to the read register, and the parallel-to-serial module is used to convert the data in the write register from parallel to serial, and then transmit it to the serial data line of the bus.
  • the number of bytes transmitted by the first host to the serial data line of the bus can be determined according to the byte counter by obtaining the counting result of the byte counter and the bit counter in the first host , according to the bit counter to determine the number of bits of the bytes transmitted by the first host to the serial data line of the bus, thus, according to the counting results of the byte counter and the bit counter, it is possible to determine the number of bits in the data transmitted by the first host
  • the first bit of the byte is at the corresponding position on the clock signal of the first host, and the clock signal generator is controlled to generate the first high-level signal at this position, that is, the first high-level signal at this position.
  • the duration is prolonged, while the duration of the second high-level signal at the position corresponding to other bits in the byte remains unchanged.
  • only one counter may be set in the first host, and the counter cyclically counts 0 to 8 bits in the byte, and when the first bit is counted, the clock signal is controlled.
  • the generator generates a first high level signal at this position.
  • the counting result of the byte counter and the bit counter of the first host it can be determined that the first bit of the byte in the data transmitted by the first host is on the clock signal of the first host.
  • the corresponding position is controlled, so that the clock signal generator is controlled to generate the first high-level signal at the position, so that the accuracy of the first clock signal can be improved.
  • the execution subject may be a multi-host arbitration device, or a control module in the multi-host arbitration device for executing the multi-host arbitration method.
  • the multi-host arbitration device provided by the embodiment of the present application is described by taking the multi-host arbitration device executing the multi-host arbitration method as an example.
  • FIG. 5 is a schematic structural diagram of a multi-host arbitration apparatus provided by an embodiment of the present application.
  • the multi-master arbitration device 500 includes:
  • the generating module 501 is configured to generate a first clock signal of the first host when the first host uses the serial data line of the bus for data transmission, and the duration of the first high-level signal in the first clock signal is greater than The duration of the second high-level signal, the first high-level signal corresponds to the first bit of the byte in the data transmitted by the first host, and the second high-level signal corresponds to the byte divided by the first bit A bit other than the bit corresponds to;
  • the first control module 502 is configured to, within the duration of the first high-level signal, detect that the data sent by the second host to the serial data line is data of repeated start bits or stop bits, and the serial data line In the case that the level signal matches the data sent by the second host, the first host is controlled to stop transmitting data, and the second host is controlled to retransmit data or stop transmitting data.
  • the multi-master arbitration apparatus 500 further includes:
  • the second control module is used for detecting that the data sent by the second host to the serial data line is a repeated start bit or a stop bit during the duration of the first high level signal, and the level of the serial data line If the signal matches the level signal of the data sent by the first host, the first host is controlled to continue to transmit data.
  • the duration of the first high-level signal is twice the duration of the second high-level signal.
  • the first host includes a byte counter, a bit counter and a clock signal generator;
  • the generation module 501 includes:
  • the acquisition unit is used to acquire the counting result of the byte counter and the bit counter;
  • a determining unit for determining, according to the counting result, the position corresponding to the first bit of the byte in the data transmitted by the first host on the clock signal of the first host;
  • the control unit is used for controlling the clock signal generator to generate the first high-level signal at the position.
  • the multi-host arbitration apparatus 500 in this embodiment of the present application may be an apparatus, or may be a component, an integrated circuit, or a chip in a terminal.
  • the apparatus may be a mobile electronic device or a non-mobile electronic device.
  • the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (personal digital assistant).
  • UMPC ultra-mobile personal computer
  • netbook or a personal digital assistant
  • non-mobile electronic devices can be servers, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (television, TV), teller machine or self-service machine, etc., this application Examples are not specifically limited.
  • Network Attached Storage NAS
  • personal computer personal computer, PC
  • television television
  • teller machine or self-service machine etc.
  • the multi-master arbitration apparatus 500 in this embodiment of the present application may be an apparatus having an operating system.
  • the operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of the present application.
  • the multi-host arbitration apparatus 500 provided in this embodiment of the present application can implement each process implemented by the method embodiments in FIG. 1 to FIG. 4 , which is not repeated here to avoid repetition.
  • an embodiment of the present application further provides an electronic device 600, including a processor 601, a memory 602, and a program or instruction stored in the memory 602 and executable on the processor 601, the program Or when the instruction is executed by the processor 601, each process of the above-mentioned embodiment of the multi-host arbitration method is implemented, and the same technical effect can be achieved. To avoid repetition, details are not described here.
  • the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.
  • FIG. 7 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.
  • the electronic device 700 includes but is not limited to: a radio frequency unit 701, a network module 702, an audio output unit 703, an input unit 704, a sensor 705, a display unit 706, a user input unit 707, an interface unit 708, a memory 709, and a processor 710, etc. part.
  • the electronic device 700 may also include a power source (such as a battery) for supplying power to various components, and the power source may be logically connected to the processor 710 through a power management system, so as to manage charging, discharging, and power management through the power management system. consumption management and other functions.
  • a power source such as a battery
  • the structure of the electronic device shown in FIG. 7 does not constitute a limitation on the electronic device.
  • the electronic device may include more or less components than the one shown, or combine some components, or arrange different components, which will not be repeated here. .
  • the processor 710 is configured to generate a first clock signal of the first host when the first host uses the serial data line of the bus to perform data transmission, and the duration of the first high-level signal in the first clock signal The time is greater than the duration of the second high-level signal, the first high-level signal corresponds to the first bit of the byte in the data transmitted by the first host, and the second high-level signal corresponds to the byte divided by the first bit.
  • a bit other than one bit corresponds to;
  • the processor 710 is further configured to, within the duration of the first high level signal, detect that the data sent by the second host to the serial data line is a repeated start bit or a stop bit, and the serial data line If the level signal of the first host matches the level signal of the data sent by the first host, the first host is controlled to continue to transmit data.
  • the duration of the first high-level signal is twice the duration of the second high-level signal.
  • the first host includes a byte counter, a bit counter and a clock signal generator
  • the processor 710 is further configured to obtain the counting result of the byte counter and the bit counter;
  • the clock signal generator is controlled to generate a first high level signal at the position.
  • the electronic device 700 can implement each process implemented by the electronic device in the foregoing embodiments, and to avoid repetition, details are not repeated here.
  • the second host when the second host sends the repeated start bit or stop bit to the serial data line, it occurs within the duration of the first high-level signal, thereby avoiding the serial data line of the bus.
  • the level transition of the serial clock line occurs at the same time, which reduces the error rate of the bus.
  • the input unit 704 may include a graphics processor (Graphics Processing Unit, GPU) 7041 and a microphone 7042. Such as camera) to obtain still pictures or video image data for processing.
  • the display unit 706 may include a display panel 7061, which may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.
  • the user input unit 707 includes a touch panel 7071 and other input devices 7072 .
  • the touch panel 7071 is also called a touch screen.
  • the touch panel 7071 may include two parts, a touch detection device and a touch controller.
  • Other input devices 7072 may include, but are not limited to, physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which are not described herein again.
  • Memory 709 may be used to store software programs as well as various data including, but not limited to, application programs and operating systems.
  • the processor 710 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the like, and the modem processor mainly processes wireless communication. It can be understood that, the above-mentioned modulation and demodulation processor may not be integrated into the processor 710.
  • the embodiments of the present application further provide a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, each process of the above-mentioned embodiment of the multi-host arbitration method is implemented, and the same can be achieved.
  • the technical effect, in order to avoid repetition, will not be repeated here.
  • the processor is the processor in the electronic device in the above embodiment.
  • the readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.
  • An embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used for running a program or an instruction to implement each process of the above-mentioned embodiment of the multi-host arbitration method, and can achieve the same In order to avoid repetition, the technical effect will not be repeated here.
  • the chip mentioned in the embodiments of the present application may also be referred to as a system-on-chip, a system-on-chip, a system-on-a-chip, or a system-on-a-chip, or the like.
  • An embodiment of the present application further provides a computer program product, which is stored in a non-volatile storage medium, and when the computer program product is executed by at least one processor, implements each of the foregoing multi-host arbitration method embodiments process, and can achieve the same technical effect, in order to avoid repetition, it will not be repeated here.
  • An embodiment of the present application further provides a communication device, the communication device includes a processor, a memory, and a program or instruction stored on the memory and executable on the processor, where the program or instruction is processed by the processor
  • the communication device includes a processor, a memory, and a program or instruction stored on the memory and executable on the processor, where the program or instruction is processed by the processor
  • the method of the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is better implementation.
  • the technical solution of the present application can be embodied in the form of a software product in essence or in a part that contributes to the prior art, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, CD-ROM), including several instructions to make a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the methods described in the various embodiments of this application.
  • a storage medium such as ROM/RAM, magnetic disk, CD-ROM

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Abstract

本申请公开了一种多主机仲裁方法、装置和可读存储介质，属于通信技术领域。该方法包括：在第一主机使用总线的串行数据线进行数据传输的情况下，生成第一主机的第一时钟信号，第一时钟信号中的第一高电平信号的持续时间大于第二高电平信号的持续时间，第一高电平信号与第一主机所传输的数据中的字节的第一个比特位对应，第二高电平信号与字节中除第一个比特位之外的一比特位对应；在第一高电平信号的持续时间内，若检测到第二主机向串行数据线发送的数据为重复起始位或停止位的数据，且串行数据线的电平信号与第二主机所发送的数据匹配的情况下，则控制第一主机停止传输数据，并控制第二主机重新传输数据或者停止传输数据。

Description

多主机仲裁方法、装置和可读存储介质
相关申请的交叉引用
本申请主张在2021年01月27日在中国提交的中国专利申请No.202110111278.6的优先权，其全部内容通过引用包含于此。
技术领域
本申请属于通信技术领域，具体涉及一种多主机仲裁方法、装置和可读存储介质。
背景技术
集成电路(Inter－Integrated Circuit，I2C)总线是一种允许多主机接入的两线式串行总线，通过串行数据(Serial Data，SDA)线和串行时钟(Serial Clock，SCL)线在连接到总线的器件间传递信息，是同步通信的一种特殊形式，具有接口线少、控制方式简单、器件封装形式小、通信速率较高等优点，已成为微电子通信控制领域广泛采用的一种总线标准。由于I2C总线没有任何定制的优先权，也没有中央主机来制定优先权，因此，I2C总线需要通过不同主机之间的相互竞争来实现优先级的仲裁。
在现有技术中，当一个主机正在使用I2C总线传输数据，且另外一个主机向I2C总线发送重复起始位或者停止位时，I2C总线中的串行数据线上的数据位会受到重复起始位或者停止位的干扰，使得串行数据线的电平跳变与串行时钟线的电平跳变可能会同时出现，这时I2C总线不能对多个主机进行仲裁，从而导致I2C总线可能出错。
发明内容
本申请实施例的目的是提供一种多主机仲裁方法、装置和可读存储介质，能够解决现有的I2C总线的串行数据线的电平跳变与串行时钟线的电平跳变可能同时出现，导致I2C总线可能出错的问题。
为了解决上述技术问题，本申请是这样实现的：
第一方面，本申请实施例提供了一种多主机仲裁方法，该方法包括：
在第一主机使用总线的串行数据线进行数据传输的情况下，生成所述第一主机的第一时钟信号，所述第一时钟信号中的第一高电平信号的持续时间大于第二高电平信号的持续时间，所述第一高电平信号与所述第一主机所传输的数据中的字节的第一个比特位对应，所述第二高电平信号与所述字节中除所述第一个比特位之外的一比特位对应；
在所述第一高电平信号的持续时间内，若检测到所述第二主机向所述串行数据线发送的数据为重复起始位或停止位的数据，且所述串行数据线的电平信号与所述第二主机所发送的数据匹配的情况下，则控制所述第一主机停止传输数据，并控制所述第二主机重新传输数据或者停止传输数据。
第二方面，本申请实施例提供了一种多主机仲裁装置，该装置包括：
生成模块，用于在第一主机使用总线的串行数据线进行数据传输的情况下，生成所述第一主机的第一时钟信号，所述第一时钟信号中的第一高电平信号的持续时间大于第二高电平信号的持续时间，所述第一高电平信号与所述第一主机所传输的数据中的字节的第一个比特位对应，所述第二高电平信号与所述字节中除所述第一个比特位之外的一比特位对应；
第一控制模块，用于在所述第一高电平信号的持续时间内，若检测到所述第二主机向所述串行数据线发送的数据为重复起始位或停止位的数据，且所述串行数据线的电平信号与所述第二主机所发送的数据匹配的情况下，则控制所述第一主机停止传输数据，并控制所述第二主机重新传输数据或者停止传输数据。
第三方面，本申请实施例提供了一种电子设备，该电子设备包括处理器、存储器及存储在所述存储器上并可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如第一方面所述的方法的步骤。
第四方面，本申请实施例提供了一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如第一方面所述的方法的步骤。
第五方面，本申请实施例提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令， 实现如第一方面所述的方法。
第六方面，本申请实施例提供了一种计算机程序产品，所述计算机程序产品被存储在非易失的存储介质中，所述计算机程序产品被至少一个处理器执行以实现如第一方面所述的方法的步骤。
第七方面，本申请实施例提供了一种通信设备，包括：处理器、存储器及存储在所述存储器上并可在所述处理器上运行的程序，所述程序被所述处理器执行时实现如第一方面所述的方法的步骤。
在本申请实施例中，在第一主机使用总线的串行数据线进行数据传输的情况下，生成所述第一主机的第一时钟信号，所述第一时钟信号中的第一高电平信号的持续时间大于第二高电平信号的持续时间，所述第一高电平信号与所述第一主机所传输的数据中的字节的第一个比特位对应，所述第二高电平信号与所述字节中除所述第一个比特位之外的一比特位对应；在所述第一高电平信号的持续时间内，若检测到所述第二主机向所述串行数据线发送的数据为重复起始位或停止位的数据，且所述串行数据线的电平信号与所述第二主机所发送的数据匹配的情况下，则控制所述第一主机停止传输数据，并控制所述第二主机重新传输数据或者停止传输数据。这样使得第二主机向串行数据线发送重复起始位或停止位时，会发生在第一高电平信号的持续时间内，从而避免总线的串行数据线的电平跳变与串行时钟线的电平跳变同时出现的情况，降低总线的出错率。
附图说明
图1为本申请实施例提供的多主机仲裁方法的流程图之一；
图2(a)为本申请实施例提供的第一主机和第二主机的仲裁示意图之一；
图2(b)为本申请实施例提供的第一主机和第二主机的仲裁示意图之二；
图2(c)为本申请实施例提供的第一主机和第二主机的仲裁示意图之三；
图3为本申请实施例提供的多主机仲裁方法的流程图之二；
图4为本申请实施例提供的第一主机的结构示意图；
图5为本申请实施例提供的多主机仲裁装置的结构示意图；
图6为本发明实施例提供的电子设备的结构图之一；
图7是本发明实施例提供的电子设备的结构图之二。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的多主机仲裁方法进行详细地说明。
参见图1，图1为本申请实施例提供的多主机仲裁方法的流程图之一。如图1所示，该多主机仲裁方法，具体包括以下步骤：
步骤101、在第一主机使用总线的串行数据线进行数据传输的情况下，生成第一主机的第一时钟信号，第一时钟信号中的第一高电平信号的持续时间大于第二高电平信号的持续时间，第一高电平信号与第一主机所传输的数据中的字节的第一个比特位对应，第二高电平信号与字节中除第一个比特位之外的一比特位对应。
其中，上述总线包括但不限于I2C总线，还可以为其他串行数据传输总线，本申请不做具体限定。上述第一主机是指使用该总线进行数据传输的一个或者多个主机。需要说明的是，该总线包括串行数据线和串行时钟线，在第一主机使用总线的串行数据线进行数据传输时，第一主机还需要生成第一时钟信号，并向总线的串行时钟线发送该第一时钟信号，通过第一主机的第一时钟信号来对总线的串行时钟线上的高低电平信号进行控制，并在总线的 串行时钟线为高电平信号时，对第一主机需要发送的数据中的各字节按照比特位依次进行传输，从而可以通过第一时钟信号控制第一主机向总线的串行数据线发送数据的速率。
在本申请实施例中，第一主机的第一时钟信号中的第一高电平信号的持续时间大于第二高电平信号的持续时间，其中，第一高电平信号与第一主机所传输的数据中的字节的第一个比特位对应，第二高电平信号与字节中除第一个比特位之外的一比特位对应，如与字节中的第二个比特位至第八个比特位中的每一比特位对应。具体地，第二高电平信号可以与字节中的第二个比特位对应，还可以与字节中的第三个比特位、第四个比特位、第五个比特位、第六个比特位、第七个比特位或者第八个比特位对应。此处的第二个比特位至第八个比特位对应的时钟信号的高电平信号的持续时间，可以相同，也可以不同。也就是说，需要第一主机所传输的数据中的字节的第一个比特位对应第一高电平信号的持续时间大于字节中其他比特位对应的第二高电平信号的持续时间。
由于总线的串行时钟线上的电平信号是由第一主机的第一时钟信号决定，即总线的串行时钟线上的电平信号是基于第一主机发送的第一时钟信号执行“线与”逻辑来实现的。当第一主机为多个时，多个第一主机可以分别向总线的串行时钟线发送第一时钟信号，总线的串行时钟线可以基于多个第一主机发送的第一时钟信号执行“线与”逻辑，从而确定总线的串行时钟线上的电平信号。其中，此处的“线与”逻辑是指，若多个第一时钟信号在某一时段存在任意一个第一时钟信号为低电平时，则总线的串行时钟线在该时段表现为低电平；若多个第一时钟信号在某一时段均为高电平时，则总线的串行时钟线在该时段表现为高电平。因此，当第一时钟信号的第一高电平信号的持续时间延长的情况下，会导致总线的时钟信号线的在对应位置的高电平信号的持续时间也延长，这样使得第一主机在进行数据传输时，其他主机发送的重复起始位或者是停止位会发生在第一高电平信号的持续时间内，而不会发生在第一高电平信号的跳变位置，这样有利于避免总线的串行数据线的电平跳变与串行时钟线的电平跳变同时出现的情况。
步骤102、在第一高电平信号的持续时间内，若检测到第二主机向串行 数据线发送的数据为重复起始位或停止位的数据，且串行数据线的电平信号与第二主机所发送的数据匹配的情况下，则控制第一主机停止传输数据，并控制第二主机重新传输数据或者停止传输数据。
其中，上述第二主机为接入总线的除上述第一主机外的其他至少一个主机。上述第二主机发送的重复起始位是指在第二主机的时钟信号为高电平信号情况下，第二主机向总线的串行数据线发送的从高电平信号向低电平信号的跳变信号，用于第二主机向总线请求传输新的数据。上述第二主机发送的停止位是指在第二主机的时钟信号为高电平信号情况下，第二主机向总线的串行数据线发送的从低电平信号向高电平信号的跳变信号，用于第二主机向总线请求停止传输数据。
在一实施例中，在第一高电平信号的持续时间内，若检测到第二主机向总线的串行数据线发送的数据为重复起始位或停止位的数据，且该串行数据线的电平信号与该第二主机所发送的数据匹配的情况下，表示此时总线的串行数据线上传输的信号与第二主机传输的信号一致，则可以确定第二总线仲裁成功，此时可以控制第一主机停止传输数据，并控制第二主机依据其发送的重复起始位重新传输数据，或者依据其发送的停止位停止传输数据。
具体地，参见图2(a)至2(b)，图2(a)至2(b)为本申请实施例提供的第一主机和第二主机的仲裁示意图。
如图2(a)所示，第一主机包括第一时钟信号和第一数据信号，第二主机包括第二时钟信号和第二数据信号，总线的串行时钟线上的电平信号为第一时钟信号与第二时钟信号执行“线与”逻辑后的电平信号，总线的串行数据线上的电平信号为第一数据信号与第二数据信号执行“线与”逻辑后的电平信号。在图2(a)所示的第一时钟信号的第一高电平信号对应的位置，由于第一主机发送的第一数据信号为高电平信号，第二主机发送的第二数据信号为一停止位，因而总线的串行数据线执行“线与”逻辑后，在第一高电平信号对应的位置的电平信号与第二主机一致，均为一停止位，因此，第二主机仲裁成功，第一主机仲裁失败，需要控制第一主机停止传输数据，并控制第二主机也停止传输数据。此后，总线进入空闲状态，总线的串行数据线和总线的串行时钟线均为高电平状态。
当然，如图2(b)所示，在图2(b)所示的第一时钟信号的第一高电平信号对应的位置，第一主机发送的第一数据信号仍为高电平信号，第二主机发送的第二数据信号为一重复起始位，那么总线的串行数据线执行“线与”逻辑后，在第一高电平信号对应的位置的电平信号与第二主机仍然一致，均为一重复起始位，因此，第二主机仲裁成功，第一主机仲裁失败，需要控制第一主机停止传输数据，并控制第二主机传输新的数据。此后，总线的串行数据线上的电平状态与第二主机的第二数据信号的电平状态一致。
在本实施例中，通过对正在进行数据传输的第一主机生成第一时钟信号，使得字节的第一个比特位对应的第一高电平信号的持续时间大于字节中其他比特位对应的第二高电平信号的持续时间，这样使得第二主机向串行数据线发送重复起始位或停止位时，会发生在第一高电平信号的持续时间内，从而避免总线的串行数据线的电平跳变与串行时钟线的电平跳变同时出现的情况，降低总线的出错率。
进一步地，参见图3，图3为本申请实施例提供的多主机仲裁方法的流程图之二。基于上述图1所示的实施例，在步骤101、在第一主机使用总线的串行数据线进行数据传输的情况下，生成第一主机的第一时钟信号之后，还包括：
步骤103、在第一高电平信号的持续时间内，若检测到第二主机向串行数据线发送的数据为重复起始位或停止位，且串行数据线的电平信号与第一主机所发送的数据的电平信号匹配的情况下，则控制第一主机继续传输数据。
其中，第一主机所发送的数据的电平信号可以是高电平信号，也可以为低电平信号，根据第一主机实际需要发送的数据确定。例如，如果第一主机在第一高电平信号的持续时间内需要发送数据0，则向总线的串行数据线发送低电平信号，如果第一主机在第一高电平信号的持续时间内需要发送数据1，则向总线的串行数据线发送高电平信号。
具体地，在第一高电平信号的持续时间内，若检测到第二主机向总线的串行数据线发送的数据为重复起始位或停止位，且该串行数据线的电平信号与该第一主机所发送的数据的电平信号匹配的情况下，表示此时总线的串行数据线上传输的信号与第一主机传输的信号一致，则可以确定第一总线仲裁 成功，第二总线仲裁失败，此时可以控制第一主机继续传输数据。
参见图2(c)，图2(c)为本申请实施例提供的另一第一主机和第二主机的仲裁示意图。在图2(c)所示的第一时钟信号的第一高电平信号对应的位置，第一主机发送的第一数据信号为低电平信号，第二主机发送的第二数据信号为一重复起始位或者一停止位，那么总线的串行数据线执行“线与”逻辑后，在第一高电平信号对应的位置的电平信号均为低电平信号，与第一主机一致，因此，此时第一主机仲裁成功，第二主机仲裁失败。此后，总线的串行数据线上的电平状态与第一主机的第一数据信号的电平状态一致。
在本实施例中，当检测到第二主机在第一高电平信号的持续时间内向串行数据线发送重复起始位或停止位时，可以通过判断总线的串行数据线的电平信号是否与第一主机所发送的数据位匹配，确定第一主机是否仲裁成功，因此，能够在第二主机发送重复起始位或停止位时能够实现正确的仲裁，降低总线的出错率。
进一步地，第一高电平信号的持续时间为第二高电平信号的持续时间的两倍。
其中，上述第一高电平信号与第一主机所传输的数据中的字节的第一个比特位对应，上述第二高电平信号与字节中除第一个比特位之外的一比特位对应，如与字节中的第二个比特位至第八个比特位中的每一比特位对应。具体地，第二高电平信号可以与字节中的第二个比特位对应，还可以与字节中的第三个比特位、第四个比特位、第五个比特位、第六个比特位、第七个比特位或者第八个比特位对应。
在一实施例中，第一高电平信号的持续时间为第二高电平信号的持续时间的两倍。例如，假设字节中的第二个比特位至第八个比特位对应的时钟信号的高电平信号的持续时间均为5毫秒，则字节中的第一个比特位的持续时间为10毫秒。通过这种方式，可以使得数据中字节的第一个比特位对应的高电平信号相比其他比特位对应的高电平信号持续时间更长，从而较好地避免总线的串行数据线的电平跳变与串行时钟线的电平跳变同时出现的情况，达到降低总线的出错率的效果。而且，即便字节中第一个比特位对应的高电平信号是字节中除第一个比特位之外的其他一比特位对应的高电平信号的持续 时间的2倍，其实际对于总线的传输效率的影响也不大，因此，这样不仅可以规避不同主机在同时发送数据重复起始位或者停止位与正常数据位之间的冲突，尤其对于累加性读写传输来说，效果比较明显。
进一步地，第一主机包括字节计数器、比特位计数器和时钟信号发生器；
上述步骤101、生成第一主机的第一时钟信号，包括：
获取字节计数器和比特位计数器的计数结果；
根据计数结果，确定第一主机所传输的数据中的字节的第一个比特位在第一主机的时钟信号上所对应的位置；
控制时钟信号发生器在位置生成第一高电平信号。
具体地，参见图4，图4为本申请实施例提供的第一主机的结构示意图。如图4所示，该第一主机包括字节计数器、比特位计数器和时钟信号发生器，其中，字节计数器用于对第一主机向总线的串行数据线传输的数据的字节进行计数，比特位计数器用于对第一主机向总线的串行数据线传输的数据的字节中的比特位进行计数，时钟信号发生器用于产生第一时钟信号。当然，该第一主机包括还可以包括控制单元、主状态机、读寄存器、写寄存器、串转并模块、并转串模块等，其中，主状态机用于对总线和接入总线的从机的忙闲状态进行监控，控制单元用于根据主状态机的监控结果对读寄存器和写寄存器中的数据进行读操作或者写操作，串转并模块用于将从总线的串行数据线上接收到的数据由串行转化为并行后，传输至读寄存器，并转串模块用于将写寄存器中的数据由并行转化为串行后，传输至总线的串行数据线。
在生成第一主机的第一时钟信号时，可以通过获取第一主机中字节计数器和比特位计数器的计数结果，根据字节计数器确定第一主机向总线的串行数据线传输的字节数量，根据比特位计数器确定第一主机向总线的串行数据线传输的字节的比特位数量，由此，可以根据字节计数器和比特位计数器的计数结果，确定第一主机所传输的数据中的字节的第一个比特位在第一主机的时钟信号上所对应的位置，并控制时钟信号发生器在该位置生成第一高电平信号，即将该位置的第一高电平信号的持续时间延长，而将字节中其他比特位对应的位置的第二高电平信号的持续时间不变。
当然，作为另一种实施方式，也可以在第一主机中仅设置一个计数器， 通过该计数器对字节中的0至8比特位循环计数，当计数到第一个比特位时，控制时钟信号发生器在该位置生成第一高电平信号。
在本实施例中，可以根据第一主机的字节计数器和比特位计数器的计数结果，确定第一主机所传输的数据中的字节的第一个比特位在第一主机的时钟信号上所对应的位置，从而控制时钟信号发生器在该位置生成第一高电平信号，这样可以提高第一时钟信号的准确性。
需要说明的是，本申请实施例提供的多主机仲裁方法，执行主体可以为多主机仲裁装置，或者该多主机仲裁装置中的用于执行多主机仲裁方法的控制模块。本申请实施例中以多主机仲裁装置执行多主机仲裁方法为例，说明本申请实施例提供的多主机仲裁装置。
参见图5，图5为本申请实施例提供的多主机仲裁装置的结构示意图。如图5所示，该多主机仲裁装置500，包括：
生成模块501，用于在第一主机使用总线的串行数据线进行数据传输的情况下，生成第一主机的第一时钟信号，第一时钟信号中的第一高电平信号的持续时间大于第二高电平信号的持续时间，第一高电平信号与第一主机所传输的数据中的字节的第一个比特位对应，第二高电平信号与字节中除第一个比特位之外的一比特位对应；
第一控制模块502，用于在第一高电平信号的持续时间内，若检测到第二主机向串行数据线发送的数据为重复起始位或停止位的数据，且串行数据线的电平信号与第二主机所发送的数据匹配的情况下，则控制第一主机停止传输数据，并控制第二主机重新传输数据或者停止传输数据。
进一步地，该多主机仲裁装置500，还包括：
第二控制模块，用于在第一高电平信号的持续时间内，若检测到第二主机向串行数据线发送的数据为重复起始位或停止位，且串行数据线的电平信号与第一主机所发送的数据的电平信号匹配的情况下，则控制第一主机继续传输数据。
进一步地，第一高电平信号的持续时间为第二高电平信号的持续时间的两倍。
进一步地，第一主机包括字节计数器、比特位计数器和时钟信号发生器； 生成模块501，包括：
获取单元，用于获取字节计数器和比特位计数器的计数结果；
确定单元，用于根据计数结果，确定第一主机所传输的数据中的字节的第一个比特位在第一主机的时钟信号上所对应的位置；
控制单元，用于控制时钟信号发生器在位置生成第一高电平信号。
本申请实施例中的多主机仲裁装置500可以是装置，也可以是终端中的部件、集成电路、或芯片。该装置可以是移动电子设备，也可以为非移动电子设备。示例性的，移动电子设备可以为手机、平板电脑、笔记本电脑、掌上电脑、车载电子设备、可穿戴设备、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本或者个人数字助理(personal digital assistant，PDA)等，非移动电子设备可以为服务器、网络附属存储器(Network Attached Storage，NAS)、个人计算机(personal computer，PC)、电视机(television，TV)、柜员机或者自助机等，本申请实施例不作具体限定。
本申请实施例中的多主机仲裁装置500可以为具有操作系统的装置。该操作系统可以为安卓(Android)操作系统，可以为ios操作系统，还可以为其他可能的操作系统，本申请实施例不作具体限定。
本申请实施例提供的多主机仲裁装置500能够实现图1至图4的方法实施例实现的各个过程，为避免重复，这里不再赘述。
可选地，如图6所示，本申请实施例还提供一种电子设备600，包括处理器601，存储器602，存储在存储器602上并可在处理器601上运行的程序或指令，该程序或指令被处理器601执行时实现上述多主机仲裁方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，本申请实施例中的电子设备包括上述的移动电子设备和非移动电子设备。
图7为实现本申请实施例的一种电子设备的硬件结构示意图。
该电子设备700包括但不限于：射频单元701、网络模块702、音频输出单元703、输入单元704、传感器705、显示单元706、用户输入单元707、接口单元708、存储器709、以及处理器710等部件。
本领域技术人员可以理解，电子设备700还可以包括给各个部件供电的 电源(比如电池)，电源可以通过电源管理系统与处理器710逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。图7中示出的电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置，在此不再赘述。
其中，处理器710，用于在第一主机使用总线的串行数据线进行数据传输的情况下，生成第一主机的第一时钟信号，第一时钟信号中的第一高电平信号的持续时间大于第二高电平信号的持续时间，第一高电平信号与第一主机所传输的数据中的字节的第一个比特位对应，第二高电平信号与字节中除第一个比特位之外的一比特位对应；
在第一高电平信号的持续时间内，若检测到第二主机向串行数据线发送的数据为重复起始位或停止位的数据，且串行数据线的电平信号与第二主机所发送的数据匹配的情况下，则控制第一主机停止传输数据，并控制第二主机重新传输数据或者停止传输数据。进一步地，处理器710，还用于在第一高电平信号的持续时间内，若检测到第二主机向串行数据线发送的数据为重复起始位或停止位，且串行数据线的电平信号与第一主机所发送的数据的电平信号匹配的情况下，则控制第一主机继续传输数据。
进一步地，第一高电平信号的持续时间为第二高电平信号的持续时间的两倍。
进一步地，第一主机包括字节计数器、比特位计数器和时钟信号发生器；
处理器710，还用于获取字节计数器和比特位计数器的计数结果；
根据计数结果，确定第一主机所传输的数据中的字节的第一个比特位在第一主机的时钟信号上所对应的位置；
控制时钟信号发生器在位置生成第一高电平信号。
电子设备700能够实现前述实施例中电子设备实现的各个过程，为避免重复，这里不再赘述。
本发明实施例的电子设备700，在第二主机向串行数据线发送重复起始位或停止位时，会发生在第一高电平信号的持续时间内，从而避免总线的串行数据线的电平跳变与串行时钟线的电平跳变同时出现的情况，降低总线的出错率。
应理解的是，本申请实施例中，输入单元704可以包括图形处理器(Graphics Processing Unit，GPU)7041和麦克风7042，图形处理器7041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。显示单元706可包括显示面板7061，可以采用液晶显示器、有机发光二极管等形式来配置显示面板7061。用户输入单元707包括触控面板7071以及其他输入设备7072。触控面板7071，也称为触摸屏。触控面板7071可包括触摸检测装置和触摸控制器两个部分。其他输入设备7072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。存储器709可用于存储软件程序以及各种数据，包括但不限于应用程序和操作系统。处理器710可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器710中。
本申请实施例还提供一种可读存储介质，可读存储介质上存储有程序或指令，该程序或指令被处理器执行时实现上述多主机仲裁方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
其中，处理器为上述实施例中的电子设备中的处理器。可读存储介质，包括计算机可读存储介质，如计算机只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等。
本申请实施例另提供了一种芯片，芯片包括处理器和通信接口，通信接口和处理器耦合，处理器用于运行程序或指令，实现上述多主机仲裁方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
应理解，本申请实施例提到的芯片还可以称为系统级芯片、系统芯片、芯片系统或片上系统芯片等。
本申请实施例还提供一种计算机程序产品，所述计算机程序产品被存储在非易失的存储介质中，所述计算机程序产品被至少一个处理器执行时实现上述多主机仲裁方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
本申请实施例还提供一种通信设备，所述通信设备包括处理器、存储器 及存储在所述存储器上并可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现上述多主机仲裁方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (13)

  1. 一种多主机仲裁方法，包括：
    在第一主机使用总线的串行数据线进行数据传输的情况下，生成所述第一主机的第一时钟信号，所述第一时钟信号中的第一高电平信号的持续时间大于第二高电平信号的持续时间，所述第一高电平信号与所述第一主机所传输的数据中的字节的第一个比特位对应，所述第二高电平信号与所述字节中除所述第一个比特位之外的一比特位对应；
    在所述第一高电平信号的持续时间内，若检测到所述第二主机向所述串行数据线发送的数据为重复起始位或停止位的数据，且所述串行数据线的电平信号与所述第二主机所发送的数据匹配的情况下，则控制所述第一主机停止传输数据，并控制所述第二主机重新传输数据或者停止传输数据。
  2. 根据权利要求1所述的方法，其中，在第一主机使用总线的串行数据线进行数据传输的情况下，生成所述第一主机的第一时钟信号之后，还包括：
    在所述第一高电平信号的持续时间内，若检测到所述第二主机向所述串行数据线发送的数据为重复起始位或停止位，且所述串行数据线的电平信号与所述第一主机所发送的数据的电平信号匹配的情况下，则控制所述第一主机继续传输数据。
  3. 根据权利要求1所述的方法，其中，所述第一高电平信号的持续时间为第二高电平信号的持续时间的两倍。
  4. 根据权利要求1所述的方法，其中，所述第一主机包括字节计数器、比特位计数器和时钟信号发生器；
    所述生成所述第一主机的第一时钟信号，包括：
    获取所述字节计数器和所述比特位计数器的计数结果；
    根据所述计数结果，确定所述第一主机所传输的数据中的字节的第一个比特位在所述第一主机的时钟信号上所对应的位置；
    控制所述时钟信号发生器在所述位置生成所述第一高电平信号。
  5. 一种多主机仲裁装置，包括：
    生成模块，用于在第一主机使用总线的串行数据线进行数据传输的情况 下，生成所述第一主机的第一时钟信号，所述第一时钟信号中的第一高电平信号的持续时间大于第二高电平信号的持续时间，所述第一高电平信号与所述第一主机所传输的数据中的字节的第一个比特位对应，所述第二高电平信号与所述字节中除所述第一个比特位之外的一比特位对应；
    第一控制模块，用于在所述第一高电平信号的持续时间内，若检测到所述第二主机向所述串行数据线发送的数据为重复起始位或停止位的数据，且所述串行数据线的电平信号与所述第二主机所发送的数据匹配的情况下，则控制所述第一主机停止传输数据，并控制所述第二主机重新传输数据或者停止传输数据。
  6. 根据权利要求5所述的装置，其中，还包括：
    第二控制模块，用于在所述第一高电平信号的持续时间内，若检测到所述第二主机向所述串行数据线发送的数据为重复起始位或停止位，且所述串行数据线的电平信号与所述第一主机所发送的数据的电平信号匹配的情况下，则控制所述第一主机继续传输数据。
  7. 根据权利要求5所述的装置，其中，所述第一高电平信号的持续时间为第二高电平信号的持续时间的两倍。
  8. 根据权利要求5所述的装置，其中，所述第一主机包括字节计数器、比特位计数器和时钟信号发生器；所述生成模块，包括：
    获取单元，用于获取所述字节计数器和所述比特位计数器的计数结果；
    确定单元，用于根据所述计数结果，确定所述第一主机所传输的数据中的字节的第一个比特位在所述第一主机的时钟信号上所对应的位置；
    控制单元，用于控制所述时钟信号发生器在所述位置生成所述第一高电平信号。
  9. 一种电子设备，包括处理器，存储器及存储在所述存储器上并可在所述处理器上运行的程序或指令，其中，所述程序或指令被所述处理器执行时实现如权利要求1-4任一项所述的多主机仲裁方法的步骤。
  10. 一种可读存储介质，其中，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如权利要求1-4任一项所述的多主机仲裁方法的步骤。
  11. 一种芯片，包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现如权利要求1-4中任一项所述的多主机仲裁方法中的步骤。
  12. 一种通信设备，被配置为执行如权利要求1-4中任一项所述的多主机仲裁方法中的步骤。
  13. 一种计算机程序产品，其中，所述计算机程序产品被存储在非易失的存储介质中，所述计算机程序产品被至少一个处理器执行以实现如权利要求1-4中任一项所述的多主机仲裁方法中的步骤。
PCT/CN2022/072956 2021-01-27 2022-01-20 多主机仲裁方法、装置和可读存储介质 WO2022161244A1 (zh)

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