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WO2022130912A1 - Production method for thin film transistor - Google Patents

Production method for thin film transistor Download PDF

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Publication number
WO2022130912A1
WO2022130912A1 PCT/JP2021/042788 JP2021042788W WO2022130912A1 WO 2022130912 A1 WO2022130912 A1 WO 2022130912A1 JP 2021042788 W JP2021042788 W JP 2021042788W WO 2022130912 A1 WO2022130912 A1 WO 2022130912A1
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Prior art keywords
thin film
insulating layer
gas
semiconductor layer
film transistor
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PCT/JP2021/042788
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French (fr)
Japanese (ja)
Inventor
敏彦 酒井
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日新電機株式会社
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Priority to KR1020237009288A priority Critical patent/KR102835739B1/en
Priority to CN202180063924.4A priority patent/CN116324019B/en
Publication of WO2022130912A1 publication Critical patent/WO2022130912A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/42—Silicides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate

Definitions

  • the present invention relates to a method for manufacturing a thin film transistor.
  • IGZO In—Ga—Zn—O-based oxide semiconductors for the semiconductor layer (channel layer)
  • various insulating layers such as a protective layer made of a silicon film (SiN x ) and a silicon oxide film (SiO x ) and a gate insulating layer are formed around the semiconductor layer.
  • a protective layer made of a silicon film (SiN x ) and a silicon oxide film (SiO x ) and a gate insulating layer are formed around the semiconductor layer.
  • an insulating layer made of a fluorine-containing silicon film is formed on a semiconductor layer by a plasma CVD method using a mixed gas containing SiCl4 gas, SiC4 gas and oxygen gas as a process gas. Things are listed.
  • the insulating layer is formed by a low temperature process of about 300 ° C., the positive fixed charge density in the insulating layer becomes high, and the threshold voltage of the thin film transistor becomes negative. It may shift in the direction and reduce reliability.
  • the present invention has been made in view of such problems, and its main object is to provide a method for manufacturing a thin film transistor capable of forming an insulating layer having a good fixed charge density even in a low temperature process.
  • the method for manufacturing a thin film film of the present invention includes a plasma treatment step in which a mixed gas containing nitrogen and oxygen is used as a process gas to perform plasma treatment on the surface of the semiconductor layer, and SiC4 , nitrogen, oxygen and hydrogen. It is characterized by comprising an insulating layer forming step of forming an insulating layer on the semiconductor layer after the plasma treatment by a plasma CVD method using a mixed gas as a process gas.
  • a plasma CVD method using a mixed gas as a process gas.
  • the insulating layer include a fluorine-containing silicon oxynitride film.
  • the insulating layer formed in the insulating layer forming step preferably has a fixed charge density of 3 ⁇ 10 11 cm -2 or less.
  • the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the plasma treatment step is preferably 70% or more, more preferably 80% or more, and more preferably 90% or more. Is even more preferable.
  • the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the plasma treatment step, and the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the insulating layer forming step. are preferably the same. By doing so, since the flow rate ratios of nitrogen gas and oxygen gas in the plasma treatment step and the insulating layer forming step are the same, the insulating layer forming step is performed while the plasma generated in the plasma treatment step is stably maintained. Can be migrated to. As a result, the tact time can be shortened and the manufacturing cost can be reduced.
  • the process of forming the insulating layer can be started while the plasma is stably maintained, the physical adsorption of process gas such as SiC4 gas on the interface between the semiconductor layer and the insulating layer can be suppressed, and the adhesion is higher. A good quality interface can be obtained.
  • the plasma treatment step and the insulating layer forming step are performed at 300 ° C. or lower.
  • a thin film transistor can be manufactured using a substrate having a low melting point such as a resin. According to the manufacturing method of the present invention, it is possible to manufacture a thin film transistor provided with an insulating layer having a good fixed charge density even in such a low temperature treatment.
  • a semiconductor layer composed of In—Ga—Zn—O can be mentioned.
  • the figure which shows typically the structure of the bottom gate type thin film transistor of this embodiment The figure which shows typically the manufacturing process of the thin film transistor of the same embodiment.
  • the thin film transistor and the manufacturing method thereof according to the embodiment of the present invention will be described below.
  • the thin film transistor 1 of the present embodiment is a so-called bottom gate type TFT, and uses an oxide semiconductor as a channel. Specifically, as shown in FIG. 1, it has a substrate 2, a gate electrode 3, a gate insulating layer 4, a semiconductor layer 5, a source electrode 6, a drain electrode 7, and a protective layer 8. It is formed in this order from the substrate 2 side.
  • the protective layer 8 corresponds to the "insulating layer" in the claims.
  • the substrate 2 is made of an arbitrary material that can transmit light, and is, for example, a plastic (synthetic resin) such as polyethylene terephthalate (PET), polyethylenaphthalate (PEN), polyether sulfone (PES), acrylic, and polyimide. ) And other resin materials and glass materials.
  • a plastic synthetic resin
  • PET polyethylene terephthalate
  • PEN polyethylenaphthalate
  • PES polyether sulfone
  • acrylic acrylic
  • polyimide polyimide
  • the gate electrode 3 controls the carrier density in the semiconductor layer 5 by the gate voltage applied to the thin film transistor 1.
  • the gate electrode 3 is made of any material having high conductivity, and is made of one or more metals selected from, for example, Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag and the like. May be done. Further, the conductivity of metal oxides such as Al-Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), and In-Ga-Zn-O (IGZO). It may be composed of a membrane.
  • the gate electrode 3 may be composed of a single-layer structure of these conductive films or a laminated structure of two or more layers.
  • the gate insulating layer 4 is made of any insulating material having high insulating properties, and is selected from, for example, SiO x , SiN x , SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , Hf 2 and the like. It may be an insulating film containing one or more oxides to be formed.
  • the gate insulating layer 4 may have a single-layer structure or a laminated structure of two or more layers of these conductive films.
  • the semiconductor layer (channel layer) 5 allows the current flowing between the source electrode 6 and the drain electrode 7 to pass through.
  • the semiconductor layer 5 of the present embodiment is made of an oxide semiconductor and contains, for example, an oxide of at least one element selected from In, Ga, Zn, Sn, Al, Ti and the like as a main component. .. Specific examples of the material constituting the semiconductor layer 5 include In-Ga-Zn-O (IGZO), In-Al-Mg-O, In-Al-Zn-O, In-Hf-Zn-O, and the like. Can be mentioned.
  • the semiconductor layer 5 is made of an amorphous oxide semiconductor film.
  • the semiconductor layer 5 of the present embodiment has a single-layer structure, but is not limited to this, and may have a laminated structure in which a plurality of layers having different compositions and crystallinities are laminated.
  • the source electrode 6 and the drain electrode 7 are formed so as to be separated from each other so as to partially cover the surface of the semiconductor layer 5. Like the gate electrode 3, the source electrode 6 and the drain electrode 7 are made of a material having high conductivity so as to function as an electrode.
  • the source electrode 6 and the drain electrode 7 may have a single-layer structure made of a single material, or may have a laminated structure in which a plurality of layers made of different materials are stacked.
  • the protective layer (passivation layer) 8 covers and protects the surface (channel region) of the semiconductor layer 5 exposed from between the source electrode 6 and the drain electrode 7, and is made of an insulating material. ..
  • the protective layer 8 is provided in contact with at least the surface of the semiconductor layer 5.
  • the protective layer 8 of the present embodiment is provided so as to further cover the surfaces of the source electrode 6 and the drain electrode 7.
  • the protective layer 8 is made of a fluorine-containing silicon oxynitride film (SiON: F).
  • the fluorine-containing silicon oxynitride film preferably has a fixed charge density of 3 ⁇ 10 11 cm -2 or less, and more preferably 1 ⁇ 10 11 cm -2 or less.
  • a second layer composed of, for example, a fluorine-containing silicon oxide film (SiN: F), a fluorine-containing silicon oxide film (SiO: F), a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like is placed on the protective layer 8.
  • a protective layer may be further provided as needed.
  • the method for manufacturing the thin film film 1 of the present embodiment includes a gate electrode forming step, a gate insulating layer forming step, a semiconductor layer forming step, a source / drain electrode forming step, a plasma processing step, and a protective layer forming step.
  • the protective layer forming step corresponds to the "insulating layer forming step" in the claims.
  • each step will be described.
  • a substrate 2 made of a resin material such as PET is prepared, and a gate electrode 3 is formed on the surface of the substrate 2.
  • the method for forming the gate electrode 3 is not particularly limited, and the gate electrode 3 may be formed by a known method such as a vacuum vapor deposition method.
  • the gate insulating layer 4 is formed so as to cover the surfaces of the substrate 2 and the gate electrode 3.
  • the method for forming the gate insulating layer 4 is not particularly limited, and the gate insulating layer 4 may be formed by a known method.
  • the semiconductor layer 5 is formed on the gate insulating layer 4.
  • the semiconductor layer 5 may be formed by a known method.
  • the semiconductor layer 5 may be formed by sputtering a conductive oxide sintered body such as InGaZnO using an inductively coupled plasma as a target.
  • the semiconductor layer 5 made of an oxide semiconductor may be formed by another method.
  • the source electrode 6 and the drain electrode 7 are formed on the semiconductor layer 5.
  • the source electrode 6 and the drain electrode 7 can be formed by a known method using, for example, RF magnetron sputtering or the like.
  • the source electrode 6 and the drain electrode 7 are formed so as to be separated from each other on the surface of the semiconductor layer 5 and to expose a part of the surface of the semiconductor layer 5.
  • the plasma processing apparatus 100 includes a vacuum container 20 in which a processing chamber 10 is evacuated and a processing chamber 10 into which the process gas G is introduced is formed inside, an antenna 30 provided outside the processing chamber 10, and an antenna 30. It is provided with a high frequency power supply 40 for applying a high frequency (13.56 MHz). When a high frequency is applied to the antenna 30 from the high frequency power supply 40, an induced electric field is generated by forming a high frequency magnetic field generated from the antenna 30 in the processing chamber 10, whereby an inductively coupled plasma P is generated.
  • a high frequency 13.56 MHz
  • a mixed gas containing at least nitrogen gas and oxygen gas is supplied into the processing chamber 10 as a process gas, and in this state, a high frequency is applied to the antenna 30 to generate an inductively coupled plasma.
  • the ratio of the flow rate of nitrogen gas (N 2 / N 2 + O 2 ) to the total flow rate of nitrogen gas and oxygen gas is preferably 70% or more, and preferably 80% or more. More preferably, it is more preferably 90% or more.
  • the larger the flow rate ratio of the nitrogen gas the smaller the fixed charge density in the protective layer 8 to be formed later, which is preferable.
  • this step is preferably performed at a substrate temperature of 150 ° C. or higher and 300 ° C. or lower.
  • the processing time for performing the plasma treatment is not particularly limited, but is preferably 15 seconds or more and 45 seconds or less from the viewpoint of further reducing the fixed charge density in the protective layer 8.
  • RF power, pressure at the time of film formation, absolute amount of process gas, etc. may be set as appropriate.
  • the protective layer 8 is formed so as to cover the surface of the semiconductor layer 5 exposed from between the source electrode 6 and the drain electrode 7. do.
  • the protective layer 8 is formed, for example, by using the plasma CVD method (chemical vapor deposition method) using the plasma CVD apparatus 100 described above.
  • the plasma processing step shifts to the protective layer forming step while maintaining the plasma generated in the processing chamber 10 of the plasma CVD apparatus 100.
  • this protective layer forming step a mixed gas containing SiF 4 (silicon tetrafluoride) gas, nitrogen gas, oxygen gas and hydrogen gas is supplied into the processing chamber 10 as a process gas, and the antenna 30 is in this state.
  • a high frequency is applied to the gas to generate an inductively coupled plasma.
  • the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas (N 2 / N 2 + O 2 ) is not particularly limited, but is substantially the same as, for example, the flow rate ratio in the plasma processing step described above. Is preferable.
  • this step is preferably performed at a substrate temperature of 150 ° C. or higher and 300 ° C. or lower.
  • RF power, pressure at the time of film formation, absolute amount of process gas, etc. may be set as appropriate.
  • the protective layer 8 for example, from a fluorine-containing silicon oxide film (SiN: F), a fluorine-containing silicon oxide film (SiO: F), a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like.
  • a second protective layer may be formed. The film formation of this protective layer can be performed by using a plasma CVD apparatus in the same manner as the protective layer 8.
  • the heat treatment may be performed in an atmosphere under atmospheric pressure containing oxygen.
  • the temperature inside the furnace in the heat treatment is not particularly limited, and is, for example, 150 ° C. or higher and 300 ° C. or lower.
  • the heat treatment time is not particularly limited, and is, for example, 1 hour or more and 3 hours or less.
  • the thin film transistor 1 of the present embodiment can be obtained.
  • the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the plasma treatment step is the same as the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the protective layer forming step. Therefore, it is possible to shift to the protective layer forming step in a state where the plasma generated in the plasma treatment step is stably maintained. As a result, the tact time can be shortened and the manufacturing cost can be reduced. Further, since the process can be shifted to the protective layer forming step while the plasma is stably maintained, the physical adsorption of process gas such as SiC4 gas on the interface between the semiconductor layer 5 and the protective layer 8 can be suppressed, and the adhesion can be improved. High quality interface can be obtained.
  • the thin film transistor 1 of the embodiment is a bottom gate type in which a gate electrode 3, a gate insulating layer 4, and a semiconductor layer 5 are laminated in order from the substrate 2 side, but the present invention is not limited to this.
  • the thin film transistor 1 may be a top gate type in which the semiconductor layer 5, the gate insulating layer 4, and the gate electrode 3 are laminated in order from the substrate 2 side.
  • the gate insulating layer 4 laminated on the semiconductor layer 5 corresponds to the "insulating layer" in the claims.
  • the gate insulating layer 4 includes a fluorine-containing silicon oxynitride film (SiON: F), a fluorine-containing silicon oxide film (SiN: F), a fluorine-containing silicon oxide film (SiO: F), and a silicon nitride film (SiNx). It is preferably composed of a silicon oxide film (SiOx) or the like, and its fixed charge density is preferably 3 ⁇ 10 11 cm -2 or less.
  • the manufacturing method is as follows by performing the semiconductor layer forming step, the source / drain electrode forming step, the plasma processing step, the gate insulating layer forming step, and the gate electrode forming step in this order. Will be done.
  • the gate insulating layer forming step corresponds to the "insulating layer forming step" in the claims. Therefore, in this embodiment, the gate insulating layer forming step is performed by a plasma CVD method using a mixed gas of SiF 4 (silicon tetrafluoride) gas, nitrogen gas, oxygen gas and hydrogen gas as a process gas.
  • SiF 4 silicon tetrafluoride
  • the semiconductor layer 5 is made of an oxide semiconductor, but the present invention is not limited to this.
  • the semiconductor layer 5 may be made of any semiconductor material such as amorphous Si and polycrystalline Si.
  • the protective layer 8 is a fluorine-containing silicon oxynitride film, but the present invention is not limited to this.
  • the protective layer 8 is made of an insulating material such as a fluorine-containing silicon oxide film (SiN: F), a fluorine-containing silicon oxide film (SiO: F), a silicon nitride film (SiNx), and a silicon oxide film (SiOx). It may be a film made of.
  • the plasma processing step is performed after the semiconductor layer forming step and the source / drain electrode forming step are performed, but the present invention is not limited to this.
  • a plasma treatment step may be performed after the semiconductor layer forming step and before the source / drain electrode forming step.
  • sample preparation Specifically, in this embodiment, the surface of the n-type Si substrate is plasma-treated using the plasma CVD apparatus described above, and then a fluorine-containing silicon oxynitride film is formed on the surface of the silicon substrate by the plasma CVD method.
  • Multiple MIS structure samples were prepared by heat treatment at 250 ° C. for 60 minutes in an air atmosphere.
  • a mixed gas containing nitrogen and oxygen was supplied as a process gas using a plasma processing device having a G4 substrate size (680 x 880 mm), and RF power: 0.47 W.
  • the procedure was performed under the conditions of / cm 2 , pressure at the time of film formation: 6 Pa, and set temperature: 200 ° C.
  • the plasma treatment time (0 to 120 seconds) and the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas (0%, 96.7%) were changed for each sample to be prepared.
  • the insulating layer was formed after the plasma treatment by using a plasma CVD apparatus and using a mixed gas of SiF 4 , N 2 , O 2 and H 2 as a raw material gas, and RF power: 0.
  • the fixed charge density of each prepared sample was measured. Specifically, the fixed charge density of each sample was calculated by forming an aluminum-containing electrode in contact with each of the fluorine-containing silicon oxynitride film and the Si substrate and obtaining the flat band shift amount from the CV measurement. The results are shown in FIG. As can be seen from FIG. 5, the sample plasma-treated with the mixed gas in which the ratio of the flow rate of nitrogen gas to the process gas is 96.7% has a good fixed charge density of 3 ⁇ 10 11 cm -2 or less. It turned out to show. Furthermore, it was found that the sample with the plasma treatment time of 15 seconds to 45 seconds showed a good fixed charge density of 1 ⁇ 10 11 cm -2 or less.
  • the present invention it is possible to provide a method for manufacturing a thin film transistor capable of forming an insulating layer having a good fixed charge density in a low temperature process.

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Abstract

A production method for a thin film transistor that includes: a plasma treatment step in which a plasma treatment is performed on the surface of a semiconductor layer using a mixed gas that includes nitrogen and oxygen as a process gas; and an insulating layer formation step in which an insulating layer is formed on the plasma-treated semiconductor layer by plasma CVD using a mixed gas that includes SiF4, nitrogen, oxygen, and hydrogen as a process gas.

Description

薄膜トランジスタの製造方法Manufacturing method of thin film transistor

　本発明は、薄膜トランジスタの製造方法に関するものである。 The present invention relates to a method for manufacturing a thin film transistor.

　近年、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系（ＩＧＺＯ）の酸化物半導体を半導体層（チャネル層）に用いた薄膜トランジスタの開発が活発に行われている。この薄膜トランジスタでは、半導体層の周辺には、シリコン膜（ＳｉＮｘ）や酸化シリコン膜（ＳｉＯｘ）等からなる保護層やゲート絶縁層等の各種絶縁層が形成されている。例えば、特許文献１には、ＳｉＣｌ４ガスとＳｉＦ４ガスと酸素ガスとを含む混合ガスをプロセスガスとして用いたプラズマＣＶＤ法により、フッ素含有シリコン膜からなる絶縁層を半導体層の上に形成するものが記載されている。 In recent years, thin film transistors using In—Ga—Zn—O-based (IGZO) oxide semiconductors for the semiconductor layer (channel layer) have been actively developed. In this thin film transistor, various insulating layers such as a protective layer made of a silicon film (SiN x ) and a silicon oxide film (SiO x ) and a gate insulating layer are formed around the semiconductor layer. For example, in Patent Document 1, an insulating layer made of a fluorine-containing silicon film is formed on a semiconductor layer by a plasma CVD method using a mixed gas containing SiCl4 gas, SiC4 gas and oxygen gas as a process gas. Things are listed.

特開２０１８－１９５６１０号公報JP-A-2018-195610

　しかしながら、特許文献１に開示される製造方法は、３００℃程度の低温プロセスにより絶縁層を成膜するので、絶縁層中の正の固定電荷密度が高くなることで、薄膜トランジスタの閾値電圧が負の方向へシフトし、信頼性が低下する恐れがある。 However, in the manufacturing method disclosed in Patent Document 1, since the insulating layer is formed by a low temperature process of about 300 ° C., the positive fixed charge density in the insulating layer becomes high, and the threshold voltage of the thin film transistor becomes negative. It may shift in the direction and reduce reliability.

　本発明はこのような問題に鑑みてなされたものであり、低温プロセスでも良好な固定電荷密度の絶縁層を形成できる薄膜トランジスタの製造方法を提供することを主たる課題とするものである。 The present invention has been made in view of such problems, and its main object is to provide a method for manufacturing a thin film transistor capable of forming an insulating layer having a good fixed charge density even in a low temperature process.

　すなわち本発明の薄膜トランジスタの製造方法は、半導体層の表面に対して、窒素及び酸素を含む混合ガスをプロセスガスとして用いてプラズマ処理を行うプラズマ処理工程と、ＳｉＦ４、窒素、酸素及び水素を含む混合ガスをプロセスガスとして用いて、プラズマＣＶＤ法により、前記プラズマ処理後の半導体層の上に絶縁層を形成する絶縁層形成工程とを備えることを特徴とする。
　このような製造方法であれば、半導体層の表面をプラズマ処理して活性化させた後で絶縁層を形成するので、例えば３００℃以下の低温プロセスにおいても、良好な固定電荷密度の絶縁層を形成することができる。これによりゲート閾値電圧が高く、信頼性に優れた薄膜トランジスタを製造することができる。 That is, the method for manufacturing a thin film film of the present invention includes a plasma treatment step in which a mixed gas containing nitrogen and oxygen is used as a process gas to perform plasma treatment on the surface of the semiconductor layer, and SiC4 , nitrogen, oxygen and hydrogen. It is characterized by comprising an insulating layer forming step of forming an insulating layer on the semiconductor layer after the plasma treatment by a plasma CVD method using a mixed gas as a process gas.
With such a manufacturing method, the surface of the semiconductor layer is plasma-treated and activated to form an insulating layer. Therefore, an insulating layer having a good fixed charge density can be obtained even in a low temperature process of, for example, 300 ° C. or lower. Can be formed. As a result, it is possible to manufacture a thin film transistor having a high gate threshold voltage and excellent reliability.

　前記絶縁層の具体的態様としてはフッ素含有シリコン酸窒化膜が挙げられる。 Specific embodiments of the insulating layer include a fluorine-containing silicon oxynitride film.

　絶縁層形成工程で形成される絶縁層は固定電荷密度が３×１０１１ｃｍ－２以下であることが好ましい。 The insulating layer formed in the insulating layer forming step preferably has a fixed charge density of 3 × 10 11 cm -2 or less.

　前記プラズマ処理工程において供給する酸素ガスの流量が多いと、半導体層の表面が酸化しすぎて、良好な固定電荷密度の絶縁層が得られない恐れがある。そのため、前記プラズマ処理工程において供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合が７０％以上であることが好ましく、８０％以上であることがより好ましく、９０％以上であることがさらに好ましい。 If the flow rate of oxygen gas supplied in the plasma processing step is large, the surface of the semiconductor layer may be excessively oxidized and an insulating layer having a good fixed charge density may not be obtained. Therefore, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the plasma treatment step is preferably 70% or more, more preferably 80% or more, and more preferably 90% or more. Is even more preferable.

　また、前記プラズマ処理工程において供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合と、前記絶縁層形成工程において供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合とが同一であることが好ましい。
　このようにすれば、プラズマ処理工程と絶縁層形成工程での窒素ガスと酸素ガスの流量割合が同じであるので、プラズマ処理工程で発生させたプラズマを安定的に維持した状態で絶縁層形成工程に移行することができる。これによりタクトタイムを短くでき、製造コストを低減できる。またプラズマを安定的に維持した状態で絶縁層形成工程に移行できるので、半導体層と絶縁層との界面へのＳｉＦ４ガス等のプロセスガスの物理的な吸着を抑制でき、より密着性が高い良質な界面を得ることができる。 Further, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the plasma treatment step, and the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the insulating layer forming step. Are preferably the same.
By doing so, since the flow rate ratios of nitrogen gas and oxygen gas in the plasma treatment step and the insulating layer forming step are the same, the insulating layer forming step is performed while the plasma generated in the plasma treatment step is stably maintained. Can be migrated to. As a result, the tact time can be shortened and the manufacturing cost can be reduced. In addition, since the process of forming the insulating layer can be started while the plasma is stably maintained, the physical adsorption of process gas such as SiC4 gas on the interface between the semiconductor layer and the insulating layer can be suppressed, and the adhesion is higher. A good quality interface can be obtained.

　本発明の効果をより顕著に奏する態様としては、前記プラズマ処理工程及び前記絶縁層形成工程を３００℃以下で行うものが挙げられる。
　このような低温であれば、樹脂等の融点が低い基板を用いた薄膜トランジスタを製造することができる。本発明の製造方法によれば、このような低温処理においても良好な固定電荷密度の絶縁層を備える薄膜トランジスタを製造できる。 As an embodiment in which the effect of the present invention is more prominent, the plasma treatment step and the insulating layer forming step are performed at 300 ° C. or lower.
At such a low temperature, a thin film transistor can be manufactured using a substrate having a low melting point such as a resin. According to the manufacturing method of the present invention, it is possible to manufacture a thin film transistor provided with an insulating layer having a good fixed charge density even in such a low temperature treatment.

　前記半導体層の具体的態様として、Ｉｎ－Ｇａ－Ｚｎ－Ｏにより構成されているものが挙げられる。 As a specific embodiment of the semiconductor layer, a semiconductor layer composed of In—Ga—Zn—O can be mentioned.

　このように構成した本発明によれば、低温プロセスでも良好な固定電荷密度の絶縁層を形成できる薄膜トランジスタの製造方法を提供することができる。 According to the present invention configured as described above, it is possible to provide a method for manufacturing a thin film transistor capable of forming an insulating layer having a good fixed charge density even in a low temperature process.

本実施形態のボトムゲート型の薄膜トランジスタの構成を模式的に示す図。The figure which shows typically the structure of the bottom gate type thin film transistor of this embodiment. 同実施形態の薄膜トランジスタの製造工程を模式的に示す図。The figure which shows typically the manufacturing process of the thin film transistor of the same embodiment. 同実施形態の薄膜トランジスタのプラズマ処理工程で用いられるプラズマ処理装置の構成を模式的に示す図。The figure which shows typically the structure of the plasma processing apparatus used in the plasma processing process of the thin film transistor of the same embodiment. 他の実施形態のトップゲート型の薄膜トランジスタの構成を模式的に示す図。The figure which shows typically the structure of the top gate type thin film transistor of another embodiment. 実験例におけるプラズマ処理と固定電荷密度との関係を示すグラフ。The graph which shows the relationship between plasma processing and fixed charge density in an experimental example.

　以下に、本発明の一実施形態に係る薄膜トランジスタ及びその製造方法について説明する。 The thin film transistor and the manufacturing method thereof according to the embodiment of the present invention will be described below.

＜１．薄膜トランジスタ＞
　本実施形態の薄膜トランジスタ１は所謂ボトムゲート型のＴＦＴであり、酸化物半導体をチャネルに用いたものである。具体的には図１に示すように、基板２と、ゲート電極３と、ゲート絶縁層４と、半導体層５と、ソース電極６及びドレイン電極７と、保護層８とを有しており、基板２側からこの順に形成されている。なおこの実施形態では、保護層８が特許請求の範囲でいう“絶縁層”に相当する。以下、各部について詳述する。 <1. Thin film transistor>
The thin film transistor 1 of the present embodiment is a so-called bottom gate type TFT, and uses an oxide semiconductor as a channel. Specifically, as shown in FIG. 1, it has a substrate 2, a gate electrode 3, a gate insulating layer 4, a semiconductor layer 5, a source electrode 6, a drain electrode 7, and a protective layer 8. It is formed in this order from the substrate 2 side. In this embodiment, the protective layer 8 corresponds to the "insulating layer" in the claims. Hereinafter, each part will be described in detail.

　基板２は光を透過できるような任意の材料から構成されており、例えば、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレナフタレート（ＰＥＮ）、ポリエーテルサルフォン（ＰＥＳ）、アクリル、ポリイミド等のプラスチック（合成樹脂）等の樹脂材料やガラス材料によって構成されてよい。 The substrate 2 is made of an arbitrary material that can transmit light, and is, for example, a plastic (synthetic resin) such as polyethylene terephthalate (PET), polyethylenaphthalate (PEN), polyether sulfone (PES), acrylic, and polyimide. ) And other resin materials and glass materials.

　ゲート電極３は、薄膜トランジスタ１に印加されるゲート電圧によって半導体層５中のキャリア密度を制御するものである。このゲート電極３は、高い導電性を有する任意の材料から構成されており、例えばＳｉ、Ａｌ、Ｍｏ、Ｃｒ、Ｔａ、Ｔｉ、Ｐｔ、Ａｕ、Ａｇ等から選択される１種以上の金属から構成されてよい。また、Ａｌ－Ｎｄ、Ａｇ合金、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫（ＩＴＯ）、酸化亜鉛インジウム（ＩＺＯ）、Ｉｎ－Ｇａ－Ｚｎ－Ｏ（ＩＧＺＯ）等の金属酸化物の導電性膜から構成されてよい。ゲート電極３は、これらの導電性膜の単層構造又は２層以上の積層構造から構成されてもよい。 The gate electrode 3 controls the carrier density in the semiconductor layer 5 by the gate voltage applied to the thin film transistor 1. The gate electrode 3 is made of any material having high conductivity, and is made of one or more metals selected from, for example, Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag and the like. May be done. Further, the conductivity of metal oxides such as Al-Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), and In-Ga-Zn-O (IGZO). It may be composed of a membrane. The gate electrode 3 may be composed of a single-layer structure of these conductive films or a laminated structure of two or more layers.

　ゲート絶縁層４は高い絶縁性を有する任意の絶縁材料から構成されており、例えば、ＳｉＯｘ、ＳｉＮｘ、ＳｉＯＮ、Ａｌ２Ｏ３、Ｙ２Ｏ３、Ｔａ２Ｏ５、Ｈｆ２等から選択される１つ以上の酸化物を含む絶縁膜であってよい。ゲート絶縁層４は、これらの導電性膜を単層構造又は２層以上の積層構造としたものであってよい。 The gate insulating layer 4 is made of any insulating material having high insulating properties, and is selected from, for example, SiO x , SiN x , SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , Hf 2 and the like. It may be an insulating film containing one or more oxides to be formed. The gate insulating layer 4 may have a single-layer structure or a laminated structure of two or more layers of these conductive films.

　半導体層（チャネル層）５は、ソース電極６とドレイン電極７間を流れる電流を通過させるものである。本実施形態の半導体層５は、酸化物半導体からなるものであり、例えばＩｎ、Ｇａ、Ｚｎ、Ｓｎ、Ａｌ、Ｔｉ等から選択される少なくとも１種の元素の酸化物を主成分として含んでいる。半導体層５を構成する材料の具体例としては、例えば、Ｉｎ－Ｇａ－Ｚｎ－Ｏ（ＩＧＺＯ）、Ｉｎ－Ａｌ－Ｍｇ－Ｏ、Ｉｎ－Ａｌ－Ｚｎ－Ｏ又はＩｎ－Ｈｆ－Ｚｎ－Ｏ等が挙げられる。この半導体層５は非晶質（アモルファス）の酸化物半導体膜により構成されている。本実施形態の半導体層５は単層構造であるが、これに限らず、組成や結晶性が互いに異なる複数の層を重ねて構成した積層構造であってもよい。 The semiconductor layer (channel layer) 5 allows the current flowing between the source electrode 6 and the drain electrode 7 to pass through. The semiconductor layer 5 of the present embodiment is made of an oxide semiconductor and contains, for example, an oxide of at least one element selected from In, Ga, Zn, Sn, Al, Ti and the like as a main component. .. Specific examples of the material constituting the semiconductor layer 5 include In-Ga-Zn-O (IGZO), In-Al-Mg-O, In-Al-Zn-O, In-Hf-Zn-O, and the like. Can be mentioned. The semiconductor layer 5 is made of an amorphous oxide semiconductor film. The semiconductor layer 5 of the present embodiment has a single-layer structure, but is not limited to this, and may have a laminated structure in which a plurality of layers having different compositions and crystallinities are laminated.

　ソース電極６及びドレイン電極７は、半導体層５の表面を部分的に覆うように、互いに離間して形成されている。ソース電極６及びドレイン電極７は、ゲート電極３と同様に、電極として機能するように高い導電性を有する材料から構成されている。ソース電極６及びドレイン電極７は、単一の材料からなる単層構造でよく、互いに異なる材料からなる複数の層を重ねた積層構造であってもよい。 The source electrode 6 and the drain electrode 7 are formed so as to be separated from each other so as to partially cover the surface of the semiconductor layer 5. Like the gate electrode 3, the source electrode 6 and the drain electrode 7 are made of a material having high conductivity so as to function as an electrode. The source electrode 6 and the drain electrode 7 may have a single-layer structure made of a single material, or may have a laminated structure in which a plurality of layers made of different materials are stacked.

　保護層（パッシベーション層）８は、ソース電極６とドレイン電極７の間から露出する半導体層５の表面（チャネル領域）を覆って保護するものであり、絶縁性の材料により構成されたものである。保護層８は、少なくとも半導体層５の表面に接触して設けられている。本実施形態の保護層８は、ソース電極６及びドレイン電極７の表面を更に覆うように設けられている。 The protective layer (passivation layer) 8 covers and protects the surface (channel region) of the semiconductor layer 5 exposed from between the source electrode 6 and the drain electrode 7, and is made of an insulating material. .. The protective layer 8 is provided in contact with at least the surface of the semiconductor layer 5. The protective layer 8 of the present embodiment is provided so as to further cover the surfaces of the source electrode 6 and the drain electrode 7.

　具体的にこの保護層８は、フッ素含有シリコン酸窒化膜（ＳｉＯＮ：Ｆ）により構成されている。このフッ素含有シリコン酸窒化膜は、固定電荷密度が３×１０１１ｃｍ－２以下であることが好ましく、１×１０１１ｃｍ－２以下であることがより好ましい。 Specifically, the protective layer 8 is made of a fluorine-containing silicon oxynitride film (SiON: F). The fluorine-containing silicon oxynitride film preferably has a fixed charge density of 3 × 10 11 cm -2 or less, and more preferably 1 × 10 11 cm -2 or less.

　なお保護層８の上には、例えばフッ素含有シリコン酸化膜（ＳｉＮ：Ｆ）、フッ素含有シリコン酸化膜（ＳｉＯ：Ｆ）、シリコン窒化膜（ＳｉＮｘ）、シリコン酸化膜（ＳｉＯｘ）等からなる第２の保護層が、必要に応じて更に設けられてもよい。 A second layer composed of, for example, a fluorine-containing silicon oxide film (SiN: F), a fluorine-containing silicon oxide film (SiO: F), a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like is placed on the protective layer 8. A protective layer may be further provided as needed.

＜２．薄膜トランジスタの製造方法＞
　次に、上述した構造の薄膜トランジスタ１の製造方法を、図２を参照して説明する。
　本実施形態の薄膜トランジスタ１の製造方法は、ゲート電極形成工程、ゲート絶縁層形成工程、半導体層形成工程、ソース・ドレイン電極形成工程、プラズマ処理工程及び保護層形成工程を含む。なおこの実施形態では、保護層形成工程が特許請求の範囲でいう“絶縁層形成工程”に相当する。以下、各工程について説明する。 <2. Manufacturing method of thin film transistor>
Next, a method for manufacturing the thin film transistor 1 having the above-mentioned structure will be described with reference to FIG.
The method for manufacturing the thin film film 1 of the present embodiment includes a gate electrode forming step, a gate insulating layer forming step, a semiconductor layer forming step, a source / drain electrode forming step, a plasma processing step, and a protective layer forming step. In this embodiment, the protective layer forming step corresponds to the "insulating layer forming step" in the claims. Hereinafter, each step will be described.

（１）ゲート電極形成工程
　まず図２の（ａ）に示すように、例えばＰＥＴ等の樹脂材料からなる基板２を準備し、基板２の表面にゲート電極３を形成する。ゲート電極３の形成方法は特に制限されず、例えば真空蒸着法等の既知の方法により形成してよい。 (1) Gate Electrode Forming Step First, as shown in FIG. 2A, a substrate 2 made of a resin material such as PET is prepared, and a gate electrode 3 is formed on the surface of the substrate 2. The method for forming the gate electrode 3 is not particularly limited, and the gate electrode 3 may be formed by a known method such as a vacuum vapor deposition method.

（２）ゲート絶縁層形成工程
　次に、図２の（ｂ）に示すように、基板２及びゲート電極３の表面を覆うようにゲート絶縁層４を形成する。ゲート絶縁層４の形成方法は特に限定されず、既知の方法により形成してよい。 (2) Gate insulating layer forming step Next, as shown in FIG. 2B, the gate insulating layer 4 is formed so as to cover the surfaces of the substrate 2 and the gate electrode 3. The method for forming the gate insulating layer 4 is not particularly limited, and the gate insulating layer 4 may be formed by a known method.

（３）半導体層形成工程
　次に、図２の（ｃ）に示すように、ゲート絶縁層４上に半導体層５を形成する。この半導体層５は、既知の方法により形成してよい。例えば、誘導結合型のプラズマを用いて、ＩｎＧａＺｎＯ等の導電性酸化物焼結体をターゲットとしてスパッタリングすることにより半導体層５を形成してよい。なおこれに限らず、他の方法により酸化物半導体からなる半導体層５を形成してもよい。 (3) Semiconductor layer forming step Next, as shown in FIG. 2 (c), the semiconductor layer 5 is formed on the gate insulating layer 4. The semiconductor layer 5 may be formed by a known method. For example, the semiconductor layer 5 may be formed by sputtering a conductive oxide sintered body such as InGaZnO using an inductively coupled plasma as a target. Not limited to this, the semiconductor layer 5 made of an oxide semiconductor may be formed by another method.

（４）ソース・ドレイン電極形成工程
　次に、図２の（ｄ）に示すように、半導体層５上にソース電極６及びドレイン電極７を形成する。ソース電極６およびドレイン電極７の形成は、例えば、ＲＦマグネトロンスパッタリング等を用いた既知の方法により形成することができる。ソース電極６及びドレイン電極７は、半導体層５の表面上で互いに離間し、半導体層５の表面の一部を露出させるように形成される。 (4) Source / Drain Electrode Forming Step Next, as shown in FIG. 2D, the source electrode 6 and the drain electrode 7 are formed on the semiconductor layer 5. The source electrode 6 and the drain electrode 7 can be formed by a known method using, for example, RF magnetron sputtering or the like. The source electrode 6 and the drain electrode 7 are formed so as to be separated from each other on the surface of the semiconductor layer 5 and to expose a part of the surface of the semiconductor layer 5.

（５）プラズマ処理工程
　次に、半導体層５の表面に保護層８を形成する前に、半導体層５の表面に対してプラズマ処理（成膜前処理）を行う。具体的にこのプラズマ処理は、図３に例示するような誘導結合型のプラズマ処理装置１００を用いて行われる。具体的にプラズマ処理装置１００は、真空排気され且つプロセスガスＧが導入される処理室１０が内側に形成された真空容器２０と、処理室１０の外部に設けられたアンテナ３０と、アンテナ３０に高周波（１３．５６ＭＨｚ）を印加する高周波電源４０とを備えている。高周波電源４０からアンテナ３０に高周波を印加すると、アンテナ３０から発生した高周波磁場が処理室１０内に形成されることで誘導電界が発生し、これにより誘導結合型のプラズマＰが生成される。 (5) Plasma Treatment Step Next, before forming the protective layer 8 on the surface of the semiconductor layer 5, plasma treatment (pretreatment for film formation) is performed on the surface of the semiconductor layer 5. Specifically, this plasma processing is performed using an inductively coupled plasma processing apparatus 100 as illustrated in FIG. Specifically, the plasma processing apparatus 100 includes a vacuum container 20 in which a processing chamber 10 is evacuated and a processing chamber 10 into which the process gas G is introduced is formed inside, an antenna 30 provided outside the processing chamber 10, and an antenna 30. It is provided with a high frequency power supply 40 for applying a high frequency (13.56 MHz). When a high frequency is applied to the antenna 30 from the high frequency power supply 40, an induced electric field is generated by forming a high frequency magnetic field generated from the antenna 30 in the processing chamber 10, whereby an inductively coupled plasma P is generated.

　具体的にこの工程では、少なくとも窒素ガスと酸素ガスとを含む混合ガスをプロセスガスとして処理室１０内に供給し、この状態でアンテナ３０に高周波を印加して誘導結合型のプラズマを生じさせる。ここで供給するプロセスガスは、窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合（Ｎ２／Ｎ２＋Ｏ２）が、７０％以上であることが好ましく、８０％以上であることがより好ましく、９０％以上であることがさらに好ましい。窒素ガスの流量割合が大きいほど、後で形成する保護層８中の固定電荷密度を小さくできるので好ましい。またこの工程は、基板温度を１５０℃以上３００℃以下の低温で行うことが好ましい。プラズマ処理を行う処理時間は特に限定されないが、保護層８中の固定電荷密度をより小さくする観点から１５秒以上４５秒以下が好ましい。その他、ＲＦパワー、成膜時圧力、プロセスガスの絶対量等は適宜設定されてよい。 Specifically, in this step, a mixed gas containing at least nitrogen gas and oxygen gas is supplied into the processing chamber 10 as a process gas, and in this state, a high frequency is applied to the antenna 30 to generate an inductively coupled plasma. In the process gas supplied here, the ratio of the flow rate of nitrogen gas (N 2 / N 2 + O 2 ) to the total flow rate of nitrogen gas and oxygen gas is preferably 70% or more, and preferably 80% or more. More preferably, it is more preferably 90% or more. The larger the flow rate ratio of the nitrogen gas, the smaller the fixed charge density in the protective layer 8 to be formed later, which is preferable. Further, this step is preferably performed at a substrate temperature of 150 ° C. or higher and 300 ° C. or lower. The processing time for performing the plasma treatment is not particularly limited, but is preferably 15 seconds or more and 45 seconds or less from the viewpoint of further reducing the fixed charge density in the protective layer 8. In addition, RF power, pressure at the time of film formation, absolute amount of process gas, etc. may be set as appropriate.

（６）保護層形成工程
　プラズマ処理工程の後、図２の（ｅ）に示すように、ソース電極６及びドレイン電極７の間から露出する半導体層５の表面を覆うように保護層８を形成する。この保護層８の形成は、例えば前記したプラズマＣＶＤ装置１００を用いてプラズマＣＶＤ法（化学気相成長法）を用いて行われる。ここでは、プラズマ処理工程においてプラズマＣＶＤ装置１００の処理室１０内に生成したプラズマを維持した状態で保護層形成工程に移行するようにしている。 (6) Protective layer forming step After the plasma treatment step, as shown in FIG. 2 (e), the protective layer 8 is formed so as to cover the surface of the semiconductor layer 5 exposed from between the source electrode 6 and the drain electrode 7. do. The protective layer 8 is formed, for example, by using the plasma CVD method (chemical vapor deposition method) using the plasma CVD apparatus 100 described above. Here, in the plasma processing step, the process shifts to the protective layer forming step while maintaining the plasma generated in the processing chamber 10 of the plasma CVD apparatus 100.

　具体的にこの保護層形成工程では、プロセスガスとして、ＳｉＦ４（四フッ化ケイ素）ガス、窒素ガス、酸素ガス及び水素ガスを含む混合ガスを処理室１０内に供給し、この状態でアンテナ３０に高周波を印加して誘導結合型のプラズマを生じさせる。供給するプロセスガスにおいて、窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合（Ｎ２／Ｎ２＋Ｏ２）は特に限定されないが、例えば前記したプラズマ処理工程における流量割合と略同一であることが好ましい。またこの工程は、基板温度を１５０℃以上３００℃以下の低温で行うことが好ましい。その他、ＲＦパワー、成膜時圧力、プロセスガスの絶対量等は適宜設定されてよい。 Specifically, in this protective layer forming step, a mixed gas containing SiF 4 (silicon tetrafluoride) gas, nitrogen gas, oxygen gas and hydrogen gas is supplied into the processing chamber 10 as a process gas, and the antenna 30 is in this state. A high frequency is applied to the gas to generate an inductively coupled plasma. In the process gas to be supplied, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas (N 2 / N 2 + O 2 ) is not particularly limited, but is substantially the same as, for example, the flow rate ratio in the plasma processing step described above. Is preferable. Further, this step is preferably performed at a substrate temperature of 150 ° C. or higher and 300 ° C. or lower. In addition, RF power, pressure at the time of film formation, absolute amount of process gas, etc. may be set as appropriate.

　必要に応じて、保護層８の上に、例えばフッ素含有シリコン酸化膜（ＳｉＮ：Ｆ）、フッ素含有シリコン酸化膜（ＳｉＯ：Ｆ）、シリコン窒化膜（ＳｉＮｘ）、シリコン酸化膜（ＳｉＯｘ）等からなる第２の保護層を成膜してもよい。この保護層の成膜は、保護層８と同様に、プラズマＣＶＤ装置を用いて行うことができる。 If necessary, on the protective layer 8, for example, from a fluorine-containing silicon oxide film (SiN: F), a fluorine-containing silicon oxide film (SiO: F), a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like. A second protective layer may be formed. The film formation of this protective layer can be performed by using a plasma CVD apparatus in the same manner as the protective layer 8.

（７）熱処理工程
　必要に応じて酸素を含む大気圧下の雰囲気中で熱処理を行ってもよい。熱処理における炉内温度は特に限定されず、例えば１５０℃以上３００℃以下である。また熱処理時間は特に限定されず、例えば１時間以上３時間以下である。 (7) Heat treatment step If necessary, the heat treatment may be performed in an atmosphere under atmospheric pressure containing oxygen. The temperature inside the furnace in the heat treatment is not particularly limited, and is, for example, 150 ° C. or higher and 300 ° C. or lower. The heat treatment time is not particularly limited, and is, for example, 1 hour or more and 3 hours or less.

　以上により、本実施形態の薄膜トランジスタ１を得ることができる。 From the above, the thin film transistor 1 of the present embodiment can be obtained.

＜３．本実施形態の効果＞
　このように構成した本実施形態の薄膜トランジスタ１の製造方法であれば、半導体層を形成した後、プラズマ処理工程において半導体層５の表面をプラズマ処理して活性化させ、その状態で保護層８を形成するので、３００℃以下の低温プロセスであっても、良好な固定電荷密度の保護層８を形成することができる。これによりゲート閾値電圧が高く、信頼性に優れた薄膜トランジスタ１を製造することができる。 <3. Effect of this embodiment>
In the manufacturing method of the thin film transistor 1 of the present embodiment configured as described above, after forming the semiconductor layer, the surface of the semiconductor layer 5 is plasma-treated and activated in the plasma processing step, and the protective layer 8 is provided in that state. Since it is formed, the protective layer 8 having a good fixed charge density can be formed even in a low temperature process of 300 ° C. or lower. As a result, the thin film transistor 1 having a high gate threshold voltage and excellent reliability can be manufactured.

　また、プラズマ処理工程において供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合と、保護層形成工程において供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合とが同一であるので、プラズマ処理工程で発生させたプラズマを安定的に維持した状態で保護層形成工程に移行することができる。これによりタクトタイムを短くでき、製造コストを低減できる。またプラズマを安定的に維持した状態で保護層形成工程に移行できるので、半導体層５と保護層８との界面へのＳｉＦ４ガス等のプロセスガスの物理的な吸着を抑制でき、より密着性が高い良質な界面を得ることができる。 In addition, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the plasma treatment step is the same as the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the protective layer forming step. Therefore, it is possible to shift to the protective layer forming step in a state where the plasma generated in the plasma treatment step is stably maintained. As a result, the tact time can be shortened and the manufacturing cost can be reduced. Further, since the process can be shifted to the protective layer forming step while the plasma is stably maintained, the physical adsorption of process gas such as SiC4 gas on the interface between the semiconductor layer 5 and the protective layer 8 can be suppressed, and the adhesion can be improved. High quality interface can be obtained.

＜４．その他の変形実施形態＞
　なお、本発明は前記実施形態に限られるものではない。 <4. Other Modifications>
The present invention is not limited to the above embodiment.

　前記実施形態の薄膜トランジスタ１は、ゲート電極３、ゲート絶縁層４及び半導体層５が基板２側から順に積層されたボトムゲート型のものであったがこれに限らない。他の実施形態では、図４に示すように、薄膜トランジスタ１は、半導体層５、ゲート絶縁層４、及びゲート電極３が基板２側から順に積層されたトップゲート型のものであってもよい。この場合には、半導体層５上に積層されるゲート絶縁層４が特許請求の範囲でいう“絶縁層”に相当する。この場合、ゲート絶縁層４は、フッ素含有シリコン酸窒化膜（ＳｉＯＮ：Ｆ）、フッ素含有シリコン酸化膜（ＳｉＮ：Ｆ）、フッ素含有シリコン酸化膜（ＳｉＯ：Ｆ）、シリコン窒化膜（ＳｉＮｘ）、シリコン酸化膜（ＳｉＯｘ）等により構成されるのが好ましく、その固定電荷密度が３×１０１１ｃｍ－２以下であることが好ましい。 The thin film transistor 1 of the embodiment is a bottom gate type in which a gate electrode 3, a gate insulating layer 4, and a semiconductor layer 5 are laminated in order from the substrate 2 side, but the present invention is not limited to this. In another embodiment, as shown in FIG. 4, the thin film transistor 1 may be a top gate type in which the semiconductor layer 5, the gate insulating layer 4, and the gate electrode 3 are laminated in order from the substrate 2 side. In this case, the gate insulating layer 4 laminated on the semiconductor layer 5 corresponds to the "insulating layer" in the claims. In this case, the gate insulating layer 4 includes a fluorine-containing silicon oxynitride film (SiON: F), a fluorine-containing silicon oxide film (SiN: F), a fluorine-containing silicon oxide film (SiO: F), and a silicon nitride film (SiNx). It is preferably composed of a silicon oxide film (SiOx) or the like, and its fixed charge density is preferably 3 × 10 11 cm -2 or less.

　また薄膜トランジスタ１がトップゲート型である場合、その製造方法は、前記した半導体層形成工程、ソース・ドレイン電極形成工程、プラズマ処理工程、ゲート絶縁層形成工程及びゲート電極形成工程をこの順に行うことで行われる。この場合には、ゲート絶縁層形成工程が特許請求の範囲でいう“絶縁層形成工程”に相当する。
　そのためこの実施形態では、ゲート絶縁層形成工程は、ＳｉＦ４（四フッ化ケイ素）ガス、窒素ガス、酸素ガス及び水素ガスの混合ガスをプロセスガスとして用いて、プラズマＣＶＤ法により行われる。具体的な方法は、前記した保護層形成工程と同様である。 When the thin film 1 is a top gate type, the manufacturing method is as follows by performing the semiconductor layer forming step, the source / drain electrode forming step, the plasma processing step, the gate insulating layer forming step, and the gate electrode forming step in this order. Will be done. In this case, the gate insulating layer forming step corresponds to the "insulating layer forming step" in the claims.
Therefore, in this embodiment, the gate insulating layer forming step is performed by a plasma CVD method using a mixed gas of SiF 4 (silicon tetrafluoride) gas, nitrogen gas, oxygen gas and hydrogen gas as a process gas. The specific method is the same as the protective layer forming step described above.

　前記実施形態では、半導体層５は酸化物半導体からなるものであったが、これに限らない。他の実施形態は、半導体層５は、例えばアモルファスＳｉや多結晶Ｓｉ等、任意の半導体材料により構成されてもよい。 In the above embodiment, the semiconductor layer 5 is made of an oxide semiconductor, but the present invention is not limited to this. In another embodiment, the semiconductor layer 5 may be made of any semiconductor material such as amorphous Si and polycrystalline Si.

　前記実施形態では、保護層８はフッ素含有シリコン酸窒化膜であったがこれに限らない。他の実施形態では、保護層８はフッ素含有シリコン酸化膜（ＳｉＮ：Ｆ）、フッ素含有シリコン酸化膜（ＳｉＯ：Ｆ）、シリコン窒化膜（ＳｉＮｘ）、シリコン酸化膜（ＳｉＯｘ）等の絶縁材料からなる膜であってもよい。 In the above embodiment, the protective layer 8 is a fluorine-containing silicon oxynitride film, but the present invention is not limited to this. In another embodiment, the protective layer 8 is made of an insulating material such as a fluorine-containing silicon oxide film (SiN: F), a fluorine-containing silicon oxide film (SiO: F), a silicon nitride film (SiNx), and a silicon oxide film (SiOx). It may be a film made of.

　また、前記実施形態では、半導体層形成工程及びソース・ドレイン電極形成工程を行った後にプラズマ処理工程を行っていたが、これに限らない。他の実施形態では、半導体層形成工程の後、ソース・ドレイン電極形成工程の前にプラズマ処理工程を行ってもよい。 Further, in the above-described embodiment, the plasma processing step is performed after the semiconductor layer forming step and the source / drain electrode forming step are performed, but the present invention is not limited to this. In another embodiment, a plasma treatment step may be performed after the semiconductor layer forming step and before the source / drain electrode forming step.

　その他、本発明は前記実施形態に限られず、その趣旨を逸脱しない範囲で種々の変形が可能であるのは言うまでもない。 In addition, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made without departing from the spirit of the present invention.

　以下、実施例を挙げて本発明をより具体的に説明する。本発明は以下の実施例によって制限を受けるものではなく、前記、後記の趣旨に適合し得る範囲で適当に変更を加えて実施することが勿論可能であり、それらはいずれも本発明の技術的範囲に包含される。 Hereinafter, the present invention will be described in more detail with reference to examples. The present invention is not limited by the following examples, and it is of course possible to carry out the present invention with appropriate modifications within a range that can be adapted to the above-mentioned purpose, and all of them are technical of the present invention. Included in the range.

＜半導体層へのプラズマ処理と固定電荷密度との関係性＞
　絶縁層の成膜前の半導体層の表面へのプラズマ処理と、成膜した絶縁層の固定電荷密度との関係性を評価した。 <Relationship between plasma treatment of semiconductor layer and fixed charge density>
The relationship between the plasma treatment on the surface of the semiconductor layer before the film formation of the insulating layer and the fixed charge density of the film-formed insulating layer was evaluated.

（サンプル作製）
　具体的にこの実施例では、前記したプラズマＣＶＤ装置を用いてｎ型のＳｉ基板の表面をプラズマ処理した後、シリコン基板表面に、フッ素含有シリコン酸窒化膜をプラズマＣＶＤ法により成膜し、その後大気雰囲気の下２５０℃で６０分間熱処理を行うことで、複数のＭＩＳ構造のサンプルを作製した。 (Sample preparation)
Specifically, in this embodiment, the surface of the n-type Si substrate is plasma-treated using the plasma CVD apparatus described above, and then a fluorine-containing silicon oxynitride film is formed on the surface of the silicon substrate by the plasma CVD method. Multiple MIS structure samples were prepared by heat treatment at 250 ° C. for 60 minutes in an air atmosphere.

　いずれのサンプルも、シリコン基板へのプラズマ処理は、Ｇ４基板サイズ（６８０×８８０ｍｍ）のプラズマ処理装置を用いて、プロセスガスとして窒素と酸素とを含む混合ガスを供給し、ＲＦパワー：０．４７Ｗ／ｃｍ２、成膜時の圧力：６Ｐａ、設定温度：２００℃の条件で行った。ここで、作製するサンプル毎に、プラズマ処理の時間（０～１２０秒）と、窒素ガス及び酸素ガスの合計流量に対する窒素ガスの流量の割合（０％、９６．７％）とを変更した。またいずれのサンプルも、プラズマ処理後の絶縁層の成膜処理を、プラズマＣＶＤ装置を用いて、原料ガスとしてＳｉＦ４、Ｎ２、Ｏ２及びＨ２の混合ガスを用い、ＲＦパワー：０．７１Ｗ／ｃｍ２、成膜時の圧力：６Ｐａ、設定温度：２００℃、ガス流量：ＳｉＦ４／Ｎ２／Ｏ２／Ｈ２＝２００／１１６０／４０／３６０ｓｃｃｍ、の条件で行った。 In each sample, for plasma treatment on a silicon substrate, a mixed gas containing nitrogen and oxygen was supplied as a process gas using a plasma processing device having a G4 substrate size (680 x 880 mm), and RF power: 0.47 W. The procedure was performed under the conditions of / cm 2 , pressure at the time of film formation: 6 Pa, and set temperature: 200 ° C. Here, the plasma treatment time (0 to 120 seconds) and the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas (0%, 96.7%) were changed for each sample to be prepared. In each sample, the insulating layer was formed after the plasma treatment by using a plasma CVD apparatus and using a mixed gas of SiF 4 , N 2 , O 2 and H 2 as a raw material gas, and RF power: 0. The procedure was performed under the conditions of 71 W / cm 2 , pressure at the time of film formation: 6 Pa, set temperature: 200 ° C., gas flow rate: SiF 4 / N 2 / O 2 / H 2 = 200/1160/40/360 sccm.

（固定電荷密度の測定）
　次に作製した各サンプルの固定電荷密度を測定した。具体的には、フッ素含有シリコン酸窒化膜およびＳｉ基板それぞれにコンタクトするアルミニウム含有の電極を形成し、ＣＶ測定からフラットバンドシフト量を求めることにより、各サンプルの固定電荷密度を算出した。その結果を図５に示す。図５から分かるように、プロセスガスにおける窒素ガスの流量の割合が９６．７％である混合ガスを用いてプラズマ処理をしたサンプルは、３×１０１１ｃｍ－２以下の良好な固定電荷密度を示すことが分かった。さらに、プラズマ処理の時間を１５秒～４５秒としたサンプルは、１×１０１１ｃｍ－２以下の良好な固定電荷密度を示すことが分かった。 (Measurement of fixed charge density)
Next, the fixed charge density of each prepared sample was measured. Specifically, the fixed charge density of each sample was calculated by forming an aluminum-containing electrode in contact with each of the fluorine-containing silicon oxynitride film and the Si substrate and obtaining the flat band shift amount from the CV measurement. The results are shown in FIG. As can be seen from FIG. 5, the sample plasma-treated with the mixed gas in which the ratio of the flow rate of nitrogen gas to the process gas is 96.7% has a good fixed charge density of 3 × 10 11 cm -2 or less. It turned out to show. Furthermore, it was found that the sample with the plasma treatment time of 15 seconds to 45 seconds showed a good fixed charge density of 1 × 10 11 cm -2 or less.

　本発明によれば、低温プロセスにおいて良好な固定電荷密度の絶縁層を形成できる薄膜トランジスタの製造方法を提供できる。 According to the present invention, it is possible to provide a method for manufacturing a thin film transistor capable of forming an insulating layer having a good fixed charge density in a low temperature process.

　１　　・・・薄膜トランジスタ
　２　　・・・基板
　３　　・・・ゲート電極
　４　　・・・ゲート絶縁層
　５　　・・・半導体層
　６　　・・・ソース電極
　７　　・・・ドレイン電極
　８　　・・・保護層 1 ・ ・ ・ Thin film transistor 2 ・ ・ ・ Substrate 3 ・ ・ ・ Gate electrode 4 ・ ・ ・ Gate insulating layer 5 ・ ・ ・ Semiconductor layer 6 ・ ・ ・ Source electrode 7 ・ ・ ・ Drain electrode 8 ・ ・ ・ Protective layer

Claims (7)

　半導体層の表面に対して、窒素及び酸素を含む混合ガスをプロセスガスとして用いてプラズマ処理を行うプラズマ処理工程と、
　ＳｉＦ４、窒素、酸素及び水素を含む混合ガスをプロセスガスとして用いて、プラズマＣＶＤ法により、前記プラズマ処理後の半導体層の上に絶縁層を形成する絶縁層形成工程と、を備える薄膜トランジスタの製造方法。 A plasma treatment step in which a mixed gas containing nitrogen and oxygen is used as a process gas to perform plasma treatment on the surface of the semiconductor layer.
Manufacture of a thin film transistor comprising a step of forming an insulating layer on the semiconductor layer after plasma treatment by a plasma CVD method using a mixed gas containing SiF 4 , nitrogen, oxygen and hydrogen as a process gas. Method. 　前記絶縁層がフッ素含有シリコン酸窒化膜である請求項１に記載の薄膜トランジスタの製造方法。 The method for manufacturing a thin film transistor according to claim 1, wherein the insulating layer is a fluorine-containing silicon oxynitride film. 　前記絶縁層の固定電荷密度が３×１０１１ｃｍ－２以下である請求項１又は２に記載の薄膜トランジスタの製造方法。 The method for manufacturing a thin film transistor according to claim 1 or 2, wherein the fixed charge density of the insulating layer is 3 × 10 11 cm -2 or less. 　前記プラズマ処理工程において供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合が９０％以上である請求項１～３のいずれか一項に記載の薄膜トランジスタの製造方法。 The method for manufacturing a thin film film according to any one of claims 1 to 3, wherein the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the plasma processing step is 90% or more. 　前記プラズマ処理工程において供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合と、前記絶縁層形成工程において供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合とが同一である請求項１～４のいずれか一項に記載の薄膜トランジスタの製造方法。 The ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the plasma treatment step is the same as the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied in the insulating layer forming step. The method for manufacturing a thin film film according to any one of claims 1 to 4. 　前記プラズマ処理工程及び前記絶縁層形成工程を３００℃以下で行う請求項１～５のいずれか一項に記載の薄膜トランジスタの製造方法。 The method for manufacturing a thin film transistor according to any one of claims 1 to 5, wherein the plasma treatment step and the insulating layer forming step are performed at 300 ° C. or lower. 　前記半導体層がＩｎ－Ｇａ－Ｚｎ－Ｏにより構成されている請求項１～６のいずれか一項に記載の薄膜トランジスタの製造方法。 The method for manufacturing a thin film transistor according to any one of claims 1 to 6, wherein the semiconductor layer is made of In—Ga—Zn—O.
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