WO2022120559A1

WO2022120559A1 - Successive-approximation-register-type analog-to-digital converter, related chip and electronic apparatus

Info

Publication number: WO2022120559A1
Application number: PCT/CN2020/134459
Authority: WO
Inventors: 陈俊熹
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2020-12-08
Filing date: 2020-12-08
Publication date: 2022-06-16

Abstract

A successive-approximation-register-type analog-to-digital converter, which converts an analog input voltage into a digital signal according to a positive reference voltage and a negative reference voltage, wherein the analog input voltage comprises a positive-terminal input voltage and a negative-terminal input voltage. During operation, the successive-approximation-register-type analog-to-digital converter sequentially enters a sampling phase, a charge reallocation phase and a conversion phase. The successive-approximation-register-type analog-to-digital converter comprises a most-significant-bit capacitor bank, a non-most-significant-bit capacitor bank, a comparator and a controller, wherein in the sampling phase, the controller controls the voltage difference between an upper polar plate and a lower polar plate of each capacitor in the most-significant-bit capacitor bank to be zero, and controls the absolute value of the voltage difference between an upper polar plate and a lower polar plate of each capacitor in the non-most-significant-bit capacitor bank to be the absolute value of the voltage difference between the positive-terminal input voltage and the negative-terminal input voltage; in the charge reallocation phase, the controller controls each capacitor in the most-significant-bit capacitor bank and in the non-most-significant-bit capacitor bank to be disconnected from the analog input voltage, and controls the upper polar plate of each capacitor in the most-significant-bit capacitor bank and in the non-most-significant-bit capacitor bank to be coupled to the comparator, such that charges accumulated by each capacitor in the non-most-significant-bit capacitor bank during the sampling phase are reallocated in each capacitor in the most-significant-bit capacitor bank and in the non-most-significant-bit capacitor bank; and the comparator outputs a first comparison result, the first comparison result corresponding to the most significant bit of the digital signal.

Description

Successive approximation register type analog-to-digital converter and related chips and electronic devices

technical field

The present application relates to an analog-to-digital converter, and in particular, to a successive approximation register-type analog-to-digital converter and related chips and electronic devices.

Background technique

Medium-high-speed, medium-high precision analog-to-digital converter designs usually use a capacitive successive-approximation-register (SAR) architecture to achieve higher energy efficiency. Common analog-to-digital converter input methods include single-ended input and differential input, among which single-ended input analog-to-digital converters are often used for power supply voltage and temperature measurement. In single-ended input applications, the input common-mode voltage will vary with the input signal. In other words, the offset voltage of the comparator will be related to the input signal, resulting in harmonic distortion and integration/differentiation in the output of the analog-to-digital conversion. Non-linear (integral/differential nonlinearities, INL/DNL) errors rise.

Therefore, how to solve the above problems has become one of the problems that need to be solved urgently in this field.

SUMMARY OF THE INVENTION

One of the objectives of the present application is to disclose a successive approximation register-based analog-to-digital converter and related chips and electronic devices to solve the above problems.

An embodiment of the present application discloses a successive approximation register type analog-to-digital converter for converting an analog input voltage into a digital signal according to a positive reference voltage and a negative reference voltage, where the analog input voltage includes a positive terminal input voltage and a For the input voltage of the negative terminal, when the successive approximation register analog-to-digital converter is in operation, it enters the sampling stage and the charge redistribution stage in sequence, and the successive approximation register analog-to-digital converter includes: the most significant bit capacitance group; a most significant bit capacitor group; a comparator; and a controller; wherein, in the sampling phase, the controller: controls the voltage between the upper plate and the lower plate of each capacitor in the most significant bit capacitance group The difference is zero; and the absolute value of the voltage difference between the upper plate and the lower plate of each capacitor in the non-most significant bit capacitance group is controlled between the positive terminal input voltage and the negative terminal input voltage The absolute value of the voltage difference; in the charge redistribution stage, the controller: control the most significant bit capacitance group and the non-most significant bit capacitance group in each capacitor and the analog input voltage disconnect; and controlling the upper plate of each capacitor in the most significant bit capacitor group and the non-most significant bit capacitor group to be coupled to the comparator, so that each capacitor in the non-most significant bit capacitor group is in the Charges accumulated in the sampling phase are redistributed among the capacitors in the most significant bit capacitor group and the non-most significant bit capacitor group by the comparator and output a first comparison result, the first comparison result corresponding to the The most significant bit of a digital signal.

An embodiment of the present application discloses a chip including the above successive approximation register type analog-to-digital converter.

An embodiment of the present application discloses an electronic device including the above-mentioned chip.

The successive approximation register type analog-to-digital converter of the present application adopts the innovative setting of the sampling stage and the charge redistribution stage. In single-ended application, the input common-mode voltage of the comparator does not change with the input signal, so the dynamic offset of the comparator can be avoided. , and improve the linearity of the analog-to-digital converter, and the hardware complexity and power consumption are much smaller than the general solution.

Description of drawings

FIG. 1 is a schematic diagram of a first embodiment of the successive approximation register type analog-to-digital converter of the present application.

FIG. 2 is an equivalent schematic diagram of the successive approximation register type analog-to-digital converter of FIG. 1 in the sampling stage.

FIG. 3 is an equivalent schematic diagram of the successive approximation register analog-to-digital converter of FIG. 1 in a charge redistribution stage and a conversion stage.

FIG. 4 is a schematic diagram of a second embodiment of the successive approximation register type analog-to-digital converter of the present application.

FIG. 5 is an equivalent schematic diagram of the successive approximation register type analog-to-digital converter of FIG. 4 in the sampling stage.

FIG. 6 is an equivalent schematic diagram of the successive approximation register analog-to-digital converter of FIG. 4 in a charge redistribution stage and a conversion stage.

Detailed ways

The following disclosure provides various implementations, or illustrations, that can be used to implement various features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. As can be appreciated, these descriptions are exemplary only, and are not intended to limit the present disclosure. For example, in the description below, forming a first feature on or over a second feature may include some embodiments in which the first and second features are in direct contact with each other; and may also include Certain embodiments may have additional components formed between the first and second features described above, such that the first and second features may not be in direct contact. Furthermore, the present disclosure may reuse reference numerals and/or reference numerals in various embodiments. Such reuse is for brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.

Furthermore, the use of spatially relative terms, such as "below", "below", "below", "above", "above" and the like, may be used to facilitate the description of the drawings. relationship between one component or feature shown with respect to another component or feature. These spatially relative terms are intended to encompass many different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be positioned in other orientations (eg, rotated 90 degrees or at other orientations) and these spatially relative descriptors should be interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broader scope of the application are approximations, the numerical values set forth in the specific examples have been reported as precisely as possible. Any numerical value, however, inherently contains the standard deviation resulting from individual testing methods. As used herein, "about" generally means within plus or minus 10%, 5%, 1%, or 0.5% of the actual value of a particular value or range. Alternatively, the word "about" means that the actual value lies within an acceptable standard error of the mean, as considered by one of ordinary skill in the art to which this application pertains. It should be understood that all ranges, quantities, numerical values and percentages used herein (for example, to describe the amount of material, the length of time, temperature, operating conditions, quantity ratio and other similar) are modified by "about". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the accompanying claims are approximate numerical values and may be changed as required. At a minimum, these numerical parameters should be construed to mean the number of significant digits indicated and the numerical values obtained by applying ordinary rounding. Numerical ranges are expressed herein as from one endpoint to the other or between the endpoints; unless otherwise indicated, the numerical ranges recited herein are inclusive of the endpoints.

In many applications, it is often necessary to configure a differential input ADC to operate as a single-ended input ADC, thus allowing the input common-mode voltage to vary with the input signal. In this way, it is necessary to limit the range of the input signal, so that the input common-mode voltage is controlled within a certain range, so that the result of the analog-to-digital conversion maintains an acceptable linearity, but it limits the flexibility of use. In order to support a wider input common mode range (Common mode rejection ratio, CMRR), in the existing solutions, it is usually necessary to design the comparator as a rail-to-rail input comparator structure with offset voltage calibration, thus increasing the design complexity and waste power consumption and chip area.

In order to solve the above-mentioned series of problems, the present application proposes a successive-approximation-register analog-to-digital converter (SAR ADC), which is used to convert an analog input voltage into a digital signal. The analog input voltage includes a positive terminal input voltage and a negative terminal input voltage. When the SAR ADC is in operation, it will enter three stages in sequence: a sampling stage, a charge redistribution stage, and a conversion stage. In the above-mentioned sampling phase and charge redistribution phase, it is only necessary to simply control the voltage difference between the upper and lower plates of each capacitor of the SAR ADC, so that the comparison in the SAR ADC can be achieved before the above-mentioned conversion phase starts. The input common mode voltage of the device is independent of the positive terminal input voltage and the negative terminal input voltage, and does not change with the change of the positive terminal input voltage and the negative terminal input voltage. Therefore, even if the SAR ADC operates under single-ended input, it will not affect the CMRR, nor will it change the Integral/differential nonlinearities (INL/DNL) characteristics of the output result of the SAR ADC. Difference. And because the application only needs to control the connection between the upper and lower plates of each capacitor in the SAR ADC and each voltage in the three stages, it can be achieved without a complicated and power-consuming circuit.

FIG. 1 is a schematic diagram of a first embodiment of the SAR ADC of the present application. Specifically, the architecture of the SAR ADC 100 of FIG. 1 adopts a common-mode voltage (Vcm-based) mechanism. In addition to the reference voltage Vrn, an additional common mode voltage Vcm is supplied to the SAR ADC 100, where Vcm=(Vrp+Vrn)/2. The SAR ADC 100 is used to convert the analog input voltage into a 3-bit digital signal according to the positive reference voltage Vrp and the negative reference voltage Vrn, that is, the SAR ADC 100 uses the positive reference voltage Vrp and the negative reference voltage Vrn as reference voltages for analog-to-digital conversion. conversion, whose number of bits is 3.

The analog input voltage includes a positive terminal input voltage Vip and a negative terminal input voltage Vin. The SAR ADC 100 includes: a most significant bit (MSB) capacitor group (including the positive terminal capacitor CP1 and the negative terminal capacitor CN1 corresponding to the most significant bit of the digital signal); a non-most significant bit capacitor group (including the positive terminal capacitors CP2, CP3 and Negative terminal capacitors CN2 and CN3, wherein the positive terminal capacitor CP2 and the negative terminal capacitor CN2 correspond to the second most significant bit of the digital signal; the positive terminal capacitor CP3 and the negative terminal capacitor CN3 correspond to the third most significant bit of the digital signal, so The third most significant bit is the least significant bit in this embodiment), in this embodiment, the sum of the capacitance values of the positive terminal capacitors CP1, CP2 and CP3 is Ctot, and the sum of the capacitance values of the positive terminal capacitor CP1 is Ctot /2, the sum of the capacitance values of the positive terminal capacitors CP2 and CP3 is Ctot/2; the sum of the capacitance values of the negative terminal capacitors CN1, CN2 and CN3 is also Ctot, and the sum of the capacitance values of the negative terminal capacitor CN1 is Ctot/2, The sum of the capacitance values of the negative terminal capacitors CN2 and CN3 is Ctot/2; the comparator 102 ; and the controller 104 . In some embodiments, the capacitor array of the SAR ADC 100 has binary weights, each capacitor in the most significant bit capacitor group (positive terminal capacitor CP1, negative terminal capacitor CN1) has a first capacitance value, and the non-most significant bit capacitors have a first capacitance value. Each capacitor in the bit capacitor group (positive terminal capacitors CP2, CP3, negative terminal capacitors CN2, CN3) has a second capacitance value, and the first capacitance value is twice the second capacitance value. In some embodiments, the capacitor array of the SAR ADC 100 has non-binary weights, so the capacitance values of the positive terminal capacitors CP2 and CP3 may be unequal; the capacitance values of the negative terminal capacitors CN2 and CN3 may be unequal.

In the three stages, the controller 104 can change the upper plates of the capacitors in the most significant bit capacitor group and the non-most significant bit capacitor group by switching the switches SP1-SP12 and SN1-SN12 and the voltage of the lower plate, in order to convert the analog input voltage into a digital signal, the connection mode of the switches SP1-SP12, SN1-SN12 can be as shown in FIG. 1, but the specific implementation of the present application is not limited to the implementation in FIG. 1 For example, as long as the same effect can be achieved.

In the sampling phase, each capacitor (including the positive terminal capacitor CP1 and the negative terminal capacitor CN1) in the most significant bit capacitor group in the SAR ADC 100 does not participate in sampling in the sampling phase, but only uses the non- The capacitors in the most significant bit capacitor group (including the positive terminal capacitor CP2 and the negative terminal capacitor CN2 of the next most significant bit capacitor group and the positive terminal capacitor CP3 and the negative terminal capacitor CN3 of the third most significant bit capacitor group) participate in the sampling. It should be noted that if the SAR ADC 100 is to be changed to more than 3 bits, in the sampling stage, the capacitance groups after the third most significant bit capacitance group (such as the fourth most significant bit capacitance group, the fifth most significant bit capacitance group, The control method of the capacitor bank, ... etc.) is the same as that of the non-most significant bit capacitor bank.

Specifically, the controller 104 controls the voltage difference between the upper plate and the lower plate of each capacitor (including the positive terminal capacitor CP1 and the negative terminal capacitor CN1 ) in the most significant bit capacitor group to be zero; and controls The absolute value of the voltage difference between the upper plate and the lower plate of each capacitor (including the positive terminal capacitors CP2, CP3 and the negative terminal capacitors CN2, CN3) in the non-most significant bit capacitor group is the positive terminal input voltage. The absolute value of the voltage difference between Vip and the negative input voltage Vin.

Specifically, the controller 104 can control the switches SP1, SP5, SP6, SP8, SP9, SP10, SP12, SN1, SN5, SN6, SN8, SN9, SN10, SN12 to be non-conductive, and control the switches SP2, SP3, SP4 , SP7, SP11, SN2, SN3, SN4, SN7, SN11 are turned on, so that the SAR ADC 100 is equivalent to form the configuration of Figure 2. The upper and lower plates of the positive capacitor CP1 and the negative capacitor CN1 are both coupled to the common mode voltage Vcm; the upper plates of the positive capacitors CP2 and CP3 are both coupled to the positive input voltage Vip; the positive capacitor The lower plates of CP2 and CP3 are both coupled to the negative input voltage Vin; the upper plates of the negative capacitors CN2 and CN3 are both coupled to the negative input voltage Vin; the lower plates of the negative capacitors CN2 and CN3 are both coupled to to the positive input voltage Vip.

When the sampling phase is completed, the total charge Qp in each capacitor (including the positive terminal capacitors CP2 and CP3) in the positive terminal non-most significant bit capacitor group is:

Qp=(Vip-Vin)*Ctot/2 (1)

The total charge Qn in the capacitors (including the negative terminal capacitors CN2 and CN3) in the negative terminal non-most significant bit capacitor group is: Qn=(Vin-Vip)*Ctot/2 (2)

The advantage of coupling the upper and lower plates of the positive terminal capacitor CP1 and the negative terminal capacitor CN1 to the common mode voltage Vcm is that the positive terminal (+) input voltage of the comparator 102 and the negative terminal during the sampling phase can be Both the terminal (-) input voltages are fixed at the common-mode voltage Vcm, and then at the end of the conversion phase, the positive (+) and negative (-) input voltages of the comparator 102 also approach the common-mode voltage Vcm nearby, thus improving the linearity of the SAR ADC 100. However, the present application is not limited to this, and the realization method of making the voltage difference between the upper plate and the lower plate of the positive terminal capacitor CP1 and the negative terminal capacitor CN1 all zero may not only include the positive terminal capacitor CP1 and the negative terminal capacitor CN1. The upper plate and the lower plate of CN1 are both coupled to the common mode voltage Vcm, for example, the upper and lower plates of the positive terminal capacitor CP1 and the negative terminal capacitor CN1 can also be coupled to the positive terminal input voltage Vip, the negative terminal The terminal input voltage Vin, positive reference voltage Vrp or negative reference voltage Vrn.

In the charge redistribution stage, the controller 104 controls each capacitor in the most significant bit capacitor group and the non-most significant bit capacitor group to be disconnected from the analog input voltage, so that there is no positive terminal input voltage Vip And under the influence of the input voltage Vin at the negative terminal, the charges in the positive terminal capacitors CP1, CP2, and CP3 are redistributed, and the charges in the negative terminal capacitors CN1, CN2, and CN3 are redistributed. Specifically, the total charge Qp in each capacitor (including the positive terminal capacitors CP2 and CP3) in the positive terminal non-most significant bit capacitor group will be redistributed among the positive terminal capacitors CP1, CP2 and CP3. According to the conservation of charge The principle is known:

Qp=(Vcp–Vcm)*Ctot (3)

Wherein Vcp is the positive terminal (+) input voltage of the comparator 102, and formulating equation (3) can be obtained:

Vcp=Qp/Ctot+Vcm (4) According to equation (1) and equation (4), it can be obtained that the positive terminal (+) input voltage Vcp of the comparator 102 after the charge redistribution is completed is:

Vcp=Vcm+(Vip-Vin)/2 (5)

Similarly, the total charge Qn in each capacitor (including the negative terminal capacitors CN2, CN3) in the negative terminal non-most significant bit capacitor group will be redistributed among the negative terminal capacitors CN1, CN2, CN3, according to the principle of charge conservation It is known that:

Qn=(Vcn–Vcm)*Ctot (6)

Where Vcn is the input voltage of the negative terminal (-) of the comparator 102, and after arranging equation (6), we can obtain:

Vcn=Qn/Ctot+Vcm (7) According to equation (2) and equation (7), it can be obtained that the negative terminal (-) input voltage Vcn of the comparator 102 after the charge redistribution is completed is:

Vcn=Vcm+(Vin-Vip)/2 (8)

It should be noted that if the SAR ADC 100 is to be changed to more than 3 bits, in the charge redistribution stage, the capacitance groups after the third most significant bit capacitance group (such as the fourth most significant bit capacitance group, the fifth most significant bit capacitance group, The control method of the effective bit capacitance group, ... etc.) is the same as the control method of the most significant bit capacitance group and the non-most significant bit capacitance group.

In detail, the controller 104 controls the upper plates of the capacitors in the most significant bit capacitor group and the non-most significant bit capacitor group to be coupled to the comparator 102, so that the capacitors in the non-most significant bit capacitor group are connected to the comparator 102. The charge accumulated by the capacitors during the sampling phase is redistributed among the capacitors in the most significant bit capacitor bank and the non-most significant bit capacitor bank. And after the redistribution is completed, the voltage of the positive input terminal (+) of the comparator 102 is Vcm+(Vip-Vin)/2; the voltage of the negative input terminal (-) of the comparator 102 is Vcm-(Vip-Vin)/2 . That is to say, in the next conversion stage, the input common-mode voltage of the comparator 102 is fixed at Vcm, and is not affected by the positive terminal input voltage Vip and the negative terminal input voltage Vin. Theoretically, the input differential signal Vip-Vin can range from Vrn-Vrp to Vrp-Vrn, within which the SAR ADC 100 will not saturate, so rail-to-rail characteristics can be achieved without additional mechanisms to dynamically Calibrate the offset voltage.

Specifically, the controller 104 can control the switches SP2, SP3, SP5, SP6, SP7, SP9, SP10, SP11, SN2, SN3, SN5, SN6, SN7, SN9, SN10, and SN11 to be non-conductive, and control the switch SP1 , SP4, SP8, SP12, SN1, SN4, SN8, SN12 are turned on, so that the SAR ADC 100 equivalently forms the configuration of (a) in Figure 3. The lower plates of the positive end capacitors CP1, CP2, CP3 and the negative end capacitors CN1, CN2, CN3 are all coupled to the common mode voltage Vcm; the upper plates of the positive end capacitors CP1, CP2, CP3 are all coupled to the comparator 102 The positive input terminal (+) of the negative terminal capacitors CN1 , CN2 and CN3 are all coupled to the negative input terminal (-) of the comparator 102 .

After the charge redistribution phase is completed, the comparator 102 generates corresponding voltages for the positive input terminal (+) voltage Vcm+(Vip-Vin)/2 and the negative input terminal (-) voltage Vcm-(Vip-Vin)/2 To output Vout, the SAR ADC 100 will first take this output as the first comparison result of the SAR ADC 100 in the next conversion stage to represent the most significant bit of the digital signal converted by the SAR ADC 100. The controller 104 selectively changes the voltages of the lower plates of at least part of the capacitors in the most significant bit capacitor group and the non-most significant bit capacitor group according to the sign of the value of the first comparison result, so that the comparison The controller 102 correspondingly generates a second comparison result, and the second comparison result corresponds to the second most significant bit of the digital signal; and so on, the controller 104 selects the second comparison result according to the sign of the value of the second comparison result. The voltage of the lower plate of at least part of the capacitors in the most significant bit capacitor group and the non-most significant bit capacitor group is changed in a grounded manner, so that the comparator 102 correspondingly generates a third comparison result, and the third comparison result corresponds to the The third most significant bit of the digital signal.

Specifically, when the first comparison result is greater than zero, the controller 104 controls the bottom plate of the positive terminal capacitor CP1 in the most significant bit capacitor group to be coupled to the negative reference instead of being coupled to the common mode voltage Vcm voltage Vrn, and control the bottom plate of the negative terminal capacitor CN1 in the most significant bit capacitor group from being coupled to the common-mode voltage Vcm to be coupled to the positive reference voltage Vrp, and the remaining part of the SAR ADC 100 The coupling mode remains The same as the charge redistribution stage to produce the second comparison result. Specifically, the controller 104 can control the switches SP2, SP3, SP4, SP5, SP7, SP9, SP10, SP11, SN2, SN3, SN4, SN6, SN7, SN9, SN10, and SN11 to be non-conductive, and control the switch SP1 , SP6, SP8, SP12, SN1, SN5, SN8, SN12 are turned on, so that the SAR ADC 100 equivalently forms the configuration in (b) of FIG. 3 .

On the contrary, when the first comparison result is less than zero, the controller 104 controls the lower plate of the positive terminal capacitor CP1 in the most significant bit capacitor group to be coupled to the positive reference voltage Vrp instead of being coupled to the common mode voltage Vcm , and control the lower plate of the negative terminal capacitor CN1 in the most significant bit capacitor group from being coupled to the common mode voltage Vcm to be coupled to the negative reference voltage Vrn, and the remaining part of the SAR ADC 100 The coupling mode remains the same The charge redistribution stage is the same to produce the second comparison result. Specifically, the controller 104 can control the switches SP2, SP3, SP4, SP6, SP7, SP9, SP10, SP11, SN2, SN3, SN4, SN5, SN7, SN9, SN10, SN11 to be non-conductive, and control the switch SP1 , SP5, SP8, SP12, SN1, SN6, SN8, SN12 are turned on, so that the SAR ADC 100 is equivalent to form the configuration of (c) in Figure 3.

When the first comparison result is greater than zero and the second comparison result is greater than zero, the controller 104 controls the lower plate of the positive terminal capacitor CP2 in the non-MSB capacitor group to change from being coupled to the common mode voltage Vcm In order to be coupled to the negative reference voltage Vrn, and to control the lower plate of the negative terminal capacitor CN2 in the non-most significant bit capacitor group from being coupled to the common mode voltage Vcm to be coupled to the positive reference voltage Vrp, so as to generate the The third comparison result is described. Specifically, the controller 104 can control the switches SP2, SP3, SP4, SP5, SP7, SP8, SP9, SP11, SN2, SN3, SN4, SN6, SN7, SN8, SN10, and SN11 to be non-conductive, and control the switch SP1 , SP6, SP10, SP12, SN1, SN5, SN9, SN12 are turned on, so that the SAR ADC 100 equivalently forms the configuration in (d) of FIG. 3 .

When the first comparison result is greater than zero and the second comparison result is less than zero, the controller 104 controls the lower plate of the positive terminal capacitor CP2 in the non-MSB capacitor group to change from being coupled to the common mode voltage Vcm In order to be coupled to the positive reference voltage Vrp, and control the lower plate of the negative terminal capacitor CN2 in the non-most significant bit capacitor group from being coupled to the common mode voltage Vcm to be coupled to the negative reference voltage Vrn, so as to generate the The third comparison result is described. Specifically, the controller 104 can control the switches SP2, SP3, SP4, SP5, SP7, SP8, SP10, SP11, SN2, SN3, SN4, SN6, SN7, SN8, SN9, and SN11 to be non-conductive, and control the switch SP1 , SP6, SP9, SP12, SN1, SN5, SN10, SN12 are turned on, so that the SAR ADC 100 is equivalent to form the configuration of (e) in Figure 3.

When the first comparison result is less than zero and the second comparison result is greater than zero, the controller 104 controls the lower plate of the positive terminal capacitor CP2 in the non-MSB capacitor group to change from being coupled to the common mode voltage Vcm In order to be coupled to the negative reference voltage Vrn, and to control the lower plate of the negative terminal capacitor CN2 in the non-most significant bit capacitor group from being coupled to the common mode voltage Vcm to be coupled to the positive reference voltage Vrp, so as to generate the The third comparison result is described. Specifically, the controller 104 can control the switches SP2, SP3, SP4, SP6, SP7, SP8, SP9, SP11, SN2, SN3, SN4, SN5, SN7, SN8, SN10, and SN11 to be non-conductive, and control the switch SP1 , SP5, SP10, SP12, SN1, SN6, SN9, SN12 are turned on, so that the SAR ADC 100 is equivalent to form the configuration of (f) in Figure 3.

When the first comparison result is less than zero and the second comparison result is less than zero, the controller 104 controls the lower plate of the positive terminal capacitor CP2 in the non-MSB capacitor group to change from being coupled to the common mode voltage Vcm In order to be coupled to the positive reference voltage Vrp, and control the lower plate of the negative terminal capacitor CN2 in the non-most significant bit capacitor group from being coupled to the common mode voltage Vcm to be coupled to the negative reference voltage Vrn, so as to generate the The third comparison result is described. Specifically, the controller 104 can control the switches SP2, SP3, SP4, SP6, SP7, SP8, SP10, SP11, SN2, SN3, SN4, SN5, SN7, SN8, SN9, and SN11 to be non-conductive, and control the switch SP1 , SP5, SP9, SP12, SN1, SN6, SN10, and SN12 are turned on, so that the SAR ADC 100 is equivalent to the configuration shown in (g) in Figure 3.

Figures 3(b) to 3(g) can be analogically applied to the configuration of the conversion stage when the SAR ADC 100 exceeds 3 bits.

In some embodiments, the SAR ADC 100 can be changed to more than 3 bits by extending the capacitor array, as long as the sum of the capacitance values of the capacitors in the most significant capacitor bank and the capacitance values of the capacitors in the non-most significant capacitor banks are met The sum is equal. For example, for an N-bit SAR ADC, where N can be greater than 3, it is assumed that the sum of the capacitance values of the capacitors in the most significant bit capacitor group and the non-most significant bit capacitor group in the N-bit SAR ADC is 2 ^N-1 unit capacitors. value, the sum of the capacitance values of the capacitors in the most significant bit capacitor group is the capacitance value of 2 ^N-2 unit capacitors, which is one-half of the total capacitance value, that is to say, each capacitor in the non-most significant bit capacitor group The sum of the capacitance values of the capacitors is also the capacitance value of 2 ^N-2 unit capacitors. The above only expresses the proportional relationship, and the capacitance value of the unit capacitor of the present application can be adjusted according to requirements.

In some embodiments, the SAR ADC 100 can be changed to 1 bit. Specifically, in the case of 1 bit, only the positive terminal capacitor CP1 and the positive terminal capacitor CP2 and the negative terminal capacitor CN1 and the negative terminal of the SAR ADC 100 need to be reserved. capacitor CN2, and the positive terminal capacitor CP1, the positive terminal capacitor CP2, the negative terminal capacitor CN1 and the negative terminal capacitor CN2 all have the same capacitance value. Herein, for the convenience of description, the positive terminal capacitor CP1 and the negative terminal capacitor CN1 are classified as the most significant bit capacitor group; and the positive terminal capacitor CP2 and the negative terminal capacitor CN2 are classified as the non-most significant bit capacitor group.

Same as SAR ADC 100, in the sampling stage of 1-bit SAR ADC, positive terminal capacitor CP1 and negative terminal capacitor CN1 do not participate in sampling, but only use positive terminal capacitor CP2 and negative terminal capacitor CN2 to participate in sampling. The upper and lower plates of the positive-end capacitor CP1 and the negative-end capacitor CN1 are both coupled to the common mode voltage Vcm; the upper plate of the positive-end capacitor CP2 is coupled to the positive-end input voltage Vip; the lower plate of the positive-end capacitor CP2 The plate is coupled to the negative input voltage Vin; the upper plate of the negative capacitor CN2 is coupled to the negative input voltage Vin; the lower plate of the negative capacitor CN2 is coupled to the positive input voltage Vip.

Same as the SAR ADC 100, in the charge redistribution stage of the 1-bit SAR ADC, each capacitor in the most significant bit capacitor group and the non-most significant bit capacitor group is disconnected from the analog input voltage to Without the influence of the positive terminal input voltage Vip and the negative terminal input voltage Vin, the charges in the positive terminal capacitors CP1 and CP2 are redistributed, and the charges in the negative terminal capacitors CN1 and CN2 are redistributed. The result is the same as equation (5 ) is the same as equation (8).

After the charge redistribution phase is completed, the comparator 102 generates a first for the positive input (+) voltage Vcm+(Vip-Vin)/2 and the negative input (-) voltage Vcm-(Vip-Vin)/2 The comparison result can be used as the output of the 1-bit SAR ADC. That is, unlike SAR ADC 100, a 1-bit SAR ADC does not require the conversion stage.

In some embodiments, the SAR ADC 100 can also be changed to 2 bits. Specifically, the capacitor array configuration of the 2-bit SAR ADC is the same as that of the 1-bit SAR ADC, and the sampling phase and the charge redistribution phase are the same. Also the same as 1-bit, the only difference is that the 2-bit SAR ADC needs to perform an additional conversion stage to generate the second comparison result. In short, the 2-bit SAR ADC generates the second comparison result in the same way as the SAR ADC. 100 produces the second comparison result in the same way. That is, when the first comparison result is greater than zero, the bottom plate of the positive terminal capacitor CP1 in the most significant bit capacitor group is changed from being coupled to the common mode voltage Vcm to the negative reference voltage Vrn, and controls the The bottom plate of the negative terminal capacitor CN1 in the most significant bit capacitor group is changed from being coupled to the common mode voltage Vcm to the positive reference voltage Vrp, and the positive terminal capacitor CP2 and the negative terminal capacitor CN2 in the non-most significant bit capacitor group are The coupling of , remains the same as in the charge redistribution stage to produce the second comparison result.

For the switch configuration of the 1-bit and 2-bit SAR ADCs, the switch configuration in FIG. 1 can be modified correspondingly through the above description, as long as the above-mentioned operating principles can be realized.

4 is a schematic diagram of a second embodiment of the SAR ADC of the present application. Specifically, the architecture of the SAR ADC 400 of FIG. 4 adopts a set-and-down mechanism, and only the positive reference voltage Vrp and the negative reference voltage Vrn are supplied to the SAR ADC 400. The SAR ADC 400 is used to convert the analog input voltage into a 3-bit digital signal, but the application is not limited to this. According to the following description of the application, the SAR ADC 400 can be changed to be more than or less than 3 bits by expanding the capacitor array, The rules for expanding the capacitor array can be referred to the above description of the SAR ADC 100. The analog input voltage includes a positive terminal input voltage Vip and a negative terminal input voltage Vin. The SAR ADC 400 includes: a most significant bit (MSB) capacitor group (including positive terminal capacitors CP1, CP2 and negative terminal capacitors CN1, CN2 corresponding to the most significant bits of the digital signal); a non-most significant bit capacitor group (including positive terminal capacitors) CP3, CP4, CP5, CP6 and negative terminal capacitors CN3, CN4, CN5, CN6, wherein positive terminal capacitors CP3, CP4 and negative terminal capacitors CN3, CN4 correspond to the second most significant bits of the digital signal; positive terminal capacitors CP5, CP6 and the negative terminal capacitors CN5, CN6 correspond to the third most significant bit of the digital signal, the third most significant bit is the least significant bit in this embodiment), in this embodiment, the positive terminal capacitors CP1, CP2, The sum of the capacitance values of CP3, CP4, CP5 and CP6 is Ctot, the sum of the capacitance values of the positive terminal capacitors CP1 and CP2 is Ctot/2, and the sum of the capacitance values of the positive terminal capacitors CP3, CP4, CP5 and CP6 is Ctot/2 ; The sum of the capacitance values of the negative terminal capacitors CN1, CN2, CN3, CN4, CN5 and CN6 is also Ctot, the sum of the capacitance values of the negative terminal capacitors CN1 and CN2 is Ctot/2, and the negative terminal capacitors CN3, CN4, CN5, CN6 The sum of the capacitance values is Ctot/2; comparator 402; and controller 404. In some embodiments, the capacitor array of the SAR ADC 400 has binary weights, so each capacitor (positive terminal capacitors CP1, CP2, negative terminal capacitors CN1, CN2) in the most significant bit capacitor group has a first capacitance value, so Each capacitor in the non-most significant bit capacitor group (positive terminal capacitors CP3, CP4, CP5, CP6 and negative terminal capacitors CN3, CN4, CN5, CN6) has a second capacitance value, and the first capacitance value is the first capacitance value. Two times the capacitance value. In some embodiments, the capacitor array of the SAR ADC 400 has non-binary weights, so the capacitance values of the positive terminal capacitors CP3, CP4, CP5, and CP6 may be unequal; the capacitance values of the negative terminal capacitors CN3, CN4, CN5, and CN6 may be unequal. .

In the three stages, the controller 404 can change the upper plate of each capacitor in the most significant bit capacitor group and the non-most significant bit capacitor group by switching the switches SP1-SP19 and SN1-SN19 and the voltage of the lower plate, in order to convert the analog input voltage into a digital signal, the connection mode of the switches SP1-SP19 and SN1-SN19 can be as shown in FIG. 4, but the specific implementation of the present application is not limited to the implementation in FIG. 4 For example, as long as the same effect can be achieved.

In the sampling phase, each capacitor in the most significant bit capacitor group in the SAR ADC 400 (including the positive terminal capacitor CP1, CP2 negative terminal capacitor CN1, CN2) does not participate in sampling in the sampling phase, but only uses Each capacitor in the non-most significant bit capacitor group (including the positive terminal capacitors CP3, CP4 and the negative terminal capacitors CN3, CN4 of the next most significant bit capacitor group and the positive terminal capacitors CP5, CP6 and the third most significant bit capacitor group) Negative terminal capacitors CN5, CN6) participate in sampling. It should be noted that if the SAR ADC 400 is to be changed to more than 3 bits, in the sampling stage, the capacitance groups after the third most significant bit capacitance group (such as the fourth most significant bit capacitance group, the fifth most significant bit capacitance group, The control method of the capacitor bank, ... etc.) is the same as that of the non-most significant bit capacitor bank.

In detail, the controller 404 controls the voltage difference between the upper plate and the lower plate of each capacitor in the most significant bit capacitor group (including the positive terminal capacitors CP1, the negative terminal capacitors CN1 and CN2 of CP2) to be zero. ; And control between the upper plate and the lower plate of each capacitance (including positive terminal capacitors CP3, CP4, CP5, CP6 and negative terminal capacitors CN3, CN4, CN5, CN6) in the non-most significant bit capacitor group The absolute value of the voltage difference is the absolute value of the voltage difference between the positive terminal input voltage Vip and the negative terminal input voltage Vin.

Specifically, the controller 404 can control the switches SP1, SP2, SP8, SP9, SP12, SP13, SP14, SP15, SP18, SP19, SN1, SN2, SN8, SN9, SN12, SN13, SN14, SN15, SN18, SN19 Non-conducting, and control switches SP3, SP4, SP5, SP6, SP7, SP10, SP11, SP16, SP17, SN3, SN4, SN5, SN6, SN7, SN10, SN11, SN16, SN17 to conduct, so that the SAR ADC 400 Equivalently form the configuration of FIG. 5 . The upper and lower plates of the positive-end capacitor CP1 and the negative-end capacitor CN1 are both coupled to the positive reference voltage Vrp; the upper and lower plates of the positive-end capacitor CP2 and the negative-end capacitor CN2 are both coupled to the negative reference The voltage Vrn; the upper plates of the positive capacitors CP3, CP4, CP5, and CP6 are all coupled to the positive input voltage Vip; the lower plates of the positive capacitors CP3, CP4, CP5, and CP6 are all coupled to the negative input voltage Vin ; The upper plates of the negative end capacitors CN3, CN4, CN5, CN6 are all coupled to the negative end input voltage Vin; the lower plates of the negative end capacitors CN3, CN4, CN5, CN6 are all coupled to the positive end input voltage Vip.

When the sampling phase is completed, the total charge Qp in each capacitor (including the positive terminal capacitors CP3, CP4, CP5, and CP6) in the positive terminal non-most significant bit capacitor group in FIG. 5 is:

Qp=(Vip-Vin)*Ctot/2 (9)

The total charge Qn in each capacitor (including the negative terminal capacitors CN3, CN4, CN5, CN6) in the negative terminal non-most significant bit capacitor group of FIG. 5 is:

Qn=(Vin-Vip)*Ctot/2 (10)

The upper and lower plates of the positive terminal capacitor CP1 and the negative terminal capacitor CN1 are both coupled to the positive reference voltage Vrp, and the upper and lower plates of the positive terminal capacitor CP2 and the negative terminal capacitor CN2 are both coupled to The advantage of the negative reference voltage Vrn is that such a configuration can be continued to the charge redistribution stage, that is, when entering the charge redistribution stage from the sampling stage, there is no need to additionally change the positive terminal capacitor CP1, the positive terminal The voltage of the lower plate configuration of the capacitor CP2, the negative terminal capacitor CN1 and the negative terminal capacitor CN2. However, this application is not limited to this, and the realization method that the voltage difference between the upper plate and the lower plate of the positive terminal capacitors CP1 and CP2 and the negative terminal capacitors CN1 and CN2 is zero can not only be shown in FIG. 5 , For example, the upper plate and the lower plate of the positive terminal capacitor CP1 and the negative terminal capacitor CN1 can be both coupled to the positive terminal input voltage Vip, the negative terminal input voltage Vin or the negative reference voltage Vrn, or the positive terminal capacitor CP2 and the negative terminal can be connected. The upper plate and the lower plate of the terminal capacitor CN2 are both coupled to the positive terminal input voltage Vip, the negative terminal input voltage Vin or the positive reference voltage Vrp.

In the charge redistribution stage, the controller 404 controls each capacitor in the most significant bit capacitor group and the non-most significant bit capacitor group to be disconnected from the analog input voltage, so that there is no positive terminal input voltage Vip Under the influence of the input voltage Vin at the negative end, the charges in the positive end capacitors CP1, CP2, CP3, CP4, CP5, and CP6 are redistributed, and the charges in the negative end capacitors CN1, CN2, CN3, CN4, CN5, and CN6 are redistributed. reassign.

Specifically, the total charge Qp in each capacitor (including the positive-side capacitors CP3, CP4, CP5, and CP6) in the positive-side non-most significant bit capacitor group in (a) of FIG. 6 will be in the positive-side capacitors CP1, CP1, According to the principle of charge conservation, we can know that:

Qp=(Vcp–Vrp)*Ctot/2+(Vcp–Vrn)*Ctot/2=Vcp*Ctot–Vrp*Ctot/2–Vrn*Ctot/2 (11)

Where Vcp is the positive terminal (+) input voltage of the comparator 402, and after arranging equation (11), we can obtain:

Vcp=Qp/Ctot+(Vrp+Vrn)/2=Vcm+Qp/Ctot (12) According to equation (9) and equation (12), the positive (+) input of the comparator 102 can be obtained after the charge redistribution is completed The voltage Vcp is:

Vcp=Vcm+(Vip-Vin)/2 (13)

Wherein Vcm=(Vrp+Vrn)/2, similarly, the sum of charges Qn in each capacitor (including the negative-end capacitors CN3, CN4, CN5, CN6) in the non-most significant bit capacitor group at the negative end will be at the negative end The capacitors CN1, CN2, CN3, CN4, CN5, CN6 are redistributed according to the principle of charge conservation:

Qn=(Vcn–Vrp)*Ctot/2+(Vcn–Vrn)*Ctot/2=Vcn*Ctot–Vrn*Ctot/2–Vrp*Ctot/2 (14)

where Vcn is the input voltage of the negative terminal (-) of the comparator 102, and after arranging equation (14), we can obtain:

Vcn=Qn/Ctot+(Vrp+Vrn)/2=Vcm+Qn/Ctot (15) According to equation (10) and equation (15), the negative terminal (-) input of the comparator 102 can be obtained after the charge redistribution is completed The voltage Vcn is:

Vcp=Vcm+(Vin-Vip)/2 (16)

It should be noted that if the SAR ADC 400 is to be changed to more than 3 bits, in the charge redistribution stage, the capacitance groups after the third most significant bit capacitance group (such as the fourth most significant bit capacitance group, the fifth most significant bit capacitance group, The control method of the effective bit capacitance group, ... etc.) is the same as the control method of the most significant bit capacitance group and the non-most significant bit capacitance group.

In detail, the controller 404 controls the upper plates of the capacitors in the most significant bit capacitor group and the non-most significant bit capacitor group to be coupled to the comparator 402, so that the capacitors in the non-most significant bit capacitor group are connected to the comparator 402. The charge accumulated by the capacitors during the sampling phase is redistributed among the capacitors in the most significant bit capacitor bank and the non-most significant bit capacitor bank. And after the redistribution is completed, the voltage of the positive input terminal (+) of the comparator 402 is (Vrp+Vrn)/2+(Vip-Vin)/2; the voltage of the negative input terminal (-) of the comparator 402 is (Vrp +Vrn)/2-(Vip-Vin)/2. That is to say, the input common mode voltage of the comparator 402 is fixed at (Vrp+Vrn)/2, and is not affected by the positive terminal input voltage Vip and the negative terminal input voltage Vin.

Specifically, the controller 404 can control switches SP3, SP4, SP5, SP8, SP9, SP10, SP11, SP14, SP15, SP16, SP17, SN3, SN4, SN5, SN8, SN9, SN10, SN11, SN14, SN15 , SN16, SN17 are not turned on, and control the switches SP1, SP2, SP6, SP7, SP12, SP13, SP18, SP19, SN1, SN2, SN6, SN7, SN12, SN13, SN18, SN19 to turn on, so that the SAR ADC400, etc. This results in the configuration shown in (a) of FIG. 6 . The lower plates of the positive end capacitors CP1, CP3, CP5 and the negative end capacitors CN1, CN3, CN5 are all coupled to the positive reference voltage Vrp; the lower plates of the positive end capacitors CP2, CP4, CP6 and the negative end capacitors CN2, CN4, CN6 The plates are all coupled to the negative reference voltage Vrn; the upper plates of the positive capacitors CP1, CP2, CP3, CP4, CP5, and CP6 are all coupled to the positive input (+) of the comparator 402; the negative capacitors CN1, CN2 The upper plates of , CN3 , CN4 , CN5 , and CN6 are all coupled to the negative input terminal (-) of the comparator 402 .

After the charge redistribution phase is complete, the comparator 402 responds to the positive input (+) voltage (Vrp+Vrn)/2+(Vip-Vin)/2 and the negative input (-) voltage (Vrp+Vrn)/2 2-(Vip-Vin)/2 will generate the corresponding output Vout, and the SAR ADC 400 will first use this output as the first comparison result of the SAR ADC 400 in the next conversion stage to represent the output converted by the SAR ADC 400. the most significant bit of the digital signal. The controller 404 selectively changes the voltages of the lower plates of at least part of the capacitors in the most significant bit capacitor group and the non-most significant bit capacitor group according to the sign of the value of the first comparison result, so that the comparison The controller 402 correspondingly generates a second comparison result, and the second comparison result corresponds to the second most significant bit of the digital signal; and so on, the controller 404 selects the second comparison result according to the sign of the value of the second comparison result. The voltages of the lower plates of at least part of the capacitors in the most significant bit capacitor group and the non-most significant bit capacitor group are changed to make the comparator 402 correspondingly generate a third comparison result, and the third comparison result corresponds to the The third most significant bit of the digital signal.

In detail, when the first comparison result is greater than zero, the controller 404 controls the bottom plate of the positive terminal capacitor CP1 in the most significant bit capacitor group to be coupled to the negative reference voltage Vrp instead of being coupled to the positive reference voltage Vrp voltage Vrn, and control the bottom plate of the negative terminal capacitor CN2 in the most significant bit capacitor group from being coupled to the negative reference voltage Vrn to be coupled to the positive reference voltage Vrp, and the remaining part of the SAR ADC 400 The coupling mode remains The same as the charge redistribution stage to produce the second comparison result. Specifically, the controller 404 can control switches SP3, SP4, SP5, SP6, SP9, SP10, SP11, SP14, SP15, SP16, SP17 and SN3, SN4, SN5, SN7, SN8, SN10, SN11, SN14, SN15 , SN16, SN17 are not turned on, and control switches SP1, SP2, SP7, SP8, SP12, SP13, SP18, SP19 and SN1, SN2, SN6, SN9, SN12, SN13, SP18, SP19 are turned on, so that the SAR ADC 400 Equivalently, the configuration in (b) of FIG. 6 is formed.

On the contrary, when the first comparison result is less than zero, the controller 404 controls the lower plate of the positive terminal capacitor CP2 in the most significant bit capacitor group to be coupled to the positive reference voltage Vrp instead of being coupled to the negative reference voltage Vrn , and control the lower plate of the negative terminal capacitor CN1 in the most significant bit capacitor group from being coupled to the positive reference voltage Vrp to be coupled to the negative reference voltage Vrn, and the remaining part of the SAR ADC 400 The coupling mode remains the same as all The charge redistribution stage is the same to produce the second comparison result. Specifically, the controller 404 can control the switches SP3, SP4, SP5, SP7, SP8, SP10, SP11, SP14, SP15, SP16, SP17 and SN3, SN4, SN5, SN6, SN9, SN10, SN11, SN14, SN15 , SN16, SN17 are not turned on, and control switches SP1, SP2, SP6, SP9, SP12, SP13, SP18, SP19 and SN1, SN2, SN7, SN8, SN12, SN13, SP18, SP19 are turned on, so that the SAR ADC 400 Equivalently, the configuration in (c) of FIG. 6 is formed.

When the first comparison result is greater than zero and the second comparison result is greater than zero, the controller 404 controls the lower plate of the positive terminal capacitor CP3 in the non-MSB capacitor group to change from being coupled to the positive reference voltage Vrp In order to be coupled to the negative reference voltage Vrn, and control the lower plate of the negative terminal capacitor CN4 in the non-MSB capacitor group from being coupled to the negative reference voltage Vrn to being coupled to the positive reference voltage Vrp, so as to generate the The third comparison result is described. Specifically, the controller 404 can control switches SP3, SP4, SP5, SP6, SP9, SP10, SP11, SP12, SP15, SP16, SP17 and SN3, SN4, SN5, SN7, SN8, SN10, SN11, SN13, SN14 , SN16, SN17 are not turned on, and control the switches SP1, SP2, SP7, SP8, SP13, SP14, SP18, SP19 and SN1, SN2, SN6, SN9, SN12, SN15, SP18, SP19 to turn on, so that the SAR ADC 400 Equivalently, the configuration in (d) of FIG. 6 is formed.

When the first comparison result is greater than zero and the second comparison result is less than zero, the controller 404 controls the lower plate of the positive terminal capacitor CP4 in the non-MSB capacitor group to change from being coupled to the negative reference voltage Vrn In order to be coupled to the positive reference voltage Vrp, and control the lower plate of the negative terminal capacitor CN3 in the non-MSB capacitor group to be coupled to the negative reference voltage Vrn from being coupled to the positive reference voltage Vrp, so as to generate the The third comparison result is described. Specifically, the controller 404 can control switches SP3, SP4, SP5, SP6, SP9, SP10, SP11, SP13, SP14, SP16, SP17 and SN3, SN4, SN5, SN7, SN8, SN10, SN11, SN12, SN15 , SN16, SN17 are not turned on, and control switches SP1, SP2, SP7, SP8, SP12, SP15, SP18, SP19 and SN1, SN2, SN6, SN9, SN13, SN14, SP18, SP19 to make the SAR ADC 400 equivalent The configuration of (e) in FIG. 6 is formed.

When the first comparison result is less than zero and the second comparison result is greater than zero, the controller 404 controls the lower plate of the positive terminal capacitor CP3 in the non-MSB capacitor group to change from being coupled to the positive reference voltage Vrp In order to be coupled to the negative reference voltage Vrn, and control the lower plate of the negative terminal capacitor CN4 in the non-MSB capacitor group from being coupled to the negative reference voltage Vrn to being coupled to the positive reference voltage Vrp, so as to generate the The third comparison result is described. Specifically, the controller 404 can control switches SP3, SP4, SP5, SP7, SP8, SP10, SP11, SP12, SP15, SP16, SP17 and SN3, SN4, SN5, SN6, SN9, SN10, SN11, SN13, SN14 , SN16, SN17 are not turned on, and control switches SP1, SP2, SP6, SP9, SP13, SP14, SP18, SP19 and SN1, SN2, SN7, SN8, SN12, SN15, SP18, SP19 are turned on, so that the SAR ADC 400 Equivalently form the configuration in (f) of FIG. 6 .

When the first comparison result is less than zero and the second comparison result is less than zero, the controller 404 controls the lower plate of the positive terminal capacitor CP4 in the non-MSB capacitor group to change from being coupled to the negative reference voltage Vrn In order to be coupled to the positive reference voltage Vrp, and control the lower plate of the negative terminal capacitor CN3 in the non-MSB capacitor group to be coupled to the negative reference voltage Vrn from being coupled to the positive reference voltage Vrp, so as to generate the The third comparison result is described. Specifically, the controller 404 can control switches SP3, SP4, SP5, SP7, SP8, SP10, SP11, SP13, SP14, SP16, SP17 and SN3, SN4, SN5, SN6, SN9, SN10, SN11, SN12, SN15 , SN16, SN17 are not turned on, and control the switches SP1, SP2, SP6, SP9, SP12, SP15, SP18, SP19 and SN1, SN2, SN7, SN8, SN13, SN14, SP18, SP19 to turn on, so that the SAR ADC 400 Equivalently, the configuration of (g) in FIG. 6 is formed.

Fig. 6(b) to Fig. 6(g) can be analogically applied to the configuration of the conversion stage when the SAR ADC 400 exceeds 3 bits.

The application also provides a chip including the SAR ADC 100/400. The present application also provides an electronic device comprising the SAR ADC 100/400 or the chip.

The foregoing description briefly sets forth features of certain embodiments of the application, so that those skilled in the art to which this application pertains can more fully understand the various aspects of the present disclosure. It should be apparent to those skilled in the art to which this application pertains that they can readily use the present disclosure as a basis to design or modify other processes and structures for carrying out the same purposes and/or of the embodiments described herein achieve the same advantages. Those with ordinary knowledge in the technical field to which this application belongs should understand that these equivalent embodiments still belong to the spirit and scope of the present disclosure, and various changes, substitutions and alterations can be made without departing from the spirit of the present disclosure. with scope.

Claims

A successive approximation register type analog-to-digital converter is used to convert an analog input voltage into a digital signal according to a positive reference voltage and a negative reference voltage, the analog input voltage includes a positive terminal input voltage and a negative terminal input voltage, and is characterized in that , when the successive approximation register analog-to-digital converter is in operation, it enters the sampling stage and the charge redistribution stage in sequence, and the successive approximation register analog-to-digital converter includes:

Most significant bit capacitor bank;

Non-most significant bit capacitor bank;

a comparator; and

controller;

in,

During the sampling phase, the controller:

controlling the voltage difference between the upper plate and the lower plate of each capacitor in the most significant bit capacitor bank to zero; and

Controlling the absolute value of the voltage difference between the upper plate and the lower plate of each capacitor in the non-most significant bit capacitor group is the absolute value of the voltage difference between the positive terminal input voltage and the negative terminal input voltage value;

During the charge redistribution phase, the controller:

controlling each capacitor in the most significant bit capacitor bank and the non-most significant bit capacitor bank to disconnect from the analog input voltage; and

controlling the upper plate of each capacitor in the most significant bit capacitor group and the non-most significant bit capacitor group to be coupled to the comparator, so that each capacitor in the non-most significant bit capacitor group is in the sampling The charge accumulated in the stage is redistributed among the capacitors in the most significant bit capacitor group and the non-most significant bit capacitor group, the comparator outputs a first comparison result, and the first comparison result corresponds to the digital The most significant bit of the signal.
The successive approximation register analog-to-digital converter of claim 1, wherein, in the charge redistribution stage, the controller makes each capacitor in the non-most significant bit capacitor group in the sampling stage The accumulated charge is redistributed among the capacitors in the most significant bit capacitor bank and the non-most significant bit capacitor bank, so that the voltage at the positive input terminal of the comparator is the common mode voltage + (the positive terminal input voltage-the negative input voltage)/2, and the voltage at the negative input of the comparator is the common-mode voltage-(the positive input voltage-the negative input voltage)/2, where all The common mode voltage is (the positive reference voltage+the negative reference voltage)/2.
The successive approximation register-type analog-to-digital converter of claim 1, wherein when the successive approximation register-type analog-to-digital converter is in operation, it also enters a conversion phase, and in the conversion phase, the controller According to the first comparison result, the voltage of the lower plate of at least part of the capacitors in the most significant bit capacitor group and the non-most significant bit capacitor group is selectively changed, so that the comparator generates a second voltage correspondingly. A comparison result, the second comparison result corresponds to the second most significant bit of the digital signal.
The successive approximation register type analog-to-digital converter according to claim 3, wherein the total capacitance value of the most significant bit capacitance group and the total capacitance value of the non-most significant bit capacitance group are equal, and the most significant bit capacitance group is equal. The bit capacitance group includes a first positive end capacitance and a first negative end capacitance, and the non-most significant bit capacitance group includes a second positive end capacitance, a third positive end capacitance, a second negative end capacitance and a third negative end capacitance, wherein During the sampling phase, the controller:

controlling the upper plates of the second positive terminal capacitor and the third positive terminal capacitor to be coupled to the positive terminal input voltage;

controlling the lower plate of the second positive terminal capacitor and the third positive terminal capacitor to be coupled to the negative terminal input voltage;

controlling the upper plate of the second negative terminal capacitor and the third negative terminal capacitor to be coupled to the negative terminal input voltage; and

The lower plate controlling the second negative terminal capacitor and the third negative terminal capacitor is coupled to the positive terminal input voltage.
The successive approximation register analog-to-digital converter of claim 4, wherein the first positive terminal capacitor and the first negative terminal capacitor both have a first capacitance value, and the second positive terminal capacitor, The second negative terminal capacitor, the third positive terminal capacitor and the third negative terminal capacitor all have a second capacitance value, and the first capacitance value is twice the second capacitance value.
The successive approximation register analog-to-digital converter of claim 4, wherein in the sampling phase, the controller:

Both the upper plate and the lower plate for controlling the first positive terminal capacitor and the first negative terminal capacitor are coupled to the common mode voltage.
The successive approximation register analog-to-digital converter of claim 4, wherein in the charge redistribution stage, the controller:

controlling the upper plate of the first positive terminal capacitor, the second positive terminal capacitor and the third positive terminal capacitor to be coupled to the positive input terminal of the comparator;

controlling the lower plate of the first positive terminal capacitor, the second positive terminal capacitor and the third positive terminal capacitor to be coupled to the common mode voltage;

The upper plate controlling the first negative terminal capacitor, the second negative terminal capacitor and the third negative terminal capacitor is coupled to the negative input terminal of the comparator; and

The bottom plate controlling the first negative terminal capacitor, the second negative terminal capacitor and the third negative terminal capacitor is coupled to the common mode voltage.
The successive approximation register analog-to-digital converter of claim 7, wherein in the conversion stage, the controller:

Control the bottom plate of the first positive terminal capacitor to be coupled to the negative reference voltage, and the bottom plate of the first negative terminal capacitor to be coupled to the positive reference voltage in response to the first comparison result being positive, and generate the second comparison result accordingly; and

Controlling the lower plate of the first positive terminal capacitor to be coupled to the positive reference voltage, and the lower plate of the first negative terminal capacitor to be coupled to the negative reference voltage in response to the first comparison result being: negative, and generate the second comparison result accordingly.
The successive approximation register type analog-to-digital converter of claim 8, wherein,

wherein during the transition phase, the controller:

The bottom plate of the second positive terminal capacitor is controlled to be coupled to the negative reference voltage, and the bottom plate of the second negative terminal capacitor is coupled to the positive reference voltage in response to the second comparison result being: positive, and produce the third comparison result accordingly; and

The bottom plate of the second positive terminal capacitor is controlled to be coupled to the positive reference voltage, and the bottom plate of the second negative terminal capacitor is coupled to the negative reference voltage in response to the second comparison result being: negative, and generate the third comparison result accordingly.
The successive approximation register type analog-to-digital converter according to claim 3, wherein the total capacitance value of the most significant bit capacitance group is equal to the total capacitance value of the non-most significant bit capacitance group, and the most significant bit capacitance group is equal. The bit capacitance group includes a first positive end capacitance, a second positive end capacitance, a first negative end capacitance and a second negative end capacitance, and the non-most significant bit capacitance group includes a third positive end capacitance, a fourth positive end capacitance, a Five positive terminal capacitors, sixth positive terminal capacitors, third negative terminal capacitors, fourth negative terminal capacitors, fifth negative terminal capacitors and sixth negative terminal capacitors, wherein in the sampling stage, the controller:

controlling the upper plate of the third positive terminal capacitor, the fourth positive terminal capacitor, the fifth positive terminal capacitor and the sixth positive terminal capacitor to be coupled to the positive terminal input voltage;

controlling the lower plate of the third positive terminal capacitor, the fourth positive terminal capacitor, the fifth positive terminal capacitor and the sixth positive terminal capacitor to be coupled to the negative terminal input voltage;

controlling the upper plate of the third negative terminal capacitor, the fourth negative terminal capacitor, the fifth negative terminal capacitor and the sixth negative terminal capacitor to be coupled to the negative terminal input voltage; and

The lower plate controlling the third negative terminal capacitor, the fourth negative terminal capacitor, the fifth negative terminal capacitor and the sixth negative terminal capacitor is coupled to the positive terminal input voltage.
The successive approximation register analog-to-digital converter of claim 10, wherein the first positive terminal capacitor, the second positive terminal capacitor, the first negative terminal capacitor and the second negative terminal capacitor The terminal capacitors all have a first capacitance value, the third positive terminal capacitor, the fourth positive terminal capacitor, the fifth positive terminal capacitor, the sixth positive terminal capacitor, the third negative terminal capacitor, the The fourth negative terminal capacitor, the fifth negative terminal capacitor and the sixth negative terminal capacitor all have a second capacitance value, and the first capacitance value is twice the second capacitance value.
11. The successive approximation register analog-to-digital converter of claim 10, wherein in the sampling phase, the controller:

Both the upper plate and the lower plate for controlling the first positive terminal capacitor and the first negative terminal capacitor are coupled to the positive reference voltage; and

Both the upper plate and the lower plate for controlling the second positive terminal capacitor and the second negative terminal capacitor are coupled to the negative reference voltage.
11. The successive approximation register analog-to-digital converter of claim 10, wherein in the charge redistribution stage, the controller:

Control the upper and lower of the first positive terminal capacitor, the second positive terminal capacitor, the third positive terminal capacitor, the fourth positive terminal capacitor, the fifth positive terminal capacitor and the sixth positive terminal capacitor the electrode plate is coupled to the positive input terminal of the comparator;

controlling the lower plates of the first positive terminal capacitor, the third positive terminal capacitor, and the fifth positive terminal capacitor to be coupled to the positive reference voltage;

controlling the lower plate of the second positive terminal capacitor, the fourth positive terminal capacitor, and the sixth positive terminal capacitor to be coupled to the negative reference voltage;

Control the upper and lower of the first negative terminal capacitor, the second negative terminal capacitor, the third negative terminal capacitor, the fourth negative terminal capacitor, the fifth negative terminal capacitor and the sixth negative terminal capacitor The electrode plate is coupled to the negative input end of the comparator; and the lower electrode plate that controls the first negative end capacitor, the third negative end capacitor, and the fifth negative end capacitor are all coupled to the the positive reference voltage;

Controlling the lower plate of the second negative terminal capacitor, the fourth negative terminal capacitor, and the sixth negative terminal capacitor to be coupled to the negative reference voltage;
14. The successive approximation register analog-to-digital converter of claim 13, wherein in the conversion stage, the controller:

Controlling the bottom plate of the first positive terminal capacitor to be coupled to the negative reference voltage and the bottom plate of the second negative terminal capacitor to be coupled to the positive reference voltage, in response to the first comparison result being: positive, and generate the second comparison result accordingly; and

Controlling the bottom plate of the second positive terminal capacitor to be coupled to the positive reference voltage and the bottom plate of the first negative terminal capacitor to be coupled to the negative reference voltage, in response to the first comparison result being: negative, and generate the second comparison result accordingly.
15. The successive approximation register-based analog-to-digital converter of claim 14, wherein in the conversion stage, the controller:

Controlling the lower plate of the third positive terminal capacitor to be coupled to the negative reference voltage and the lower plate of the fourth negative terminal capacitor to be coupled to the positive reference voltage, in response to the second comparison result being: positive, and produce the third comparison result accordingly; and

Controlling the lower plate of the fourth positive terminal capacitor to be coupled to the positive reference voltage and the lower plate of the third negative terminal capacitor to be coupled to the negative reference voltage, in response to the second comparison result being: negative, and generate the third comparison result accordingly.
A chip, characterized in that it includes:

A successive approximation register type analog-to-digital converter as claimed in any one of claims 1 to 15.
An electronic device, comprising:

The chip of claim 16 .