WO2022118630A1 - Imaging device and electronic apparatus - Google Patents

Abstract

[Problem] To reduce the variation in charge injection during sample holding. [Solution] The imaging device of the present disclosure comprises: a pixel array unit; and a plurality of sample hold circuits provided corresponding to a pixel array of the pixel array unit. The sample hold circuit includes a write circuit which writes a reset signal and a data signal output from a pixel, a first capacitive element which holds the written reset signal, a second capacitive element which holds the written data signal, and a read circuit which reads out the reset signal held in the first capacitive element and the data signal held in the second capacitive element. The write circuit includes first/second charging transistors connected between an input terminal and first/second capacitive elements, a sampling transistor which samples the reset signal and the data signal, and first/second write transistors connected between the sampling transistor and the first/second capacitive elements.

Description

Imaging equipment and electronic equipment

This disclosure relates to an image pickup device and an electronic device.

The image pickup device is equipped with an analog-to-digital converter that digitizes the analog pixel signal read from the pixels. The analog-to-digital converter mounted on the image pickup apparatus is a so-called column-parallel analog-to-digital converter, which is composed of a plurality of analog-to-digital converters arranged corresponding to a pixel row.

In the analog-to-digital conversion process, the signal read operation from the pixel and the analog-digital conversion operation are pipelined (pipelined), so that the actual pixel signal read operation including the analog-digital conversion process can be performed. Since the speed can be increased, the frame rate can be improved. In order to realize the pipeline processing between the signal reading operation and the analog-digital conversion operation, it is necessary to mount a sample hold circuit in front of the analog-digital converter.

By the way, the signal output from the pixel is a reset signal (so-called P-phase signal) which is a reset level output from the pixel at the time of reset, and a data signal (so-called so-called) which is a signal level output from the pixel at the time of photoelectric conversion. D-phase signal) is included. As a sample hold circuit for sample-holding a pixel signal including a reset signal and a data signal, there is a sample hold circuit separately provided with a path for sample-holding the reset signal and a path for sample-holding the data signal (for example, Patent Document 1). reference).

Japanese Unexamined Patent Publication No. 2009-253930

As described above, the sample hold circuit described in Patent Document 1 is provided with a path for sample-holding the reset signal and a path for sample-holding the data signal separately. Therefore, the variation in charge injection due to the switching operation of each path causes the variation in sampling error, appears as vertical stripes on the captured image, and contributes to the deterioration of image quality.

It is an object of the present disclosure to provide an image pickup device provided with a sample hold circuit capable of reducing variations in charge injection due to a switching operation during sample hold of the sample hold circuit, and an electronic device having the image pickup device.

The image pickup apparatus according to the first aspect of the present disclosure for achieving the above object is
A pixel array unit in which a plurality of pixels including a photoelectric conversion unit are arranged in a matrix, and a pixel array unit.
It is provided corresponding to the pixel sequence of the pixel array unit, and is equipped with a plurality of sample hold circuits that sample-hold the pixel signal output from the pixel through the signal line.
The sample hold circuit is
Input terminal for inputting reset signal and data signal output from pixel,
A write circuit that writes the reset signal and data signal input from the input terminal,
A first capacitive element that holds the reset signal written by the write circuit,
A second capacitive element that holds the data signal written by the write circuit,
A reset signal held in the first capacitive element, a read circuit for reading a data signal held in the second capacitive element, and a read circuit.
Equipped with an output terminal that outputs the reset signal and data signal read by the read circuit.
The writing circuit is
A first charging transistor connected between an input terminal and a first capacitive element,
A second charging transistor connected between the input terminal and the second capacitive element,
Sampling transistor that samples the reset signal and data signal input from the input terminal,
A first write transistor connected between the sampling transistor and the first capacitive element, as well as
It has a second write transistor connected between the sampling transistor and the second capacitive element.

The image pickup apparatus according to the second aspect of the present disclosure for achieving the above object is
A pixel array unit in which a plurality of pixels including a photoelectric conversion unit are arranged in a matrix, and a pixel array unit.
It is provided corresponding to the pixel sequence of the pixel array unit, and is equipped with a plurality of sample hold circuits that sample-hold the pixel signal output from the pixel through the signal line.
The sample hold circuit is
Input terminal for inputting reset signal and data signal output from pixel,
A write circuit that writes the reset signal and data signal input from the input terminal,
A first capacitive element that holds the reset signal written by the write circuit,
A second capacitive element that holds the data signal written by the write circuit,
A reset signal held in the first capacitive element, a read circuit for reading a data signal held in the second capacitive element, and a read circuit.
Equipped with an output terminal that outputs the reset signal and data signal read by the read circuit.
The read circuit is
A first output circuit connected between the first capacitive element and the output terminal,
A second output circuit connected between the second capacitive element and the output terminal, and
It has a reset transistor that resets the potential of each output node of the first output circuit and the second output circuit.
The first output circuit and the second output circuit are a front-stage output transistor and a rear-stage output transistor connected in series between the first capacitive element and the output node and between the second capacitive element and the output node, respectively. It has an output transistor.

The image pickup apparatus according to the third aspect of the present disclosure for achieving the above object is
A pixel array unit in which a plurality of pixels including a photoelectric conversion unit are arranged in a matrix, and a pixel array unit.
It is provided corresponding to the pixel sequence of the pixel array unit, and is equipped with a plurality of sample hold circuits that sample-hold the pixel signal output from the pixel through the signal line.
The sample hold circuit is
Input terminal for inputting reset signal and data signal output from pixel,
A write circuit that writes the reset signal and data signal input from the input terminal,
A first capacitive element that holds the reset signal written by the write circuit,
A second capacitive element that holds the data signal written by the write circuit,
A reset signal held in the first capacitive element, a read circuit for reading a data signal held in the second capacitive element, and a read circuit.
Equipped with an output terminal that outputs the reset signal and data signal read by the read circuit.
The writing circuit is
A first charging transistor connected between an input terminal and a first capacitive element,
A second charging transistor connected between the input terminal and the second capacitive element,
Sampling transistor that samples the reset signal and data signal input from the input terminal,
A first write transistor connected between the sampling transistor and the first capacitive element, as well as
It has a second write transistor connected between the sampling transistor and the second capacitive element.
The read circuit is
A first output circuit connected between the first capacitive element and the output terminal,
A second output circuit connected between the second capacitive element and the output terminal, and
It has a reset transistor that resets the potential of each output node of the first output circuit and the second output circuit.
The first output circuit and the second output circuit are a front-stage output transistor and a rear-stage output transistor connected in series between the first capacitive element and the output node and between the second capacitive element and the output node, respectively. It has an output transistor.

The electronic device of the present disclosure for achieving the above object has the image pickup device according to the first aspect, the image pickup device according to the second aspect, or the image pickup device according to the third aspect.

FIG. 1 is a block diagram schematically showing an outline of a system configuration of a CMOS image sensor, which is an example of an image pickup apparatus to which the technique according to the present disclosure is applied. FIG. 2 is a circuit diagram showing an example of a pixel circuit configuration. FIG. 3A is a perspective view schematically showing a horizontal chip structure, and FIG. 3B is an exploded perspective view schematically showing a laminated semiconductor chip structure. FIG. 4 is a block diagram schematically showing an example of the configuration of the analog-to-digital conversion unit. FIG. 5A is a circuit diagram showing a configuration example of a sample hold circuit according to the prior art, and FIG. 5B is a timing chart used for explaining the circuit operation. 6A and 6B are diagrams illustrating a mechanism in which the variation in charge injection causes a sampling error. FIG. 7 is a block diagram showing a basic configuration of the sample hold circuit according to the embodiment of the present disclosure. FIG. 8 is a circuit diagram showing a circuit configuration example of the writing circuit according to the first embodiment. FIG. 9 is a timing chart provided for explaining the circuit operation of the writing circuit according to the first embodiment. FIG. 10 is an explanatory diagram of a sampling error at the time of signal writing in the writing circuit according to the first embodiment. FIG. 11 is a circuit diagram showing a circuit configuration example of the readout circuit according to the second embodiment. FIG. 12 is a timing chart used to explain the circuit operation of the readout circuit according to the second embodiment. 13A, 13B, and 13C are operation explanatory diagrams (No. 1) regarding an error of the output voltage at the time of reading out the channel charge in the reading circuit according to the second embodiment. 14A, 14B, and 14C are operation explanatory diagrams (No. 2) regarding the error of the output voltage at the time of reading the channel charge in the reading circuit according to the second embodiment. FIG. 15 is a circuit diagram showing a circuit configuration example of the sample hold circuit according to the third embodiment. FIG. 16 is a timing chart used to explain the circuit operation of the sample hold circuit according to the third embodiment. 17A, 17B, 17C, and 17D are operation explanatory diagrams showing the state of the sample / hold operation of the P phase in the sample hold circuit according to the third embodiment. FIG. 18 is a diagram showing an application example of the technique according to the present disclosure. FIG. 19 is a block diagram showing an outline of a configuration example of an imaging system which is an example of the electronic device of the present disclosure. FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving body control system to which the technique according to the present disclosure can be applied. FIG. 21 is a diagram showing an example of an installation position of an image pickup unit in a mobile control system.

Hereinafter, embodiments for carrying out the technique according to the present disclosure (hereinafter, referred to as “embodiments”) will be described in detail with reference to the drawings. The technique according to the present disclosure is not limited to the embodiment. In the following description, the same reference numerals will be used for the same elements or elements having the same function, and duplicate description will be omitted. The explanation will be given in the following order.
1. 1. Description of the image pickup device and electronic device of the present disclosure in general 2. Image pickup device to which the technique according to the present disclosure is applied 2-1. Configuration example of CMOS image sensor 2-2. Pixel circuit configuration example 2-3. Semiconductor chip structure 2-3-1. Flat semiconductor chip structure 2-3-2. Laminated semiconductor chip structure 2-4. Configuration example of analog-to-digital converter 2-5. About pipeline processing 2-6. Conventional Techniques for Sample Hold Circuits 3. Embodiments of the present disclosure 3-1. Example 1 (Example of suppressing fixed pattern noise by the action of a writing circuit)
3-1-1. Circuit configuration example 3-1-2. Circuit operation example 3-1-3. Sampling error during writing 3-2. Example 2 (Example of suppressing fixed pattern noise by the action of a readout circuit)
3-2-1. Circuit configuration example 3-2-2. Circuit operation example 3-2-3. About the error of the output voltage at the time of reading out the P phase 3-3. Example 3 (Example of suppressing fixed pattern noise by a write circuit and a read circuit)
3-3-1. Circuit configuration example 3-3-2. Circuit operation example 3-3-3. P-phase sample / hold operation 4. Modification example 5. Application example 6. Application example of the technique according to the present disclosure 6-1. Electronic device of the present disclosure (example of image pickup device)
6-2. Application example to moving body 7. Configuration that can be taken by this disclosure

<Explanation of the image pickup device and electronic device of the present disclosure, in general>
In the image pickup apparatus and the electronic device according to the first aspect of the present disclosure, the first charging transistor is turned on, the first capacitive element is charged based on the reset signal, and the first charging transistor is turned off. After the state is set, the charging path of the first capacitive element is switched to the path of the sampling transistor and the first writing transistor, and then the second charging transistor is turned on and the second charging path is based on the reset signal. After charging the capacitive element and turning off the second charging transistor, the charging path of the second capacitive element can be switched to the path of the sampling transistor and the second writing transistor.

In the image pickup apparatus and the electronic device according to the first aspect of the present disclosure including the above-mentioned preferable configuration, the reset signal is sampled by the sampling transistor in the path of the sampling transistor and the first writing transistor, and the first It is held by the first capacitive element via the write transistor, the reset signal is sampled by the sampling transistor in the path of the sampling transistor and the second write transistor, and the second capacitance is sampled via the second write transistor. It can be configured to be held by the element.

In the image pickup apparatus and the electronic apparatus according to the second aspect of the present disclosure, the first output circuit and the second output circuit are in the ON state during the sample hold period of the reset signal and the data signal by the write circuit. The configuration may be such that the front-stage output transistor is turned off, and then the reset transistor and the rear-stage output transistor are turned on to reset the potential of the output node.

In the image pickup apparatus and the electronic device according to the second aspect of the present disclosure including the above-mentioned preferable configuration, in the first output circuit and the second output circuit, the post-stage output transistor after resetting the potential of the output node is used. The configuration may be such that the reset signal held in the first capacitive element and the data signal held in the second capacitive element are read out in the ON state, and then the subsequent output transistor is turned off.

In the image pickup apparatus and the electronic device according to the third aspect of the present disclosure, the first charging transistor is turned on, the first capacitive element is charged based on the reset signal, and the first charging transistor is turned off. After the state is set, the charging path of the first capacitive element is switched to the path of the sampling transistor and the first writing transistor, and then the second charging transistor is turned on and the second charging path is based on the reset signal. After charging the capacitive element and turning off the second charging transistor, the charging path of the second capacitive element can be switched to the path of the sampling transistor and the second writing transistor.

In the image pickup apparatus and the electronic device according to the third aspect of the present disclosure including the above-mentioned preferable configuration, the reset signal is sampled by the sampling transistor in the path of the sampling transistor and the first writing transistor, and the first It is held by the first capacitive element via the write transistor, the reset signal is sampled by the sampling transistor in the path of the sampling transistor and the second write transistor, and the second capacitance is sampled via the second write transistor. It can be configured to be held by the element.

Further, in the image pickup apparatus and the electronic device according to the third aspect of the present disclosure including the above-mentioned preferable configuration, in the first output circuit and the second output circuit, a sample of a reset signal and a data signal by a write circuit is used. The front-stage output transistor that is in the on-state during the hold period can be turned off, and then the reset transistor and the rear-stage output transistor can be turned on to reset the potential of the output node.

Further, in the image pickup apparatus and the electronic device according to the third aspect of the present disclosure including the above-mentioned preferable configuration, in the first output circuit and the second output circuit, the potential of the output node is reset and the previous stage output is performed. The transistor may be turned on, the reset signal held in the first capacitive element and the data signal held in the second capacitive element may be read out, and then the subsequent output transistor may be turned off. can.

<Image pickup device to which the technique according to the present disclosure is applied>
As an image pickup device to which the technique according to the present disclosure is applied, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is a kind of XY address type image pickup device, will be described as an example. A CMOS image sensor is an image sensor made by applying or partially using a CMOS process.

[Configuration example of CMOS image sensor]
FIG. 1 is a block diagram schematically showing an outline of a system configuration of a CMOS image sensor, which is an example of an image pickup apparatus to which the technique according to the present disclosure is applied.

The CMOS image sensor 1 according to this application example has a configuration including a pixel array unit 11 and a peripheral circuit unit of the pixel array unit 11. The pixel array unit 11 has a configuration in which pixels (pixel circuits) 20 including a photoelectric conversion unit (photoelectric conversion element / light receiving element) are two-dimensionally arranged in a row direction and a column direction, that is, in a matrix. Here, the row direction means the arrangement direction of the pixels 20 in the pixel row, and the column direction means the arrangement direction of the pixels 20 in the pixel row. By performing photoelectric conversion, the pixel 20 generates and accumulates a light charge according to the amount of light received.

The peripheral circuit units of the pixel array unit 11 include, for example, a row selection unit 12, a load MOS unit 13, a sample hold unit 14, an analog-to-digital conversion unit 15, a memory unit 16, a data processing unit 17, an output unit 18, and timing. It is composed of a control unit 19 and the like.

In the pixel array unit 11, pixel drive lines 31 (31 ₁ to 31 _m ) are wired along the row direction for each pixel row with respect to the matrix-shaped pixel array, and vertical signal lines 32 (321 to 31 m) are wired for _each pixel column. 32 _n ) are wired along the column direction. The pixel drive line 31 transmits a drive signal for driving when reading a signal from the pixel 20. In FIG. 1, the pixel drive line 31 is shown as one wiring, but the wiring is not limited to one. One end of the pixel drive line 31 is connected to the output end corresponding to each row of the row selection unit 12.

Below, each circuit unit of the peripheral circuit unit of the pixel array unit 11, that is, the row selection unit 12, the load MOS unit 13, the sample hold unit 14, the analog-to-digital conversion unit 15, the memory unit 16, the data processing unit 17, and the output. A unit 18 and a timing control unit 19 will be described.

The row selection unit 12 is composed of a shift register, an address decoder, and the like, and controls the scanning of the pixel row and the address of the pixel row when selecting each pixel 20 of the pixel array unit 11. Although the specific configuration of the row selection unit 12 is not shown, it generally has two scanning systems, a read scanning system and a sweep scanning system.

The read-out scanning system selectively scans the pixels 20 of the pixel array unit 11 row by row in order to read the pixel signal from the pixels 20. The pixel signal read from the pixel 20 is an analog signal. The sweep-out scanning system performs sweep-out scanning for the read-out row performed by the read-out scanning system in advance of the read-out scan by the time of the shutter speed.

By the sweep scan by this sweep scan system, the photoelectric conversion unit is reset by sweeping out unnecessary charges from the photoelectric conversion unit of the pixel 20 in the read row. Then, by sweeping out (resetting) unnecessary charges by this sweep-out scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of discarding the optical charge of the photoelectric conversion unit and starting a new exposure (starting the accumulation of the optical charge).

The signal read by the read operation by the read scan system corresponds to the amount of light received after the read operation or the electronic shutter operation immediately before that. The period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the exposure period of the light charge in the pixel 20.

The load MOS unit 13 is composed of a set of current sources I composed of MOS transistors connected to each of the vertical signal lines 32 ( _{321 to 32 n )} for each pixel row (see FIG. 2), and is selected by the row selection unit 12. A bias current is supplied to each pixel 20 in the scanned pixel row through each of the vertical signal lines 32.

The sample hold unit 14 samples and holds (sample hold) the pixel signal supplied through the vertical signal line 32 ( _{321 to 32 n )} . The technique according to the present disclosure is applied to the sample hold unit 14. Details of the sample hold unit 14 to which the technique according to the present disclosure is applied will be described later.

The analog-to-digital (A / D) conversion unit 15 is composed of a set of a plurality of analog-to-digital converters provided corresponding to the vertical signal lines 32 ( _{321 to 32 n )} , and is a pixel array from the sample hold unit 14. The analog pixel signal output each time is converted into a digital signal. The analog-to-digital converter can be a well-known analog-to-digital converter. Specifically, as the analog-to-digital converter, a single slope type analog-to-digital converter, a sequential comparison type analog-to-digital converter, or a delta-sigma type (ΔΣ type) analog-to-digital converter can be exemplified. can. However, the analog-to-digital converter is not limited to these.

The memory unit 16 stores the analog-to-digital conversion result in the analog-to-digital conversion unit 15 under the processing by the data processing unit 17.

The data processing unit 17 is a digital signal processing unit that processes a digital signal output from the analog-digital conversion unit 15, and performs write / read processing of the analog-digital conversion result to the memory unit 16 or the analog-. Various processes are performed on the digital conversion result.

The output unit 18 outputs the signal after processing by the data processing unit 17. The timing control unit 19 generates various timing signals, clock signals, control signals, and the like, and based on these generated signals, the row selection unit 12, the sample hold unit 14, the analog-digital conversion unit 15, and the timing control unit 19. Drive control of the data processing unit 17 and the like is performed.

[Pixel circuit configuration example]
FIG. 2 is a circuit diagram showing an example of the circuit configuration of the pixel 20. The pixel 20 has, for example, a photodiode 21 as a photoelectric conversion unit (photoelectric conversion element). The pixel 20 has a pixel configuration including a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in addition to the photodiode 21.

Here, for example, an N-channel MOS field effect transistor is used as the four transistors of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25. However, the combination of the conductive type of the four transistors 22 to 25 exemplified here is only an example, and is not limited to these combinations.

With respect to the pixel 20, a plurality of pixel drive lines are commonly wired to each pixel 20 in the same pixel row as the pixel drive line 31 (31 ₁ to 31 _m ) described above. These plurality of pixel drive lines are connected to the output end corresponding to each pixel row of the row selection unit 12 in pixel row units. The row selection unit 12 appropriately outputs the transfer signal TRG, the reset signal RST, and the selection signal SEL to the plurality of pixel drive lines.

In the photodiode 21, the anode electrode is connected to a low-potential side power supply (for example, ground), and the received light is photoelectrically converted into a light charge (here, a photoelectron) having a charge amount corresponding to the light amount, and the light thereof is converted. Accumulates electric charge. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistor 22. Here, the region in which the gate electrode of the amplification transistor 24 is electrically connected is a floating diffusion (floating diffusion region / impurity diffusion region) FD. The floating diffusion FD is a charge-voltage conversion unit that converts electric charge into voltage.

A transfer signal TRG in which a high level (for example, V _DD level) is active is given to the gate electrode of the transfer transistor 22 from the row selection unit 12. The transfer transistor 22 becomes conductive in response to the transfer signal TRG, is photoelectrically converted by the photodiode 21, and transfers the optical charge stored in the photodiode 21 to the floating diffusion FD.

The reset transistor 23 is connected between the node of the high potential side power supply _VDD and the floating diffusion FD. A reset signal RST that activates a high level is given to the gate electrode of the reset transistor 23 from the row selection unit 12. The reset transistor 23 becomes conductive in response to the reset signal RST, and resets the floating diffusion FD by discarding the charge of the floating diffusion FD to the node of the voltage V _DD .

In the amplification transistor 24, the gate electrode is connected to the floating diffusion FD, and the drain electrode is connected to the node of the high potential side power supply _VDD . The amplification transistor 24 serves as an input unit for a source follower that reads out a signal obtained by photoelectric conversion in the photodiode 21. That is, in the amplification transistor 24, the source electrode is connected to the vertical signal line 32 via the selection transistor 25. The amplification transistor 24 and the current source I connected to one end of the vertical signal line 32 form a source follower that converts the voltage of the floating diffusion FD into the potential of the vertical signal line 32.

In the selection transistor 25, for example, the drain electrode is connected to the source electrode of the amplification transistor 24, and the source electrode is connected to the vertical signal line 32, respectively. A selection signal SEL in which a high level is active is given to the gate electrode of the selection transistor 25 from the row selection unit 12. The selection transistor 25 enters a conduction state in response to the selection signal SEL, so that the signal output from the amplification transistor 24 is transmitted to the vertical signal line 32 with the pixel 20 in the selection state.

In the above circuit example, the pixel 20 is composed of a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25, that is, a 4Tr configuration composed of four transistors (Tr) is given as an example. , Not limited to this. For example, the selection transistor 25 may be omitted, and the amplification transistor 24 may have a 3Tr configuration in which the function of the selection transistor 25 is provided. If necessary, the number of transistors may be increased to a configuration of 5Tr or more. ..

From the pixel 20 of the above circuit configuration example, there are a reset signal (so-called P-phase signal) which is a reset level at the time of resetting the floating diffusion FD by the reset transistor 23, and a signal level based on photoelectric conversion in the photodiode 21. Data signals (so-called D-phase signals) are output in order. That is, the pixel signal output from the pixel 20 includes a reset signal at the time of reset and a data signal at the time of photoelectric conversion by the photodiode 21.

[Semiconductor chip structure]
As the semiconductor chip structure of the CMOS image sensor 1 having the above configuration, a horizontal semiconductor chip structure and a laminated semiconductor chip structure can be exemplified. Further, regarding the pixel structure, when the substrate surface on the side where the wiring layer is formed is the front surface (front surface), a back surface irradiation type pixel structure that takes in the light emitted from the back surface side on the opposite side can also be used. However, a surface-illuminated pixel structure that captures the light emitted from the surface side can also be used.

The outline of the horizontal semiconductor chip structure and the laminated semiconductor chip structure will be described below.

(Flat type semiconductor chip structure)
FIG. 3A is a perspective view schematically showing a horizontal chip structure of the CMOS image sensor 1. As shown in FIG. 3A, in the horizontal semiconductor chip structure, each component of the peripheral circuit unit of the pixel array unit 11 is placed on the same semiconductor substrate 41 as the pixel array unit 11 in which the pixels 20 are arranged in a matrix. It has a formed structure. Specifically, on the same semiconductor substrate 41 as the pixel array unit 11, the row selection unit 12, the load MOS unit 13, the sample hold unit 14, the analog-to-digital conversion unit 15, the memory unit 16, the data processing unit 17, and so on. A timing control unit 19 and the like are formed. Pads 42 for external connection and power supply are provided at, for example, both left and right ends of the semiconductor chip 41 of the first layer.

(Laminated semiconductor chip structure)
FIG. 3B is an exploded perspective view schematically showing a laminated semiconductor chip structure of the CMOS image sensor 1. As shown in FIG. 3B, the laminated semiconductor chip structure has a structure in which at least two semiconductor chips of the first layer semiconductor chip 43 and the second layer semiconductor chip 44 are laminated.

In this laminated semiconductor chip structure, the first-layer semiconductor chip 43 is formed with a pixel array portion 11 in which pixels 20 including a photoelectric conversion element (for example, a photodiode 21) are two-dimensionally arranged in a matrix. It is a pixel chip. Pads 42 for external connection and power supply are provided at, for example, both left and right ends of the semiconductor chip 43 of the first layer.

The second layer semiconductor chip 44 is a peripheral circuit unit of the pixel array unit 11, that is, a row selection unit 12, a load MOS unit 13, a sample hold unit 14, an analog-to-digital conversion unit 15, a memory unit 16, and a data processing unit 17. , And a circuit chip on which the timing control unit 19 and the like are formed. The arrangement of the row selection unit 12, the load MOS unit 13, the sample hold unit 14, the analog-to-digital conversion unit 15, the memory unit 16, the data processing unit 17, the timing control unit 19, etc. is an example. It is not limited to this arrangement example.

The pixel array portion 11 on the first-layer semiconductor chip 43 and the peripheral circuit portion on the second-layer semiconductor chip 44 are metal-metal junctions including Cu—Cu junctions and through silicon vias (Through Silicon Via: TSV). ), Micro bumps and the like (not shown) are electrically connected.

According to the laminated semiconductor chip structure described above, a process suitable for manufacturing the pixel array portion 11 can be applied to the semiconductor chip 43 of the first layer, and the semiconductor chip 44 of the second layer is suitable for manufacturing the circuit portion. Process can be applied. This makes it possible to optimize the process in manufacturing the CMOS image sensor 1. In particular, advanced processes can be applied to the fabrication of circuit parts.

[Analog-to-digital conversion unit configuration example]
Subsequently, an example of the configuration of the analog-to-digital conversion unit 15 will be described. FIG. 4 shows an example of the configuration of the analog-to-digital conversion unit 15.

In the CMOS image sensor 1, the analog-to-digital converter 15 is composed of a set of a plurality of analog-to-digital converters provided corresponding to each pixel sequence of the pixel array unit 11. Here, as an analog-to-digital converter, a single-slope type analog-to-digital converter is exemplified. However, the analog-to-digital converter is not limited to the single-slope type analog-to-digital converter.

The analog-to-digital converter 150 in the nth row will be described by taking as an example a single-slope analog-to-digital converter 150. The analog-to-digital converter 150 has a circuit configuration including a comparator 151 and a counter 152. In the single slope type analog-to-digital converter 150, the reference signal V _RAMP generated by the reference signal generation unit 160 is used. The reference signal generation unit 160 is composed of, for example, a digital-to-analog converter (DAC), and generates a reference signal V _RAMP having a gradient waveform (so-called ramp wave) whose level (voltage) monotonically decreases with the passage of time. It is generated and given as a reference signal to the comparator 151 provided for each pixel row.

The comparator 151 uses the analog pixel signal V _VSL read from the pixel 20 as a comparison input and the reference signal V _RAMP of the lamp wave generated by the reference signal generation unit 160 as a reference input, and compares both signals. Then, for example, when the reference signal V _RAMP is larger than the pixel signal V _VSL , the output of the comparator 151 is in the first state (for example, high level), and when the reference signal V _RAMP is equal to or less than the pixel signal V _VSL . The output is in the second state (eg, low level). As a result, the comparator 151 outputs a pulse signal having a pulse width corresponding to the signal level of the pixel signal _VVSL , specifically, a pulse width corresponding to the magnitude of the signal level, as a comparison result.

A clock signal CLK is given to the counter 152 from the timing control unit 19 at the same timing as the supply start timing of the reference signal V _RAMP to the comparator 151. Then, the counter 152 measures the period of the pulse width of the output pulse of the comparator 151, that is, the period from the start of the comparison operation to the end of the comparison operation by performing the counting operation in synchronization with the clock signal CLK. The count result (count value) of the counter 152 is supplied to the logic circuit unit 14 as a digital value obtained by digitizing the analog pixel signal _VVSL .

As the counter 152, for example, an up / down counter can be used. In the counter 152 including the up / down counters, a down (DOWN) count or an up (UP) count is performed in synchronization with the clock signal CLK. Specifically, the reset signal (P-phase signal), which is the reset level at the time of resetting the floating diffusion FD, and the data signal (D-phase signal), which is the signal level based on photoelectric conversion, are output from the pixel 20. For example, the reset signal is down-counted, and the data signal is up-counted.

By this down count / up count operation, the difference between the data signal and the reset signal can be taken. As a result, the analog-to-digital conversion unit 15 performs CDS (Correlated Double Sampling) processing in addition to the analog-to-digital conversion processing. Here, the "CDS process" takes the difference between the data signal (D-phase signal), which is a signal level based on photoelectric conversion, and the reset signal (P-phase signal), which is the reset level at the time of resetting the floating diffusion FD. This is a process for removing fixed pattern noise peculiar to the pixel such as reset noise of the pixel 20 and threshold variation of the amplification transistor 24.

According to the analog-digital conversion unit 15 composed of the set of the single slope type analog-digital converter 150 described above, the reference signal V _RAMP of the lamp wave generated by the reference signal generation unit 160 and the vertical signal line from the pixel 20. A digital value can be obtained from the time information until the magnitude relationship with the analog pixel signal _VVSL read through 32 changes.

In the above example, the analog-to-digital converter 150 is arranged as the analog-to-digital converter 15 in a one-to-one correspondence with the pixel array of the pixel array unit 11. It is also possible to configure the analog-to-digital converter 150 by arranging the pixel strings of the above as a unit.

[Pipeline processing]
In the CMOS image sensor 1 to which the technique according to the present disclosure described above is applied, that is, the CMOS image sensor 1 equipped with the column-parallel analog-digital conversion unit 15, the sample hold unit is in front of the analog-digital conversion unit 15. By providing 14, it is possible to realize a pipeline process of a signal reading operation from the pixel 20 and an analog-to-digital conversion operation. The sample hold unit 14 is composed of a set of a plurality of sample hold circuits provided corresponding to each pixel row of the pixel array unit 11.

By pipeline processing (pipelined) between the signal reading operation and the analog-digital conversion operation, the actual pixel signal reading operation including the analog-digital conversion processing can be speeded up, so the frame rate should be improved. Can be done. On the contrary, if the frame rate is not improved (that is, if the frame rate is the same as the conventional one), the blanking period in which signal reading and analog-to-digital conversion are not performed can be increased, so that the CMOS image The power consumption of the sensor 1 can be reduced.

[Conventional technology of sample hold circuit]
Here, the conventional technique of the sample hold circuit necessary for realizing the pipeline processing between the signal reading operation and the analog-to-digital conversion operation will be described. A configuration example of the sample hold circuit according to the prior art is shown in FIG. 5A, and a timing chart for explaining the circuit operation is shown in FIG. 5B.

As shown in FIG. 5A, the sample hold circuit according to the prior art has a P-phase path 60p for sample-holding a reset signal ( _P -phase signal), which is a reset level when the floating diffusion FD is reset, and photoelectric conversion. It has a circuit configuration having a D-phase path 60 _d for sample-holding a data signal (D-phase signal) which is a signal level based on the data signal (D-phase signal).

The P-phase path 60 _p is composed of a sampling transistor 61 _p for sampling the reset signal, a capacitive element 62 _p for holding the reset signal sampled by the sampling transistor 61 _p , and an output transistor 63 _p . The sampling transistor 61 _p samples the reset signal based on the control signal p_spl and causes the capacitive element 62 _p to hold the reset signal. The output transistor 63 _p outputs the reset signal held in the capacitive element 62 _p according to the control signal p_out.

The D-phase path 60 _d is composed of a sampling transistor 61 _d for sampling a data signal, a capacitive element 62 _d for holding a data signal sampled by the sampling transistor 61 _d , and an output transistor 63 _d . The sampling transistor 61 _d samples a data signal based on the control signal d_spl and causes the capacitive element 62 _d to hold the data signal. The output transistor 63 _d outputs the data signal held in the capacitive element 62 _d according to the control signal d_out.

As described above, the sample hold circuit according to the prior art has a configuration in which a P-phase path 60 _p for sample-holding the reset signal and a D-phase path 60 _d for sample-holding the data signal are separately provided. ing. Therefore, the channel charges of the sampling transistor 61 _p and the output transistor 63 _p may vary due to manufacturing variations such as the threshold voltage V _th and the gate area of the transistors in each of the paths 60 _p and 60 _d . This variation in charge injection becomes a sampling error, that is, fixed pattern noise of the pixel sequence, and appears as vertical streaks on the captured image.

The mechanism by which the above-mentioned charge injection variation causes a sampling error will be described with reference to FIGS. 6A and 6B. Although the _P -phase path 60p in FIG. 5A is taken out and shown in FIG. 6A for convenience of explanation, the same thing as the _P -phase path 60p occurs in the _D -phase path 60d.

In the P-phase path 60 _p , when the capacitance value of the capacitance element 62 _p is C _p and the capacitance value of the parasitic capacitance attached to the output side of the output transistor 63 _p is c _x , generally, C _p >> c _x . be. Therefore, the impedance of the node S (∝1 / C _p ) is lower than the impedance of the node OUT (∝1 / c _x ).

As shown in FIG. 6B, in the sampling transistor 61p, when the control signal _{p_spl} transitions from a high level (Hi) to a low level (Lo), most of the channel charge is discharged to the low impedance input node IN side. At this time, a part of the channel charge enters the node S side of the medium impedance, and this becomes a sampling error. Further, in the output transistor 63p, when the control signal _{p_out} transitions from a low level to a high level, most of the channel charge is supplied from the medium impedance node S, and a part of the charge accumulated in the node S is consumed. , This is also a sampling error.

<Embodiment of the present disclosure>
The sample hold circuit according to the embodiment of the present disclosure is made in order to reduce the variation in charge injection due to the switching operation at the time of sample hold in the CMOS image sensor 1 provided with the column-parallel analog-digital conversion unit 15. Is. By reducing the variation in charge injection due to the switching operation during sample hold, it is possible to suppress the fixed pattern noise of the pixel array, so that vertical streaks caused by the fixed pattern noise of the pixel array appear on the captured image. It is possible to improve the image quality.

FIG. 7 shows a basic configuration of a sample hold circuit according to an embodiment of the present disclosure (hereinafter, abbreviated as “the present embodiment”). The sample hold circuit 50 according to the present embodiment includes an input terminal 51, a write circuit 52, a first capacitive element 53 _p , a second capacitive element 53 _d , a read circuit 54, and an output terminal 55.

The input terminal 51 inputs a reset signal and a data signal output from each pixel 20 of the pixel array unit 11. The reset signal is a P-phase signal which is a reset level when the floating diffusion FD is reset. The data signal is a D-phase signal, which is a signal level based on photoelectric conversion in the photodiode 21.

The writing circuit 52 samples and writes a reset signal and a data signal input from the input terminal 51. The first capacitive element 53 _p is a capacitive element for the P phase and holds a reset signal written by the writing circuit 52. The second capacitive element 53 _d is a capacitive element for the D phase and holds the data signal written by the writing circuit 52. The read circuit 54 reads out the reset signal held in the first capacitive element 53 _p and the data signal held in the second capacitive element 53 _d . The output terminal 55 outputs the reset signal and the data signal read by the read circuit 54.

In the sample hold circuit 50 according to the present embodiment having the above basic configuration, the action of the write circuit 52, the action of the read circuit 54, or the action of the combination of the write circuit 52 and the read circuit 54 causes the sample hold to occur. It is possible to obtain the effect of suppressing the fixed pattern noise of the pixel array caused by the charge injection accompanying the switching operation. Specific examples will be described below.

[Example 1]
The first embodiment is an example of suppressing the fixed pattern noise caused by the charge injection accompanying the switching operation at the time of sample holding by the action of the writing circuit 52. FIG. 8 shows a circuit configuration example of the writing circuit 52 according to the first embodiment.

(Circuit configuration example)
The writing circuit 52 according to the first embodiment includes a first charging transistor 521 _p connected between the input terminal 51 and the first capacitive element 53 _p , and the input terminal 51 and the second capacitive element 53 _d . It has a second charging transistor 521 _d connected between the two. The write circuit 52 further includes a sampling transistor 522 that samples a reset signal and a data signal input from the input terminal 51, and a first write transistor 523 connected between the sampling transistor 522 and the first capacitive element _53p . It has _p and a second write transistor 523 _d connected between the sampling transistor 522 and the second capacitive element 53 _d .

In the write circuit 52 having the above circuit configuration, the P phase in which the reset signal is sample-held by the first charging transistor 521 _p , the sampling transistor 522, the first write transistor 523 _p , and the first capacitive element 53 _p . The route of is constructed. Further, the second charging transistor 521 _d , the sampling transistor 522, the second writing transistor 523 _d , and the second capacitive element 53 _d form a D-phase path for sample-holding the data signal. That is, in the writing circuit 52 according to the first embodiment, the sampling transistor 522 has a configuration in which the P-phase path and the D-phase path are shared.

The first charging transistor 521 _p is turned on in response to the control signal p_charge to charge the first capacitive element 53 _p based on the reset signal input from the input terminal 51. The second charging transistor 521 _d is turned on in response to the control signal d_charge to charge the second capacitive element 53 _d based on the data signal input from the input terminal 51. The sampling transistor 522 samples the reset signal and the data signal based on the control signal spl. The first write transistor 523 _p is turned on in response to the control signal p_slen, so that the reset signal sampled by the sampling transistor 522 is written to and held by the first capacitive element 53 _p . The second write transistor 523 _d is turned on in response to the control signal d_splen, so that the data signal sampled by the sampling transistor 522 is written to and held by the second capacitive element 53 _d .

(Circuit operation example)
Subsequently, the circuit operation of the writing circuit 52 according to the first embodiment will be described with reference to the timing chart of FIG.

At the time t ₁₁ when the reset signal is input from the input terminal 51, the control signal p_charge transitions from the low level to the high level, so that the first charging transistor 521 _p is turned on and the reset input from the input terminal 51 is performed. The first capacitive element _53p is charged based on the signal.

Next, at time t12, the control signal _{p_charge} transitions from a high level to a low level, so that the first charging transistor 521 _p is turned off. At the same time, the control signal spl and the control signal p_splen transition from the low level to the high level, so that the sampling transistor 522 and the first write transistor 523 _p are turned on. As a result, the reset signal sampled by the sampling transistor 522 is held by the first capacitive element 53 _p through the first write transistor 523 _p .

Next, at time _t13 , the control signal spl transitions from a high level to a low level, and the sampling transistor 522 is turned off, so that the amount of charge held by the first capacitive element _53p is determined. From time t ₁₃ to time t ₁₅ , the first capacitive element 53 _p is in the hold state. During the period from time t ₁₃ to time t ₁₅ , the potential level corresponding to the amount of electric charge held by the first capacitive element 53 _p can be read out by the read circuit 54 in the subsequent stage.

The same operation as that for the P-phase path is performed for the D-phase path. That is, when the control signal d_charge transitions from the low level to the high level at the time t ₁₄ when the data signal is input from the input terminal 51, the second charging transistor 521 _d is turned on and input from the input terminal 51. The second capacitive element 53 _d is charged based on the data signal.

Next, at time t ₁₆ , the control signal d_charge transitions from a high level to a low level, so that the second charging transistor 521 _d is turned off. At the same time, the control signal spl and the control signal d_splen transition from the low level to the high level, so that the sampling transistor 522 and the second write transistor 523 _d are turned on. As a result, the data signal sampled by the sampling transistor 522 is held by the second capacitive element 53 _d through the second write transistor 523 _d .

Next, at time t ₁₇ , the control signal spl transitions from a high level to a low level, and the sampling transistor 522 is turned off, so that the amount of charge held by the second capacitive element 53 _d is determined. From time t ₁₇ to time t ₁₈ , the second capacitive element 53 _d is in the hold state. During the period from time t ₁₇ to time t ₁₈ , the potential level corresponding to the amount of electric charge held by the second capacitive element 53 _d can be read out by the read circuit 54 in the subsequent stage.

As described above, in the writing circuit 52 according to the first embodiment, in the period from time t ₁₁ to time t ₁₂ , under the control of the control signal p_charge, the first capacitance is passed through the first charging transistor 521 _p . The element 53 _p is charged to the signal level input from the input terminal 51. As a result, in a short period from time t ₁₂ to time t ₁₃ , the path is switched to the path by the sampling transistor 522 and the first write transistor 523 _p at high speed, and the sample hold voltage of the first capacitive element 53 _p is determined. (The D-phase path is the same as the P-phase path). As a result, the time occupied by the sampling transistor 522 commonly used by the D-phase path / P-phase path is short, so that the time overhead can be reduced.

(Sampling error when writing a signal)
The sampling error at the time of signal writing in the writing circuit 52 according to the trowel and the first embodiment will be described with reference to FIG. FIG. 10 schematically shows the channel charge of the sampling transistor 522 immediately before and immediately after the timing (time t ₁₃ ) when the control signal spl of the sampling transistor 522 transitions from the high level to the low level. Here, the path of the P phase is illustrated, but the path of the D phase is the same as that of the path of the P phase.

When the sampling transistor 522 is switched from the on state to the off state, a part q ₁ of the channel charge of the sampling transistor 522 becomes a connection node a (see FIG. 8) between the sampling transistor 522 and the first write transistor 523 _p . It flows. Here, assuming that the capacitance value of the first capacitive element 53 _p is C _p , the sampling error at the time of writing to the first capacitive element 53 _p is q ₁ / C _p . Further, assuming that the capacitance value of the second capacitance element 53 _d is C _d , the sampling error at the time of writing to the second capacitance element 53 _d is q ₁ / C _d . Assuming that C _p = C _d , the writing error after the correlated double sampling (CDS) processing is almost zero.

As described above, after the sampling confirmation operation of the first capacitance element 53 _p / the second capacitance element 53 _d , both are determined by the on ⇒ off state of the sampling transistor 522. Then, the sampling error due to the feedthrough / charge injection of the sampling transistor 522 commonly occurs in the first capacitive element 53 _p / the second capacitive element 53 _d . Therefore, the sampling error commonly generated in the first capacitive element 53 _p / the second capacitive element 53 _d can be removed by, for example, the CDS processing executed in the column-parallel analog-digital converter 15. ..

[Example 2]
The second embodiment is an example of suppressing the fixed pattern noise caused by the charge injection accompanying the switching operation at the time of sample holding by the action of the read circuit 54. FIG. 11 shows a circuit configuration example of the readout circuit 54 according to the second embodiment.

(Circuit configuration example)
In the read circuit 54 according to the second embodiment, the first output circuit 540 _p connected between the first capacitive element 53 _p and the output terminal 55, and between the second capacitive element 53 _d and the output terminal 55. It has a second output circuit 540 _d connected to, and a reset transistor 543 that resets the potential of each output node N _out of the first and second output circuits 540 _p and 540 _d . The output nodes N _out of the first and second output circuits 540 _p and 540 _d are electrically connected to the output terminal 55.

The first output circuit 540 _p is a P-phase output path, and includes a front-stage output transistor 541 _p and a rear-stage output transistor 542 _p connected in series between the first capacitive element 53 _p and the output node N _out . Have. The second output circuit 540 _d is a D-phase output path, and has a front-stage output transistor 541 _d and a rear-stage output transistor 542 _d connected in series between the second capacitive element 53 _d and the output node N _out . Have. The reset transistor 543 is connected between a node having a predetermined reference potential V _ref and an output node N _out connected to the output terminal 55.

In the first output circuit 540 _p , the front-stage output transistor 541 _p performs an on / off operation according to the control signal p_out1, and the rear-stage output transistor 542 _p performs an on / off operation according to the control signal p_out2. In the second output circuit 540 _d , the front-stage output transistor 541 _d performs an on / off operation according to the control signal d_out1, and the rear-stage output transistor 542 _d performs an on / off operation according to the control signal d_out2. The reset transistor 543 performs an on / off operation according to the node reset signal rst.

The readout circuit 54 sets the potential level according to the amount of charge held by the first capacitance element 53 _{p having the capacitance value C p and} the second capacitance element 53 _d having the capacitance value C _d through the output terminal 55 in the subsequent row. It is output to the parallel type analog-to-digital conversion unit 15. The output node N _out connected to the output terminal 55 has a parasitic capacitance c _x . When reading from the first capacitive element 53 _p or the second capacitive element 53 _d while the potential history of the previous readout remains in this parasitic capacitance c _x , a readout error depending on the reading history occurs. There is a problem that it will be done.

Therefore, in the read circuit 54 according to the second embodiment, a reset transistor 543 for resetting the potential of the output node N _out is provided immediately before reading from the first capacitive element 53 _p or the second capacitive element 53 _d . , The potential of the output node N _out is reset to a predetermined reference potential V _ref . By adopting this configuration, the above-mentioned problems can be prevented in advance.

(Circuit operation example)
Subsequently, the circuit operation of the readout circuit 54 according to the second embodiment will be described with reference to the timing chart of FIG.

During the period from time t ₂₁ to time t ₂₂ , sampling (writing) of the P phase (reset signal) is performed in the path of the P phase including the first capacitance element 53 _p having the capacitance value C _p . During this sampling period, the control signal p_out1 of the pre-stage output transistor 541 _p of the first output circuit 540 _p is in a high level state, and the pre-stage output transistor 541 _p is in an on state.

Next, in the period from time t ₂₂ to time t ₂₆ , the potential level is read out according to the amount of charge held by the first capacitive element 53 _p . Specifically, first, the control signal _{p_out1} transitions from a high level to a low level at time t22, so that the pre-stage output transistor _541p is turned off.

Next, at time t ₂₃ , the control signal p_out2 and the node reset signal rst transition from the low level to the high level, so that the subsequent output transistor 542 _p and the reset transistor 543 are both turned on. As a result, the potential of the output node N _out of the read circuit 54 is reset to a predetermined reference potential V _ref . Then, at time t ₂₄ , the node reset signal rst transitions from the low level to the high level, and the reset transistor 543 is turned off, so that the reset operation of the output node N _out is completed.

Next, at time t ₂₅ , the control signal p_out1 transitions from a low level to a high level, and the previous stage output transistor 541 _p is turned on again, depending on the amount of charge held by the first capacitive element 53 _p . The potential level is read out to the output terminal 55 through the front-stage output transistor 541 _p and the rear-stage output transistor 542 _p . Then, the control signal p_out2 transitions from the high level to the low level, and the subsequent output transistor _542p is turned off, so that the reading operation of the P phase (reset signal) is completed.

The same operation as that for the P-phase path is performed for the D-phase path. That is, during the period from time t ₂₂ to time t ₂₆ , sampling (writing) of the D phase (data signal) is performed in the path of the D phase including the second capacitance element 53 _d having the capacitance value C _d . During this sampling period, the control signal d_out1 of the pre-stage output transistor 541 _d of the second output circuit 540 _d is in a high level state, and the pre-stage output transistor 541 _d is in an on state.

Next, in the period from time t ₂₆ to time t ₃₀ , the potential level is read out according to the amount of charge held by the second capacitive element 53 _d . Specifically, first, the control signal d_out1 transitions from a high level to a low level at time t ₂₆ , so that the pre-stage output transistor 541 _d is turned off.

Next, at time t ₂₇ , the control signal d_out2 and the node reset signal rst transition from the low level to the high level, so that the subsequent output transistor 542 _d and the reset transistor 543 are both turned on. As a result, the potential of the output node N _out of the read circuit 54 is reset to a predetermined reference potential V _ref . Then, at time t ₂₈ , the node reset signal rst transitions from the low level to the high level, and the reset transistor 543 is turned off, so that the reset of the output node N _out is completed.

Next, at time t ₂₉ , the control signal d_out1 transitions from a low level to a high level, and the previous stage output transistor 541 _d is turned on again, depending on the amount of charge held by the second capacitive element 53 _d . The potential level is read out to the output terminal 55 through the front-stage output transistor 541 _d and the rear-stage output transistor 542 _d . Then, the control signal d_out2 transitions from the high level to the low level, and the subsequent output transistor 542 _d is turned off, so that the D phase (data signal) reading operation is completed.

(About the error of the output voltage when reading the channel charge)
An error in the output voltage at the time of channel reading in the reading circuit 54 according to the second embodiment of the iron will be described with reference to the operation explanatory diagrams of FIGS. 13 and 14 based on the timing chart of FIG.

FIG. 13A is an operation explanatory diagram at the time of reading out the P phase between the time t ₂₁ and the time t ₂₂ . In FIG. 13A, q _s is the signal charge, and q _c is the channel charge of the pre-stage output transistor 541 _p to which the control signal p_out1 is applied. This point is the same in the operation description described later.

FIG. 13B is an operation explanatory diagram regarding the movement of the channel charge when the P-phase front-stage output transistor 541 _p switches from the on state to the off state in response to the control signal _{p_out1} at time t22. In FIG. 11, since the impedance of the node b is lower than the impedance of the node c, most of the channel charge q ₂ of the P-phase pre-stage output transistor 541 _p flows to the node b, and a part q _2'flows to the node c. (Q ₂ ≫ q ₂ ').

13C is an operation explanatory diagram between time t ₂₃ and time t ₂₄ .

FIG. 14A is an operation explanatory diagram regarding the movement of the channel charge when the reset transistor 543 switches from the on state to the off state in response to the node reset signal rst at time _t24 . When the reset transistor 543 shifts to the off state, a part of the channel charge q _3'flows to the output node N _out .

14B is an operation explanatory diagram between time t ₂₅ and time t ₂₆ . In response to the control signal p_out1, the P-phase pre-stage output transistor 541 _p is turned on again, and its channel charge q _c is supplied from the node b / node c / output node N _out .

In the above-mentioned operation during P-phase readout, when the capacitance value of the first capacitive element 53 _p is C _p , the error ΔV _p of the output voltage during P-phase readout is
ΔV _p = (q _3' -q ₂ ') / C _p
Will be.

FIG. 14C is an operation explanatory diagram regarding the movement of the channel charge when the D-phase front-stage output transistor 541 _d switches from the on state to the off state in response to the control signal _{d_out1} at time t26. In FIG. 11, since the impedance of the node d is lower than the impedance of the node e, most of the channel charge q ₄ of the front-stage output transistor 541 _d of the D phase flows to the node d, and a part q _4'flows to the node e. (Q ₄ ≫ q ₄ ').

Hereinafter, the operation of reading out the charge of the D phase is performed in the same manner as in the case of reading out the P phase. When the capacitance value of the second capacitance element 53 _d is C _d , the error ΔV of the output voltage at the time of reading the D phase is
ΔV _d = (q _3' -q ₄ ') / C _d
Will be.

Then, assuming C _p = C _d = C, the error ΔV of the output voltage after the correlated double sampling (CDS) processing is
ΔV = (q _{2'-q 4 '} ) / C
Will be. That is, q _3'is removed by the CDS process. As for q _{2'and q 4 '} , the absolute amount of variation is small because it is a small ratio to the total channel charge of the preceding output transistors 541 _p and 541 _d . Therefore, it is possible to suppress variations in the output voltage error after the CDS processing.

[Example 3]
The third embodiment is an example of suppressing the fixed pattern noise caused by the charge injection accompanying the switching operation at the time of sample holding by the action of the write circuit 52 and the read circuit 54. FIG. 15 shows a circuit configuration example of the sample hold circuit 50 according to the third embodiment.

(Circuit configuration example)
The sample hold circuit 50 according to the third embodiment is a specific circuit configuration example of the sample hold circuit 50 shown in FIG. 7, that is, a specific circuit configuration example of the write circuit 52 shown in FIG. 8 and a read-out shown in FIG. The circuit configuration is composed of a combination of specific circuit configuration examples of the circuit 54.

(Circuit operation example)
Subsequently, the circuit operation of the sample hold circuit 50 according to the third embodiment will be described with reference to the timing chart of FIG.

-P-phase sampling operation At time t ₃₁ , the control signal p_charge transitions from a low level to a high level, so that the first charging transistor 521 _p of the P phase is turned on. As a result, the first capacitive element 53 _p is charged based on the reset signal input from the input terminal 51. At that time, the P-phase front-stage output transistor 541 _p is in the on state, and the rear-stage output transistor 542 _p is in the off state.

At time t ₃₂ , the first charging transistor 521 _p of the P phase is turned off, and at the same time, the control signal spl and the control signal p_splen transition from low level to high level, and the sampling transistor 522 and the first write transistor are turned off. When 523 _p is turned on, the charging path is switched to the path of the sampling transistor 522 and the first write transistor 523 _p .

Next, at time t ₃₃ , the control signal spl transitions from a high level to a low level, so that the sampling transistor 522 is turned off. As a result, the amount of charge held by the first capacitive element 53 _p is determined. From time t ₁₃ to time t ₁₅ , the first capacitive element 53 _p is in the hold state. During the period from time t ₁₃ to time t ₁₅ , the potential level corresponding to the held charge amount of the first capacitive element 53 _p can be read out by the read circuit 54 in the subsequent stage.

Then, from time t ₃₃ , the P-phase is held by the first capacitive element 53 _p , and the output operation to the analog-digital conversion unit 15 in the subsequent stage is performed.

At time t ₃₄ , the control signal p_out1 that had been at a high level until then transitions from a high level to a low level, so that the previous stage output transistor 541 _p is turned off.

Next, at time t ₃₅ , the control signal p_out2 and the node reset signal rst transition from a low level to a high level. As a result, both the post-stage output transistor 542 _p and the reset transistor 543 are turned on, and the potential reset operation of the output node N _out of the read circuit 54 is performed.

This reset operation clears the history of the previous data. Then, at time t ₃₆ , the node reset signal rst transitions from the low level to the high level, and the reset transistor 543 is turned off, so that the reset operation of the output node N _out is completed.

Next, at time t ₃₇ , the control signal p_out1 transitions from a low level to a high level, so that the previous stage output transistor 541 _p is turned on. As a result, the P-phase signal held by the first capacitive element 53 _p is read out to the output terminal 55 through the post-stage output transistor 542 _p in the ON state.

After that, the analog-to-digital conversion of the P-phase signal is performed in the analog-to-digital conversion unit 15 connected to the output terminal 55.

At time t ₃₈ , the control signal p_slen of the first write transistor 523 _p transitions from a high level to a low level, so that the first write transistor 523 _p is turned off. At this point, the analog-to-digital conversion of the P-phase signal needs to be completed. Then, at time t ₃₉ , the control signal p_out2 transitions from the high level to the low level, so that the subsequent output transistor 542 _p is turned off.

-D-phase sampling operation From time t ₃₄ , the D-phase sampling operation is started. The D-phase sampling operation is performed in the same manner as the P-phase sampling operation. Then, from time t ₄₀ , the hold of the D phase by the second capacitive element 53 _d and the output operation to the analog-digital conversion unit 15 in the subsequent stage are performed in the same manner as in the case of the P phase.

(P-phase sample / hold operation)
Subsequently, the state of the sample / hold operation of the P phase in the sample hold circuit 50 according to the third embodiment will be described with reference to the operation explanatory diagram of FIG.

17A is an operation explanatory diagram at time t ₃₃ . When the sampling transistor 522 is switched from the on state to the off state, a part q ₁ of the channel charge of the sampling transistor 522 flows to the connection node a between the sampling transistor 522 and the first writing transistor 523 _p .

17B is an operation explanatory diagram at time t ₃₄ . Since the impedance of the node c in a conductive state with the output node N _out is higher than the impedance of the node b, most of the channel charge q ₂ of the P-phase pre-stage output transistor 541 _p escapes to the node b, and a part of it q ₂ 'Flows to node c (q ₂ '<< q ₂ ).

17C is an operation explanatory diagram after the time t ₃₄ (before the time t ₃₇ ).

17D is an operation explanatory diagram at time t ₃₇ . At time t ₃₇ , the control signal p_out1 transitions from a low level to a high level, and the front-stage output transistor 541 _p is turned on, so that a channel is formed again in the front-stage output transistor 541 _p .

In the sample / hold operation described above, when the capacitance value of the first capacitive element 53 _p is C _p , the error ΔV _p of the output voltage of the P phase is
ΔV _p = (q ₁ −q ₂ ′) / C _p
Will be. Similarly, the error ΔV _d of the output voltage of the D phase is
ΔV _d = (q ₁ −q ₄ ′) / C _p
Will be. Here, q _4'is the amount of charge that escapes to the output node N _out side when the D-phase front-stage output transistor 541 _d is in the off state.

Then, assuming C _p = C _d = C, the error ΔV of the output voltage after the correlated double sampling (CDS) processing is
ΔV = (q _{2'-q 4 '} ) / C
Will be. That is, q _3'is removed by the CDS process. Since q _2'and q _4'are small in proportion to the total channel charge of the pre-stage output transistors 541 _p and 541 _d , the output voltage error after CDS processing can be kept small even if the channel charge varies. can.

As described above, according to the sample hold circuit 50 according to the third embodiment, by sharing the sampling transistor 522 with the P phase and the D phase, the charge injection component of the sampling transistor 522 is removed by the subsequent CDS process. be able to. Further, by setting the state of the sampling transistor 522 and the state of the preceding output transistor 541 _p / 541 _d to be the same (both are on), the influence of the charge injection of the sampling transistor 522 can be suppressed to a small value.

Further, the charge injection of the first charging transistor 521 _p / second charging transistor 521 _d and the subsequent output transistor 542 _p / subsequent output transistor 542 _d does not give an error to the sample / hold signal and is a reset transistor. The charge injection of 543 can also be removed by the CDS process.

Further, the first capacitive element 53 _p / the second capacitive element 53 _d should be made to follow the voltage change of the input IN in advance through the charging path of the first charging transistor 521 _p / the second charging transistor 521 _d . Therefore, even if the charging path is switched from the charging path to the charging path of the sampling transistor 522 common to the P phase / D phase, the voltage fluctuation to the first capacitive element 53 _p / the second capacitive element 53 _d and the input IN does not have to occur. .. As a result, the control signal spl of the sampling transistor 522 can sample the P-phase or D-phase signal in a short period of high level.

Further, since the circuit configuration is such that the first write transistor 523 _p / the second write transistor 523 _d are separately provided for the P phase and the D phase, the sample and hold of the P phase is controlled by a predetermined timing. It is possible to prevent signal interference between the D phase hold (sample) and the D phase hold (sample).

<Modification example>
Although the technique according to the present disclosure has been described above based on the preferred embodiment, the technique according to the present disclosure is not limited to the embodiment. The configuration and structure of the image pickup apparatus described in the above embodiment are examples, and can be changed as appropriate.

<Application example>
As shown in FIG. 18, for example, the image pickup apparatus according to the present embodiment described above can be used in various devices for sensing light such as visible light, infrared light, ultraviolet light, and X-ray. Specific examples of various devices are listed below.

・ Devices that take images for viewing, such as digital cameras and portable devices with camera functions. ・ For safe driving such as automatic stop and recognition of the driver's condition, in front of the car Devices used for traffic, such as in-vehicle sensors that capture images of the rear, surroundings, and interior of vehicles, surveillance cameras that monitor traveling vehicles and roads, and distance measuring sensors that measure distance between vehicles. Equipment used in home appliances such as TVs, refrigerators, and air conditioners to take pictures and operate the equipment according to the gestures ・ Endoscopes, devices that perform angiography by receiving infrared light, etc. Equipment used for medical and healthcare purposes ・ Equipment used for security such as surveillance cameras for crime prevention and cameras for person authentication ・ Skin measuring instruments for taking pictures of the skin and taking pictures of the scalp Equipment used for beauty such as microscopes ・ Equipment used for sports such as action cameras and wearable cameras for sports applications ・ Camera for monitoring the condition of fields and crops, etc. Equipment used for agriculture

<Application example of the technique according to the present disclosure>
The techniques according to the present disclosure can be applied to various products. A more specific application example will be described below.

[Electronic device of the present disclosure]
Here, a case where it is applied to an image pickup system such as a digital still camera or a video camera, a portable terminal device having an image pickup function such as a mobile phone, and an electronic device such as a copying machine using an image pickup device for an image reading unit will be described.

(Example of imaging system)
FIG. 19 is a block diagram showing a configuration example of an imaging system which is an example of the electronic device of the present disclosure.

As shown in FIG. 19, the image pickup system 100 according to this example includes an image pickup optical system 101 including a lens group and the like, an image pickup unit 102, a DSP (Digital Signal Processor) circuit 103, a frame memory 104, a display device 105, and a recording device 106. , Operation system 107, power supply system 108, and the like. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via the bus line 109.

The image pickup optical system 101 captures incident light (image light) from the subject and forms an image on the image pickup surface of the image pickup unit 102. The image pickup unit 102 converts the amount of incident light imaged on the image pickup surface by the optical system 101 into an electric signal in pixel units and outputs it as a pixel signal. The DSP circuit 103 performs general camera signal processing, for example, white balance processing, demosaic processing, gamma correction processing, and the like.

The frame memory 104 is appropriately used for storing data in the process of signal processing in the DSP circuit 103. The display device 105 comprises a panel-type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image pickup unit 102. The recording device 106 records the moving image or still image captured by the imaging unit 102 on a portable semiconductor memory, an optical disk, a recording medium such as an HDD (Hard Disk Drive), or the like.

The operation system 107 issues operation commands for various functions of the image pickup apparatus 100 under the operation of the user. The power supply system 108 appropriately supplies various power sources that serve as operating power sources for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.

In the image pickup system 100 having the above configuration, as the image pickup unit 102, an image pickup device provided with a column-parallel analog-to-digital conversion unit according to the above-described embodiment can be used. According to the image pickup apparatus, it is possible to suppress the fixed pattern noise of the pixel array by reducing the variation in charge injection due to the switching operation at the time of sample holding. Therefore, vertical streaks caused by the fixed pattern noise of the pixel row do not appear on the captured image, so that a high-quality captured image can be obtained.

[Application example to moving objects]
The technique according to the present disclosure (the present technique) can be applied to various products. For example, the technology according to the present disclosure is any kind of movement such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, a construction machine, and an agricultural machine (tractor). It may be realized as an image pickup device mounted on a body.

FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technique according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001. In the example shown in FIG. 20, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 has a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, turn signals or fog lamps. In this case, the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches. The body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.

The outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image pickup unit 12031 is connected to the vehicle outside information detection unit 12030. The vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The out-of-vehicle information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or a character on the road surface based on the received image.

The image pickup unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received. The image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the image pickup unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects the in-vehicle information. For example, a driver state detection unit 12041 that detects a driver's state is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether or not the driver has fallen asleep.

The microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.

Further, the microcomputer 12051 controls the driving force generating device, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform coordinated control for the purpose of automatic driving that runs autonomously without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.

The audio image output unit 12052 transmits an output signal of at least one of audio and image to an output device capable of visually or audibly notifying information to the passenger or the outside of the vehicle. In the example of FIG. 20, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

FIG. 21 is a diagram showing an example of the installation position of the imaging unit 12031.

In FIG. 21, the vehicle 12100 has image pickup units 12101, 12102, 12103, 12104, 12105 as image pickup units 12031.

The image pickup units 12101, 12102, 12103, 12104, 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The image pickup unit 12101 provided on the front nose and the image pickup section 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The image pickup units 12102 and 12103 provided in the side mirror mainly acquire images of the side of the vehicle 12100. The image pickup unit 12104 provided in the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The images in front acquired by the image pickup units 12101 and 12105 are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note that FIG. 21 shows an example of the shooting range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging range of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates the imaging range. The imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 can be obtained.

At least one of the image pickup units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image pickup units 12101 to 12104 may be a stereo camera including a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.

For example, the microcomputer 12051 has a distance to each three-dimensional object within the imaging range 12111 to 12114 based on the distance information obtained from the imaging unit 12101 to 12104, and a temporal change of this distance (relative speed with respect to the vehicle 12100). By obtaining can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like that autonomously travels without relying on the driver's operation.

For example, the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles, and other three-dimensional objects based on the distance information obtained from the image pickup units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.

At least one of the image pickup units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging unit 12101 to 12104. Such recognition of a pedestrian is, for example, a procedure for extracting feature points in an image captured by an image pickup unit 12101 to 12104 as an infrared camera, and a pattern matching process for a series of feature points showing the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine. When the microcomputer 12051 determines that a pedestrian is present in the captured image of the image pickup unit 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 determines the square contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

The above is an example of a vehicle control system to which the technique according to the present disclosure can be applied. The technique according to the present disclosure can be applied to, for example, the image pickup unit 12031 among the configurations described above. Then, when the imaging unit 12031 or the like includes a column-parallel analog-digital conversion unit, by applying the technique according to the present disclosure to the column-parallel analog-digital conversion unit, charging associated with the switching operation during sample holding is performed. By reducing the variation in injection, fixed pattern noise of the pixel array can be suppressed. Therefore, vertical streaks caused by the fixed pattern noise of the pixel row do not appear on the captured image, so that a high-quality captured image can be obtained.

<Structure that can be taken by this disclosure>
The present disclosure may also have the following configuration.

<< A. Imaging device according to the first aspect >>
[A-01] A pixel array unit in which a plurality of pixels including a photoelectric conversion unit are arranged in a matrix, and a pixel array unit.
It is provided corresponding to the pixel sequence of the pixel array unit, and is equipped with a plurality of sample hold circuits that sample-hold the pixel signal output from the pixel through the signal line.
The sample hold circuit is
Input terminal for inputting reset signal and data signal output from pixel,
A write circuit that writes the reset signal and data signal input from the input terminal,
A first capacitive element that holds the reset signal written by the write circuit,
A second capacitive element that holds the data signal written by the write circuit,
A reset signal held in the first capacitive element, a read circuit for reading a data signal held in the second capacitive element, and a read circuit.
Equipped with an output terminal that outputs the reset signal and data signal read by the read circuit.
The writing circuit is
A first charging transistor connected between an input terminal and a first capacitive element,
A second charging transistor connected between the input terminal and the second capacitive element,
Sampling transistor that samples the reset signal and data signal input from the input terminal,
A first write transistor connected between the sampling transistor and the first capacitive element, as well as
It has a second write transistor connected between the sampling transistor and the second capacitive element.
Imaging device.
[A-02] The first charging transistor is turned on, the first capacitive element is charged based on the reset signal, the first charging transistor is turned off, and then the charging path of the first capacitive element is set. , Switching to the path of the sampling transistor and the first write transistor,
After that, the second charging transistor is turned on to charge the second capacitive element based on the reset signal, the second charging transistor is turned off, and then the charging path of the second capacitive element is sampled. Switch to the transistor and second write transistor path,
The image pickup apparatus according to the above [A-01].
[A-03] In the path of the sampling transistor and the first write transistor, the reset signal is sampled by the sampling transistor and held by the first capacitive element via the first write transistor.
In the path of the sampling transistor and the second write transistor, the reset signal is sampled by the sampling transistor and held by the second capacitive element via the second write transistor.
The image pickup apparatus according to the above [A-02].

<< B. Imaging device according to the second aspect >>
[B-01] A pixel array unit in which a plurality of pixels including a photoelectric conversion unit are arranged in a matrix, and a pixel array unit.
It is provided corresponding to the pixel sequence of the pixel array unit, and is equipped with a plurality of sample hold circuits that sample-hold the pixel signal output from the pixel through the signal line.
The sample hold circuit is
Input terminal for inputting reset signal and data signal output from pixel,
A write circuit that writes the reset signal and data signal input from the input terminal,
A first capacitive element that holds the reset signal written by the write circuit,
A second capacitive element that holds the data signal written by the write circuit,
A reset signal held in the first capacitive element, a read circuit for reading a data signal held in the second capacitive element, and a read circuit.
Equipped with an output terminal that outputs the reset signal and data signal read by the read circuit.
The read circuit is
A first output circuit connected between the first capacitive element and the output terminal,
A second output circuit connected between the second capacitive element and the output terminal, and
It has a reset transistor that resets the potential of each output node of the first output circuit and the second output circuit.
The first output circuit and the second output circuit are a front-stage output transistor and a rear-stage output transistor connected in series between the first capacitive element and the output node and between the second capacitive element and the output node, respectively. Has an output transistor,
Imaging device.
[B-02] In the first output circuit and the second output circuit,
During the sample hold period of the reset signal and data signal by the write circuit, the pre-stage output transistor that is in the on state is turned off.
After that, the reset transistor and the subsequent output transistor are turned on to reset the potential of the output node.
The image pickup apparatus according to the above [B-01].
[B-03] In the first output circuit and the second output circuit,
After resetting the potential of the output node, the pre-stage output transistor is turned on, the reset signal held in the first capacitive element and the data signal held in the second capacitive element are read out, and then the post-stage output transistor is read. To turn off,
The image pickup apparatus according to the above [B-02].

<< C. Imaging device according to the third aspect >>
[C-01] A pixel array unit in which a plurality of pixels including a photoelectric conversion unit are arranged in a matrix, and a pixel array unit.
It is provided corresponding to the pixel sequence of the pixel array unit, and is equipped with a plurality of sample hold circuits that sample-hold the pixel signal output from the pixel through the signal line.
The sample hold circuit is
Input terminal for inputting reset signal and data signal output from pixel,
A write circuit that writes the reset signal and data signal input from the input terminal,
A first capacitive element that holds the reset signal written by the write circuit,
A second capacitive element that holds the data signal written by the write circuit,
A reset signal held in the first capacitive element, a read circuit for reading a data signal held in the second capacitive element, and a read circuit.
Equipped with an output terminal that outputs the reset signal and data signal read by the read circuit.
The writing circuit is
A first charging transistor connected between an input terminal and a first capacitive element,
A second charging transistor connected between the input terminal and the second capacitive element,
Sampling transistor that samples the reset signal and data signal input from the input terminal,
A first write transistor connected between the sampling transistor and the first capacitive element, as well as
It has a second write transistor connected between the sampling transistor and the second capacitive element.
The read circuit is
A first output circuit connected between the first capacitive element and the output terminal,
A second output circuit connected between the second capacitive element and the output terminal, and
It has a reset transistor that resets the potential of each output node of the first output circuit and the second output circuit.
The first output circuit and the second output circuit are a front-stage output transistor and a rear-stage output transistor connected in series between the first capacitive element and the output node and between the second capacitive element and the output node, respectively. Has an output transistor,
Imaging device.
[C-02] The first charging transistor is turned on, the first capacitive element is charged based on the reset signal, the first charging transistor is turned off, and then the charging path of the first capacitive element is set. , Switching to the path of the sampling transistor and the first write transistor,
After that, the second charging transistor is turned on to charge the second capacitive element based on the reset signal, the second charging transistor is turned off, and then the charging path of the second capacitive element is sampled. Switch to the transistor and second write transistor path,
The image pickup apparatus according to the above [C-01].
[C-03] In the path of the sampling transistor and the first write transistor, the reset signal is sampled by the sampling transistor and held by the first capacitive element via the first write transistor.
In the path of the sampling transistor and the second write transistor, the reset signal is sampled by the sampling transistor and held by the second capacitive element via the second write transistor.
The image pickup apparatus according to the above [C-02].
[C-04] In the first output circuit and the second output circuit,
During the sample hold period of the reset signal and data signal by the write circuit, the pre-stage output transistor that is in the on state is turned off.
After that, the reset transistor and the subsequent output transistor are turned on to reset the potential of the output node.
The image pickup apparatus according to the above [C-01].
[C-05] In the first output circuit and the second output circuit,
After resetting the potential of the output node, the pre-stage output transistor is turned on, the reset signal held in the first capacitive element and the data signal held in the second capacitive element are read out, and then the post-stage output transistor is read. To turn off,
The image pickup apparatus according to the above [C-04].

<< D. Electronic equipment ≫
[D-01] A pixel array unit in which a plurality of pixels including a photoelectric conversion unit are arranged in a matrix, and a pixel array unit.
It is provided corresponding to the pixel sequence of the pixel array unit, and is equipped with a plurality of sample hold circuits that sample-hold the pixel signal output from the pixel through the signal line.
The sample hold circuit is
Input terminal for inputting reset signal and data signal output from pixel,
A write circuit that writes the reset signal and data signal input from the input terminal,
A first capacitive element that holds the reset signal written by the write circuit,
A second capacitive element that holds the data signal written by the write circuit,
A reset signal held in the first capacitive element, a read circuit for reading a data signal held in the second capacitive element, and a read circuit.
Equipped with an output terminal that outputs the reset signal and data signal read by the read circuit.
The writing circuit is
A first charging transistor connected between an input terminal and a first capacitive element,
A second charging transistor connected between the input terminal and the second capacitive element,
Sampling transistor that samples the reset signal and data signal input from the input terminal,
A first write transistor connected between the sampling transistor and the first capacitive element, as well as
It has a second write transistor connected between the sampling transistor and the second capacitive element.
An electronic device equipped with an image pickup device.
[D-02] The read circuit is
A first output circuit connected between the first capacitive element and the output terminal,
A second output circuit connected between the second capacitive element and the output terminal, and
It has a reset transistor that resets the potential of each output node of the first output circuit and the second output circuit.
The first output circuit and the second output circuit are a front-stage output transistor and a rear-stage output transistor connected in series between the first capacitive element and the output node and between the second capacitive element and the output node, respectively. Has an output transistor,
The electronic device according to the above [D-01].

1 ... CMOS image sensor (imaging device), 20 ... pixel (pixel circuit), 11 ... pixel array section, 12 ... row selection section, 13 ... load MOS section, 14 ... Sample hold unit, 15 ... analog-to-digital conversion unit, 16 ... memory unit, 17 ... data processing unit, 18 ... output unit, 19 ... timing control unit, 21 ... photodiode (Photoelectric conversion unit), 22 ... transfer transistor, 23 ... reset transistor, 24 ... amplification transistor, 25 ... selection transistor, 31 (31 ₁ to 31 _m ) ... pixel drive line, 32 (32 ₁ to 32 _n ) ・ ・ ・ Vertical signal line, 50 ・ ・ ・ Sample hold circuit, 51 ・ ・ ・ Input terminal, 52 ・ ・ ・ Write circuit, 53 _p・ ・ ・ First capacitive element, 53 _d・・ ・ Second capacitive element, 54 ・ ・ ・ read circuit, 55 ・ ・ ・ output terminal

Claims (13)

A pixel array unit in which a plurality of pixels including a photoelectric conversion unit are arranged in a matrix, and a pixel array unit.
It is provided corresponding to the pixel sequence of the pixel array unit, and is equipped with a plurality of sample hold circuits that sample-hold the pixel signal output from the pixel through the signal line.
The sample hold circuit is
Input terminal for inputting reset signal and data signal output from pixel,
A write circuit that writes the reset signal and data signal input from the input terminal,
A first capacitive element that holds the reset signal written by the write circuit,
A second capacitive element that holds the data signal written by the write circuit,
A reset signal held in the first capacitive element, a read circuit for reading a data signal held in the second capacitive element, and a read circuit.
Equipped with an output terminal that outputs the reset signal and data signal read by the read circuit.
The writing circuit is
A first charging transistor connected between an input terminal and a first capacitive element,
A second charging transistor connected between the input terminal and the second capacitive element,
Sampling transistor that samples the reset signal and data signal input from the input terminal,
A first write transistor connected between the sampling transistor and the first capacitive element, as well as
It has a second write transistor connected between the sampling transistor and the second capacitive element.
Imaging device. After turning on the first charging transistor to charge the first capacitive element based on the reset signal and turning off the first charging transistor, the charging path of the first capacitive element is set to the sampling transistor and the first capacitive element. Switch to the path of 1 write transistor,
After that, the second charging transistor is turned on to charge the second capacitive element based on the reset signal, the second charging transistor is turned off, and then the charging path of the second capacitive element is sampled. Switch to the transistor and second write transistor path,
The imaging device according to claim 1. In the path of the sampling transistor and the first write transistor, the reset signal is sampled by the sampling transistor and held by the first capacitive element via the first write transistor.
In the path of the sampling transistor and the second write transistor, the reset signal is sampled by the sampling transistor and held by the second capacitive element via the second write transistor.
The imaging device according to claim 2. A pixel array unit in which a plurality of pixels including a photoelectric conversion unit are arranged in a matrix, and a pixel array unit.
It is provided corresponding to the pixel sequence of the pixel array unit, and is equipped with a plurality of sample hold circuits that sample-hold the pixel signal output from the pixel through the signal line.
The sample hold circuit is
Input terminal for inputting reset signal and data signal output from pixel,
A write circuit that writes the reset signal and data signal input from the input terminal,
A first capacitive element that holds the reset signal written by the write circuit,
A second capacitive element that holds the data signal written by the write circuit,
A reset signal held in the first capacitive element, a read circuit for reading a data signal held in the second capacitive element, and a read circuit.
Equipped with an output terminal that outputs the reset signal and data signal read by the read circuit.
The read circuit is
A first output circuit connected between the first capacitive element and the output terminal,
A second output circuit connected between the second capacitive element and the output terminal, and
It has a reset transistor that resets the potential of each output node of the first output circuit and the second output circuit.
The first output circuit and the second output circuit are a front-stage output transistor and a rear-stage output transistor connected in series between the first capacitive element and the output node and between the second capacitive element and the output node, respectively. Has an output transistor,
Imaging device. In the first output circuit and the second output circuit,
During the sample hold period of the reset signal and data signal by the write circuit, the pre-stage output transistor that is in the on state is turned off.
After that, the reset transistor and the subsequent output transistor are turned on to reset the potential of the output node.
The imaging device according to claim 4. In the first output circuit and the second output circuit,
After resetting the potential of the output node, the pre-stage output transistor is turned on, the reset signal held in the first capacitive element and the data signal held in the second capacitive element are read out, and then the post-stage output transistor is read. To turn off,
The imaging device according to claim 5. A pixel array unit in which a plurality of pixels including a photoelectric conversion unit are arranged in a matrix, and a pixel array unit.
It is provided corresponding to the pixel array of the pixel array unit, and is equipped with a plurality of sample hold circuits that sample-hold the pixel signal output from the pixel through the signal line.
The sample hold circuit is
Input terminal for inputting reset signal and data signal output from pixel,
A write circuit that writes the reset signal and data signal input from the input terminal,
A first capacitive element that holds the reset signal written by the write circuit,
A second capacitive element that holds the data signal written by the write circuit,
A reset signal held in the first capacitive element, a read circuit for reading a data signal held in the second capacitive element, and a read circuit.
Equipped with an output terminal that outputs the reset signal and data signal read by the read circuit.
The writing circuit is
A first charging transistor connected between an input terminal and a first capacitive element,
A second charging transistor connected between the input terminal and the second capacitive element,
Sampling transistor that samples the reset signal and data signal input from the input terminal,
A first write transistor connected between the sampling transistor and the first capacitive element, as well as
It has a second write transistor connected between the sampling transistor and the second capacitive element.
The read circuit is
A first output circuit connected between the first capacitive element and the output terminal,
A second output circuit connected between the second capacitive element and the output terminal, and
It has a reset transistor that resets the potential of each output node of the first output circuit and the second output circuit.
The first output circuit and the second output circuit are a front-stage output transistor and a rear-stage output transistor connected in series between the first capacitive element and the output node and between the second capacitive element and the output node, respectively. Has an output transistor,
Imaging device. After turning on the first charging transistor to charge the first capacitive element based on the reset signal and turning off the first charging transistor, the charging path of the first capacitive element is set to the sampling transistor and the first capacitive element. Switch to the path of 1 write transistor,
After that, the second charging transistor is turned on to charge the second capacitive element based on the reset signal, the second charging transistor is turned off, and then the charging path of the second capacitive element is sampled. Switch to the transistor and second write transistor path,
The imaging device according to claim 7. In the path of the sampling transistor and the first write transistor, the reset signal is sampled by the sampling transistor and held by the first capacitive element via the first write transistor.
In the path of the sampling transistor and the second write transistor, the reset signal is sampled by the sampling transistor and held by the second capacitive element via the second write transistor.
The imaging device according to claim 8. In the first output circuit and the second output circuit,
During the sample hold period of the reset signal and data signal by the write circuit, the pre-stage output transistor that is in the on state is turned off.
After that, the reset transistor and the subsequent output transistor are turned on to reset the potential of the output node.
The imaging device according to claim 7. In the first output circuit and the second output circuit,
After resetting the potential of the output node, the pre-stage output transistor is turned on, the reset signal held in the first capacitive element and the data signal held in the second capacitive element are read out, and then the post-stage output transistor is read. To turn off,
The imaging device according to claim 10. A pixel array unit in which a plurality of pixels including a photoelectric conversion unit are arranged in a matrix, and a pixel array unit.
It is provided corresponding to the pixel sequence of the pixel array unit, and is equipped with a plurality of sample hold circuits that sample-hold the pixel signal output from the pixel through the signal line.
The sample hold circuit is
Input terminal for inputting reset signal and data signal output from pixel,
A write circuit that writes the reset signal and data signal input from the input terminal,
A first capacitive element that holds the reset signal written by the write circuit,
A second capacitive element that holds the data signal written by the write circuit,
A reset signal held in the first capacitive element, a read circuit for reading a data signal held in the second capacitive element, and a read circuit.
Equipped with an output terminal that outputs the reset signal and data signal read by the read circuit.
The writing circuit is
A first charging transistor connected between an input terminal and a first capacitive element,
A second charging transistor connected between the input terminal and the second capacitive element,
Sampling transistor that samples the reset signal and data signal input from the input terminal,
A first write transistor connected between the sampling transistor and the first capacitive element, as well as
It has a second write transistor connected between the sampling transistor and the second capacitive element.
An electronic device equipped with an image pickup device. The read circuit is
A first output circuit connected between the first capacitive element and the output terminal,
A second output circuit connected between the second capacitive element and the output terminal, and
It has a reset transistor that resets the potential of each output node of the first output circuit and the second output circuit.
The first output circuit and the second output circuit are a front-stage output transistor and a rear-stage output transistor connected in series between the first capacitive element and the output node and between the second capacitive element and the output node, respectively. Has an output transistor,
The electronic device according to claim 12.

Images