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WO2021164602A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021164602A1
WO2021164602A1 PCT/CN2021/075887 CN2021075887W WO2021164602A1 WO 2021164602 A1 WO2021164602 A1 WO 2021164602A1 CN 2021075887 W CN2021075887 W CN 2021075887W WO 2021164602 A1 WO2021164602 A1 WO 2021164602A1
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WIPO (PCT)
Prior art keywords
light
layer
display
display area
area
Prior art date
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PCT/CN2021/075887
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English (en)
French (fr)
Inventor
罗程远
张小磊
李晓虎
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/607,813 priority Critical patent/US20220238614A1/en
Publication of WO2021164602A1 publication Critical patent/WO2021164602A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80524—Transparent cathodes, e.g. comprising thin metal layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/822—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/828—Transparent cathodes, e.g. comprising thin metal layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the embodiments of the present disclosure relate to a display substrate, a preparation method thereof, and a display device.
  • a display area with higher light transmittance is set on the screen, and components such as a front camera, light sensor, etc. are set below the display area.
  • At least some embodiments of the present disclosure provide a display substrate including a first display area provided on the substrate, the first display area including a plurality of light-emitting areas and a plurality of light-transmitting areas, the plurality of light-emitting areas Arranged in an array, the plurality of light-transmitting regions are arranged in an array, and the plurality of light-emitting regions and the plurality of light-transmitting regions are arranged at intervals;
  • Each of the light-emitting areas includes:
  • a conductive layer disposed in the light-emitting area
  • the cathode block is arranged on the conductive layer
  • the first display area further includes an overlap portion, the overlap portion is disposed in the light-transmitting area and is located on the same layer as the conductive layer and has the same material, and is configured to electrically connect two adjacent light-emitting areas Cathode block.
  • the light-emitting area includes a pixel circuit layer, and the pixel circuit layer includes the conductive layer.
  • the pixel circuit layer includes a thin film transistor, the thin film transistor includes a gate electrode, and the conductive layer is the gate electrode.
  • the pixel circuit layer includes a thin film transistor, the thin film transistor includes a source electrode, and the conductive layer is the source electrode.
  • the pixel circuit layer includes a capacitor, the capacitor includes a first electrode plate and a second electrode plate, the second electrode plate is located above the first electrode plate, and the conductive layer Is the second plate.
  • the light-emitting area further includes an anode and an organic light-emitting material, the anode is disposed on the pixel electrode, and the organic light-emitting material is disposed between the anode and the cathode block,
  • the conductive layer is the anode.
  • the orthographic projection of the overlapping portion on the substrate overlaps the orthographic projection of the cathode block electrically connected to the overlapping portion on the substrate.
  • the overlapping part of the orthographic projection of the overlapping portion on the substrate and the orthographic projection of the cathode block electrically connected to the overlapping portion on the substrate is in the first
  • the size range in the direction is [500 ⁇ m, 1000 ⁇ m], wherein the first direction refers to a direction along the light-transmitting area to the light-emitting area.
  • the ratio of the total area of the light-emitting area to the total area of the light-transmitting area ranges from 1:1 to 1:2.
  • each of the plurality of light-transmitting regions is provided with at least two overlapping portions, and along the extending direction of the light-transmitting regions, the at least two overlapping portions are parallel to each other. Arranged in parallel in the direction of the first direction.
  • the display substrate further includes a second display area, and the light transmittance of the second display area is lower than the light transmittance of the first display area.
  • At least one embodiment of the present disclosure provides a display device including the above-mentioned display substrate.
  • At least one embodiment of the present disclosure provides a method for manufacturing a display substrate.
  • the display substrate includes a first display area; the first display area includes a plurality of light-emitting areas and a plurality of light-transmitting areas, and the The regions are arranged in an array, the plurality of light-transmitting regions are arranged in an array, and the plurality of light-emitting regions and the plurality of light-transmitting regions are arranged at intervals;
  • the preparation method of the display substrate includes:
  • a conductive layer located in each of the plurality of light-emitting regions and an overlapping portion located in each of the plurality of light-transmitting regions are formed on the substrate, the conductive layer and the overlapping portion Formed in the same process step;
  • a cathode block is formed on the conductive layer, the cathode block covers the light-emitting area, and the cathode blocks of two adjacent light-emitting areas pass through the overlap portion in the light-transmitting area between the two adjacent light-emitting areas Electric connection.
  • the display substrate includes a pixel circuit layer
  • the pixel circuit layer includes a thin film transistor
  • the thin film transistor includes a gate electrode
  • the conductive layer is the gate electrode
  • the pixel circuit further includes a capacitor, the capacitor includes a first electrode plate and a second electrode plate, and the first electrode plate and the conductive layer are formed in the same process step; After the conductive layer and the lap portion are formed on the substrate, the preparation method further includes:
  • a pixel defining layer covering the first display area is formed on the anode, and the pixel defining layer is etched to expose the overlapping portion.
  • the pixel circuit further includes a capacitor, the capacitor includes a first electrode plate and a second electrode plate, and the first electrode plate and the conductive layer are formed in the same process step; After the conductive layer and the lap portion are formed on the substrate, the preparation method further includes:
  • the pixel defining layer, the planarization layer, the interlayer dielectric layer, and the capacitor insulating layer are simultaneously etched to expose the overlapped portion.
  • the forming a cathode layer on the conductive layer includes:
  • the mask including openings corresponding to the plurality of cathode blocks
  • the cathode block is formed through the opening of the mask.
  • the orthographic projection of the opening on the substrate, and the overlap portion adjacent to the opening is in the The size range of the overlapped portion of the orthographic projection on the substrate is [500 ⁇ m, 1000 ⁇ m].
  • Fig. 1 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure
  • Fig. 2 is a partial cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 3 is a partial cross-sectional view of a display substrate according to another exemplary embodiment of the present disclosure.
  • FIG. 4 is a partial cross-sectional view of a display substrate according to still another exemplary embodiment of the present disclosure.
  • FIG. 5 is a partial cross-sectional view of a display substrate according to another exemplary embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a manufacturing method of a display substrate according to an exemplary embodiment of the present disclosure
  • Fig. 7 is a schematic diagram of using a mask to evaporate an organic light-emitting material according to an exemplary embodiment of the present disclosure.
  • Fig. 8 is a schematic diagram of using a mask to evaporate a cathode according to an exemplary embodiment of the present disclosure.
  • first, second, third, etc. may be used in this disclosure to describe various information, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as second information, and similarly, the second information may also be referred to as first information.
  • word “if” as used herein can be interpreted as "when” or “when” or "in response to determination”.
  • the direction from the substrate to the conductive layer is defined as up, and the direction from the conductive layer to the substrate is defined as down, so as to determine the up and down directions. It is easy to understand that different ways of defining directions will not affect the actual operation content of the process and the actual form of the product.
  • the display substrate 100 includes a first display area 101 and a second display area 102, and the light transmittance of the first display area 101 is greater than the light transmittance of the second display area 102.
  • the first display area 101 includes a plurality of light-emitting areas 1011 and a plurality of light-transmitting areas 1012.
  • the light-emitting areas 1011 are arranged in an array, and the light-transmitting areas 1012 are arranged in an array.
  • the light-emitting areas and the plurality of light-transmitting areas are arranged at intervals.
  • the first display area 101 can be used to display parts of the screen that do not require high-quality display effects, such as icons indicating power and time
  • the second display area 102 can be used to display images or videos.
  • a plurality of sub-pixels 110 are respectively provided in the second display area 102 and the light-emitting area 1011, so that the first display area 101 and the second display area 102 can display.
  • Sub-pixels are not provided in the plurality of light-transmitting areas 1012 of the first display area 101, so the light transmittance of the first display area 101 is relatively high, so that the first display area 101 enters the area provided below the first display area 101.
  • the front camera, infrared lens, light sensor and other photosensitive elements have a large amount of external light, which can ensure the normal operation of the photosensitive elements.
  • the sub-pixel 110 includes an anode 113, an organic light-emitting material 112 on the anode 113, and a cathode 111 on the organic light-emitting material 112.
  • the cathode 111 of each sub-pixel in the second display area 102 is a connected cathode block
  • the cathode 111 of each sub-pixel in the light-emitting area 1011 can be a connected cathode block
  • the cathode blocks of adjacent light-emitting areas 1011 can be electrically connected.
  • the cathode block of the second display area 102 and the cathode block of the light-emitting area 1011 can be connected into one piece.
  • the display substrate 100 includes a substrate 10, a conductive layer 20 and an overlap portion 30 disposed on the substrate 10, and a cathode layer disposed on the conductive layer 20.
  • the conductive layer 20 is located in the second display area 102 and the light-emitting area 1011, the overlapping portion 30 is located in the light-transmitting area 1012, and the area of the overlapping portion 30 is smaller than the area of the light-transmitting area 1012.
  • the conductive layer 20 and the overlapping portion 30 are located on the same layer and have the same material.
  • the cathode layer includes a plurality of cathode blocks located in the first display area and the second display area. The cathode blocks cover the second display area 102 or cover the light-emitting area 1011.
  • the cathodes of two adjacent light-emitting areas 1011 are The blocks are electrically connected through the overlap portion 30 between the two light-emitting areas 1011.
  • the display substrate 100 provided by the embodiment of the present disclosure includes a first display area 101 and a second display area 102.
  • the light transmittance of the first display area 101 is greater than the light transmittance of the second display area 102, and the photosensitive element Set under the first display area 101, a full-screen display of the display substrate can be realized under the premise of ensuring the normal operation of the photosensitive element.
  • the overlapping portion 30 electrically connects the cathode blocks of two adjacent light-emitting areas, which can ensure the normal display of the display substrate 100; and the arrangement of the overlapping portion 30 can reduce the transparency.
  • the area of the cathode block in the light area 1012 helps to increase the light transmittance of the first display area 101.
  • the conductive layer 20 and the overlapping portion 30 of the display substrate 100 are located in the same layer and the materials are the same.
  • the conductive layer 20 and the overlapping portion 30 can be formed in the same process step, so the formation of the overlapping portion 30 does not increase the mask.
  • the number of plates helps reduce the complexity of the preparation process.
  • that the conductive layer 20 and the overlapping portion 30 are formed in the same process step means that the conductive layer 20 and the overlapping portion 30 are formed at the same time in one patterning process.
  • the display substrate 100 includes a pixel circuit layer 27, and the pixel circuit layer 27 includes the conductive layer 20.
  • the pixel circuit layer is disposed on the substrate 10 and is located between the sub-pixel 110 and the substrate 10.
  • the pixel circuit layer 27 includes a pixel circuit for driving the sub-pixel 110.
  • the pixel circuit includes a thin film transistor 25 and a capacitor 26.
  • the thin film transistor 25 includes a source electrode 251, a drain electrode 252, a gate electrode 253, and a semiconductor layer 254.
  • the capacitor 26 includes a first electrode plate 261 and a second electrode plate 262 located on the first electrode plate 261 and insulated and spaced apart from the first electrode plate 261. Wherein, the first electrode plate 261 and the gate electrode 253 can be located in the same layer, and both can be formed in the same process step.
  • the conductive layer 20 may be an electrode in a thin film transistor, or the conductive layer 20 may be the second plate 262 of the capacitor 26.
  • the display substrate 100 may further include a buffer layer 41 disposed between the substrate 10 and the semiconductor layer 254.
  • the pixel circuit layer 27 may also include a gate insulating layer 42 disposed between the semiconductor layer 254 and the gate electrode 253, a capacitive insulating layer 43 disposed between the first plate 261 and the second plate 262, and a gate insulating layer 43 disposed between the second plate 261 and the second plate 262.
  • the interlayer dielectric layer 44 between the electrode plate 262 and the source electrode 251 and the planarization layer 45 disposed between the source electrode 251 and the anode 113.
  • the display substrate 100 may further include a pixel defining layer 46 disposed on the planarization layer 45.
  • the pixel defining layer 46 is provided with pixel openings corresponding to the anode 113 one-to-one, the pixel openings expose a part of the corresponding anode 113, and the organic light-emitting material 112 is provided in the pixel openings.
  • the orthographic projection of the film layer of the pixel circuit layer 27 on the overlap portion 30 on the substrate 10 and the orthographic projection of the overlap portion 30 on the substrate 10 No overlap; the orthographic projection of the anode 113 on the substrate 10 and the orthographic projection of the overlap portion 30 on the substrate 10 do not overlap; the organic light-emitting material 112 is on the substrate 10
  • the orthographic projection of and the orthographic projection of the overlapping portion 30 on the substrate 10 do not overlap.
  • the conductive layer 20 is the gate electrode 253 of the thin film transistor 25, that is, the overlap portion 30 and the gate electrode 253 are located in the same layer, and the two materials are the same.
  • the portions of the capacitor insulating layer 43, the interlayer dielectric layer 44, the planarization layer 45, and the pixel defining layer 46 above the overlapping portion 30 are etched away, and the overlapping portion 30 is exposed, so that the cathode block of the light-emitting area 1011 is adjacent to the
  • the overlap portion 30 is in direct contact, and the cathode blocks of two adjacent light-emitting regions 1011 are electrically connected through the overlap portion 30.
  • the material of the gate electrode 253 may be Mo, Nd, Al, and the material of the overlap portion 30 is the same as that of the gate electrode 253, so that the overlap portion 30 has better conductivity.
  • the thickness range of the gate electrode 253 is generally [560nm, 770nm]
  • the thickness range of the source electrode 251 and the drain electrode 252 is generally [380nm, 580nm]
  • the thickness range of the second plate 262 of the capacitor 26 is generally [350nm, 550nm] . It can be seen that the thickness of the gate electrode 253 is greater than the thickness of the source electrode 251 and the thickness of the second electrode plate 262.
  • the overlap portion 30 and the gate electrode 253 are formed at the same time, the thickness of the overlap portion 30 is larger and the resistance is lower. It can be seen from the above that when the conductive layer 20 is the gate electrode 253, the lap portion 30 has better conductivity and lower resistance, which can make the display substrate 100 display a smaller voltage drop and lower power consumption.
  • the conductive layer 20 is the second plate 262 of the capacitor 26, that is, the overlap portion 30 and the second plate 262 of the capacitor 26 are located on the same layer. , And the two materials are the same.
  • the portions of the interlayer dielectric layer 44, the planarization layer 45, and the pixel defining layer 46 above the overlap portion 30 are etched away, and the overlap portion 30 is exposed, so that the cathode block of the light-emitting area 1011 is directly connected to the adjacent overlap portion 30 In contact, the cathode blocks of two adjacent light-emitting regions 1011 are electrically connected by the overlap portion 30.
  • the material of the second electrode plate 262 of the capacitor 26 is usually Mo, Ti, or Cu, which has good conductivity.
  • the material of the overlap portion 30 and the second electrode plate 262 are the same, so that the overlap portion 30 has better conductivity.
  • the overlap portion 30 and the second electrode plate 262 are located on the same layer, which can reduce the height difference between the overlap portion 30 and the adjacent cathode block in the film layer stacking direction, thereby reducing the height of the cathode 111 during the evaporation process.
  • the climbing difficulty reduces the risk of the cathode 111 breaking.
  • the number of insulating layers located above the overlap portion 30 is small, which can reduce the probability of over-etching when etching the insulating layer.
  • the conductive layer 20 is the source electrode 251, that is, the overlap portion 30 and the source electrode 251 are located in the same layer, and the materials of the two are the same.
  • the portions of the planarization layer 45 and the pixel defining layer 46 above the overlapping portion 30 are etched away, and the overlapping portion 30 is exposed, so that the cathode block of the light-emitting area 1011 is in direct contact with the adjacent overlapping portion 30, two adjacent ones
  • the cathode 111 of the light-emitting area 1011 is electrically connected by the overlap portion 30.
  • the source electrode 251 generally includes two Ti film layers and an Al film layer located between the two Ti film layers.
  • the conductivity is good.
  • the material of the overlap portion 30 and the source electrode 251 are the same, which can make the overlap portion 30 more conductive. good.
  • the overlap portion 30 and the source electrode 251 are located in the same layer, which can further reduce the height difference between the overlap portion 30 and the adjacent cathode block in the film layer stacking direction, thereby reducing the crawling of the cathode 111 during the evaporation process.
  • the slope is difficult to reduce the risk of fracture of the cathode 111.
  • the number of insulating layers located above the overlap portion 30 is smaller, which can reduce the probability of over-etching when etching the insulating layer.
  • the conductive layer 20 is the anode 113, that is, the overlap portion 30 and the anode 113 are located on the same layer, and the materials of the two are the same.
  • the part of the pixel defining layer 46 above the overlapping portion 30 is etched away, and the overlapping portion 30 is exposed, so that the cathode block of the light-emitting area 1011 is in direct contact with the adjacent overlapping portion 30, and the cathode block of the adjacent light-emitting area 1011 is in direct contact with the adjacent overlapping portion 30.
  • the electrical connection of the lap 30 is the anode 113, that is, the overlap portion 30 and the anode 113 are located on the same layer, and the materials of the two are the same.
  • the overlap portion 30 and the anode 113 are located in the same layer, which can minimize the height difference between the overlap portion 30 and the adjacent cathode block in the film layer stacking direction, further reduce the climbing difficulty of the cathode 111 during the evaporation process, and reduce the cathode There is a risk of breakage of the 111, thereby ensuring the electrical connection between the overlap portion 30 and the cathode 111.
  • the insulating layer located above the overlap portion 30 is only the pixel defining layer 46, which can further reduce the probability of over-etching when the insulating layer is etched.
  • the orthographic projection of the overlapping portion 30 on the substrate 10 and the orthographic projection of the cathode block electrically connected to the overlapping portion 30 on the substrate 10 overlap. In this way, it can be ensured that the electrical connection effect between the overlapping portion 30 and the adjacent cathode block is better.
  • the orthographic projection of the overlapping portion 30 on the substrate 10 and the cathode block electrically connected to the overlapping portion 30 are located there.
  • the range of the size d1 of the overlapped portion of the orthographic projection on the substrate is [500 ⁇ m, 1000 ⁇ m]. In this way, the size of the overlapped portion of the cathode block and the adjacent overlapping portion 30 is larger, which is more beneficial to avoid poor contact between the cathode block and the adjacent overlapping portion 30 and result in poor electrical connection effect.
  • the size d1 can be 500 ⁇ m, 600 ⁇ m, 700 ⁇ m, 800 ⁇ m, 900 ⁇ m, 1000 ⁇ m, etc.
  • the ratio of the total area of the light-emitting area 1011 to the total area of the light-transmitting area 1012 ranges from 1:1 to 1:2. In this way, it can not only ensure that the display effect of the first display area 101 is better, but also ensure that the light transmittance of the first display area 101 meets the requirements of the photosensitive element disposed under the first display area 101.
  • the ratio of the total area of the light-emitting area 1011 to the total area of the light-transmitting area 1012 in the first display area 101 may be 1:1, 1:1.2, 1:1.4, 1:1.8, 1:2, and so on.
  • the size range of the light-emitting area 1011 in the first direction and the second direction may both be [500 ⁇ m, 1000 ⁇ m]; the light-transmitting area 1012 is in the first direction And the range of the size in the second direction may both be [500 ⁇ m, 1000 ⁇ m].
  • the size of the light-emitting area 1011 may be 800 ⁇ m, and the size of the light-transmitting area 1012 may be 500 ⁇ m; in the second direction, the size of the light-transmitting area 1012 may be 1000 ⁇ m.
  • the first direction refers to the direction along the light-emitting area 1011 to the light-transmitting area 1012
  • the second direction refers to the direction perpendicular to the first direction along the surface of the display screen.
  • At least two overlapping portions 30 are provided in the same transparent region 1012, and the at least two overlapping portions 30 are arranged in an array along the second direction.
  • the arrangement of at least two overlapping portions 30 in an array means that two adjacent overlapping portions 30 are arranged at a certain distance and they are not in direct contact.
  • At least two overlapping parts 30 are arranged in the same light-transmitting area 1012, which can further ensure the electrical connection effect between the cathode block and the adjacent overlapping parts 30; The display effects of all parts of the area 1011 are more consistent, which helps to improve the user experience.
  • the display substrate provided by the embodiment of the present disclosure includes a first display area and a second display area.
  • the light transmittance of the first display area is greater than the light transmittance of the second display area, and the photosensitive element can be arranged under the first display area.
  • the full-screen display of the display substrate can be realized under the premise of ensuring the normal operation of the photosensitive element.
  • the overlap portion electrically connects the cathode blocks of two adjacent light-emitting areas, so that the cathode blocks of each light-emitting area in the first display area can be electrically connected to ensure the normal display of the display substrate;
  • the arrangement of the overlapping portion can reduce the area of the cathode in the light-transmitting area, which helps to improve the light transmittance of the first display area. Since the conductive layer and the overlapped portion of the display substrate can be formed in the same process step, the formation of the overlapped portion does not increase the number of masks, which helps to reduce the complexity of the manufacturing process.
  • the embodiment of the present disclosure also provides a method for preparing the display substrate.
  • the display substrate 100 includes a first display area 101 and a second display area 102, and the light transmittance of the first display area 101 is greater than the light transmittance of the second display area 102.
  • the first display area 101 includes a plurality of light-emitting areas 1011 and a plurality of light-transmitting areas 1012.
  • the light-emitting areas 1011 are arranged in an array
  • the light-transmitting areas 1012 are arranged in an array
  • the light-emitting areas 1012 are arranged in an array.
  • the plurality of light-transmitting regions are arranged at intervals.
  • a plurality of sub-pixels 110 are respectively provided in the second display area 102 and the light-emitting area 1011, so that the first display area 101 and the second display area 102 can display images.
  • Sub-pixels are not provided in the light-transmitting area 1012 of the first display area 101, and the light-transmitting rate of the light-transmitting area 1012 is relatively high, so the light transmittance of the first display area 101 is relatively high, so that ambient light can pass through the first display area 101 Enter into the front camera, infrared lens, light sensor and other photosensitive elements arranged under the first display area 101.
  • the sub-pixel 110 includes an anode 113, an organic light-emitting material 112 located on the anode 113, and a cathode 111 located on the organic light-emitting material 112.
  • the cathodes 111 of each sub-pixel in the second display area 102 are connected together.
  • a cathode block, the cathode 111 of each sub-pixel in the light-emitting area 1011 can be a connected cathode block, the cathode blocks of the adjacent light-emitting area 1011 can be electrically connected, and the cathode block of the second display area 102 and the light-emitting area 1011 can be electrically connected.
  • the cathode blocks can be connected into one piece.
  • the preparation method includes the following steps 210 to 230.
  • step 210 a substrate is provided.
  • the substrate 10 may be a flexible substrate or a rigid substrate.
  • the flexible substrate may be a transparent substrate prepared from one or more of PET (polyethylene terephthalate), PI (polyimide), PC (polycarbonate), and the like.
  • the rigid substrate may be, for example, a transparent substrate such as a glass substrate, a quartz substrate, or a plastic substrate.
  • step 220 a conductive layer in each of the plurality of light-emitting regions and a lap portion located in each of the plurality of light-transmitting regions are formed on a substrate, and the conductive layer is located in the light-emitting region, The overlapping portion is located in the light-transmitting area; the conductive layer and the overlapping portion are formed in the same process step.
  • the display substrate 100 includes a pixel circuit layer 27, and the pixel circuit layer 27 includes the conductive layer.
  • the pixel circuit layer 27 is formed on the substrate 10 and is located between the sub-pixel 110 and the substrate 10.
  • the pixel circuit layer 27 includes a pixel circuit for driving the sub-pixel 110.
  • the pixel circuit includes a thin film transistor 25 and a capacitor 26.
  • the thin film transistor 25 includes a source electrode 251, a drain electrode 252, a gate electrode 253, and a semiconductor layer 254.
  • the capacitor 26 includes a first electrode plate 261 and a second electrode plate 262 located on the first electrode plate 261 and insulated from the first electrode plate 261.
  • the first plate 261 and the gate electrode 253 of the capacitor 26 can be formed in the same process step.
  • the conductive layer 20 is the gate electrode 253 of the thin film transistor 25, that is, the overlap portion 30 and the gate electrode 253 are formed in the same process step.
  • the material of the gate electrode 253 may be Mo, Nd, Al, and the material of the overlap portion 30 is the same as that of the gate electrode 253, so that the overlap portion 30 has better conductivity.
  • the thickness of the gate electrode 253 is generally [560nm, 770nm].
  • the thickness of the gate electrode 253 is greater than the thickness of the source electrode 251 and the second plate 262 of the capacitor 26.
  • the thickness of the overlap portion 30 can be made larger, and the conductive performance of the overlap portion 30 is better, and the resistance is lower, so that the voltage drop during the display of the display substrate 100 Smaller, less power consumption.
  • the preparation method when the conductive layer 20 is the gate electrode 253 of the thin film transistor 25, after step 220, the preparation method further includes the following steps 221 to 227 to form pixels on the display substrate The circuit layer 27 and the anode of the sub-pixel.
  • step 221 a capacitor insulating layer covering the first display area 101 and the second display area 102 is formed on the gate electrode 253, and the capacitor insulating layer is etched to make the overlap Department exposed.
  • step 222 a second plate of the capacitor is formed on the capacitor insulating layer.
  • the second electrode plate is only formed in the second display area 102 and the light-emitting area 1011, and the second electrode plate is not formed in the light-transmitting area 1012.
  • step 223 an interlayer dielectric layer covering the first display area and the second display area is formed on the second electrode plate, and the interlayer dielectric layer is etched to make the overlap The junction is exposed.
  • a source electrode 251 and a drain electrode 252 are formed on the interlayer dielectric layer.
  • the source electrode 251 and the drain electrode 252 are formed only in the second display area 102 and the light-emitting area 1011, and the active electrode and the drain electrode are not formed in the light-transmitting area 1012.
  • step 225 a planarization layer covering the first display area and the second display area is formed on the source electrode 251, and the planarization layer is etched to expose the overlapped portion .
  • step 2266 an anode is formed on the planarization layer.
  • the anode is formed only in the second display area 102 and the light-emitting area 1011, and the anode is not formed in the light-transmitting area 1012.
  • step 227 a pixel defining layer covering the first display area and the second display area is formed on the anode, and the pixel defining layer is etched to expose the overlapping portion.
  • step 222 to step 227 the pixel circuit layer 27 of the display substrate and the anode 113 of the sub-pixel can be formed.
  • the insulating layer above the overlapping portion 30 is removed while etching each insulating layer, so that the overlapping portion 30 is exposed, and no additional process is required to insulate the overlapping portion 30.
  • the layer is etched, which helps reduce the complexity of the process.
  • the preparation method further includes the following steps 228 to 235 to form a pixel circuit of the display substrate The layer 27 and the anode 113 of the sub-pixel.
  • step 2208 a capacitor insulating layer 43 covering the first display area 101 and the second display area 102 is formed on the gate electrode 253.
  • step 229 a second electrode plate 262 is formed on the capacitor insulating layer 43.
  • the second electrode plate 262 is only formed in the second display area 102 and the light-emitting area 1011, and the second electrode plate 262 is not formed in the light-transmitting area 1012.
  • step 230 an interlayer dielectric layer 44 covering the first display area 101 and the second display area 102 is formed on the second electrode plate 44.
  • step 231 a source electrode 251 and a drain electrode 252 are formed on the interlayer dielectric layer 44;
  • the source electrode 251 and the drain electrode 252 are formed only in the second display area 102 and the light-emitting area 1011, and the active electrode and the drain electrode are not formed in the light-transmitting area 1012.
  • step 232 a planarization layer 45 covering the first display area 101 and the second display area 102 is formed on the source electrode 251.
  • step 233 an anode 113 is formed on the planarization layer 45.
  • the anode is formed only in the second display area 102 and the light-emitting area 1011, and the anode is not formed in the light-transmitting area 1012.
  • step 234 a pixel defining layer 46 covering the first display area 101 and the second display area 102 is formed on the anode 113.
  • step 235 the pixel defining layer 46, the planarization layer 45, the interlayer dielectric layer 44, and the capacitor insulating layer 43 are simultaneously etched to expose the overlap portion 30.
  • step 220 step 228 to step 235, the pixel circuit layer 27 of the display substrate 100 and the anode 113 of the sub-pixel can be formed.
  • the pixel defining layer 46, the planarization layer 45, the interlayer dielectric layer 44 and the capacitor insulating layer 43 are simultaneously etched to remove the part located above the overlap portion 30, so that the overlap portion 30 is exposed Compared with the solution of removing a layer of insulating layer each time, it helps to reduce the risk of etching to the overlap portion 30 due to over-etching.
  • the conductive layer 20 is the second plate 262 of the capacitor 26, that is, the overlap portion 30 and the second plate 262 of the capacitor 26 are in the same process. Formed in steps.
  • the conductive layer 20 is the source electrode 251, that is, the overlap portion 30 and the source electrode 251 are formed in the same process step.
  • the conductive layer 20 is the anode 20, that is, the overlap portion 30 and the anode 20 are formed in the same process step.
  • the preparation method of the display substrate may further include: forming an organic light-emitting material 112 over the anode 113.
  • a mask 200 as shown in FIG. 7 needs to be used, and the mask 200 is provided with a plurality of openings 210 and 220.
  • the mask 200 is placed above the pixel defining layer 46, the opening 220 of the mask 200 corresponds to the second display area 102, and the multiple openings 210 of the mask 200 and multiple light-emitting areas 1011 has a one-to-one correspondence. After that, the organic light-emitting material is vapor-deposited through the openings 210 and 220 of the mask 200.
  • a cathode layer is formed on the conductive layer 20.
  • the cathode layer includes a plurality of cathode blocks.
  • the cathode blocks cover the second display area or cover the light-emitting area. The lap part between is electrically connected.
  • step 230 may be completed by the following steps 236 to 238.
  • step 2366 a mask is provided, and the mask includes openings corresponding to the plurality of cathode blocks.
  • the mask 300 includes a plurality of openings 310 and 320.
  • the plurality of openings 310 correspond to the plurality of light-emitting regions 1101 one-to-one
  • the shape of the opening 310 and the corresponding light-emitting region 1101 are substantially the same
  • the shape of the opening 320 and the second display region 102 are substantially the same.
  • step 237 the mask is placed on the conductive layer, and the orthographic projection of the opening corresponding to the light-emitting area overlaps the orthographic projection of the overlapping portion adjacent to the opening on the substrate.
  • the cathode vapor-deposited through the opening 310 of the mask 300 partially overlaps the overlap portion 30, which can ensure that the overlap portion 30 and the adjacent cathode block have a better electrical connection effect.
  • the orthographic projection of the opening on the substrate, and the overlap portion adjacent to the opening is in the The size range of the overlapped portion of the orthographic projection on the substrate is [500 ⁇ m, 1000 ⁇ m]. In this way, the size of the part where the prepared cathode block overlaps with the adjacent overlap portion 30 is larger, which can ensure that the cathode block formed by the mask 300 has a better electrical connection effect with the adjacent overlap portion 30. It helps to avoid poor contact between the cathode block and the adjacent overlapping portion 30.
  • the dimension d2 of the orthographic projection of the opening 310 on the substrate 10 and the orthographic projection of the overlap portion 30 adjacent to the opening 310 on the substrate 10 in the first direction may be 500 ⁇ m, 600 ⁇ m, 700 ⁇ m, or 800 ⁇ m. , 900 ⁇ m, 1000 ⁇ m, etc., where the first direction refers to the direction along the light-transmitting area 1012 to the light-emitting area 1011.
  • step 2308 the cathode block is formed through the opening of the mask.
  • an evaporation process can be used to form a cathode block through the opening of the mask.
  • the ratio of the total area of the light-emitting area to the total area of the light-transmitting area ranges from 1:1 to 1:2.
  • At least two overlapping portions are provided in the same light transmission area, and the at least two overlapping portions are arranged in parallel along the first direction.
  • the display substrate includes a first display area 101 and a second display area 102, and the light transmittance of the first display area 101 is greater than the light transmittance of the second display area 102, then
  • the photosensitive element can be arranged under the first display area 101, and a full-screen display of the display substrate can be realized under the premise of ensuring the normal operation of the photosensitive element.
  • the overlap portion 30 electrically connects the cathode blocks of two adjacent light-emitting areas, so that the cathode blocks of each light-emitting area 1011 in the first display area 101 are electrically connected to ensure the display Normal display of the substrate 100; and the arrangement of the overlap portion 30 can reduce the area of the cathode block in the light-transmitting area 1012, which helps to improve the light transmittance of the first display area 101. Since the conductive layer 20 and the overlap portion 30 of the display substrate 100 are formed in the same process step, the formation of the overlap portion 30 does not increase the number of masks, which helps reduce the complexity of the manufacturing process.
  • At least one embodiment of the present disclosure also provides a display device, which includes the display substrate 100 described in any of the foregoing embodiments.
  • the display device can be: liquid crystal display panel, OLED display panel, mini-LED display panel, electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator and other products or components with display function.
  • the display device includes a housing and a display panel, and the display panel is connected to the housing, for example, the display panel is embedded in the housing.
  • the sizes of layers and regions may be exaggerated for clarity of illustration.
  • the size of the first display area is relatively large. In practice, the size of the first display area is much smaller than the size shown in FIG. 1.
  • an element or layer is referred to as being "on” another element or layer, it can be directly on the other element or intervening layers may be present.
  • an element or layer is referred to as being "under” another element or layer, it can be directly under the other element, or there may be more than one intervening layer or element.

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Abstract

一种显示基板(100)，包括设置于衬底(10)上的第一显示区(101)，所述第一显示区(101)包括均呈阵列排布的多个发光区(1011)与多个透光区(1012)，且所述多个发光区(1011)和所述多个透光区(1012)间隔排布；所述发光区(1011)的每一个包括：导电层，设置于所述发光区(1011)；以及阴极块(111)，设置于所述导电层上；其中，所述第一显示区(101)还包括所述搭接部(30)，所述搭接部设置于所述透光区并与所述导电层位于同一层且材料相同，并构造为电连接相邻两个发光区的阴极块。还提供了一种显示基板的制备方法。

Description

显示基板及其制备方法、显示装置 技术领域
本公开的实施例涉及一种显示基板及其制备方法、显示装置。
背景技术
随着电子设备的快速发展，用户对屏占比的要求越来越高。为了提高电子设备的全面屏显示，在屏幕上设置透光率较高的显示区，将前置摄像头、光线传感器等元件设置在该显示区下方。
发明内容
本公开的至少一些实施例提供了一种显示基板，包括设置于衬底上的第一显示区，所述第一显示区包括多个发光区与多个透光区，所述多个发光区呈阵列排布，所述多个透光区呈阵列排布，且所述多个发光区和所述多个透光区间隔排布；
所述发光区的每一个包括：
导电层，设置于所述发光区；以及
阴极块，设置于所述导电层上；
其中，所述第一显示区还包括搭接部，所述搭接部设置于所述透光区并与所述导电层位于同一层且材料相同，并构造为电连接相邻两个发光区的阴极块。
在本公开的一个实施例中，所述发光区包括像素电路层，所述像素电路层包括所述导电层。
在本公开的一个实施例中，所述像素电路层包括薄膜晶体管，所述薄膜晶体管包括栅电极，所述导电层为所述栅电极。
在本公开的一个实施例中，所述像素电路层包括薄膜晶体管，所述薄膜晶体管包括源电极，所述导电层为所述源电极。
在本公开的一个实施例中，所述像素电路层包括电容，所述电容包括第一极板和第二极板，所述第二极板位于所述第一极板上方，所述导电层为所述第二极板。
在本公开的一个实施例中，所述发光区还包括阳极和有机发光材料，所述阳极设置 于所述像素电极上，所述有机发光材料设置于所述阳极和所述阴极块之间，所述导电层为所述阳极。
在本公开的一个实施例中，所述搭接部在所述衬底上的正投影和与该搭接部电连接的阴极块在所述衬底上的正投影重叠。
在本公开的一个实施例中，所述搭接部在所述衬底上的正投影、及与该搭接部电连接的阴极块在所述衬底上的正投影的重叠部分在第一方向上的尺寸范围为[500μm，1000μm]，其中，所述第一方向指的是沿所述透光区指向所述发光区的方向。
在本公开的一个实施例中，所述第一显示区内，所述发光区的总面积与所述透光区的总面积的比值范围为1:1～1:2。
在本公开的一个实施例中，所述多个透光区中的每一个中设置有至少两个搭接部，沿所述透光区的延伸方向，所述至少两个搭接部在平行于第一方向的方向上平行排布。
在本公开的一个实施例中，所述显示基板还包括第二显示区，所述第二显示区的透光率小于所述第一显示区的透光率。
本公开的至少一个实施例提供了一种显示装置，所述显示装置包括上述的显示基板。
本公开的至少一个实施例提供了一种显示基板的制备方法，所述显示基板包括第一显示区；所述第一显示区包括多个发光区与多个透光区，所述多个发光区呈阵列排布，所述多个透光区呈阵列排布，且所述多个发光区和所述多个透光区间隔排布；
所述显示基板的制备方法包括：
提供衬底；
在所述衬底上形成位于所述多个发光区的每一个中的导电层及位于所述多个透光区中的每一个中的搭接部，所述导电层与所述搭接部在同一工艺步骤中形成；
在所述导电层上形成阴极块，所述阴极块覆盖所述发光区，相邻两个发光区的阴极块通过该相邻两个发光区之间的透光区中的所述搭接部电连接。
在本公开的一个实施例中，所述显示基板包括像素电路层，所述像素电路层包括薄膜晶体管，所述薄膜晶体管包括栅电极，所述导电层为所述栅电极。
在本公开的一个实施例中，所述像素电路还包括电容，所述电容包括第一极板及第二极板，所述第一极板与所述导电层在同一工艺步骤中形成；在所述衬底上形成所述导电层及所述搭接部之后，所述制备方法还包括：
在所述栅电极上形成覆盖所述第一显示区的电容绝缘层，对所述电容绝缘层进行刻蚀，以使所述搭接部露出；
在所述电容绝缘层上形成第二极板；
在所述第二极板上形成覆盖所述第一显示区的层间介质层，对所述层间介质层进行刻蚀，以使所述搭接部露出；
在所述层间介质层上形成源电极与漏电极；
在所述源电极上形成覆盖所述第一显示区的平坦化层，对所述平坦化层进行刻蚀，以使所述搭接部露出；
在所述平坦化层上形成阳极；
在所述阳极上形成覆盖所述第一显示区的像素限定层，对所述像素限定层进行刻蚀，以使所述搭接部露出。
在本公开的一个实施例中，所述像素电路还包括电容，所述电容包括第一极板及第二极板，所述第一极板与所述导电层在同一工艺步骤中形成；所述在所述衬底上形成导电层及搭接部之后，所述制备方法还包括：
在所述栅电极上形成覆盖所述第一显示区的电容绝缘层；
在所述电容绝缘层上形成第二极板；
在所述第二极板上形成覆盖所述第一显示区的层间介质层；
在所述层间介质层上形成源电极与漏电极；
在所述源电极上形成覆盖所述第一显示区与所述第二显示区的平坦化层；
在所述平坦化层上形成阳极；
在所述阳极上形成覆盖所述第一显示区的像素限定层；
对所述像素限定层、所述平坦化层、所述层间介质层以及所述电容绝缘层同时进行刻蚀，以使所述搭接部露出。
在本公开的一个实施例中，所述在所述导电层上形成阴极层，包括：
提供掩膜版，所述掩膜版包括与所述多个阴极块对应的开口；
将所述掩膜版置于所述导电层上，所述发光区对应的开口的正投影和与该开口相邻 的搭接部在所述衬底上的正投影重叠；
通过所述掩膜版的开口形成所述阴极块。
在本公开的一个实施例中，沿所述透光区指向所述发光区的方向，所述开口在所述衬底上的正投影、与该开口相邻的所述搭接部在所述衬底上的正投影重叠的部分的尺寸范围为[500μm，1000μm]。
附图说明
图1是根据本公开一示例性实施例的显示基板的结构示意图；
图2是根据本公开一示例性实施例的显示基板的局部剖视图；
图3是根据本公开另一示例性实施例的显示基板的局部剖视图；
图4是根据本公开再一示例性实施例的显示基板的局部剖视图；
图5是根据本公开又一示例性实施例的显示基板的局部剖视图；
图6是根据本公开一示例性实施例的显示基板的制备方法的流程图；
图7是根据本公开一示例性实施例的使用掩膜版蒸镀有机发光材料时的示意图；以及
图8是根据本公开一示例性实施例的使用掩膜版蒸镀阴极时的示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施例并不代表与本公开相一致的所有实施例。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
在本公开使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本公开。在本公开和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本公开可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不 脱离本公开范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
下面结合附图，对本公开实施例中的显示基板及其制备方法、显示装置进行详细说明。在不冲突的情况下，下述的实施例中的特征可以相互补充或相互组合。
在本公开实施例中，为描述方便，将由衬底指向导电层的方向定义为上，将由导电层指向衬底的方向定义为下，以此确定出上下方向。容易理解，不同的方向定义方式并不会影响工艺的实质操作内容以及产品的实际形态。
本公开的至少一些实施例提供了一种显示基板。参见图1，所述显示基板100包括第一显示区101与第二显示区102，所述第一显示区101的透光率大于所述第二显示区102的透光率。所述第一显示区101包括多个发光区1011与多个透光区1012，所述多个发光区1011呈阵列排布，所述多个透光区1012呈阵列排布，所述多个发光区和所述多个透光区间隔排布。显示基板100在显示时，第一显示区101可用于显示指示电量的图标和指示时间的图标等不需高品质显示效果的画面部分，第二显示区102可用于显示图像或者视频。
第二显示区102与发光区1011内分别设有多个子像素110，从而使得第一显示区101与第二显示区102可进行显示。第一显示区101的多个透光区1012内均未设置子像素，因而第一显示区101的透光率较高，从而通过第一显示区101进入到设置在第一显示区101下方的前置摄像头、红外镜头、光线传感器等感光元件中的外部光线的量较多，可保证感光元件的正常工作。
参见图2至图5，子像素110包括阳极113、位于阳极113上的有机发光材料112、以及位于有机发光材料112上的阴极111。第二显示区102中各个子像素的阴极111为连成一片的阴极块，发光区1011中各子像素的阴极111可为连成一片的阴极块，相邻的发光区1011的阴极块可电连接，第二显示区102的阴极块与发光区1011的阴极块可连成一片。
所述显示基板100包括衬底10、设置于衬底10上的导电层20及搭接部30、以及设置于所述导电层20上的阴极层。
所述导电层20位于所述第二显示区102及所述发光区1011，所述搭接部30位于所述透光区1012，搭接部30的面积小于透光区1012的面积。所述导电层20与所述搭接 部30位于同一层且材料相同。阴极层包括位于第一显示区及第二显示区的多个阴极块，所述阴极块覆盖所述第二显示区102或覆盖所述发光区1011，相邻两个所述发光区1011的阴极块通过该两个发光区1011之间的所述搭接部30电连接。
本公开实施例提供的显示基板100，显示基板包括第一显示区101与第二显示区102，第一显示区101的透光率大于第二显示区102的透光率，则可将感光元件设置在第一显示区101下方，可在保证感光元件正常工作的前提下实现显示基板的全面屏显示。通过在透光区1012内设置搭接部30，搭接部30将相邻两个发光区的阴极块电连接，可保证显示基板100的正常显示；并且搭接部30的设置可减小透光区1012内阴极块的面积，有助于提升第一显示区101的透光率。显示基板100的导电层20与搭接部30位于同一层且二者材料相同，则导电层20与搭接部30可在同一工艺步骤中形成，因而搭接部30的形成不会增加掩膜版的数量，有助于降低制备工艺的复杂度。
在本公开实施例中，导电层20与搭接部30在同一工艺步骤中形成指的是，导电层20与搭接部30在一次构图工艺中同时形成。
在本公开的一个实施例中，所述显示基板100包括像素电路层27，所述像素电路层27包括所述导电层20。
像素电路层设置于衬底10上，位于子像素110与衬底10之间。像素电路层27包括用于驱动子像素110的像素电路。像素电路包括薄膜晶体管25与电容26。薄膜晶体管25包括源电极251、漏电极252、栅电极253及半导体层254。电容26包括第一极板261及位于第一极板261之上并与第一极板261绝缘间隔设置的第二极板262。其中，第一极板261与栅电极253可位于同一层，二者可在同一工艺步骤中形成。导电层20可以是薄膜晶体管中的一个电极，或者导电层20可为电容26的第二极板262。
显示基板100还可包括设置于衬底10与半导体层254之间的缓冲层41。像素电路层27还可包括设置于半导体层254与栅电极253之间的栅极绝缘层42、设置于第一极板261与第二极板262之间的电容绝缘层43、设置于第二极板262与源电极251之间的层间介质层44及设置于源电极251与阳极113之间的平坦化层45。显示基板100还可包括设置于平坦化层45上的像素限定层46。像素限定层46中设置有与阳极113一一对应的像素开口，像素开口暴露对应的阳极113的一部分，有机发光材料112设置于像素开口中。
在本公开的一个实施例中，像素电路层27位于搭接部30之上的膜层在所述衬底10 上的正投影与所述搭接部30在所述衬底10上的正投影不重叠；所述阳极113在所述衬底10上的正投影与所述搭接部30在所述衬底10上的正投影不重叠；所述有机发光材料112在所述衬底10上的正投影与所述搭接部30在所述衬底10上的正投影不重叠。如此设置，搭接部30上方的区域无像素电路层、阳极113及有机发光材料，有助于提升透光区1012的透光率。
在本公开的一个实施例中，如图2所示，所述导电层20为薄膜晶体管25的栅电极253，也即是搭接部30与栅电极253位于同一层，且二者材料相同。电容绝缘层43、层间介质层44、平坦化层45及像素限定层46位于搭接部30上方的部分被刻蚀掉，搭接部30露出，从而发光区1011的阴极块与相邻的搭接部30直接接触，相邻两个发光区1011的阴极块通过搭接部30电连接。
栅电极253的材料可为Mo、Nd、Al，搭接部30与栅电极253的材料相同，可使得搭接部30导电性能较好。栅电极253的厚度范围一般为[560nm，770nm]，源电极251与漏电极252的厚度范围一般为[380nm，580nm]，电容26的第二极板262的厚度范围一般为[350nm，550nm]。可知栅电极253的厚度大于源电极251的厚度及第二极板262的厚度，搭接部30与栅电极253同时形成时，搭接部30的厚度较大，电阻较小。由上可知，导电层20为栅电极253时，搭接部30的导电性能较好，电阻较小，可使得显示基板100显示时电压降较小，功耗较低。
在本公开的另一个实施例中，如图3所示，所述导电层20为电容26的第二极板262，也即是搭接部30与电容26的第二极板262位于同一层，且二者材料相同。层间介质层44、平坦化层45及像素限定层46位于搭接部30上方的部分被刻蚀掉，搭接部30露出，从而发光区1011的阴极块与相邻的搭接部30直接接触，相邻两个发光区1011的阴极块通过搭接部30电连接。
电容26的第二极板262材料通常为Mo、或者Ti、或者Cu，导电性较好，搭接部30与第二极板262的材料相同，可使得搭接部30导电性能较好。并且，搭接部30与第二极板262位于同一层，可减小搭接部30与相邻的阴极块在膜层层叠方向上的高度差，进而减小在蒸镀过程中阴极111的爬坡难度，降低阴极111发生断裂的风险。并且，位于搭接部30上方的绝缘层的数量较小，可减小在刻蚀绝缘层时发生过刻的几率。
在本公开的再一个实施例中，如图4所示，所述导电层20为源电极251，也即是搭接部30与源电极251位于同一层，且二者材料相同。平坦化层45及像素限定层46位于搭接部30上方的部分被刻蚀掉，搭接部30露出，从而发光区1011的阴极块与相邻 的搭接部30直接接触，相邻两个发光区1011的阴极111通过搭接部30的电连接。
源电极251一般包括两层Ti膜层及位于两层Ti膜层之间的Al膜层，导电性较好，搭接部30与源电极251的材料相同，可使得搭接部30导电性能较好。并且，搭接部30与源电极251位于同一层，可进一步减小搭接部30与相邻的阴极块在膜层层叠方向上的高度差，进而减小在蒸镀过程中阴极111的爬坡难度，降低阴极111发生断裂的风险。并且，位于搭接部30上方的绝缘层的数量更小，可减小在刻蚀绝缘层时发生过刻的几率。
在本公开的又一个实施例中，如图5所示，所述导电层20为阳极113，也即是搭接部30与阳极113位于同一层，且二者材料相同。像素限定层46位于搭接部30上方的部分被刻蚀掉，搭接部30露出，从而发光区1011的阴极块与相邻的搭接部30直接接触，相邻发光区1011的阴极块与搭接部30的电连接。
搭接部30与阳极113位于同一层，可使得搭接部30与相邻的阴极块在膜层层叠方向上的高度差最小，进一步降低在蒸镀过程中阴极111的爬坡难度，降低阴极111发生断裂的风险，从而确保搭接部30与阴极111的电连接。并且，位于搭接部30上方的绝缘层只有像素限定层46，可进一步减小在刻蚀绝缘层时发生过刻的几率。
在本公开的一个实施例中，所述搭接部30在所述衬底10上的正投影、以及与该搭接部30电连接的阴极块在所述衬底10上的正投影重叠。如此，可保证搭接部30与相邻的阴极块的电连接效果较好。
进一步地，沿所述透光区1012指向所述发光区1011的方向，所述搭接部30在所述衬底10上的正投影、及与该搭接部30电连接的阴极块在所述衬底上的正投影重叠的部分的尺寸d1的范围为[500μm，1000μm]。如此，阴极块与相邻的搭接部30搭接的部分的尺寸较大，更利于避免阴极块与相邻的搭接部30接触不良更导致电连接效果较差。其中，沿透光区1012指向发光区1011的方向，搭接部30在衬底10上的正投影、及与该搭接部30电连接的阴极块在衬底10上的正投影重叠的部分的尺寸d1可为500μm、600μm、700μm、800μm、900μm、1000μm等。
在本公开的一个实施例中，所述第一显示区101内，所述发光区1011的总面积与所述透光区1012的总面积的比值范围为1:1～1:2。如此，既可保证第一显示区101的显示效果较好，又可保证第一显示区101的透光率满足设置在第一显示区101下方的感光元件的需求。第一显示区101中发光区1011的总面积与透光区1012的总面积的比值可以 是1:1、1:1.2、1:1.4、1:1.8、1:2等。
在本公开的一个实施例中，第一显示区101中，发光区1011在第一方向以及第二方向上的尺寸的范围，可均为[500μm，1000μm]；透光区1012在第一方向以及第二方向上的尺寸的范围，可均为[500μm，1000μm]。在一个示例性实施例中，在第一方向上，发光区1011的尺寸可为800μm，透光区1012的尺寸可为500μm；在第二方向上，透光区1012的尺寸可为1000μm。第一方向指的是在沿发光区1011指向透光区1012方向，第二方向指的是沿显示屏表面垂直于第一方向的方向。如此，可避免由于单个发光区1011或透光区1012的面积较大导致第一显示区101的显示效果较差。
在本公开的一个实施例中，同一所述透光区1012内设有至少两个搭接部30，沿第二方向，所述至少两个搭接部30阵列排布。至少两个搭接部30阵列排布指的是，相邻的两个搭接部30间隔一定距离设置，二者不直接接触。同一透光区1012内设置至少两个搭接部30，可进一步保证阴极块与相邻的搭接部30的电连接效果；并且如此设置可使得发光区1011各处的电压降更接近，发光区1011各处的显示效果更一致，有助于提升用户的使用体验。
本公开实施例提供的显示基板包括第一显示区与第二显示区，第一显示区的透光率大于第二显示区的透光率，则可将感光元件设置在第一显示区下方，可在保证感光元件正常工作的前提下实现显示基板的全面屏显示。通过在透光区内形成搭接部，搭接部将相邻两个发光区的阴极块电连接，可使得第一显示区中各个发光区的阴极块电连接，保证显示基板的正常显示；并且搭接部的设置可减小透光区内阴极的面积，有助于提升第一显示区的透光率。由于显示基板的导电层与搭接部可在同一工艺步骤中形成，则搭接部的形成不会增加掩膜版的数量，有助于降低制备工艺的复杂度。
本公开实施例还提供了一种显示基板的制备方法。参见图1，所述显示基板100包括第一显示区101与第二显示区102，所述第一显示区101的透光率大于所述第二显示区102的透光率。所述第一显示区101包括多个发光区1011与多个透光区1012，所述多个发光区1011阵列排布，所述多个透光区1012阵列排布，所述多个发光区和所述多个透光区间隔排布。
第二显示区102与发光区1011内分别设有多个子像素110，从而使得第一显示区101与第二显示区102可显示图像。第一显示区101的透光区1012内未设置子像素，透光区1012的透光率较高，因而第一显示区101的透光率较高，从而环境光可通过第一显示区101进入到设置在第一显示区101下方的前置摄像头、红外镜头、光线传感器等感 光元件中。
参见图2至图5，子像素110包括阳极113、位于阳极113上的有机发光材料112、以及位于有机发光材料112上的阴极111，第二显示区102中各个子像素的阴极111为连成一片的阴极块，发光区1011中各子像素的阴极111可为连成一片的阴极块，相邻的发光区1011的阴极块可电连接，第二显示区102的阴极块与发光区1011的阴极块可连成一片。
下文参照图6对根据本公开一个实施例的显示基板的制备方法进行详细描述。如图6所示，所述制备方法包括如下步骤210至步骤230。
在步骤210中，提供衬底。
在本公开的一个实施例中，衬底10可以是柔性衬底或刚性衬底。柔性衬底可以由PET(聚对苯二甲酸乙二醇酯)、PI(聚酰亚胺)、PC(聚碳酸酯)等中的一种或多种制备得到的透明衬底。刚性衬底例如可以是玻璃衬底、石英衬底或者塑料衬底等透明衬底。
在步骤220中，在衬底上形成所述多个发光区的每一个中的导电层及位于所述多个透光区中的每一个中的搭接部，所述导电层位于发光区，搭接部位于所述透光区；导电层与搭接部在同一工艺步骤中形成。
在本公开的一个实施例中，所述显示基板100包括像素电路层27，所述像素电路层27包括所述导电层。
像素电路层27形成于衬底10上，位于子像素110与衬底10之间。像素电路层27包括用于驱动子像素110的像素电路。像素电路包括薄膜晶体管25与电容26。薄膜晶体管25包括源电极251、漏电极252、栅电极253及半导体层254。电容26包括第一极板261及位于第一极板261之上并与所述第一极板261绝缘隔离的第二极板262。电容26的第一极板261与栅电极253可在同一工艺步骤中形成。
在本公开的一个实施例中，如图2所示，所述导电层20为薄膜晶体管25的栅电极253，也即是，搭接部30与栅电极253在同一工艺步骤中形成。
栅电极253的材料可为Mo、Nd、Al，搭接部30与栅电极253的材料相同，可使得搭接部30导电性能较好。栅电极253的厚度范围一般为[560nm，770nm]，栅电极253的厚度大于源电极251及电容26的第二极板262的厚度，搭接部30与栅电极253同时形成时，则搭接部30的厚度与栅电极253的厚度相同。因而，在导电层20为栅电极253 的情况下，可使得搭接部30的厚度较大，进而使得搭接部30的导电性能较好，电阻较小，从而使得显示基板100显示时电压降较小，功耗较小。
在本公开的一个实施例中，所述导电层20为薄膜晶体管25的栅电极253的情况下，在步骤220之后，所述制备方法还包括如下步骤221至步骤227，以形成显示基板的像素电路层27以及子像素的阳极。
在步骤221中，在所述栅电极253上形成覆盖所述第一显示区101与所述第二显示区102的电容绝缘层，对所述电容绝缘层进行刻蚀，以使所述搭接部露出。
在步骤222中，在所述电容绝缘层上形成电容的第二极板。
在该步骤中，第二极板仅形成于第二显示区102及发光区1011，透光区1012中未形成有第二极板。
在步骤223中，在所述第二极板上形成覆盖所述第一显示区与所述第二显示区的层间介质层，对所述层间介质层进行刻蚀，以使所述搭接部露出。
在步骤224中，在所述层间介质层上形成源电极251与漏电极252。
在该步骤中，源电极251与漏电极252仅形成于第二显示区102及发光区1011，透光区1012中未形成有源电极与漏电极。
在步骤225中，在所述源电极251上形成覆盖所述第一显示区与所述第二显示区的平坦化层，对所述平坦化层进行刻蚀，以使所述搭接部露出。
在步骤226中，在所述平坦化层上形成阳极。
在该步骤中，阳极仅形成于第二显示区102及发光区1011，透光区1012中未形成有阳极。
在步骤227中，在所述阳极上形成覆盖所述第一显示区与所述第二显示区的像素限定层，对所述像素限定层进行刻蚀，以使所述搭接部露出。
通过步骤220、步骤222至步骤227可形成显示基板的像素电路层27以及子像素的阳极113。上述步骤222至步骤227中，在对各个绝缘层进行刻蚀的同时将搭接部30上方的绝缘层去除，使搭接部30露出，无需增加额外的工序来对搭接部30上的绝缘层进行刻蚀，有利于降低工艺复杂性。
在另一个实施例中，在所述导电层20为薄膜晶体管25的栅电极253的情况下，在步骤220之后，所述制备方法还包括如下步骤228至步骤235，以形成显示基板的像 素电路层27以及子像素的阳极113。
在步骤228中，在所述栅电极253上形成覆盖所述第一显示区101与所述第二显示区102的电容绝缘层43。
在步骤229中，在所述电容绝缘层43上形成第二极板262。
在该步骤中，第二极板262仅形成于第二显示区102及发光区1011，透光区1012中未形成有第二极板262。
在步骤230中，在所述第二极板44上形成覆盖所述第一显示区101与所述第二显示区102的层间介质层44。
在步骤231中，在所述层间介质层44上形成源电极251与漏电极252；
在该步骤中，源电极251与漏电极252仅形成于第二显示区102及发光区1011，透光区1012中未形成有源电极与漏电极。
在步骤232中，在所述源电极251上形成覆盖所述第一显示区101与所述第二显示区102的平坦化层45。
在步骤233中，在所述平坦化层45上形成阳极113。
在该步骤中，阳极仅形成于第二显示区102及发光区1011，透光区1012中未形成有阳极。
在步骤234中，在所述阳极113上形成覆盖所述第一显示区101与所述第二显示区102的像素限定层46。
在步骤235中，对所述像素限定层46、所述平坦化层45、所述层间介质层44以及所述电容绝缘层43同时进行刻蚀，以使所述搭接部30露出。
通过步骤220、步骤228至步骤235可形成显示基板100的像素电路层27以及子像素的阳极113。上述步骤228至步骤235中，对像素限定层46、平坦化层45、层间介质层44以及电容绝缘层43同时进行刻蚀，去除位于搭接部30上方的部分，使搭接部30露出，相对于每次刻蚀去除一层绝缘层的方案来说，有助于降低因过刻而刻蚀到搭接部30的风险。
在本公开的另一个实施例中，如图3所示，所述导电层20为电容26的第二极板262，也即是搭接部30与电容26的第二极板262在同一工艺步骤中形成。
在本公开的再一个实施例中，如图4所示，所述导电层20为源电极251，也即是搭接部30与源电极251在同一工艺步骤中形成。
在本公开的又一个实施例中，如图5所示，所述导电层20为阳极20，也即是搭接部30与阳极20在同一工艺步骤中形成。
在形成阳极113之后，显示基板的制备方法还可包括：在阳极113上方形成有机发光材料112。
在形成有机发光材料113时，需采用如图7所示的掩膜版200，掩膜版200设有多个开口210、220。在蒸镀有机发光材料时，将掩膜版200置于像素限定层46上方，掩膜版200的开口220与第二显示区102对应，掩膜版200的多个开口210与多个发光区1011一一对应。之后，通过掩膜版200的开口210、220蒸镀有机发光材料。
在步骤230中，在导电层20上形成阴极层，阴极层包括多个阴极块，阴极块覆盖第二显示区或覆盖发光区，相邻两个发光区的阴极块通过该两个发光区之间的搭接部电连接。
在本公开的一个实施例中，步骤230可通过如下步骤236至步骤238完成。
在步骤236中，提供掩膜版，所述掩膜版包括与所述多个阴极块对应的开口。
参见图8，掩膜版300包括多个开口310、320。其中，多个开口310与多个发光区1101一一对应，开口310与对应的发光区1101的形状大致相同，开口320与第二显示区102的形状大致相同。
在步骤237中，将所述掩膜版置于所述导电层上，所述发光区对应的开口的正投影和与该开口相邻的搭接部在所述衬底上的正投影重叠。
如此，通过掩膜版300的开口310蒸镀的阴极与搭接部30部分重叠，可保证搭接部30与相邻的阴极块的电连接效果较好。
在本公开的一个实施例中，沿所述透光区指向所述发光区的方向，所述开口在所述衬底上的正投影、与该开口相邻的所述搭接部在所述衬底上的正投影重叠的部分的尺寸范围为[500μm，1000μm]。如此，制备得到的阴极块与相邻的搭接部30搭接的部分的尺寸较大，可保证通过掩膜版300形成的阴极块与相邻的搭接部30的电连接效果较好，有助于避免阴极块与相邻的搭接部30接触不良。开口310在衬底10上的正投影、与该开口310相邻的搭接部30在衬底10上的正投影重叠的部分在第一方向上的尺寸d2 可为500μm、600μm、700μm、800μm、900μm、1000μm等，其中，第一方向指的是沿透光区1012指向发光区1011的方向。
在步骤238中，通过所述掩膜版的开口形成所述阴极块。
在该步骤中，可采用蒸镀工艺在通过掩膜版的开口形成阴极块。
在本公开的一个实施例中，所述第一显示区内，所述发光区的总面积与所述透光区的总面积的比值范围为1:1～1:2。
在本公开的一个实施例中，同一透光区内设置有至少两个搭接部，所述至少两个搭接部沿第一方向平行排布。
在根据本公开实施例的显示基板的制备方法中，显示基板包括第一显示区101与第二显示区102，第一显示区101的透光率大于第二显示区102的透光率，则可将感光元件设置在第一显示区101下方，可在保证感光元件正常工作的前提下实现显示基板的全面屏显示。通过在透光区1012内形成搭接部30，搭接部30将相邻两个发光区的阴极块电连接，可使得第一显示区101中各个发光区1011的阴极块电连接，保证显示基板100的正常显示；并且搭接部30的设置可减小透光区1012内阴极块的面积，有助于提升第一显示区101的透光率。由于显示基板100的导电层20与搭接部30在同一工艺步骤中形成，则搭接部30的形成不会增加掩膜版的数量，有助于降低制备工艺的复杂度。
对于方法实施例而言，由于其基本对应于产品的实施例，所以相关细节及有益效果的描述参见产品实施例的部分说明即可，不再进行赘述。
本公开的至少一个实施例还提供了一种显示装置，所述显示装置包括上述任一实施例所述的显示基板100。
显示装置可以为：液晶显示面板、OLED显示面板、mini-LED显示面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本公开的一些实施例中，显示装置包括壳体及显示面板，显示面板与壳体相连接，例如，显示面板嵌入到壳体内。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。例如图1中，为了视觉上更清楚，第一显示区的尺寸较大，实际中第一显示区的尺寸远小于 图1中所示的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (19)

  1. 一种显示基板，包括设置于衬底上的第一显示区，所述第一显示区包括多个发光区与多个透光区，所述多个发光区呈阵列排布，所述多个透光区呈阵列排布，且所述多个发光区和所述多个透光区间隔排布；
    所述多个发光区的每一个包括：
    导电层；以及
    阴极块，设置于所述导电层上；
    其中，所述第一显示区还包括搭接部，所述搭接部设置于所述透光区并与所述导电层位于同一层且材料相同，并构造为电连接相邻两个发光区的阴极块。
  2. 根据权利要求1所述的显示基板，其包括像素电路层，所述像素电路层位于所述多个发光区的每一个中并包括所述导电层。
  3. 根据权利要求2所述的显示基板，其中，所述像素电路层包括薄膜晶体管，所述薄膜晶体管包括栅电极，所述导电层为所述栅电极。
  4. 根据权利要求2所述的显示基板，其中，所述像素电路层包括薄膜晶体管，所述薄膜晶体管包括源电极，所述导电层为所述源电极。
  5. 根据权利要求2所述的显示基板，其中，所述像素电路层包括电容，所述电容包括第一极板和第二极板，所述第二极板位于所述第一极板上方，所述导电层为所述第二极板。
  6. 根据权利要求2至5中任一项所述的显示基板，其中，所述多个发光区的每一个还包括阳极和有机发光材料，所述阳极设置于所述像素电路层上，所述有机发光材料设置于所述阳极和所述阴极之间，所述导电层为所述阳极。
  7. 根据权利要求1至6中任一项所述的显示基板，其中，所述搭接部在所述衬底上的正投影和与该搭接部电连接的阴极块在所述衬底上的正投影重叠。
  8. 根据权利要求1至7中任一项所述的显示基板，其中，所述搭接部在所述衬底 上的正投影、及与该搭接部电连接的阴极块在所述衬底上的正投影的重叠部分在第一方向上的尺寸范围为[500μm，1000μm]，其中，所述第一方向指的是沿所述透光区指向所述发光区的方向。
  9. 根据权利要求1至8中任一项所述的显示基板，其中，所述第一显示区内，所述发光区的总面积与所述透光区的总面积的比值范围为1:1～1:2。
  10. 根据权利要求1至9中任一项所述的显示基板，其中，同一透光区内设有至少两个搭接部，所述至少两个搭接部在平行于第一方向的方向上平行排布。
  11. 根据权利要求1至10中任一项所述的显示基板，其中，所述显示基板还包括第二显示区，所述第二显示区的透光率小于所述第一显示区的透光率。
  12. 一种显示装置，包括权利要求1至11中任一项所述的显示基板。
  13. 一种显示基板的制备方法，其中，所述显示基板包括第一显示区，所述第一显示区包括多个发光区与多个透光区，所述多个发光区呈阵列排布，所述多个透光区呈阵列排布，且所述多个发光区和所述多个透光区间隔排布；
    所述显示基板的制备方法包括：
    提供衬底；
    在所述衬底上形成位于所述多个发光区的每一个中的导电层及位于所述多个透光区中的每一个中的搭接部，所述导电层与所述搭接部在同一工艺步骤中形成；
    在所述导电层上形成阴极块，所述阴极块覆盖所述多个发光区中的每一个，其中，相邻两个发光区的阴极块通过位于该相邻两个发光区之间的透光区中的所述搭接部电连接。
  14. 根据权利要求10所述的显示基板的制备方法，其中，所述显示基板包括像素电路层，所述像素电路层包括薄膜晶体管，所述薄膜晶体管包括栅电极，所述导电层为所述栅电极。
  15. 根据权利要求14所述的显示基板的制备方法，其中，所述像素电路还包括电容，所述电容包括第一极板及第二极板，所述第一极板与所述导电层在同一工艺步骤中 形成；在所述衬底上形成所述导电层及所述搭接部之后，所述制备方法还包括：
    在所述栅电极上形成覆盖所述第一显示区的电容绝缘层，对所述电容绝缘层进行刻蚀，以使所述搭接部露出；
    在所述电容绝缘层上形成第二极板；
    在所述第二极板上形成覆盖所述第一显示区的层间介质层，对所述层间介质层进行刻蚀，以使所述搭接部露出；
    在所述层间介质层上形成源电极与漏电极；
    在所述源电极上形成覆盖所述第一显示区的平坦化层，对所述平坦化层进行刻蚀，以使所述搭接部露出；
    在所述平坦化层上形成阳极；
    在所述阳极上形成覆盖所述第一显示区的像素限定层，对所述像素限定层进行刻蚀，以使所述搭接部露出。
  16. 根据权利要求14所述的显示基板的制备方法，其中，所述像素电路还包括电容，所述电容包括第一极板及第二极板，所述第一极板与所述导电层在同一工艺步骤中形成；在所述衬底上形成导电层及搭接部之后，所述制备方法还包括：
    在所述栅电极上形成覆盖所述第一显示区的电容绝缘层；
    在所述电容绝缘层上形成第二极板；
    在所述第二极板上形成覆盖所述第一显示区的层间介质层；
    在所述层间介质层上形成源电极与漏电极；
    在所述源电极上形成覆盖所述第一显示区的平坦化层；
    在所述平坦化层上形成阳极；
    在所述阳极上形成覆盖所述第一显示区的像素限定层；
    对所述像素限定层、所述平坦化层、所述层间介质层以及所述电容绝缘层同时进行刻蚀，以使所述搭接部露出。
  17. 根据权利要求13所述的显示基板的制备方法，其中，所述在所述导电层上形成阴极层，包括：
    提供掩膜版，所述掩膜版包括与所述多个阴极块对应的开口；
    将所述掩膜版置于所述导电层上，所述多个发光区对应的开口在所述衬底上的正投影和与该开口相邻的搭接部在所述衬底上的正投影重叠；以及
    通过所述掩膜版的开口形成所述阴极块。
  18. 根据权利要求17所述的显示基板的制备方法，其中，所述开口在所述衬底上的正投影、与该开口相邻的所述搭接部在所述衬底上的正投影的重叠部分在第一方向上的尺寸范围为[500μm，1000μm]，其中，所述第一方向指的是沿所述透光区指向所述发光区的方向。
  19. 根据权利要求13所述的显示基板的制备方法，其中，还包括形成第二显示区，所述第二显示区的透光率小于所述第一显示区的透光率。
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