WO2021135662A1

WO2021135662A1 - Flash memory

Info

Publication number: WO2021135662A1
Application number: PCT/CN2020/128141
Authority: WO
Inventors: 刘佳庆; 张新展
Original assignee: 芯天下技术股份有限公司
Priority date: 2019-12-30
Filing date: 2020-11-11
Publication date: 2021-07-08
Also published as: CN111210861B; CN111210861A

Abstract

A flash memory, comprising a bidirectional I/O interface (10), a processing unit (20) and a storage unit (30); the processing unit (20) is electrically connected to the bidirectional I/O interface (10) and the storage unit (30) respectively. The processing unit (20) is used for acquiring, at a rising edge of a clock signal (SCK), stored data outputted by the storage unit (30), so as to obtain a first group of output data, and sending the first group of output data to the bidirectional I/O interface (10) to be output by the bidirectional I/O interface (10); acquiring, at a falling edge of the clock signal (SCK), stored data outputted by the storage unit (30); and performing a shift operation processing thereon, so as to obtain a second group of output data, and sending the second group of output data to the bidirectional I/O interface (10) to be output by the bidirectional I/O interface (10).

Description

A kind of flash memory

Technical field

The present invention relates to the field of circuits, in particular to a flash memory.

Background technique

The serial interface flash memory is a commonly used data storage component, but all its operations such as instructions, addresses, and data are serial input and output, resulting in a slow data transmission rate, especially during read operations.

In order to increase the data transmission rate, the prior art usually improves the frequency of the transmission clock and multi-pin multiplexing. The former scheme is specifically: using an internal high-speed clock to sample the rising and falling edges of the external transmission clock separately , And use it as an internal clock signal or control signal for data transmission to achieve twice the transmission rate of the external transmission clock; the latter scheme, that is, the multi-pin multiplexing mechanism is similar to the parallel transmission of multiple lines, which can reach The transmission clock is twice or even four times the transmission rate; the combination of the foregoing two solutions can further increase the data transmission rate of the memory. The disadvantage of the aforementioned two solutions is that due to the existence of the internal high-speed clock, the external clock has an upper limit problem. Generally, when the frequency of the external clock is greater than a quarter of the internal high-speed clock, the internal clock signal or control signal will not be stably generated. , Resulting in data cannot be transmitted, and due to the existence of the internal high-speed clock, the power consumption will be very large. However, multi-pin multiplexing may not be used in some states.

Summary of the invention

In view of the above technical problems, the present invention proposes a flash memory.

The technical scheme proposed by the present invention is as follows:

The present invention provides a flash memory, which includes a bidirectional I/O interface, a processing unit, and a storage unit; the processing unit is electrically connected to the bidirectional I/O interface and the storage unit, respectively;

The bidirectional I/O interface is used to receive external clock signals and input data signals, and sample the input data signal on the rising edge of the clock signal to obtain the first set of input data; sample the input data signal on the falling edge of the clock signal to obtain the first group of input data. Two sets of input data;

The storage unit is used to store the first group of input data and the second group of input data; it is also used to output its stored data;

The processing unit is used to obtain the stored data output by the storage unit at the rising edge of the clock signal, obtain the first set of output data, and send the first set of output data to the bidirectional I/O interface for output by the bidirectional I/O interface; Obtain the stored data output by the storage unit at the falling edge of the clock signal and perform the shift operation processing on it to obtain the second set of output data, and send the second set of output data to the bidirectional I/O interface by the bidirectional I/O interface. O interface output.

In the above-mentioned flash memory of the present invention, the processing unit is also used to synchronize the first group of input data and the second group of input data to output the data synchronization result; the storage unit is also used to store the data synchronization result.

In the above-mentioned flash memory of the present invention, the bidirectional I/O interface includes an input interface; the processing unit includes a combination unit electrically connected to the input interface and an input synchronization unit electrically connected to the combination unit and the storage unit; the input interface includes:

The first set of registers is used to receive external clock signals and input data signals, and sample the input data signals on the rising edge of the clock signal to obtain the first set of input data;

The second set of registers is used to receive external clock signals and input data signals, and sample the input data signals on the falling edge of the clock signal to obtain the second set of input data;

The combination unit is electrically connected to the first set of registers and the second set of registers, and is used to combine the first set of input data and the second set of input data;

The input synchronization unit is used to synchronize the first group of input data with the second group of input data, and output the data synchronization result to the storage unit at the rising edge of the clock signal.

In the above-mentioned flash memory of the present invention, the first set of registers includes two D flip-flops, the D flip-flops have a CK terminal, a Q terminal and a D terminal; the CK terminals of the two D flip-flops of the first set of registers are used to pass clk The signal line receives the external clock signal; the D terminals of the two D flip-flops of the first group of registers are used to receive the input data signal through the Data_in signal line;

The input interface also includes a first inverter; the second set of registers also includes two D flip-flops; the CK terminals of the two D flip-flops of the second set of registers are used to receive external signals through the clk signal line after the first inverter The D terminal of the two D flip-flops of the second set of registers is used to receive the input data signal through the Data_in signal line;

The combination unit includes a buffer Q[3:0], the input synchronization unit includes a D flip-flop; the CK terminal of the D flip-flop of the input synchronization unit is used to receive an external clock signal through the clk signal line; the D flip-flop of the input synchronization unit The D terminal of the D is electrically connected to the Q terminals of the two D flip-flops of the first set of registers and the Q terminal of the two D flip-flops of the second set of registers through the buffer Q[3:0]; the D of the input synchronization unit The Q terminal of the flip-flop is used to output the data synchronization result.

In the above-mentioned flash memory of the present invention, the bidirectional I/O interface further includes an output interface; the processing unit includes a first output synchronization module, a second output synchronization module, a first shift unit, and a second shift unit;

The first output synchronization module is electrically connected with the storage unit, the first shift unit, the second shift unit and the output interface respectively; the second output synchronization module is electrically connected with the second shift unit and the output interface respectively;

The first output synchronization module is used to obtain the stored data output by the storage unit at the rising edge of the clock signal, so as to synchronize the stored data output by the storage unit with the rising edge of the clock signal and send it to the first shift unit;

The first shift unit is used to perform the operation of shifting the data sent by the first output synchronization module by two bits to the left, so that the first output synchronization module shifts and outputs to the output interface by the highest bit of the stored data. The first set of output data composed;

The first output synchronization module is also used to obtain the stored data output by the storage unit at the falling edge of the clock signal and send it to the second shift unit;

The second shift unit is used to move the data sent by the first output synchronization module one bit to the left, so that the second output synchronization module uses the falling edge of the clock signal to synchronize the data and shift it to the output interface The second group of output data composed of the second high bit of the stored data is output.

In the above flash memory of the present invention, the first output synchronization module includes a third set of registers and a fourth set of registers; the first shift unit includes a first set of multiplexers composed of two multiplexers and two The second group of multiplexers composed of two multiplexers; the third group of registers and the fourth group of registers each contain two D flip-flops;

The CK terminals of the two D flip-flops of the third group of registers and the CK terminals of the two D flip-flops of the fourth group of registers are used to receive external clock signals through the clk signal line; the two D flip-flops of the third group of registers The D terminals of the are respectively connected to the two Y terminals of the first group of multiplexers; the D terminals of the two D flip-flops of the fourth group of registers are respectively connected to the two Y terminals of the second group of multiplexers;

The two input terminals A of the first group of multiplexers are respectively connected to the storage unit for obtaining the stored data output by the storage unit; the two input terminals B of the first group of multiplexers are respectively connected to the two registers of the fourth group The Q terminals of a D flip-flop, and the two selection terminals SEL of the first group of multiplexers are connected through the data_sel signal line to obtain internal control signals;

The two input terminals A of the second group of multiplexers are respectively connected to the storage unit to obtain the stored data data [3:0] output by the storage unit; the two selection terminals SEL of the second group of multiplexers pass data_sel Signal line connection, used to obtain internal control signals;

The second output synchronization module includes a fifth group of registers and a second inverter; the second shift unit includes a multiplexer; the fifth group of registers adopts D flip-flops; the CK terminal of the fifth group of registers is used to pass through the second After the inverter, the external clock signal is received through the clk signal line; the D terminal of the fifth group of registers is connected to the Q terminal of a D flip-flop in the third group of registers, and the input terminal A of the multiplexer of the second shift unit Connect the Q terminal of another D flip-flop in the third set of registers; the input B of the multiplexer of the second shift unit is connected to the Q terminal of the fifth set of registers; the multiplexer of the second shift unit The selection terminal SEL terminal is used to receive an external clock signal through the clk signal line after the second inverter; the Y terminal of the multiplexer of the second shift unit is used to output the first group of output data and the second group of output data .

In the above-mentioned flash memory of the present invention, the bidirectional I/O interface further includes a switching unit and an input-output channel. The switching unit is electrically connected to the input interface, the output interface, and the input-output channel, respectively, for connecting the input interface and the output interface. One switch is connected to the input and output channels.

In the above-mentioned flash memory of the present invention, the switching unit includes a first tri-state buffer, a second tri-state buffer and a third inverter;

The enable terminal of the first three-state buffer is used to obtain the enable signal I/O_en, the input terminal of the first three-state buffer is connected to the input and output channels, and the output terminal of the first three-state buffer is connected to the input interface;

The enable terminal of the second three-state buffer is used to obtain the enable signal I/O_en through the third inverter, the output terminal of the second three-state buffer is connected to the input and output channels, and the input terminal of the second three-state buffer is connected Output Interface.

The flash memory of the present invention samples the input data signal on the rising edge and the falling edge of the clock signal SCK through the bidirectional I/O interface, and outputs two sets of data signals on the rising edge and the falling edge of the clock signal SCK through the bidirectional I/O interface. Output data to achieve twice the data input rate and data output rate under a low-frequency clock. The flash memory of the present invention has novel design and strong practicability.

Description of the drawings

The present invention will be further described below in conjunction with the accompanying drawings and embodiments. In the accompanying drawings:

Figure 1 shows a block diagram of functional modules of a flash memory according to a preferred embodiment of the present invention;

FIG. 2 shows a connection circuit diagram of the input interface and the processing unit of the bidirectional I/O interface of the flash memory shown in FIG. 1;

3 shows a circuit diagram of the output interface of the bidirectional I/O interface of the flash memory shown in FIG. 1 and the connection circuit diagram of the processing unit of the preferred embodiment of the present invention;

FIG. 4 shows a circuit diagram of the switching unit 18 of the bidirectional I/O interface 10 according to a preferred embodiment of the present invention.

Detailed ways

In order to make the technical objectives, technical solutions, and technical effects of the present invention clearer, so that those skilled in the art can understand and implement the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

As shown in Fig. 1, Fig. 1 shows a block diagram of functional modules of a flash memory according to a preferred embodiment of the present invention. Specifically, the flash memory includes a bidirectional I/O interface 10, a processing unit 20, and a storage unit 30; the processing unit 20 is electrically connected to the bidirectional I/O interface 10 and the storage unit 30, respectively;

The bidirectional I/O interface 10 is used to receive the external clock signal SCK and the input data signal, and sample the input data signal on the rising edge of the clock signal SCK to obtain the first group of input data; and input the data signal on the falling edge of the clock signal SCK. Sampling to get the second set of input data;

The storage unit 30 is used to store the first set of input data and the second set of input data; it is also used to output its stored data;

The processing unit 20 is used to obtain the stored data output by the storage unit 30 at the rising edge of the clock signal SCK, obtain the first set of output data, and send the first set of output data to the bidirectional I/O interface 10 by the bidirectional I/O interface. O interface 10 output; at the falling edge of the clock signal SCK to obtain the stored data output by the storage unit 30 and perform shift processing to obtain the second set of output data, and send the second set of output data to the bidirectional I The /O interface 10 is output by the bidirectional I/O interface 10.

In the above technical solution, the input data signal is sampled at the rising edge and the falling edge of the clock signal SCK through the bidirectional I/O interface 10, and the input data signal is sampled at the rising edge and the falling edge of the clock signal SCK through the bidirectional I/O interface 10. Two sets of output data can achieve twice the data input rate and data output rate under a low-frequency clock. Specifically, this embodiment mainly improves the I/O interface of the flash memory, so that double rate and external data can be used; the other components of the flash memory, the transmission between each part, and the control implementation scheme And the connection scheme with the outside (such as high level Vcc, ground GND, chip selection signals CS#, W#, and HOLD#) can adopt existing technologies.

Further, in this embodiment, the bidirectional I/O interface 10 is also used to obtain the third group of output data SO by selecting the clock signal SCK.

Further, in this embodiment, the processing unit 20 is also used to synchronize the first set of input data and the second set of input data, and output the data synchronization result; the storage unit 30 is also used to store the data synchronization result;

Specifically, the bidirectional I/O interface 10 includes an input interface 11; the processing unit 20 includes a combination unit 15 electrically connected to the input interface 11, and an input synchronization unit 16 electrically connected to the combination unit 15 and the storage unit 30, respectively;

In this embodiment, as shown in FIG. 1 and FIG. 2, FIG. 2 shows a connection circuit diagram of the input interface of the bidirectional I/O interface of the flash memory shown in FIG. 1 and the processing unit. The input interface 11 specifically includes:

The first set of registers 13 is used to receive the external clock signal SCK and the input data signal, and sample the input data signal on the rising edge of the clock signal SCK to obtain the first set of input data;

The second set of registers 14 is used to receive the external clock signal SCK and the input data signal, and sample the input data signal on the falling edge of the clock signal SCK to obtain the second set of input data;

The combination unit 15 is electrically connected to the first group of registers 13 and the second group of registers 14 respectively, and is used to combine the first group of input data and the second group of input data;

The input synchronization unit 16 is configured to synchronize the first group of input data and the second group of input data, and output the data synchronization result to the storage unit 30 at the rising edge of the clock signal SCK.

The first set of registers 13 includes two D flip-flops, the D flip-flops have CK, Q and D ends; the CK ends of the two D flip-flops of the first set of registers 13 are used to receive external clock signals through the clk signal line SCK; The D terminals of the two D flip-flops of the first set of registers 13 are used to receive the input data signal through the Data_in signal line; the input data signal is serial data, and the internal counter determines the effective data position of the first set of registers 13.

The input interface 11 also includes a first inverter 17; the second set of registers 14 also includes two D flip-flops; the CK terminals of the two D flip-flops of the second set of registers 14 are used to pass through the first inverter 17 The clk signal line receives the external clock signal SCK; the D terminals of the two D flip-flops of the second set of registers 14 are used to receive the input data signal through the Data_in signal line; the input data signal is serial data, and the internal counter judges the first set of registers 13 valid data location.

The combination unit 15 includes a buffer Q[3:0], the input synchronization unit 16 includes a D flip-flop; the CK end of the D flip-flop of the input synchronization unit 16 is used to receive the external clock signal SCK through the clk signal line; the input synchronization unit The D terminals of the 16 D flip-flops are electrically connected to the Q terminals of the two D flip-flops of the first set of registers 13 and the Q terminals of the two D flip-flops of the second set of registers 14 through the buffer Q[3:0]. Connection; the Q terminal of the D flip-flop of the input synchronization unit 16 is used to output the data synchronization result data[3:0].

In the above technical solution, the data transmission rate of the Data_in signal line can reach twice the rate of the clock signal SCK. It can be seen that the first set of registers 13 samples data on the rising edge of the clock signal SCK, and the second set of registers 14 samples data on the falling edge of the clock signal SCK. The input synchronization unit 16 synchronizes the data output from the first set of registers 13 and the second set of registers 14, so that both sets of input data are synchronously output to the storage unit on the rising edge of the clock signal SCK; therefore, it can be used without changing the clock signal SCK. In the case of frequency, the transmission rate of the input data is doubled. At the same time, the data rate is reduced inside the chip, which reduces power consumption and facilitates subsequent processing.

The above is only an implementation scheme of the input interface 11, the combination unit 15 and the input synchronization unit 16 of this embodiment. In practical applications, other schemes can also be used to implement the scheme of this embodiment, as long as it is ensured that the rising edge of the clock signal SCK and The input data signal is sampled at the falling edges, and is simultaneously transmitted to the storage unit 30 at the rising and falling edges of the clock signal SCK.

Further, as shown in FIGS. 1 and 3, FIG. 3 shows a circuit diagram of the output interface of the bidirectional I/O interface of the flash memory shown in FIG. 1 and the connection circuit diagram of the processing unit in the preferred embodiment of the present invention. In this embodiment, the bidirectional I/O interface 10 further includes an output interface 12; the processing unit 20 may specifically include a first output synchronization module 21, a second output synchronization module 22, a first shift unit 23, and a second shift unit 24. ；

The first output synchronization module 21 is electrically connected to the storage unit 30, the first shift unit 23, the second shift unit 24 and the output interface 12, respectively; the second output synchronization module 22 is respectively connected to the second shift unit 24 and the output interface 12 Electrical connection;

The first output synchronization module 21 is used to obtain the stored data output by the storage unit 30 at the rising edge of the clock signal SCK, so as to use the rising edge of the clock signal SCK to synchronize the stored data output by the storage unit 30 and send it to the first A shift unit 23;

The first shift unit 23 is used to perform the operation of shifting the data sent by the first output synchronization module 21 to the left by two bits, so that the first output synchronization module 21 shifts to the output interface 12 to output the stored data. The first set of output data composed of the highest bit;

The first output synchronization module 21 is also used to obtain the stored data output by the storage unit 30 at the falling edge of the clock signal SCK, and send it to the second shift unit 24;

The second shift unit 24 is used to perform the operation of shifting the data sent by the first output synchronization module 21 by one bit to the left, so that the second output synchronization module 22 uses the falling edge of the clock signal SCK to synchronize the data and to The output interface 12 shifts and outputs a second group of output data composed of the second high bit of the stored data.

Specifically, as shown in FIG. 3, the first output synchronization module 21 includes a third group of registers 25 and a fourth group of registers 26; the first shift unit 23 includes a first group of multiplexers composed of two multiplexers. The second group of multiplexers 28 composed of two multiplexers 27 and the second group of multiplexers 28; the third group of registers 25 and the fourth group of registers 26 each include two D flip-flops;

The CK terminals of the two D flip-flops of the third group of registers 25 and the CK terminals of the two D flip-flops of the fourth group of registers 26 are both used to receive the external clock signal SCK through the clk signal line; the two of the third group of registers 25 The D terminals of each D flip-flop are respectively connected to the two Y terminals of the first group of multiplexers 27; the D terminals of the two D flip-flops of the fourth group of registers 26 are respectively connected to two of the second group of multiplexers 28 Y end;

The two input terminals A of the first group of multiplexers 27 are respectively connected to the storage unit 30 for obtaining the stored data data [3:0] output by the storage unit 30; the two inputs of the first group of multiplexers 27 Terminal B is respectively connected to the Q terminals of the two D flip-flops of the fourth group of registers 26, and the two selection terminals SEL of the first group of multiplexers 27 are connected through the data_sel signal line for obtaining internal control signals;

The two input terminals A of the second group of multiplexers 28 are respectively connected to the storage unit 30 for obtaining the stored data data [3:0] output by the storage unit 30; two options of the second group of multiplexers 28 The terminal SEL is connected through the data_sel signal line for obtaining internal control signals;

The second output synchronization module 22 includes a fifth set of registers 29 and a second inverter 31; the second shift unit 24 includes a multiplexer; the fifth set of registers 29 are D flip-flops; the fifth set of registers 29 is CK The terminal is used to receive the external clock signal SCK through the clk signal line after the second inverter 31; the D terminal of the fifth group of registers 29 is connected to the Q terminal of a D flip-flop in the third group of registers 25, and the second shift The input terminal A of the multiplexer of the unit 24 is connected to the Q terminal of another D flip-flop in the third set of registers 25; the input terminal B of the multiplexer of the second shift unit 24 is connected to the fifth set of registers 29 Q terminal; the selection terminal SEL of the multiplexer of the second shift unit 24 is used to receive the external clock signal SCK through the clk signal line after the second inverter 31; when the clock signal SCK is high, select The Q terminal of the fifth set of registers 29 outputs data. When the clock signal SCK is low, the D flip-flop connected to the input terminal A of the second shift unit 24 in the third set of registers 25 is selected to output data, so that the first The data Data_out output by the Y terminal of the multiplexer of the two shift unit 24 may be the first group of output data or the second group of output data. The first output synchronization module 21 and the second output synchronization module 22 synchronize the two channels of data, and realize the double rate of data output without changing the clock frequency.

The above is only a connection implementation scheme of the output interface 12 and the processing unit 20 of this embodiment. In practical applications, other schemes can also be used to achieve the technical effects of this embodiment, as long as it is ensured that both the rising and falling edges of the clock signal are output. data.

In this embodiment, the bidirectional I/O interface 10 may also include a switching unit 18 and an input/output channel 19. The switching unit 18 is electrically connected to the input interface 11, the output interface 12, and the input/output channel 19, respectively, for connecting the input interface 11 , One of the output interfaces 12 is switched to be connected to the input/output channel 19.

As shown in FIG. 4, FIG. 4 shows a circuit diagram of the switching unit 18 of the bidirectional I/O interface 10 of the preferred embodiment of the present invention. Among them, the circuit structures of the input interface 11 and the output interface 12 are shown in Figure 2 and Figure 3 respectively;

The switching unit 18 includes a first tri-state buffer 32, a second tri-state buffer 33, and a third inverter 34; the enable terminal ENB of the first tri-state buffer 32 is used to obtain the enable signal I/O_en, The input end of the first three-state buffer 32 is connected to the input/output channel 19, and the output end of the first three-state buffer 32 is connected to the input interface 11. Specifically, the output ends of the first three-state buffer 32 are respectively connected to the first group The D terminals of the two D flip-flops of the register 13 and the D terminals of the two D flip-flops of the second group of registers 14;

The enable terminal ENB of the second three-state buffer 33 is used to obtain the enable signal I/O_en via the third inverter 34, the output terminal of the second three-state buffer 33 is connected to the input and output channel 19, and the second three-state buffer The input end of the converter 33 is connected to the output interface 12, specifically, the input end of the second three-state buffer 33 is connected to the Y end of the multiplexer of the second shift unit 24.

When the enable signal I/O_en is at a high level, the first three-state buffer 32 is in a high-impedance state, and the second three-state buffer 33 is turned on. At this time, the input and output channel 19 is connected to the output interface 12, and the input and output channel The output channel in 19 is turned on to achieve double the data output rate; when the enable signal I/O_en is low, the second three-state buffer 33 is in a high-impedance state, and the first three-state buffer 32 is turned on, At this time, the input/output channel 19 is connected to the input interface 11, and the input channel in the input/output channel 19 is turned on, realizing twice the data input rate.

The embodiments of the present invention are described above with reference to the accompanying drawings, but the present invention is not limited to the above-mentioned specific embodiments. The above-mentioned specific embodiments are only illustrative and not restrictive. Those of ordinary skill in the art are Under the enlightenment of the present invention, many forms can be made without departing from the purpose of the present invention and the protection scope of the claims, and these all fall within the protection of the present invention.

Claims

A flash memory, which is characterized by comprising a bidirectional I/O interface (10), a processing unit (20) and a storage unit (30); the processing unit (20) is respectively connected to the bidirectional I/O interface (10) and the storage unit (30) Electrical connection;

The bidirectional I/O interface (10) is used to receive the external clock signal (SCK) and input data signal, and sample the input data signal on the rising edge of the clock signal (SCK) to obtain the first group of input data; in the clock signal (SCK) The falling edge of) samples the input data signal to obtain the second group of input data;

The storage unit (30) is used to store the first group of input data and the second group of input data; it is also used to output its stored data;

The processing unit (20) is used to obtain the stored data output by the storage unit (30) at the rising edge of the clock signal (SCK), obtain the first set of output data, and send the first set of output data to the bidirectional I/O The interface (10) is output by the bidirectional I/O interface (10); at the falling edge of the clock signal (SCK), the stored data output by the storage unit (30) is obtained and the shift operation is performed to obtain the second set of output The second set of output data is sent to the bidirectional I/O interface (10) and output by the bidirectional I/O interface (10).
The flash memory according to claim 1, wherein the processing unit (20) is also used to synchronize the first group of input data and the second group of input data, and output the data synchronization result; the storage unit (30) also uses Used to store data synchronization results.
The flash memory according to claim 2, wherein the bidirectional I/O interface (10) comprises an input interface (11); the processing unit (20) comprises a combination unit (15) electrically connected to the input interface (11) ) And an input synchronization unit (16) electrically connected to the combination unit (15) and the storage unit (30); the input interface (11) includes:

The first set of registers (13) are used to receive external clock signals (SCK) and input data signals, and sample the input data signals on the rising edge of the clock signal (SCK) to obtain the first set of input data;

The second set of registers (14) is used to receive the external clock signal (SCK) and input data signal, and sample the input data signal on the falling edge of the clock signal (SCK) to obtain the second set of input data;

The combination unit (15) is electrically connected to the first set of registers (13) and the second set of registers (14), and is used to combine the first set of input data and the second set of input data;

The input synchronization unit (16) is used for synchronizing the first group of input data and the second group of input data, and outputs the data synchronization result to the storage unit (30) at the rising edge of the clock signal (SCK).
The flash memory according to claim 3, wherein the first set of registers (13) includes two D flip-flops, the D flip-flops have a CK terminal, a Q terminal and a D terminal; the first set of registers (13) The CK terminals of the two D flip-flops are used to receive the external clock signal (SCK) through the clk signal line; the D terminals of the two D flip-flops of the first group of registers (13) are used to receive the input data signal through the Data_in signal line;

The input interface (11) also includes a first inverter (17); the second set of registers (14) also includes two D flip-flops; the CK terminals of the two D flip-flops of the second set of registers (14) are used for After the first inverter (17) receives the external clock signal (SCK) through the clk signal line; the D terminals of the two D flip-flops of the second set of registers (14) are used to receive the input data signal through the Data_in signal line;

The combination unit (15) includes a buffer Q[3:0], the input synchronization unit (16) includes a D flip-flop; the CK terminal of the D flip-flop of the input synchronization unit (16) is used to receive an external clock through the clk signal line Signal (SCK); the D terminal of the D flip-flop input to the synchronization unit (16) is connected to the Q terminal of the two D flip-flops of the first set of registers (13) and the second set of registers through the buffer Q[3:0] The Q terminals of the two D flip-flops of (14) are electrically connected; the Q terminal of the D flip-flops of the input synchronization unit (16) is used to output the data synchronization result.
The flash memory according to claim 1, wherein the bidirectional I/O interface (10) further includes an output interface (12); the processing unit (20) includes a first output synchronization module (21), a second output synchronization module (21), and a second output synchronization module (21). Module (22), first shift unit (23) and second shift unit (24);

The first output synchronization module (21) is electrically connected to the storage unit (30), the first shift unit (23), the second shift unit (24) and the output interface (12); the second output synchronization module (22) ) Are respectively electrically connected to the second shift unit (24) and the output interface (12);

The first output synchronization module (21) is used to obtain the stored data output by the storage unit (30) at the rising edge of the clock signal (SCK), so as to use the rising edge of the clock signal (SCK) to output data from the storage unit (30). The stored data of is synchronized and sent to the first shift unit (23);

The first shift unit (23) is used to perform the operation of shifting the data sent by the first output synchronization module (21) to the left by two bits, so that the first output synchronization module (21) shifts to the output interface (12) Outputting the first group of output data consisting of the highest bit of the stored data;

The first output synchronization module (21) is also used to obtain the stored data output by the storage unit (30) at the falling edge of the clock signal (SCK) and send it to the second shift unit (24);

The second shift unit (24) is used to perform the operation of shifting the data sent by the first output synchronization module (21) by one bit to the left, so that the second output synchronization module (22) uses the falling of the clock signal (SCK) The data is synchronized along and shifted to the output interface (12) to output the second group of output data composed of the second high bit of the stored data.
The flash memory according to claim 5, wherein the first output synchronization module (21) includes a third group of registers (25) and a fourth group of registers (26); the first shift unit (23) includes The first group of multiplexers (27) composed of two multiplexers and the second group of multiplexers (28) composed of two multiplexers; the third group of registers (25) and the fourth group Each register (26) contains two D flip-flops;

The CK terminals of the two D flip-flops of the third group of registers (25) and the CK terminals of the two D flip-flops of the fourth group of registers (26) are both used to receive an external clock signal (SCK) through the clk signal line; The D terminals of the two D flip-flops of the three groups of registers (25) are respectively connected to the two Y terminals of the first group of multiplexers (27); the D terminals of the two D flip-flops of the fourth group of registers (26) are respectively connected Connect the two Y ends of the second group of multiplexers (28);

The two input terminals A of the first group of multiplexers (27) are respectively connected to the storage unit (30) for obtaining the stored data output by the storage unit (30); the two inputs of the first group of multiplexers (27) Two input terminals B are respectively connected to the Q terminals of the two D flip-flops of the fourth group of registers (26), and the two selection terminals SEL of the first group of multiplexers (27) are connected through the data_sel signal line to obtain internal control signal;

The two input terminals A of the second group of multiplexers (28) are respectively connected to the storage unit (30) for obtaining the stored data data [3:0] output by the storage unit (30); the second group of multiplexers The two selection terminals SEL of the device (28) are connected through the data_sel signal line for obtaining internal control signals;

The second output synchronization module (22) includes a fifth set of registers (29) and a second inverter (31); the second shift unit (24) includes a multiplexer; the fifth set of registers (29) uses D Flip-flop; the CK terminal of the fifth group of registers (29) is used to receive the external clock signal (SCK) through the clk signal line after the second inverter (31); the D terminal of the fifth group of registers (29) is connected to the first The Q terminal of one D flip-flop in the three sets of registers (25), the input A of the multiplexer of the second shift unit (24) is connected to the Q terminal of another D flip-flop in the third set of registers (25) The input terminal B of the multiplexer of the second shift unit (24) is connected to the Q terminal of the fifth group of registers (29); the multiplexer of the second shift unit (24) is used for the selection terminal SEL terminal After passing through the second inverter (31), the external clock signal (SCK) is received through the clk signal line; the Y terminal of the multiplexer of the second shift unit (24) is used to output the first set of output data and the first set of output data. Two sets of output data.
The flash memory according to claim 1, wherein the bidirectional I/O interface (10) further comprises a switching unit (18) and an input/output channel (19), and the switching unit (18) is connected to the input interface (11) respectively. , The output interface (12) and the input/output channel (19) are electrically connected for switching one of the input interface (11) and the output interface (12) to be connected to the input/output channel (19).
The flash memory according to claim 7, wherein the switching unit (18) comprises a first tri-state buffer (32), a second tri-state buffer (33) and a third inverter (34);

The enable terminal (ENB) of the first three-state buffer (32) is used to obtain the enable signal I/O_en, the input terminal of the first three-state buffer (32) is connected to the input/output channel (19), and the first three-state buffer (32) is The output terminal of the state buffer (32) is connected to the input interface (11);

The enable terminal (ENB) of the second three-state buffer (33) is used to obtain the enable signal I/O_en via the third inverter (34), and the output terminal of the second three-state buffer (33) is connected to the input and output In the channel (19), the input end of the second three-state buffer (33) is connected to the output interface (12).